opcodes/ChangeLog

   1 2020-02-17  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (AddrPrefixOpReg): Define.
   4         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
   5         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
   6         templates. Drop NoRex64.
   7         * i386-tbl.h: Re-generate.
   8
   9 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  10
  11         PR gas/6518
  12         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  13         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
  14         into Intel syntax instance (with Unpsecified) and AT&T one
  15         (without).
  16         (vcvtneps2bf16): Likewise, along with folding the two so far
  17         separate ones.
  18         * i386-tbl.h: Re-generate.
  19
  20 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  21
  22         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
  23         CPU_ANY_SSE4A_FLAGS.
  24
  25 2020-02-17  Alan Modra  <amodra@gmail.com>
  26
  27         * i386-gen.c (cpu_flag_init): Correct last change.
  28
  29 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  30
  31         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
  32         CPU_ANY_SSE4_FLAGS.
  33
  34 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  35
  36         * i386-opc.tbl (movsx): Remove Intel syntax comments.
  37         (movzx): Likewise.
  38
  39 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  40
  41         PR gas/25438
  42         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  43         destination for Cpu64-only variant.
  44         (movzx): Fold patterns.
  45         * i386-tbl.h: Re-generate.
  46
  47 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  48
  49         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  50         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  51         CPU_ANY_SSE4_FLAGS entry.
  52         * i386-init.h: Re-generate.
  53
  54 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  55
  56         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
  57         with Unspecified, making the present one AT&T syntax only.
  58         * i386-tbl.h: Re-generate.
  59
  60 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  61
  62         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
  63         * i386-tbl.h: Re-generate.
  64
  65 2020-02-12  Jan Beulich  <jbeulich@suse.com>
  66
  67         PR gas/24546
  68         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
  69         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
  70         Amd64 and Intel64 templates.
  71         (call, jmp): Likewise for far indirect variants. Dro
  72         Unspecified.
  73         * i386-tbl.h: Re-generate.
  74
  75 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  76
  77         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
  78         * i386-opc.h (ShortForm): Delete.
  79         (struct i386_opcode_modifier): Remove shortform field.
  80         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
  81         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
  82         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
  83         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
  84         Drop ShortForm.
  85         * i386-tbl.h: Re-generate.
  86
  87 2020-02-11  Jan Beulich  <jbeulich@suse.com>
  88
  89         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
  90         fucompi): Drop ShortForm from operand-less templates.
  91         * i386-tbl.h: Re-generate.
  92
  93 2020-02-11  Alan Modra  <amodra@gmail.com>
  94
  95         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
  96         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
  97         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
  98         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
  99         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 100
 101 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 102
 103         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 104         (cde_opcodes): Add VCX* instructions.
 105
 106 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 107             Matthew Malcomson  <matthew.malcomson@arm.com>
 108
 109         * arm-dis.c (struct cdeopcode32): New.
 110         (CDE_OPCODE): New macro.
 111         (cde_opcodes): New disassembly table.
 112         (regnames): New option to table.
 113         (cde_coprocs): New global variable.
 114         (print_insn_cde): New
 115         (print_insn_thumb32): Use print_insn_cde.
 116         (parse_arm_disassembler_options): Parse coprocN args.
 117
 118 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 119
 120         PR gas/25516
 121         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 122         with ISA64.
 123         * i386-opc.h (AMD64): Removed.
 124         (Intel64): Likewose.
 125         (AMD64): New.
 126         (INTEL64): Likewise.
 127         (INTEL64ONLY): Likewise.
 128         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 129         * i386-opc.tbl (Amd64): New.
 130         (Intel64): Likewise.
 131         (Intel64Only): Likewise.
 132         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 133         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 134         * i386-tbl.h: Regenerated.
 135
 136 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 137
 138         PR 25469
 139         * z80-dis.c: Add support for GBZ80 opcodes.
 140
 141 2020-02-04  Alan Modra  <amodra@gmail.com>
 142
 143         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 144
 145 2020-02-03  Alan Modra  <amodra@gmail.com>
 146
 147         * m32c-ibld.c: Regenerate.
 148
 149 2020-02-01  Alan Modra  <amodra@gmail.com>
 150
 151         * frv-ibld.c: Regenerate.
 152
 153 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 154
 155         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 156         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 157         (OP_E_memory): Replace xmm_mdq_mode case label by
 158         vex_scalar_w_dq_mode one.
 159         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 160
 161 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 164         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 165         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 166         (intel_operand_size): Drop vex_w_dq_mode case label.
 167
 168 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 169
 170         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 171         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 172
 173 2020-01-30  Alan Modra  <amodra@gmail.com>
 174
 175         * m32c-ibld.c: Regenerate.
 176
 177 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 178
 179         * bpf-opc.c: Regenerate.
 180
 181 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 184         (dis386): Use them to replace C2/C3 table entries.
 185         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 186         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 187         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 188         * i386-tbl.h: Re-generate.
 189
 190 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 191
 192         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 193         forms.
 194         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 195         DefaultSize.
 196         * i386-tbl.h: Re-generate.
 197
 198 2020-01-30  Alan Modra  <amodra@gmail.com>
 199
 200         * tic4x-dis.c (tic4x_dp): Make unsigned.
 201
 202 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 203             Jan Beulich  <jbeulich@suse.com>
 204
 205         PR binutils/25445
 206         * i386-dis.c (MOVSXD_Fixup): New function.
 207         (movsxd_mode): New enum.
 208         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 209         (intel_operand_size): Handle movsxd_mode.
 210         (OP_E_register): Likewise.
 211         (OP_G): Likewise.
 212         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 213         register on movsxd.  Add movsxd with 16-bit destination register
 214         for AMD64 and Intel64 ISAs.
 215         * i386-tbl.h: Regenerated.
 216
 217 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 218
 219         PR 25403
 220         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 221         * aarch64-asm-2.c: Regenerate
 222         * aarch64-dis-2.c: Likewise.
 223         * aarch64-opc-2.c: Likewise.
 224
 225 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-opc.tbl (sysret): Drop DefaultSize.
 228         * i386-tbl.h: Re-generate.
 229
 230 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 231
 232         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 233         Dword.
 234         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 235         * i386-tbl.h: Re-generate.
 236
 237 2020-01-20  Nick Clifton  <nickc@redhat.com>
 238
 239         * po/de.po: Updated German translation.
 240         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 241         * po/uk.po: Updated Ukranian translation.
 242
 243 2020-01-20  Alan Modra  <amodra@gmail.com>
 244
 245         * hppa-dis.c (fput_const): Remove useless cast.
 246
 247 2020-01-20  Alan Modra  <amodra@gmail.com>
 248
 249         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 250
 251 2020-01-18  Nick Clifton  <nickc@redhat.com>
 252
 253         * configure: Regenerate.
 254         * po/opcodes.pot: Regenerate.
 255
 256 2020-01-18  Nick Clifton  <nickc@redhat.com>
 257
 258         Binutils 2.34 branch created.
 259
 260 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 261
 262         * opintl.h: Fix spelling error (seperate).
 263
 264 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 265
 266         * i386-opc.tbl: Add {vex} pseudo prefix.
 267         * i386-tbl.h: Regenerated.
 268
 269 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 270
 271         PR 25376
 272         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 273         (neon_opcodes): Likewise.
 274         (select_arm_features): Make sure we enable MVE bits when selecting
 275         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 276         any architecture.
 277
 278 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 279
 280         * i386-opc.tbl: Drop stale comment from XOP section.
 281
 282 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 283
 284         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 285         (extractps): Add VexWIG to SSE2AVX forms.
 286         * i386-tbl.h: Re-generate.
 287
 288 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 289
 290         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 291         Size64 from and use VexW1 on SSE2AVX forms.
 292         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 293         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 294         * i386-tbl.h: Re-generate.
 295
 296 2020-01-15  Alan Modra  <amodra@gmail.com>
 297
 298         * tic4x-dis.c (tic4x_version): Make unsigned long.
 299         (optab, optab_special, registernames): New file scope vars.
 300         (tic4x_print_register): Set up registernames rather than
 301         malloc'd registertable.
 302         (tic4x_disassemble): Delete optable and optable_special.  Use
 303         optab and optab_special instead.  Throw away old optab,
 304         optab_special and registernames when info->mach changes.
 305
 306 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 307
 308         PR 25377
 309         * z80-dis.c (suffix): Use .db instruction to generate double
 310         prefix.
 311
 312 2020-01-14  Alan Modra  <amodra@gmail.com>
 313
 314         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 315         values to unsigned before shifting.
 316
 317 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 318
 319         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 320         flow instructions.
 321         (print_insn_thumb16, print_insn_thumb32): Likewise.
 322         (print_insn): Initialize the insn info.
 323         * i386-dis.c (print_insn): Initialize the insn info fields, and
 324         detect jumps.
 325
 326 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 327
 328         * arc-opc.c (C_NE): Make it required.
 329
 330 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 331
 332         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 333         reserved register name.
 334
 335 2020-01-13  Alan Modra  <amodra@gmail.com>
 336
 337         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 338         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 339
 340 2020-01-13  Alan Modra  <amodra@gmail.com>
 341
 342         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 343         result of wasm_read_leb128 in a uint64_t and check that bits
 344         are not lost when copying to other locals.  Use uint32_t for
 345         most locals.  Use PRId64 when printing int64_t.
 346
 347 2020-01-13  Alan Modra  <amodra@gmail.com>
 348
 349         * score-dis.c: Formatting.
 350         * score7-dis.c: Formatting.
 351
 352 2020-01-13  Alan Modra  <amodra@gmail.com>
 353
 354         * score-dis.c (print_insn_score48): Use unsigned variables for
 355         unsigned values.  Don't left shift negative values.
 356         (print_insn_score32): Likewise.
 357         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 358
 359 2020-01-13  Alan Modra  <amodra@gmail.com>
 360
 361         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 362
 363 2020-01-13  Alan Modra  <amodra@gmail.com>
 364
 365         * fr30-ibld.c: Regenerate.
 366
 367 2020-01-13  Alan Modra  <amodra@gmail.com>
 368
 369         * xgate-dis.c (print_insn): Don't left shift signed value.
 370         (ripBits): Formatting, use 1u.
 371
 372 2020-01-10  Alan Modra  <amodra@gmail.com>
 373
 374         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 375         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 376
 377 2020-01-10  Alan Modra  <amodra@gmail.com>
 378
 379         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 380         and XRREG value earlier to avoid a shift with negative exponent.
 381         * m10200-dis.c (disassemble): Similarly.
 382
 383 2020-01-09  Nick Clifton  <nickc@redhat.com>
 384
 385         PR 25224
 386         * z80-dis.c (ld_ii_ii): Use correct cast.
 387
 388 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 389
 390         PR 25224
 391         * z80-dis.c (ld_ii_ii): Use character constant when checking
 392         opcode byte value.
 393
 394 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 395
 396         * i386-dis.c (SEP_Fixup): New.
 397         (SEP): Define.
 398         (dis386_twobyte): Use it for sysenter/sysexit.
 399         (enum x86_64_isa): Change amd64 enumerator to value 1.
 400         (OP_J): Compare isa64 against intel64 instead of amd64.
 401         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 402         forms.
 403         * i386-tbl.h: Re-generate.
 404
 405 2020-01-08  Alan Modra  <amodra@gmail.com>
 406
 407         * z8k-dis.c: Include libiberty.h
 408         (instr_data_s): Make max_fetched unsigned.
 409         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 410         Don't exceed byte_info bounds.
 411         (output_instr): Make num_bytes unsigned.
 412         (unpack_instr): Likewise for nibl_count and loop.
 413         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 414         idx unsigned.
 415         * z8k-opc.h: Regenerate.
 416
 417 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 418
 419         * arc-tbl.h (llock): Use 'LLOCK' as class.
 420         (llockd): Likewise.
 421         (scond): Use 'SCOND' as class.
 422         (scondd): Likewise.
 423         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 424         (scondd): Likewise.
 425
 426 2020-01-06  Alan Modra  <amodra@gmail.com>
 427
 428         * m32c-ibld.c: Regenerate.
 429
 430 2020-01-06  Alan Modra  <amodra@gmail.com>
 431
 432         PR 25344
 433         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 434         Peek at next byte to prevent recursion on repeated prefix bytes.
 435         Ensure uninitialised "mybuf" is not accessed.
 436         (print_insn_z80): Don't zero n_fetch and n_used here,..
 437         (print_insn_z80_buf): ..do it here instead.
 438
 439 2020-01-04  Alan Modra  <amodra@gmail.com>
 440
 441         * m32r-ibld.c: Regenerate.
 442
 443 2020-01-04  Alan Modra  <amodra@gmail.com>
 444
 445         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 446
 447 2020-01-04  Alan Modra  <amodra@gmail.com>
 448
 449         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 450
 451 2020-01-04  Alan Modra  <amodra@gmail.com>
 452
 453         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 454
 455 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 456
 457         * aarch64-tbl.h (aarch64_opcode_table): Use
 458         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 459
 460 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 461
 462         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 463         forms of SUDOT and USDOT.
 464
 465 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 466
 467         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 468         uzip{1,2}.
 469         * opcodes/aarch64-dis-2.c: Re-generate.
 470
 471 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 472
 473         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 474         FMMLA encoding.
 475         * opcodes/aarch64-dis-2.c: Re-generate.
 476
 477 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 478
 479         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 480
 481 2020-01-01  Alan Modra  <amodra@gmail.com>
 482
 483         Update year range in copyright notice of all files.
 484
 485 For older changes see ChangeLog-2019
 486 \f
 487 Copyright (C) 2020 Free Software Foundation, Inc.
 488
 489 Copying and distribution of this file, with or without modification,
 490 are permitted in any medium without royalty provided the copyright
 491 notice and this notice are preserved.
 492
 493 Local Variables:
 494 mode: change-log
 495 left-margin: 8
 496 fill-column: 74
 497 version-control: never
 498 End: