1 2018-07-06 Tamar Christina <tamar.christina@arm.com>
4 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
5 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
7 2018-07-02 Maciej W. Rozycki <macro@mips.com>
10 * mips-dis.c (mips_option_arg_t): New enumeration.
11 (mips_options): New variable.
12 (disassembler_options_mips): New function.
13 (print_mips_disassembler_options): Reimplement in terms of
14 `disassembler_options_mips'.
15 * arm-dis.c (disassembler_options_arm): Adapt to using the
16 `disasm_options_and_args_t' structure.
17 * ppc-dis.c (disassembler_options_powerpc): Likewise.
18 * s390-dis.c (disassembler_options_s390): Likewise.
20 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
22 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
24 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
25 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
26 * testsuite/ld-arm/tls-longplt.d: Likewise.
28 2018-06-29 Tamar Christina <tamar.christina@arm.com>
31 * aarch64-asm-2.c: Regenerate.
32 * aarch64-dis-2.c: Likewise.
33 * aarch64-opc-2.c: Likewise.
34 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
35 * aarch64-opc.c (operand_general_constraint_met_p,
36 aarch64_print_operand): Likewise.
37 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
38 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
40 (AARCH64_OPERANDS): Add Em2.
42 2018-06-26 Nick Clifton <nickc@redhat.com>
44 * po/uk.po: Updated Ukranian translation.
45 * po/de.po: Updated German translation.
46 * po/pt_BR.po: Updated Brazilian Portuguese translation.
48 2018-06-26 Nick Clifton <nickc@redhat.com>
50 * nfp-dis.c: Fix spelling mistake.
52 2018-06-24 Nick Clifton <nickc@redhat.com>
54 * configure: Regenerate.
55 * po/opcodes.pot: Regenerate.
57 2018-06-24 Nick Clifton <nickc@redhat.com>
61 2018-06-19 Tamar Christina <tamar.christina@arm.com>
63 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
64 * aarch64-asm-2.c: Regenerate.
65 * aarch64-dis-2.c: Likewise.
67 2018-06-21 Maciej W. Rozycki <macro@mips.com>
69 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
70 `-M ginv' option description.
72 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
75 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
78 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
80 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
81 * configure.ac: Remove AC_PREREQ.
82 * Makefile.in: Re-generate.
83 * aclocal.m4: Re-generate.
84 * configure: Re-generate.
86 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
88 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
90 (parse_mips_ase_option): Handle -Mginv option.
91 (print_mips_disassembler_options): Document -Mginv.
92 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
94 (mips_opcodes): Define ginvi and ginvt.
96 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
97 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
99 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
100 * mips-opc.c (CRC, CRC64): New macros.
101 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
102 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
105 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
108 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
109 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
111 2018-06-06 Alan Modra <amodra@gmail.com>
113 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
114 setjmp. Move init for some other vars later too.
116 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
118 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
119 (dis_private): Add new fields for property section tracking.
120 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
121 (xtensa_instruction_fits): New functions.
122 (fetch_data): Bump minimal fetch size to 4.
123 (print_insn_xtensa): Make struct dis_private static.
124 Load and prepare property table on section change.
125 Don't disassemble literals. Don't disassemble instructions that
126 cross property table boundaries.
128 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
130 * configure: Regenerated.
132 2018-06-01 Jan Beulich <jbeulich@suse.com>
134 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
135 * i386-tbl.h: Re-generate.
137 2018-06-01 Jan Beulich <jbeulich@suse.com>
139 * i386-opc.tbl (sldt, str): Add NoRex64.
140 * i386-tbl.h: Re-generate.
142 2018-06-01 Jan Beulich <jbeulich@suse.com>
144 * i386-opc.tbl (invpcid): Add Oword.
145 * i386-tbl.h: Re-generate.
147 2018-06-01 Alan Modra <amodra@gmail.com>
149 * sysdep.h (_bfd_error_handler): Don't declare.
150 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
151 * rl78-decode.opc: Likewise.
152 * msp430-decode.c: Regenerate.
153 * rl78-decode.c: Regenerate.
155 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
157 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
158 * i386-init.h : Regenerated.
160 2018-05-25 Alan Modra <amodra@gmail.com>
162 * Makefile.in: Regenerate.
163 * po/POTFILES.in: Regenerate.
165 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
167 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
168 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
169 (insert_bab, extract_bab, insert_btab, extract_btab,
170 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
171 (BAT, BBA VBA RBS XB6S): Delete macros.
172 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
173 (BB, BD, RBX, XC6): Update for new macros.
174 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
175 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
176 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
177 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
179 2018-05-18 John Darrington <john@darrington.wattle.id.au>
181 * Makefile.am: Add support for s12z architecture.
182 * configure.ac: Likewise.
183 * disassemble.c: Likewise.
184 * disassemble.h: Likewise.
185 * Makefile.in: Regenerate.
186 * configure: Regenerate.
187 * s12z-dis.c: New file.
190 2018-05-18 Alan Modra <amodra@gmail.com>
192 * nfp-dis.c: Don't #include libbfd.h.
193 (init_nfp3200_priv): Use bfd_get_section_contents.
194 (nit_nfp6000_mecsr_sec): Likewise.
196 2018-05-17 Nick Clifton <nickc@redhat.com>
198 * po/zh_CN.po: Updated simplified Chinese translation.
200 2018-05-16 Tamar Christina <tamar.christina@arm.com>
203 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
204 * aarch64-dis-2.c: Regenerate.
206 2018-05-15 Tamar Christina <tamar.christina@arm.com>
209 * aarch64-asm.c (opintl.h): Include.
210 (aarch64_ins_sysreg): Enforce read/write constraints.
211 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
212 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
213 (F_REG_READ, F_REG_WRITE): New.
214 * aarch64-opc.c (aarch64_print_operand): Generate notes for
216 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
217 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
218 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
219 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
220 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
221 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
222 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
223 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
224 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
225 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
226 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
227 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
228 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
229 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
230 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
231 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
232 msr (F_SYS_WRITE), mrs (F_SYS_READ).
234 2018-05-15 Tamar Christina <tamar.christina@arm.com>
237 * aarch64-dis.c (no_notes: New.
238 (parse_aarch64_dis_option): Support notes.
239 (aarch64_decode_insn, print_operands): Likewise.
240 (print_aarch64_disassembler_options): Document notes.
241 * aarch64-opc.c (aarch64_print_operand): Support notes.
243 2018-05-15 Tamar Christina <tamar.christina@arm.com>
246 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
247 and take error struct.
248 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
249 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
250 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
251 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
252 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
253 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
254 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
255 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
256 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
257 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
258 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
259 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
260 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
261 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
262 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
263 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
264 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
265 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
266 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
267 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
268 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
269 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
270 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
271 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
272 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
273 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
274 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
275 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
276 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
277 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
278 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
279 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
280 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
281 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
282 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
283 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
284 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
285 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
286 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
287 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
288 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
289 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
290 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
291 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
292 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
293 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
294 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
295 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
296 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
297 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
298 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
299 (determine_disassembling_preference, aarch64_decode_insn,
300 print_insn_aarch64_word, print_insn_data): Take errors struct.
301 (print_insn_aarch64): Use errors.
302 * aarch64-asm-2.c: Regenerate.
303 * aarch64-dis-2.c: Regenerate.
304 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
305 boolean in aarch64_insert_operan.
306 (print_operand_extractor): Likewise.
307 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
309 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
311 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
313 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
315 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
317 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
319 * cr16-opc.c (cr16_instruction): Comment typo fix.
320 * hppa-dis.c (print_insn_hppa): Likewise.
322 2018-05-08 Jim Wilson <jimw@sifive.com>
324 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
325 (match_c_slli64, match_srxi_as_c_srxi): New.
326 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
327 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
328 <c.slli, c.srli, c.srai>: Use match_s_slli.
329 <c.slli64, c.srli64, c.srai64>: New.
331 2018-05-08 Alan Modra <amodra@gmail.com>
333 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
334 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
335 partition opcode space for index lookup.
337 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
339 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
340 <insn_length>: ...with this. Update usage.
341 Remove duplicate call to *info->memory_error_func.
343 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
344 H.J. Lu <hongjiu.lu@intel.com>
346 * i386-dis.c (Gva): New.
347 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
348 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
349 (prefix_table): New instructions (see prefix above).
350 (mod_table): New instructions (see prefix above).
351 (OP_G): Handle va_mode.
352 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
354 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
355 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
356 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
357 * i386-opc.tbl: Add movidir{i,64b}.
358 * i386-init.h: Regenerated.
359 * i386-tbl.h: Likewise.
361 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
363 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
365 * i386-opc.h (AddrPrefixOp0): Renamed to ...
366 (AddrPrefixOpReg): This.
367 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
368 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
370 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
372 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
373 (vle_num_opcodes): Likewise.
374 (spe2_num_opcodes): Likewise.
375 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
377 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
378 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
381 2018-05-01 Tamar Christina <tamar.christina@arm.com>
383 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
385 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
387 Makefile.am: Added nfp-dis.c.
388 configure.ac: Added bfd_nfp_arch.
389 disassemble.h: Added print_insn_nfp prototype.
390 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
391 nfp-dis.c: New, for NFP support.
392 po/POTFILES.in: Added nfp-dis.c to the list.
393 Makefile.in: Regenerate.
394 configure: Regenerate.
396 2018-04-26 Jan Beulich <jbeulich@suse.com>
398 * i386-opc.tbl: Fold various non-memory operand AVX512VL
399 templates into their base ones.
400 * i386-tlb.h: Re-generate.
402 2018-04-26 Jan Beulich <jbeulich@suse.com>
404 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
405 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
406 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
407 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
408 * i386-init.h: Re-generate.
410 2018-04-26 Jan Beulich <jbeulich@suse.com>
412 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
413 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
414 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
415 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
417 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
419 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
421 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
422 cpuregzmm, and cpuregmask.
423 * i386-init.h: Re-generate.
424 * i386-tbl.h: Re-generate.
426 2018-04-26 Jan Beulich <jbeulich@suse.com>
428 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
429 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
430 * i386-init.h: Re-generate.
432 2018-04-26 Jan Beulich <jbeulich@suse.com>
434 * i386-gen.c (VexImmExt): Delete.
435 * i386-opc.h (VexImmExt, veximmext): Delete.
436 * i386-opc.tbl: Drop all VexImmExt uses.
437 * i386-tlb.h: Re-generate.
439 2018-04-25 Jan Beulich <jbeulich@suse.com>
441 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
443 * i386-tlb.h: Re-generate.
445 2018-04-25 Tamar Christina <tamar.christina@arm.com>
447 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
449 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
451 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
453 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
454 (cpu_flags): Add CpuCLDEMOTE.
455 * i386-init.h: Regenerate.
456 * i386-opc.h (enum): Add CpuCLDEMOTE,
457 (i386_cpu_flags): Add cpucldemote.
458 * i386-opc.tbl: Add cldemote.
459 * i386-tbl.h: Regenerate.
461 2018-04-16 Alan Modra <amodra@gmail.com>
463 * Makefile.am: Remove sh5 and sh64 support.
464 * configure.ac: Likewise.
465 * disassemble.c: Likewise.
466 * disassemble.h: Likewise.
467 * sh-dis.c: Likewise.
468 * sh64-dis.c: Delete.
469 * sh64-opc.c: Delete.
470 * sh64-opc.h: Delete.
471 * Makefile.in: Regenerate.
472 * configure: Regenerate.
473 * po/POTFILES.in: Regenerate.
475 2018-04-16 Alan Modra <amodra@gmail.com>
477 * Makefile.am: Remove w65 support.
478 * configure.ac: Likewise.
479 * disassemble.c: Likewise.
480 * disassemble.h: Likewise.
483 * Makefile.in: Regenerate.
484 * configure: Regenerate.
485 * po/POTFILES.in: Regenerate.
487 2018-04-16 Alan Modra <amodra@gmail.com>
489 * configure.ac: Remove we32k support.
490 * configure: Regenerate.
492 2018-04-16 Alan Modra <amodra@gmail.com>
494 * Makefile.am: Remove m88k support.
495 * configure.ac: Likewise.
496 * disassemble.c: Likewise.
497 * disassemble.h: Likewise.
498 * m88k-dis.c: Delete.
499 * Makefile.in: Regenerate.
500 * configure: Regenerate.
501 * po/POTFILES.in: Regenerate.
503 2018-04-16 Alan Modra <amodra@gmail.com>
505 * Makefile.am: Remove i370 support.
506 * configure.ac: Likewise.
507 * disassemble.c: Likewise.
508 * disassemble.h: Likewise.
509 * i370-dis.c: Delete.
510 * i370-opc.c: Delete.
511 * Makefile.in: Regenerate.
512 * configure: Regenerate.
513 * po/POTFILES.in: Regenerate.
515 2018-04-16 Alan Modra <amodra@gmail.com>
517 * Makefile.am: Remove h8500 support.
518 * configure.ac: Likewise.
519 * disassemble.c: Likewise.
520 * disassemble.h: Likewise.
521 * h8500-dis.c: Delete.
522 * h8500-opc.h: Delete.
523 * Makefile.in: Regenerate.
524 * configure: Regenerate.
525 * po/POTFILES.in: Regenerate.
527 2018-04-16 Alan Modra <amodra@gmail.com>
529 * configure.ac: Remove tahoe support.
530 * configure: Regenerate.
532 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
534 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
536 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
538 * i386-tbl.h: Regenerated.
540 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
542 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
543 PREFIX_MOD_1_0FAE_REG_6.
545 (OP_E_register): Use va_mode.
546 * i386-dis-evex.h (prefix_table):
547 New instructions (see prefixes above).
548 * i386-gen.c (cpu_flag_init): Add WAITPKG.
549 (cpu_flags): Likewise.
550 * i386-opc.h (enum): Likewise.
551 (i386_cpu_flags): Likewise.
552 * i386-opc.tbl: Add umonitor, umwait, tpause.
553 * i386-init.h: Regenerate.
554 * i386-tbl.h: Likewise.
556 2018-04-11 Alan Modra <amodra@gmail.com>
558 * opcodes/i860-dis.c: Delete.
559 * opcodes/i960-dis.c: Delete.
560 * Makefile.am: Remove i860 and i960 support.
561 * configure.ac: Likewise.
562 * disassemble.c: Likewise.
563 * disassemble.h: Likewise.
564 * Makefile.in: Regenerate.
565 * configure: Regenerate.
566 * po/POTFILES.in: Regenerate.
568 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
571 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
573 (print_insn): Clear vex instead of vex.evex.
575 2018-04-04 Nick Clifton <nickc@redhat.com>
577 * po/es.po: Updated Spanish translation.
579 2018-03-28 Jan Beulich <jbeulich@suse.com>
581 * i386-gen.c (opcode_modifiers): Delete VecESize.
582 * i386-opc.h (VecESize): Delete.
583 (struct i386_opcode_modifier): Delete vecesize.
584 * i386-opc.tbl: Drop VecESize.
585 * i386-tlb.h: Re-generate.
587 2018-03-28 Jan Beulich <jbeulich@suse.com>
589 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
590 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
591 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
592 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
593 * i386-tlb.h: Re-generate.
595 2018-03-28 Jan Beulich <jbeulich@suse.com>
597 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
599 * i386-tlb.h: Re-generate.
601 2018-03-28 Jan Beulich <jbeulich@suse.com>
603 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
604 (vex_len_table): Drop Y for vcvt*2si.
605 (putop): Replace plain 'Y' handling by abort().
607 2018-03-28 Nick Clifton <nickc@redhat.com>
610 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
611 instructions with only a base address register.
612 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
613 handle AARHC64_OPND_SVE_ADDR_R.
614 (aarch64_print_operand): Likewise.
615 * aarch64-asm-2.c: Regenerate.
616 * aarch64_dis-2.c: Regenerate.
617 * aarch64-opc-2.c: Regenerate.
619 2018-03-22 Jan Beulich <jbeulich@suse.com>
621 * i386-opc.tbl: Drop VecESize from register only insn forms and
622 memory forms not allowing broadcast.
623 * i386-tlb.h: Re-generate.
625 2018-03-22 Jan Beulich <jbeulich@suse.com>
627 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
628 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
629 sha256*): Drop Disp<N>.
631 2018-03-22 Jan Beulich <jbeulich@suse.com>
633 * i386-dis.c (EbndS, bnd_swap_mode): New.
634 (prefix_table): Use EbndS.
635 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
636 * i386-opc.tbl (bndmov): Move misplaced Load.
637 * i386-tlb.h: Re-generate.
639 2018-03-22 Jan Beulich <jbeulich@suse.com>
641 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
642 templates allowing memory operands and folded ones for register
644 * i386-tlb.h: Re-generate.
646 2018-03-22 Jan Beulich <jbeulich@suse.com>
648 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
649 256-bit templates. Drop redundant leftover Disp<N>.
650 * i386-tlb.h: Re-generate.
652 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
654 * riscv-opc.c (riscv_insn_types): New.
656 2018-03-13 Nick Clifton <nickc@redhat.com>
658 * po/pt_BR.po: Updated Brazilian Portuguese translation.
660 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
662 * i386-opc.tbl: Add Optimize to clr.
663 * i386-tbl.h: Regenerated.
665 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
667 * i386-gen.c (opcode_modifiers): Remove OldGcc.
668 * i386-opc.h (OldGcc): Removed.
669 (i386_opcode_modifier): Remove oldgcc.
670 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
671 instructions for old (<= 2.8.1) versions of gcc.
672 * i386-tbl.h: Regenerated.
674 2018-03-08 Jan Beulich <jbeulich@suse.com>
676 * i386-opc.h (EVEXDYN): New.
677 * i386-opc.tbl: Fold various AVX512VL templates.
678 * i386-tlb.h: Re-generate.
680 2018-03-08 Jan Beulich <jbeulich@suse.com>
682 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
683 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
684 vpexpandd, vpexpandq): Fold AFX512VF templates.
685 * i386-tlb.h: Re-generate.
687 2018-03-08 Jan Beulich <jbeulich@suse.com>
689 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
690 Fold 128- and 256-bit VEX-encoded templates.
691 * i386-tlb.h: Re-generate.
693 2018-03-08 Jan Beulich <jbeulich@suse.com>
695 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
696 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
697 vpexpandd, vpexpandq): Fold AVX512F templates.
698 * i386-tlb.h: Re-generate.
700 2018-03-08 Jan Beulich <jbeulich@suse.com>
702 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
703 64-bit templates. Drop Disp<N>.
704 * i386-tlb.h: Re-generate.
706 2018-03-08 Jan Beulich <jbeulich@suse.com>
708 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
709 and 256-bit templates.
710 * i386-tlb.h: Re-generate.
712 2018-03-08 Jan Beulich <jbeulich@suse.com>
714 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
715 * i386-tlb.h: Re-generate.
717 2018-03-08 Jan Beulich <jbeulich@suse.com>
719 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
721 * i386-tlb.h: Re-generate.
723 2018-03-08 Jan Beulich <jbeulich@suse.com>
725 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
726 * i386-tlb.h: Re-generate.
728 2018-03-08 Jan Beulich <jbeulich@suse.com>
730 * i386-gen.c (opcode_modifiers): Delete FloatD.
731 * i386-opc.h (FloatD): Delete.
732 (struct i386_opcode_modifier): Delete floatd.
733 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
735 * i386-tlb.h: Re-generate.
737 2018-03-08 Jan Beulich <jbeulich@suse.com>
739 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
741 2018-03-08 Jan Beulich <jbeulich@suse.com>
743 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
744 * i386-tlb.h: Re-generate.
746 2018-03-08 Jan Beulich <jbeulich@suse.com>
748 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
750 * i386-tlb.h: Re-generate.
752 2018-03-07 Alan Modra <amodra@gmail.com>
754 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
756 * disassemble.h (print_insn_rs6000): Delete.
757 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
758 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
759 (print_insn_rs6000): Delete.
761 2018-03-03 Alan Modra <amodra@gmail.com>
763 * sysdep.h (opcodes_error_handler): Define.
764 (_bfd_error_handler): Declare.
765 * Makefile.am: Remove stray #.
766 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
768 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
769 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
770 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
771 opcodes_error_handler to print errors. Standardize error messages.
772 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
773 and include opintl.h.
774 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
775 * i386-gen.c: Standardize error messages.
776 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
777 * Makefile.in: Regenerate.
778 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
779 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
780 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
781 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
782 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
783 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
784 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
785 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
786 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
787 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
788 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
789 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
790 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
792 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
794 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
795 vpsub[bwdq] instructions.
796 * i386-tbl.h: Regenerated.
798 2018-03-01 Alan Modra <amodra@gmail.com>
800 * configure.ac (ALL_LINGUAS): Sort.
801 * configure: Regenerate.
803 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
805 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
806 macro by assignements.
808 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
811 * i386-gen.c (opcode_modifiers): Add Optimize.
812 * i386-opc.h (Optimize): New enum.
813 (i386_opcode_modifier): Add optimize.
814 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
815 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
816 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
817 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
818 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
820 * i386-tbl.h: Regenerated.
822 2018-02-26 Alan Modra <amodra@gmail.com>
824 * crx-dis.c (getregliststring): Allocate a large enough buffer
825 to silence false positive gcc8 warning.
827 2018-02-22 Shea Levy <shea@shealevy.com>
829 * disassemble.c (ARCH_riscv): Define if ARCH_all.
831 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
833 * i386-opc.tbl: Add {rex},
834 * i386-tbl.h: Regenerated.
836 2018-02-20 Maciej W. Rozycki <macro@mips.com>
838 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
839 (mips16_opcodes): Replace `M' with `m' for "restore".
841 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
843 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
845 2018-02-13 Maciej W. Rozycki <macro@mips.com>
847 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
848 variable to `function_index'.
850 2018-02-13 Nick Clifton <nickc@redhat.com>
853 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
854 about truncation of printing.
856 2018-02-12 Henry Wong <henry@stuffedcow.net>
858 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
860 2018-02-05 Nick Clifton <nickc@redhat.com>
862 * po/pt_BR.po: Updated Brazilian Portuguese translation.
864 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
866 * i386-dis.c (enum): Add pconfig.
867 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
868 (cpu_flags): Add CpuPCONFIG.
869 * i386-opc.h (enum): Add CpuPCONFIG.
870 (i386_cpu_flags): Add cpupconfig.
871 * i386-opc.tbl: Add PCONFIG instruction.
872 * i386-init.h: Regenerate.
873 * i386-tbl.h: Likewise.
875 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
877 * i386-dis.c (enum): Add PREFIX_0F09.
878 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
879 (cpu_flags): Add CpuWBNOINVD.
880 * i386-opc.h (enum): Add CpuWBNOINVD.
881 (i386_cpu_flags): Add cpuwbnoinvd.
882 * i386-opc.tbl: Add WBNOINVD instruction.
883 * i386-init.h: Regenerate.
884 * i386-tbl.h: Likewise.
886 2018-01-17 Jim Wilson <jimw@sifive.com>
888 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
890 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
892 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
893 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
894 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
895 (cpu_flags): Add CpuIBT, CpuSHSTK.
896 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
897 (i386_cpu_flags): Add cpuibt, cpushstk.
898 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
899 * i386-init.h: Regenerate.
900 * i386-tbl.h: Likewise.
902 2018-01-16 Nick Clifton <nickc@redhat.com>
904 * po/pt_BR.po: Updated Brazilian Portugese translation.
905 * po/de.po: Updated German translation.
907 2018-01-15 Jim Wilson <jimw@sifive.com>
909 * riscv-opc.c (match_c_nop): New.
910 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
912 2018-01-15 Nick Clifton <nickc@redhat.com>
914 * po/uk.po: Updated Ukranian translation.
916 2018-01-13 Nick Clifton <nickc@redhat.com>
918 * po/opcodes.pot: Regenerated.
920 2018-01-13 Nick Clifton <nickc@redhat.com>
922 * configure: Regenerate.
924 2018-01-13 Nick Clifton <nickc@redhat.com>
928 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
930 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
931 * i386-tbl.h: Regenerate.
933 2018-01-10 Jan Beulich <jbeulich@suse.com>
935 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
936 * i386-tbl.h: Re-generate.
938 2018-01-10 Jan Beulich <jbeulich@suse.com>
940 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
941 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
942 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
943 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
944 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
945 Disp8MemShift of AVX512VL forms.
946 * i386-tbl.h: Re-generate.
948 2018-01-09 Jim Wilson <jimw@sifive.com>
950 * riscv-dis.c (maybe_print_address): If base_reg is zero,
951 then the hi_addr value is zero.
953 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
955 * arm-dis.c (arm_opcodes): Add csdb.
956 (thumb32_opcodes): Add csdb.
958 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
960 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
961 * aarch64-asm-2.c: Regenerate.
962 * aarch64-dis-2.c: Regenerate.
963 * aarch64-opc-2.c: Regenerate.
965 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
968 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
969 Remove AVX512 vmovd with 64-bit operands.
970 * i386-tbl.h: Regenerated.
972 2018-01-05 Jim Wilson <jimw@sifive.com>
974 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
977 2018-01-03 Alan Modra <amodra@gmail.com>
979 Update year range in copyright notice of all files.
981 2018-01-02 Jan Beulich <jbeulich@suse.com>
983 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
984 and OPERAND_TYPE_REGZMM entries.
986 For older changes see ChangeLog-2017
988 Copyright (C) 2018 Free Software Foundation, Inc.
990 Copying and distribution of this file, with or without modification,
991 are permitted in any medium without royalty provided the copyright
992 notice and this notice are preserved.
998 version-control: never