opcodes/ChangeLog

   1 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
   2
   3         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
   4         sve_size_013 iclass encode.
   5         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
   6         sve_size_013 iclass decode.
   7
   8 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
   9
  10         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  11         sve_size_bh iclass encode.
  12         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  13         sve_size_bh iclass decode.
  14
  15 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  16
  17         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  18         sve_size_sd2 iclass encode.
  19         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  20         sve_size_sd2 iclass decode.
  21         * aarch64-opc.c (fields): Handle SVE_sz2 field.
  22         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
  23
  24 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  25
  26         * aarch64-asm-2.c: Regenerated.
  27         * aarch64-dis-2.c: Regenerated.
  28         * aarch64-opc-2.c: Regenerated.
  29         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  30         for SVE_ADDR_ZX.
  31         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
  32         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
  33
  34 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  35
  36         * aarch64-asm-2.c: Regenerated.
  37         * aarch64-dis-2.c: Regenerated.
  38         * aarch64-opc-2.c: Regenerated.
  39         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  40         for SVE_Zm3_11_INDEX.
  41         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
  42         (fields): Handle SVE_i3l and SVE_i3h2 fields.
  43         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
  44         fields.
  45         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
  46
  47 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  48
  49         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
  50         sve_size_hsd2 iclass encode.
  51         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
  52         sve_size_hsd2 iclass decode.
  53         * aarch64-opc.c (fields): Handle SVE_size field.
  54         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
  55
  56 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  57
  58         * aarch64-asm-2.c: Regenerated.
  59         * aarch64-dis-2.c: Regenerated.
  60         * aarch64-opc-2.c: Regenerated.
  61         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
  62         for SVE_IMM_ROT3.
  63         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
  64         (fields): Handle SVE_rot3 field.
  65         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
  66         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
  67
  68 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  69
  70         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
  71         instructions.
  72
  73 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
  74
  75         * aarch64-tbl.h
  76         (aarch64_feature_sve2, aarch64_feature_sve2aes,
  77         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
  78         aarch64_feature_sve2bitperm): New feature sets.
  79         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
  80         for feature set addresses.
  81         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
  82         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
  83
  84 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
  85             Faraz Shahbazker  <fshahbazker@wavecomp.com>
  86
  87         * mips-dis.c (mips_calculate_combination_ases): Add ISA
  88         argument and set ASE_EVA_R6 appropriately.
  89         (set_default_mips_dis_options): Pass ISA to above.
  90         (parse_mips_dis_option): Likewise.
  91         * mips-opc.c (EVAR6): New macro.
  92         (mips_builtin_opcodes): Add llwpe, scwpe.
  93
  94 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
  95
  96         * aarch64-asm-2.c: Regenerated.
  97         * aarch64-dis-2.c: Regenerated.
  98         * aarch64-opc-2.c: Regenerated.
  99         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
 100         AARCH64_OPND_TME_UIMM16.
 101         (aarch64_print_operand): Likewise.
 102         * aarch64-tbl.h (QL_IMM_NIL): New.
 103         (TME): New.
 104         (_TME_INSN): New.
 105         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
 106
 107 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
 108
 109         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
 110
 111 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
 112             Faraz Shahbazker  <fshahbazker@wavecomp.com>
 113
 114         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
 115
 116 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 117
 118         * s12z-opc.h: Add extern "C" bracketing to help
 119         users who wish to use this interface in c++ code.
 120
 121 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
 122
 123         * s12z-opc.c (bm_decode): Handle bit map operations with the
 124         "reserved0" mode.
 125
 126 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 127
 128         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
 129         specifier.  Add entries for VLDR and VSTR of system registers.
 130         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
 131         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
 132         of %J and %K format specifier.
 133
 134 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 135
 136         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
 137         Add new entries for VSCCLRM instruction.
 138         (print_insn_coprocessor): Handle new %C format control code.
 139
 140 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 141
 142         * arm-dis.c (enum isa): New enum.
 143         (struct sopcode32): New structure.
 144         (coprocessor_opcodes): change type of entries to struct sopcode32 and
 145         set isa field of all current entries to ANY.
 146         (print_insn_coprocessor): Change type of insn to struct sopcode32.
 147         Only match an entry if its isa field allows the current mode.
 148
 149 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 150
 151         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
 152         CLRM.
 153         (print_insn_thumb32): Add logic to print %n CLRM register list.
 154
 155 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 156
 157         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
 158         and %Q patterns.
 159
 160 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 161
 162         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
 163         (print_insn_thumb32): Edit the switch case for %Z.
 164
 165 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 166
 167         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
 168
 169 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 170
 171         * arm-dis.c (thumb32_opcodes): New instruction bfl.
 172
 173 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 174
 175         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
 176
 177 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 178
 179         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
 180         Arm register with r13 and r15 unpredictable.
 181         (thumb32_opcodes): New instructions for bfx and bflx.
 182
 183 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 184
 185         * arm-dis.c (thumb32_opcodes): New instructions for bf.
 186
 187 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 188
 189         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
 190
 191 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
 192
 193         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
 194
 195 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 196
 197         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
 198
 199 2019-04-12  John Darrington <john@darrington.wattle.id.au>
 200
 201         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
 202         "optr". ("operator" is a reserved word in c++).
 203
 204 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 205
 206         * aarch64-opc.c (aarch64_print_operand): Add case for
 207         AARCH64_OPND_Rt_SP.
 208         (verify_constraints): Likewise.
 209         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
 210         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
 211         to accept Rt|SP as first operand.
 212         (AARCH64_OPERANDS): Add new Rt_SP.
 213         * aarch64-asm-2.c: Regenerated.
 214         * aarch64-dis-2.c: Regenerated.
 215         * aarch64-opc-2.c: Regenerated.
 216
 217 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
 218
 219         * aarch64-asm-2.c: Regenerated.
 220         * aarch64-dis-2.c: Likewise.
 221         * aarch64-opc-2.c: Likewise.
 222         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
 223
 224 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
 225
 226         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
 227
 228 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
 229
 230         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
 231         * i386-init.h: Regenerated.
 232
 233 2019-04-07  Alan Modra  <amodra@gmail.com>
 234
 235         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
 236         op_separator to control printing of spaces, comma and parens
 237         rather than need_comma, need_paren and spaces vars.
 238
 239 2019-04-07  Alan Modra  <amodra@gmail.com>
 240
 241         PR 24421
 242         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
 243         (print_insn_neon, print_insn_arm): Likewise.
 244
 245 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
 246
 247         * i386-dis-evex.h (evex_table): Updated to support BF16
 248         instructions.
 249         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
 250         and EVEX_W_0F3872_P_3.
 251         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
 252         (cpu_flags): Add bitfield for CpuAVX512_BF16.
 253         * i386-opc.h (enum): Add CpuAVX512_BF16.
 254         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
 255         * i386-opc.tbl: Add AVX512 BF16 instructions.
 256         * i386-init.h: Regenerated.
 257         * i386-tbl.h: Likewise.
 258
 259 2019-04-05  Alan Modra  <amodra@gmail.com>
 260
 261         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
 262         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
 263         to favour printing of "-" branch hint when using the "y" bit.
 264         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
 265
 266 2019-04-05  Alan Modra  <amodra@gmail.com>
 267
 268         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
 269         opcode until first operand is output.
 270
 271 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
 272
 273         PR gas/24349
 274         * ppc-opc.c (valid_bo_pre_v2): Add comments.
 275         (valid_bo_post_v2): Add support for 'at' branch hints.
 276         (insert_bo): Only error on branch on ctr.
 277         (get_bo_hint_mask): New function.
 278         (insert_boe): Add new 'branch_taken' formal argument.  Add support
 279         for inserting 'at' branch hints.
 280         (extract_boe): Add new 'branch_taken' formal argument.  Add support
 281         for extracting 'at' branch hints.
 282         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
 283         (BOE): Delete operand.
 284         (BOM, BOP): New operands.
 285         (RM): Update value.
 286         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
 287         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
 288         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
 289         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
 290         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
 291         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
 292         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
 293         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
 294         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
 295         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
 296         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
 297         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
 298         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
 299         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
 300         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
 301         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
 302         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
 303         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
 304         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
 305         bttarl+>: New extended mnemonics.
 306
 307 2019-03-28  Alan Modra  <amodra@gmail.com>
 308
 309         PR 24390
 310         * ppc-opc.c (BTF): Define.
 311         (powerpc_opcodes): Use for mtfsb*.
 312         * ppc-dis.c (print_insn_powerpc): Print fields with both
 313         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
 314
 315 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 316
 317         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
 318         (mapping_symbol_for_insn): Implement new algorithm.
 319         (print_insn): Remove duplicate code.
 320
 321 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 322
 323         * aarch64-dis.c (print_insn_aarch64):
 324         Implement override.
 325
 326 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 327
 328         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
 329         order.
 330
 331 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
 332
 333         * aarch64-dis.c (last_stop_offset): New.
 334         (print_insn_aarch64): Use stop_offset.
 335
 336 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
 337
 338         PR gas/24359
 339         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
 340         CPU_ANY_AVX2_FLAGS.
 341         * i386-init.h: Regenerated.
 342
 343 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
 344
 345         PR gas/24348
 346         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
 347         vmovdqu16, vmovdqu32 and vmovdqu64.
 348         * i386-tbl.h: Regenerated.
 349
 350 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 351
 352         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
 353         from vstrszb, vstrszh, and vstrszf.
 354
 355 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
 356
 357         * s390-opc.txt: Add instruction descriptions.
 358
 359 2019-02-08  Jim Wilson  <jimw@sifive.com>
 360
 361         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
 362         <bne>: Likewise.
 363
 364 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 365
 366         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
 367
 368 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
 369
 370         PR binutils/23212
 371         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
 372         * aarch64-opc.c (verify_elem_sd): New.
 373         (fields): Add FLD_sz entr.
 374         * aarch64-tbl.h (_SIMD_INSN): New.
 375         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
 376         fmulx scalar and vector by element isns.
 377
 378 2019-02-07  Nick Clifton  <nickc@redhat.com>
 379
 380         * po/sv.po: Updated Swedish translation.
 381
 382 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
 383
 384         * s390-mkopc.c (main): Accept arch13 as cpu string.
 385         * s390-opc.c: Add new instruction formats and instruction opcode
 386         masks.
 387         * s390-opc.txt: Add new arch13 instructions.
 388
 389 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 390
 391         * aarch64-tbl.h (QL_LDST_AT): Update macro.
 392         (aarch64_opcode): Change encoding for stg, stzg
 393         st2g and st2zg.
 394         * aarch64-asm-2.c: Regenerated.
 395         * aarch64-dis-2.c: Regenerated.
 396         * aarch64-opc-2.c: Regenerated.
 397
 398 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 399
 400         * aarch64-asm-2.c: Regenerated.
 401         * aarch64-dis-2.c: Likewise.
 402         * aarch64-opc-2.c: Likewise.
 403         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
 404
 405 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
 406             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
 407
 408         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
 409         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
 410         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
 411         * aarch64-dis.h (ext_addr_simple_2): Likewise.
 412         * aarch64-opc.c (operand_general_constraint_met_p): Remove
 413         case for ldstgv_indexed.
 414         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
 415         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
 416         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
 417         * aarch64-asm-2.c: Regenerated.
 418         * aarch64-dis-2.c: Regenerated.
 419         * aarch64-opc-2.c: Regenerated.
 420
 421 2019-01-23  Nick Clifton  <nickc@redhat.com>
 422
 423         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 424
 425 2019-01-21  Nick Clifton  <nickc@redhat.com>
 426
 427         * po/de.po: Updated German translation.
 428         * po/uk.po: Updated Ukranian translation.
 429
 430 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
 431         * mips-dis.c (mips_arch_choices): Fix typo in
 432         gs464, gs464e and gs264e descriptors.
 433
 434 2019-01-19  Nick Clifton  <nickc@redhat.com>
 435
 436         * configure: Regenerate.
 437         * po/opcodes.pot: Regenerate.
 438
 439 2018-06-24  Nick Clifton  <nickc@redhat.com>
 440
 441         2.32 branch created.
 442
 443 2019-01-09  John Darrington <john@darrington.wattle.id.au>
 444
 445         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
 446         if it is null.
 447         -dis.c (opr_emit_disassembly): Do not omit an index if it is
 448         zero.
 449
 450 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
 451
 452         * configure: Regenerate.
 453
 454 2019-01-07  Alan Modra  <amodra@gmail.com>
 455
 456         * configure: Regenerate.
 457         * po/POTFILES.in: Regenerate.
 458
 459 2019-01-03  John Darrington <john@darrington.wattle.id.au>
 460
 461         * s12z-opc.c: New file.
 462         * s12z-opc.h: New file.
 463         * s12z-dis.c: Removed all code not directly related to display
 464         of instructions.  Used the interface provided by the new files
 465         instead.
 466         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
 467         * Makefile.in: Regenerate.
 468         * configure.ac (bfd_s12z_arch): Correct the dependencies.
 469         * configure: Regenerate.
 470
 471 2019-01-01  Alan Modra  <amodra@gmail.com>
 472
 473         Update year range in copyright notice of all files.
 474
 475 For older changes see ChangeLog-2018
 476 \f
 477 Copyright (C) 2019 Free Software Foundation, Inc.
 478
 479 Copying and distribution of this file, with or without modification,
 480 are permitted in any medium without royalty provided the copyright
 481 notice and this notice are preserved.
 482
 483 Local Variables:
 484 mode: change-log
 485 left-margin: 8
 486 fill-column: 74
 487 version-control: never
 488 End: