opcodes/ChangeLog

   1 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
   2
   3         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
   4         DC instruction.
   5
   6 2021-04-19  Jan Beulich  <jbeulich@suse.com>
   7
   8         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
   9         "qualifier".
  10         (convert_mov_to_movewide): Add initializer for "value".
  11
  12 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  13
  14         * aarch64-opc.c: Add RME system registers.
  15
  16 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  17
  18         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  19         "addi d,CV,z" to "c.mv d,CV".
  20
  21 2021-04-12  Alan Modra  <amodra@gmail.com>
  22
  23         * configure.ac (--enable-checking): Add support.
  24         * config.in: Regenerate.
  25         * configure: Regenerate.
  26
  27 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
  28
  29         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
  30         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
  31
  32 2021-04-09  Alan Modra  <amodra@gmail.com>
  33
  34         * ppc-dis.c (struct dis_private): Add "special".
  35         (POWERPC_DIALECT): Delete.  Replace uses with..
  36         (private_data): ..this.  New inline function.
  37         (disassemble_init_powerpc): Init "special" names.
  38         (skip_optional_operands): Add is_pcrel arg, set when detecting R
  39         field of prefix instructions.
  40         (bsearch_reloc, print_got_plt): New functions.
  41         (print_insn_powerpc): For pcrel instructions, print target address
  42         and symbol if known, and decode plt and got loads too.
  43
  44 2021-04-08  Alan Modra  <amodra@gmail.com>
  45
  46         PR 27684
  47         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
  48
  49 2021-04-08  Alan Modra  <amodra@gmail.com>
  50
  51         PR 27676
  52         * ppc-opc.c (DCBT_EO): Move earlier.
  53         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
  54         (powerpc_operands): Add THCT and THDS entries.
  55         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
  56
  57 2021-04-06  Alan Modra  <amodra@gmail.com>
  58
  59         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
  60         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
  61         symbol_at_address_func.
  62
  63 2021-04-05  Alan Modra  <amodra@gmail.com>
  64
  65         * configure.ac: Don't check for limits.h, string.h, strings.h or
  66         stdlib.h.
  67         (AC_ISC_POSIX): Don't invoke.
  68         * sysdep.h: Include stdlib.h and string.h unconditionally.
  69         * i386-opc.h: Include limits.h unconditionally.
  70         * wasm32-dis.c: Likewise.
  71         * cgen-opc.c: Don't include alloca-conf.h.
  72         * config.in: Regenerate.
  73         * configure: Regenerate.
  74
  75 2021-04-01  Martin Liska  <mliska@suse.cz>
  76
  77         * arm-dis.c (strneq): Remove strneq and use startswith.
  78         * cr16-dis.c (print_insn_cr16): Likewise.
  79         * score-dis.c (streq): Likewise.
  80         (strneq): Likewise.
  81         * score7-dis.c (strneq): Likewise.
  82
  83 2021-04-01  Alan Modra  <amodra@gmail.com>
  84
  85         PR 27675
  86         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
  87
  88 2021-03-31  Alan Modra  <amodra@gmail.com>
  89
  90         * sysdep.h (POISON_BFD_BOOLEAN): Define.
  91         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
  92         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
  93         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
  94         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
  95         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
  96         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
  97         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
  98         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
  99         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 100         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 101         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 102         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 103         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 104         and TRUE with true throughout.
 105
 106 2021-03-31  Alan Modra  <amodra@gmail.com>
 107
 108         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 109         * aarch64-dis.h: Likewise.
 110         * aarch64-opc.c: Likewise.
 111         * avr-dis.c: Likewise.
 112         * csky-dis.c: Likewise.
 113         * nds32-asm.c: Likewise.
 114         * nds32-dis.c: Likewise.
 115         * nfp-dis.c: Likewise.
 116         * riscv-dis.c: Likewise.
 117         * s12z-dis.c: Likewise.
 118         * wasm32-dis.c: Likewise.
 119
 120 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 121
 122         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 123         (i386_seg_prefixes): New.
 124         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 125         (i386_seg_prefixes): Declare.
 126
 127 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 128
 129         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 130
 131 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 132
 133         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 134         * i386-reg.tbl (st): Move down.
 135         (st(0)): Delete. Extend comment.
 136         * i386-tbl.h: Re-generate.
 137
 138 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 139
 140         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 141         (cmpsd): Move next to cmps.
 142         (movsd): Move next to movs.
 143         (cmpxchg16b): Move to separate section.
 144         (fisttp, fisttpll): Likewise.
 145         (monitor, mwait): Likewise.
 146         * i386-tbl.h: Re-generate.
 147
 148 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 151         (vpsadbw): Add C.
 152         * i386-tbl.h: Re-generate.
 153
 154 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 157         pclmul, gfni): New templates. Use them wherever possible. Move
 158         SSE4.1 pextrw into respective section.
 159         * i386-tbl.h: Re-generate.
 160
 161 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 164         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 165         "length".
 166         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 167         Convert all of their uses to representation in opcode.
 168
 169 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 170
 171         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 172         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 173         value of None. Shrink operands to 3 bits.
 174
 175 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 176
 177         * i386-gen.c (process_i386_opcode_modifier): New parameter
 178         "space".
 179         (output_i386_opcode): New local variable "space". Adjust
 180         process_i386_opcode_modifier() invocation.
 181         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 182         invocation.
 183         * i386-tbl.h: Re-generate.
 184
 185 2021-03-29  Alan Modra  <amodra@gmail.com>
 186
 187         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 188         (fp_qualifier_p, get_data_pattern): Likewise.
 189         (aarch64_get_operand_modifier_from_value): Likewise.
 190         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 191         (operand_variant_qualifier_p): Likewise.
 192         (qualifier_value_in_range_constraint_p): Likewise.
 193         (aarch64_get_qualifier_esize): Likewise.
 194         (aarch64_get_qualifier_nelem): Likewise.
 195         (aarch64_get_qualifier_standard_value): Likewise.
 196         (get_lower_bound, get_upper_bound): Likewise.
 197         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 198         (aarch64_print_operand): Likewise.
 199         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 200         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 201         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 202         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 203         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 204         (print_insn_tic6x): Likewise.
 205
 206 2021-03-29  Alan Modra  <amodra@gmail.com>
 207
 208         * arc-dis.c (extract_operand_value): Correct NULL cast.
 209         * frv-opc.h: Regenerate.
 210
 211 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 212
 213         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 214         MMX form.
 215         * i386-tbl.h: Re-generate.
 216
 217 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 218
 219         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 220         immediate in br.n instruction.
 221
 222 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 223
 224         * i386-dis.c (XMGatherD, VexGatherD): New.
 225         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 226         (print_insn): Check masking for S/G insns.
 227         (OP_E_memory): New local variable check_gather. Extend mandatory
 228         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 229         Extend check for disallowed 16-bit addressing.
 230         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 231         if()s to switch(). Check register conflicts for (VEX-encoded)
 232         gathers. Drop no longer reachable cases.
 233         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 234         vgatherdp*.
 235
 236 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 237
 238         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 239         zeroing-masking without masking.
 240
 241 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 242
 243         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 244         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 245         single-operand forms as deprecated.
 246         * i386-tbl.h: Re-generate.
 247
 248 2021-03-25  Alan Modra  <amodra@gmail.com>
 249
 250         PR 27647
 251         * ppc-opc.c (XLOCB_MASK): Delete.
 252         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 253         XLBH_MASK.
 254         (powerpc_opcodes): Accept a BH field on all extended forms of
 255         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 256
 257 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 258
 259         * i386-gen.c (output_i386_opcode): Drop processing of
 260         opcode_length. Calculate length from base_opcode. Adjust prefix
 261         encoding determination.
 262         (process_i386_opcodes): Drop output of fake opcode_length.
 263         * i386-opc.h (struct insn_template): Drop opcode_length field.
 264         * i386-opc.tbl: Drop opcode length field from all templates.
 265         * i386-tbl.h: Re-generate.
 266
 267 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 270         parameter "prefix". Drop local variable "regular_encoding".
 271         Record prefix setting / check for consistency.
 272         (output_i386_opcode): Parse opcode_length and base_opcode
 273         earlier. Derive prefix encoding. Drop no longer applicable
 274         consistency checking. Adjust process_i386_opcode_modifier()
 275         invocation.
 276         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 277         invocation.
 278         * i386-tbl.h: Re-generate.
 279
 280 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 281
 282         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 283         check.
 284         * i386-opc.h (Prefix_*): Move #define-s.
 285         * i386-opc.tbl: Move pseudo prefix enumerator values to
 286         extension opcode field. Introduce pseudopfx template.
 287         * i386-tbl.h: Re-generate.
 288
 289 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 290
 291         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 292         comment.
 293         * i386-tbl.h: Re-generate.
 294
 295 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 296
 297         * i386-opc.h (struct insn_template): Move cpu_flags field past
 298         opcode_modifier one.
 299         * i386-tbl.h: Re-generate.
 300
 301 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 302
 303         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 304         * i386-opc.h (OpcodeSpace): New enumerator.
 305         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 306         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 307         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 308         (struct i386_opcode_modifier): New field opcodespace. Shrink
 309         opcodeprefix field.
 310         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 311         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 312         OpcodePrefix uses.
 313         * i386-tbl.h: Re-generate.
 314
 315 2021-03-22  Martin Liska  <mliska@suse.cz>
 316
 317         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 318         * arc-dis.c (parse_option): Likewise.
 319         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 320         * cris-dis.c (print_with_operands): Likewise.
 321         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 322         * i386-dis.c (print_insn): Likewise.
 323         * ia64-gen.c (fetch_insn_class): Likewise.
 324         (parse_resource_users): Likewise.
 325         (in_iclass): Likewise.
 326         (lookup_specifier): Likewise.
 327         (insert_opcode_dependencies): Likewise.
 328         * mips-dis.c (parse_mips_ase_option): Likewise.
 329         (parse_mips_dis_option): Likewise.
 330         * s390-dis.c (disassemble_init_s390): Likewise.
 331         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 332
 333 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 334
 335         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 336
 337 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 338
 339         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 340         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 341
 342 2021-03-12  Alan Modra  <amodra@gmail.com>
 343
 344         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 345
 346 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 347
 348         * i386-dis.c (OP_XMM): Re-order checks.
 349
 350 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 351
 352         * i386-dis.c (putop): Drop need_vex check when also checking
 353         vex.evex.
 354         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 355         checking vex.b.
 356
 357 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 358
 359         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 360         checks. Move case label past broadcast check.
 361
 362 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 363
 364         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 365         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 366         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 367         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 368         EVEX_W_0F38C7_M_0_L_2): Delete.
 369         (REG_EVEX_0F38C7_M_0_L_2): New.
 370         (intel_operand_size): Handle VEX and EVEX the same for
 371         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 372         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 373         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 374         vex_vsib_q_w_d_mode uses.
 375         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 376         0F38A1, and 0F38A3 entries.
 377         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 378         entry.
 379         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 380         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 381         0F38A3 entries.
 382
 383 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 384
 385         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 386         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 387         MOD_VEX_0FXOP_09_12): Rename to ...
 388         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 389         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 390         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 391         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 392         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 393         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 394         (reg_table): Adjust comments.
 395         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 396         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 397         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 398         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 399         (vex_len_table): Adjust opcode 0A_12 entry.
 400         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 401         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 402         (rm_table): Move hreset entry.
 403
 404 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 405
 406         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 407         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 408         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 409         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 410         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 411         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 412         (get_valid_dis386): Also handle 512-bit vector length when
 413         vectoring into vex_len_table[].
 414         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 415         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 416         entries.
 417         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 418         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 419         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 420         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 421         entries.
 422
 423 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 424
 425         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 426         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 427         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 428         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 429         entries.
 430         * i386-dis-evex-len.h (evex_len_table): Likewise.
 431         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 432
 433 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 434
 435         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 436         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 437         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 438         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 439         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 440         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 441         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 442         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 443         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 444         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 445         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 446         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 447         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 448         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 449         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 450         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 451         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 452         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 453         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 454         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 455         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 456         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 457         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 458         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 459         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 460         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 461         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 462         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 463         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 464         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 465         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 466         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 467         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 468         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 469         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 470         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 471         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 472         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 473         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 474         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 475         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 476         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 477         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 478         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 479         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 480         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 481         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 482         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 483         EVEX_W_0F3A43_L_n): New.
 484         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 485         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 486         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 487         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 488         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 489         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 490         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 491         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 492         0F385B, 0F38C6, and 0F38C7 entries.
 493         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 494         0F38C6 and 0F38C7.
 495         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 496         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 497         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 498         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 499
 500 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 501
 502         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 503         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 504         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 505         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 506         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 507         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 508         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 509         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 510         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 511         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 512         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 513         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 514         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 515         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 516         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 517         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 518         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 519         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 520         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 521         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 522         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 523         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 524         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 525         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 526         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 527         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 528         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 529         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 530         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 531         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 532         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 533         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 534         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 535         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 536         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 537         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 538         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 539         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 540         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 541         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 542         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 543         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 544         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 545         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 546         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 547         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 548         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 549         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 550         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 551         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 552         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 553         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 554         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 555         VEX_W_0F99_P_2_LEN_0): Delete.
 556         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 557         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 558         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 559         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 560         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 561         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 562         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 563         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 564         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 565         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 566         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 567         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 568         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 569         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 570         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 571         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 572         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 573         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 574         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 575         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 576         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 577         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 578         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 579         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 580         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 581         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 582         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 583         (prefix_table): No longer link to vex_len_table[] for opcodes
 584         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 585         0F92, 0F93, 0F98, and 0F99.
 586         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 587         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 588         0F98, and 0F99.
 589         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 590         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 591         0F98, and 0F99.
 592         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 593         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 594         0F98, and 0F99.
 595         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 596         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 597         0F98, and 0F99.
 598
 599 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 600
 601         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 602         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 603         REG_VEX_0F73_M_0 respectively.
 604         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 605         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 606         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 607         MOD_VEX_0F73_REG_7): Delete.
 608         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 609         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 610         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 611         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 612         PREFIX_VEX_0F3AF0_L_0 respectively.
 613         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 614         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 615         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 616         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 617         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 618         VEX_LEN_0F38F7): New.
 619         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 620         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 621         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 622         0F38F3.
 623         (prefix_table): No longer link to vex_len_table[] for opcodes
 624         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 625         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 626         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 627         0F38F6, 0F38F7, and 0F3AF0.
 628         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 629         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 630         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 631         0F73.
 632
 633 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 634
 635         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 636         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 637         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 638         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 639         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 640         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 641         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 642         73.
 643         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 644         0F72, and 0F73.
 645         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 646         0F73.
 647
 648 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 649
 650         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 651         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 652         (reg_table): Don't link to mod_table[] where not needed. Add
 653         PREFIX_IGNORED to nop entries.
 654         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 655         (mod_table): Add nop entries next to prefetch ones. Drop
 656         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 657         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 658         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 659         PREFIX_OPCODE from endbr* entries.
 660         (get_valid_dis386): Also consider entry's name when zapping
 661         vindex.
 662         (print_insn): Handle PREFIX_IGNORED.
 663
 664 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 665
 666         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 667         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 668         element.
 669         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 670         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 671         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 672         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 673         (struct i386_opcode_modifier): Delete notrackprefixok,
 674         islockable, hleprefixok, and repprefixok fields. Add prefixok
 675         field.
 676         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 677         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 678         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 679         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 680         Replace HLEPrefixOk.
 681         * opcodes/i386-tbl.h: Re-generate.
 682
 683 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 684
 685         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 686         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 687         64-bit form.
 688         * opcodes/i386-tbl.h: Re-generate.
 689
 690 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 691
 692         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 693         for {} instead of {0}. Don't look for '0'.
 694         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 695         size specifiers.
 696
 697 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 698
 699         PR 27158
 700         * riscv-dis.c (print_insn_args): Updated encoding macros.
 701         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 702         (match_c_addi16sp): Updated encoding macros.
 703         (match_c_lui): Likewise.
 704         (match_c_lui_with_hint): Likewise.
 705         (match_c_addi4spn): Likewise.
 706         (match_c_slli): Likewise.
 707         (match_slli_as_c_slli): Likewise.
 708         (match_c_slli64): Likewise.
 709         (match_srxi_as_c_srxi): Likewise.
 710         (riscv_insn_types): Added .insn css/cl/cs.
 711
 712 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 713
 714         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 715         (default_priv_spec): Updated type to riscv_spec_class.
 716         (parse_riscv_dis_option): Updated.
 717         * riscv-opc.c: Moved stuff and make the file tidy.
 718
 719 2021-02-17  Alan Modra  <amodra@gmail.com>
 720
 721         * wasm32-dis.c: Include limits.h.
 722         (CHAR_BIT): Provide backup define.
 723         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 724         Correct signed overflow checking.
 725
 726 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 727
 728         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 729         * i386-tbl.h: Re-generate.
 730
 731 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 732
 733         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 734         Oword.
 735         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 736
 737 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 738
 739         * s390-mkopc.c (main): Accept arch14 as cpu string.
 740         * s390-opc.txt: Add new arch14 instructions.
 741
 742 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 743
 744         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 745         favour of LIBINTL.
 746         * configure: Regenerated.
 747
 748 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 749
 750         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 751         * tic54x-opc.c (regs): Rename to ...
 752         (tic54x_regs): ... this.
 753         (mmregs): Rename to ...
 754         (tic54x_mmregs): ... this.
 755         (condition_codes): Rename to ...
 756         (tic54x_condition_codes): ... this.
 757         (cc2_codes): Rename to ...
 758         (tic54x_cc2_codes): ... this.
 759         (cc3_codes): Rename to ...
 760         (tic54x_cc3_codes): ... this.
 761         (status_bits): Rename to ...
 762         (tic54x_status_bits): ... this.
 763         (misc_symbols): Rename to ...
 764         (tic54x_misc_symbols): ... this.
 765
 766 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 767
 768         * riscv-opc.c (MASK_RVB_IMM): Removed.
 769         (riscv_opcodes): Removed zb* instructions.
 770         (riscv_ext_version_table): Removed versions for zb*.
 771
 772 2021-01-26  Alan Modra  <amodra@gmail.com>
 773
 774         * i386-gen.c (parse_template): Ensure entire template_instance
 775         is initialised.
 776
 777 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 778
 779         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 780         (riscv_fpr_names_abi): Likewise.
 781         (riscv_opcodes): Likewise.
 782         (riscv_insn_types): Likewise.
 783
 784 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 785
 786         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 787
 788 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 789
 790         * riscv-dis.c: Comments tidy and improvement.
 791         * riscv-opc.c: Likewise.
 792
 793 2021-01-13  Alan Modra  <amodra@gmail.com>
 794
 795         * Makefile.in: Regenerate.
 796
 797 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 798
 799         PR binutils/26792
 800         * configure.ac: Use GNU_MAKE_JOBSERVER.
 801         * aclocal.m4: Regenerated.
 802         * configure: Likewise.
 803
 804 2021-01-12  Nick Clifton  <nickc@redhat.com>
 805
 806         * po/sr.po: Updated Serbian translation.
 807
 808 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 809
 810         PR ld/27173
 811         * configure: Regenerated.
 812
 813 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 814
 815         * aarch64-asm-2.c: Regenerate.
 816         * aarch64-dis-2.c: Likewise.
 817         * aarch64-opc-2.c: Likewise.
 818         * aarch64-opc.c (aarch64_print_operand):
 819         Delete handling of AARCH64_OPND_CSRE_CSR.
 820         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 821         (CSRE): Likewise.
 822         (_CSRE_INSN): Likewise.
 823         (aarch64_opcode_table): Delete csr.
 824
 825 2021-01-11  Nick Clifton  <nickc@redhat.com>
 826
 827         * po/de.po: Updated German translation.
 828         * po/fr.po: Updated French translation.
 829         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 830         * po/sv.po: Updated Swedish translation.
 831         * po/uk.po: Updated Ukranian translation.
 832
 833 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 834
 835         * configure: Regenerated.
 836
 837 2021-01-09  Nick Clifton  <nickc@redhat.com>
 838
 839         * configure: Regenerate.
 840         * po/opcodes.pot: Regenerate.
 841
 842 2021-01-09  Nick Clifton  <nickc@redhat.com>
 843
 844         * 2.36 release branch crated.
 845
 846 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 847
 848         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 849         (DW, (XRC_MASK): Define.
 850         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 851
 852 2021-01-09  Alan Modra  <amodra@gmail.com>
 853
 854         * configure: Regenerate.
 855
 856 2021-01-08  Nick Clifton  <nickc@redhat.com>
 857
 858         * po/sv.po: Updated Swedish translation.
 859
 860 2021-01-08  Nick Clifton  <nickc@redhat.com>
 861
 862         PR 27129
 863         * aarch64-dis.c (determine_disassembling_preference): Move call to
 864         aarch64_match_operands_constraint outside of the assertion.
 865         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 866         Replace with a return of FALSE.
 867
 868         PR 27139
 869         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 870         core system register.
 871
 872 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 873
 874         * configure: Regenerate.
 875
 876 2021-01-07  Nick Clifton  <nickc@redhat.com>
 877
 878         * po/fr.po: Updated French translation.
 879
 880 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 881
 882         * m68k-opc.c (chkl): Change minimum architecture requirement to
 883         m68020.
 884
 885 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 886
 887         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 888
 889 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 890             Jim Wilson  <jimw@sifive.com>
 891             Andrew Waterman  <andrew@sifive.com>
 892             Maxim Blinov  <maxim.blinov@embecosm.com>
 893             Kito Cheng  <kito.cheng@sifive.com>
 894             Nelson Chu  <nelson.chu@sifive.com>
 895
 896         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 897         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 898
 899 2021-01-01  Alan Modra  <amodra@gmail.com>
 900
 901         Update year range in copyright notice of all files.
 902
 903 For older changes see ChangeLog-2020
 904 \f
 905 Copyright (C) 2021 Free Software Foundation, Inc.
 906
 907 Copying and distribution of this file, with or without modification,
 908 are permitted in any medium without royalty provided the copyright
 909 notice and this notice are preserved.
 910
 911 Local Variables:
 912 mode: change-log
 913 left-margin: 8
 914 fill-column: 74
 915 version-control: never
 916 End: