opcodes/ChangeLog

   1 2004-06-26  Alan Modra  <amodra@bigpond.net.au>
   2
   3         * ppc-opc.c (BH, XLBH_MASK): Define.
   4         (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
   5
   6 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
   7
   8         * i386-dis.c (x_mode): Comment.
   9         (two_source_ops): File scope.
  10         (float_mem): Correct fisttpll and fistpll.
  11         (float_mem_mode): New table.
  12         (dofloat): Use it.
  13         (OP_E): Correct intel mode PTR output.
  14         (ptr_reg): Use open_char and close_char.
  15         (PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
  16         operands.  Set two_source_ops.
  17
  18 2004-06-15  Alan Modra  <amodra@bigpond.net.au>
  19
  20         * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
  21         instead of _raw_size.
  22
  23 2004-06-08  Jakub Jelinek  <jakub@redhat.com>
  24
  25         * ia64-gen.c (in_iclass): Handle more postinc st
  26         and ld variants.
  27         * ia64-asmtab.c: Rebuilt.
  28
  29 2004-06-01  Martin Schwidefsky  <schwidefsky@de.ibm.com>
  30
  31         * s390-opc.txt: Correct architecture mask for some opcodes.
  32         lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
  33         in the esa mode as well.
  34
  35 2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
  36
  37         * sh-dis.c (target_arch): Make unsigned.
  38         (print_insn_sh): Replace (most of) switch with a call to
  39         sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
  40         * sh-opc.h: Redefine architecture flags values.
  41         Add sh3-nommu architecture.
  42         Reorganise <arch>_up macros so they make more visual sense.
  43         (SH_MERGE_ARCH_SET): Define new macro.
  44         (SH_VALID_BASE_ARCH_SET): Likewise.
  45         (SH_VALID_MMU_ARCH_SET): Likewise.
  46         (SH_VALID_CO_ARCH_SET): Likewise.
  47         (SH_VALID_ARCH_SET): Likewise.
  48         (SH_MERGE_ARCH_SET_VALID): Likewise.
  49         (SH_ARCH_SET_HAS_FPU): Likewise.
  50         (SH_ARCH_SET_HAS_DSP): Likewise.
  51         (SH_ARCH_UNKNOWN_ARCH): Likewise.
  52         (sh_get_arch_from_bfd_mach): Add prototype.
  53         (sh_get_arch_up_from_bfd_mach): Likewise.
  54         (sh_get_bfd_mach_from_arch_set): Likewise.
  55         (sh_merge_bfd_arc): Likewise.
  56
  57 2004-05-24  Peter Barada  <peter@the-baradas.com>
  58
  59         * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
  60         into new match_insn_m68k function.  Loop over canidate
  61         matches and select first that completely matches.
  62         * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
  63         * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
  64         to verify addressing for MAC/EMAC.
  65         * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
  66         reigster halves since 'fpu' and 'spl' look misleading.
  67         * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
  68         * m68k-opc.c: Rearragne mac/emac cases to use longest for
  69         first, tighten up match masks.
  70         * m68k-opc.c: Add 'size' field to struct m68k_opcode.  Produce
  71         'size' from special case code in print_insn_m68k to
  72         determine decode size of insns.
  73
  74 2004-05-19  Alan Modra  <amodra@bigpond.net.au>
  75
  76         * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
  77         well as when -mpower4.
  78
  79 2004-05-13  Nick Clifton  <nickc@redhat.com>
  80
  81         * po/fr.po: Updated French translation.
  82
  83 2004-05-05  Peter Barada  <peter@the-baradas.com>
  84
  85         * m68k-dis.c(print_insn_m68k): Add new chips, use core
  86         variants in arch_mask.  Only set m68881/68851 for 68k chips.
  87         * m68k-op.c: Switch from ColdFire chips to core variants.
  88
  89 2004-05-05  Alan Modra  <amodra@bigpond.net.au>
  90
  91         PR 147.
  92         * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
  93
  94 2004-04-29  Ben Elliston  <bje@au.ibm.com>
  95
  96         * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
  97         (powerpc_opcodes): Add "dbczl" instruction for PPC970.
  98
  99 2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
 100
 101         * sh-dis.c (print_insn_sh): Print the value in constant pool
 102         as a symbol if it looks like a symbol.
 103
 104 2004-04-22  Peter Barada <peter@the-baradas.com>
 105
 106         * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
 107         appropriate ColdFire architectures.
 108         (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
 109         mask addressing.
 110         Add EMAC instructions, fix MAC instructions. Remove
 111         macmw/macml/msacmw/msacml instructions since mask addressing now
 112         supported.
 113
 114 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 115
 116         * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
 117         (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
 118         suffix.  Use fmov*x macros, create all 3 fpsize variants in one
 119         macro.  Adjust all users.
 120
 121 2004-04-15  Anil Paranjpe  <anilp1@kpitcummins.com>
 122
 123         * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
 124         separately.
 125
 126 2004-03-30  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
 127
 128         * m32r-asm.c: Regenerate.
 129
 130 2004-03-29  Stan Shebs  <shebs@apple.com>
 131
 132         * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
 133         used.
 134
 135 2004-03-19  Alan Modra  <amodra@bigpond.net.au>
 136
 137         * aclocal.m4: Regenerate.
 138         * config.in: Regenerate.
 139         * configure: Regenerate.
 140         * po/POTFILES.in: Regenerate.
 141         * po/opcodes.pot: Regenerate.
 142
 143 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 144
 145         * ppc-dis.c (print_insn_powerpc): Don't print tabs.  Handle
 146         PPC_OPERANDS_GPR_0.
 147         * ppc-opc.c (RA0): Define.
 148         (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
 149         (RAOPT): Rename from RAO.  Update all uses.
 150         (powerpc_opcodes): Use RA0 as appropriate.
 151
 152 2004-03-15  Aldy Hernandez  <aldyh@redhat.com>
 153
 154         * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
 155
 156 2004-03-15  Alan Modra  <amodra@bigpond.net.au>
 157
 158         * sparc-dis.c (print_insn_sparc): Update getword prototype.
 159
 160 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 161
 162         * i386-dis.c (GRPPLOCK): Delete.
 163         (grps): Delete GRPPLOCK entry.
 164
 165 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 166
 167         * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
 168         (M, Mp): Use OP_M.
 169         (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
 170         (GRPPADLCK): Define.
 171         (dis386): Use NOP_Fixup on "nop".
 172         (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
 173         (twobyte_has_modrm): Set for 0xa7.
 174         (padlock_table): Delete.  Move to..
 175         (grps): ..here, using OP_0f07.  Use OP_Ofae on lfence, mfence
 176         and clflush.
 177         (print_insn): Revert PADLOCK_SPECIAL code.
 178         (OP_E): Delete sfence, lfence, mfence checks.
 179
 180 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 181
 182         * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
 183         (INVLPG_Fixup): New function.
 184         (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
 185
 186 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 187
 188         * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
 189         (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
 190         (padlock_table): New struct with PadLock instructions.
 191         (print_insn): Handle PADLOCK_SPECIAL.
 192
 193 2004-03-12  Alan Modra  <amodra@bigpond.net.au>
 194
 195         * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
 196         (OP_E): Twiddle clflush to sfence here.
 197
 198 2004-03-08  Nick Clifton  <nickc@redhat.com>
 199
 200         * po/de.po: Updated German translation.
 201
 202 2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
 203
 204         * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
 205         nofpu mode.  Add BFD type bfd_mach_sh4_nommu_nofpu.
 206         * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
 207         accordingly.
 208
 209 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 210
 211         * frv-asm.c: Regenerate.
 212         * frv-desc.c: Regenerate.
 213         * frv-desc.h: Regenerate.
 214         * frv-dis.c: Regenerate.
 215         * frv-ibld.c: Regenerate.
 216         * frv-opc.c: Regenerate.
 217         * frv-opc.h: Regenerate.
 218
 219 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 220
 221         * frv-desc.c, frv-opc.c: Regenerate.
 222
 223 2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
 224
 225         * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
 226
 227 2004-02-26  Andrew Stubbs  <andrew.stubbs@superh.com>
 228
 229         * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
 230         Also correct mistake in the comment.
 231
 232 2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
 233
 234         * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
 235         ensure that double registers have even numbers.
 236         Add REG_N_B01 for nn01 (binary 01) nibble to ensure
 237         that reserved instruction 0xfffd does not decode the same
 238         as 0xfdfd (ftrv).
 239         * sh-opc.h: Add REG_N_D nibble type and use it whereever
 240         REG_N refers to a double register.
 241         Add REG_N_B01 nibble type and use it instead of REG_NM
 242         in ftrv.
 243         Adjust the bit patterns in a few comments.
 244
 245 2004-02-25  Aldy Hernandez  <aldyh@redhat.com>
 246
 247         * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
 248
 249 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 250
 251         * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
 252
 253 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 254
 255         * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
 256
 257 2004-02-20  Aldy Hernandez  <aldyh@redhat.com>
 258
 259         * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
 260         mtivor32, mtivor33, mtivor34.
 261
 262 2004-02-19  Aldy Hernandez  <aldyh@redhat.com>
 263
 264         * ppc-opc.c (powerpc_opcodes): Add mfmcar.
 265
 266 2004-02-10  Petko Manolov  <petkan@nucleusys.com>
 267
 268         * arm-opc.h Maverick accumulator register opcode fixes.
 269
 270 2004-02-13  Ben Elliston  <bje@wasabisystems.com>
 271
 272         * m32r-dis.c: Regenerate.
 273
 274 2004-01-27  Michael Snyder  <msnyder@redhat.com>
 275
 276         * sh-opc.h (sh_table): "fsrra", not "fssra".
 277
 278 2004-01-23  Andrew Over <andrew.over@cs.anu.edu.au>
 279
 280         * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
 281         contraints.
 282
 283 2004-01-19  Andrew Over  <andrew.over@cs.anu.edu.au>
 284
 285         * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
 286
 287 2004-01-19  Alan Modra  <amodra@bigpond.net.au>
 288
 289         * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
 290         1.  Don't print scale factor on AT&T mode when index missing.
 291
 292 2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
 293
 294         * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
 295         when loaded into XR registers.
 296
 297 2004-01-14  Richard Sandiford  <rsandifo@redhat.com>
 298
 299         * frv-desc.h: Regenerate.
 300         * frv-desc.c: Regenerate.
 301         * frv-opc.c: Regenerate.
 302
 303 2004-01-13  Michael Snyder  <msnyder@redhat.com>
 304
 305         * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
 306
 307 2004-01-09  Paul Brook  <paul@codesourcery.com>
 308
 309         * arm-opc.h (arm_opcodes): Move generic mcrr after known
 310         specific opcodes.
 311
 312 2004-01-07  Daniel Jacobowitz  <drow@mvista.com>
 313
 314         * Makefile.am (libopcodes_la_DEPENDENCIES)
 315         (libopcodes_la_LIBADD): Revert 2003-05-17 change.  Add explanatory
 316         comment about the problem.
 317         * Makefile.in: Regenerate.
 318
 319 2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
 320
 321         2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
 322         * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
 323         cut&paste errors in shifting/truncating numerical operands.
 324         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 325         * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
 326         (parse_uslo16): Likewise.
 327         (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
 328         (parse_d12): Parse gotoff12 and gotofffuncdesc12.
 329         (parse_s12): Likewise.
 330         2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
 331         * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
 332         (parse_uslo16): Likewise.
 333         (parse_uhi16): Parse gothi and gotfuncdeschi.
 334         (parse_d12): Parse got12 and gotfuncdesc12.
 335         (parse_s12): Likewise.
 336
 337 2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
 338
 339         * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
 340         instruction which looks similar to an 'rla' instruction.
 341
 342 For older changes see ChangeLog-0203
 343 \f
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 345 mode: change-log
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