opcodes/ChangeLog

   1 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
   2
   3         * arc-dis.c: Revamped file for ARC support
   4         * arc-dis.h: Likewise.
   5         * arc-ext.c: Likewise.
   6         * arc-ext.h: Likewise.
   7         * arc-opc.c: Likewise.
   8         * arc-fxi.h: New file.
   9         * arc-regs.h: Likewise.
  10         * arc-tbl.h: Likewise.
  11
  12 2015-10-02  Yao Qi  <yao.qi@linaro.org>
  13
  14         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
  15         argument insn type to aarch64_insn.  Rename to ...
  16         (aarch64_decode_insn): ... it.
  17         (print_insn_aarch64_word): Caller updated.
  18
  19 2015-10-02  Yao Qi  <yao.qi@linaro.org>
  20
  21         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
  22         (print_insn_aarch64_word): Caller updated.
  23
  24 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
  25
  26         * s390-mkopc.c (main): Parse htm and vx flag.
  27         * s390-opc.txt: Mark instructions from the hardware transactional
  28         memory and vector facilities with the "htm"/"vx" flag.
  29
  30 2015-09-28  Nick Clifton  <nickc@redhat.com>
  31
  32         * po/de.po: Updated German translation.
  33
  34 2015-09-28  Tom Rix  <tom@bumblecow.com>
  35
  36         * ppc-opc.c (PPC500): Mark some opcodes as invalid
  37
  38 2015-09-23  Nick Clifton  <nickc@redhat.com>
  39
  40         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
  41         function.
  42         * tic30-dis.c (print_branch): Likewise.
  43         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
  44         value before left shifting.
  45         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
  46         * hppa-dis.c (print_insn_hppa): Likewise.
  47         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
  48         array.
  49         * msp430-dis.c (msp430_singleoperand): Likewise.
  50         (msp430_doubleoperand): Likewise.
  51         (print_insn_msp430): Likewise.
  52         * nds32-asm.c (parse_operand): Likewise.
  53         * sh-opc.h (MASK): Likewise.
  54         * v850-dis.c (get_operand_value): Likewise.
  55
  56 2015-09-22  Nick Clifton  <nickc@redhat.com>
  57
  58         * rx-decode.opc (bwl): Use RX_Bad_Size.
  59         (sbwl): Likewise.
  60         (ubwl): Likewise.  Rename to ubw.
  61         (uBWL): Rename to uBW.
  62         Replace all references to uBWL with uBW.
  63         * rx-decode.c: Regenerate.
  64         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
  65         (opsize_names): Likewise.
  66         (print_insn_rx): Detect and report RX_Bad_Size.
  67
  68 2015-09-22  Anton Blanchard  <anton@samba.org>
  69
  70         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
  71
  72 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
  73
  74         * sparc-dis.c (print_insn_sparc): Handle the privileged register
  75         %pmcdper.
  76
  77 2015-08-24  Jan Stancek  <jstancek@redhat.com>
  78
  79         * i386-dis.c (print_insn): Fix decoding of three byte operands.
  80
  81 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
  82
  83         PR binutils/18257
  84         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
  85         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
  86         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
  87         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
  88         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
  89         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
  90         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
  91         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
  92         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
  93         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
  94         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
  95         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
  96         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
  97         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
  98         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
  99         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 100         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 101         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 102         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 103         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 104         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 105         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 106         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 107         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 108         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 109         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 110         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 111         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 112         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 113         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 114         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 115         (vex_w_table): Replace terminals with MOD_TABLE entries for
 116         most of mask instructions.
 117
 118 2015-08-17  Alan Modra  <amodra@gmail.com>
 119
 120         * cgen.sh: Trim trailing space from cgen output.
 121         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 122         (print_dis_table): Likewise.
 123         * opc2c.c (dump_lines): Likewise.
 124         (orig_filename): Warning fix.
 125         * ia64-asmtab.c: Regenerate.
 126
 127 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 128
 129         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 130         and higher with ARM instruction set will now mark the 26-bit
 131         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 132         (arm_opcodes): Fix for unpredictable nop being recognized as a
 133         teq.
 134
 135 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 136
 137         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 138         based on 'or' is first.
 139         * mips-opc.c (mips_builtin_opcodes): Ditto.
 140
 141 2015-08-11  Nick Clifton  <nickc@redhat.com>
 142
 143         PR 18800
 144         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 145         instruction.
 146
 147 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 148
 149         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 150
 151 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 152
 153         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 154         * i386-init.h: Regenerated.
 155
 156 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 157
 158         PR binutils/13571
 159         * i386-dis.c (MOD_0FC3): New.
 160         (PREFIX_0FC3): Renamed to ...
 161         (PREFIX_MOD_0_0FC3): This.
 162         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 163         (prefix_table): Replace Ma with Ev on movntiS.
 164         (mod_table): Add MOD_0FC3.
 165
 166 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 167
 168         * configure: Regenerated.
 169
 170 2015-07-23  Alan Modra  <amodra@gmail.com>
 171
 172         PR 18708
 173         * i386-dis.c (get64): Avoid signed integer overflow.
 174
 175 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 176
 177         PR binutils/18631
 178         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 179         "EXEvexHalfBcstXmmq" for the second operand.
 180         (EVEX_W_0F79_P_2): Likewise.
 181         (EVEX_W_0F7A_P_2): Likewise.
 182         (EVEX_W_0F7B_P_2): Likewise.
 183
 184 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 185
 186         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 187         float bitfield format.
 188         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 189         quarter float bitfield format.
 190
 191 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * configure: Regenerated.
 194
 195 2015-07-03  Alan Modra  <amodra@gmail.com>
 196
 197         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 198         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 199         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 200
 201 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 202             Cesar Philippidis  <cesar@codesourcery.com>
 203
 204         * nios2-dis.c (nios2_extract_opcode): New.
 205         (nios2_disassembler_state): New.
 206         (nios2_find_opcode_hash): Use mach parameter to select correct
 207         disassembler state.
 208         (nios2_print_insn_arg): Extend to support new R2 argument letters
 209         and formats.
 210         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 211         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 212         (NIOS2_NUM_OPCODES): Rename to...
 213         (NIOS2_NUM_R1_OPCODES): This.
 214         (nios2_r2_opcodes): New.
 215         (NIOS2_NUM_R2_OPCODES): New.
 216         (nios2_num_r2_opcodes): New.
 217         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 218         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 219         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 220         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 221         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 222
 223 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 224
 225         * i386-dis.c (OP_Mwaitx): New.
 226         (rm_table): Add monitorx/mwaitx.
 227         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 228         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 229         (operand_type_init): Add CpuMWAITX.
 230         * i386-opc.h (CpuMWAITX): New.
 231         (i386_cpu_flags): Add cpumwaitx.
 232         * i386-opc.tbl: Add monitorx and mwaitx.
 233         * i386-init.h: Regenerated.
 234         * i386-tbl.h: Likewise.
 235
 236 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 237
 238         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 239         (insert_esync): New function.
 240         (LS, WC): Use insert_ls.
 241         (ESYNC): Use insert_esync.
 242
 243 2015-06-22  Nick Clifton  <nickc@redhat.com>
 244
 245         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 246         requested region lies beyond it.
 247         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 248         looking for 32-bit insns.
 249         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 250         data.
 251         * sh-dis.c (print_insn_sh): Likewise.
 252         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 253         blocks of instructions.
 254         * vax-dis.c (print_insn_vax): Check that the requested address
 255         does not clash with the stop_vma.
 256
 257 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 258
 259         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 260         * ppc-opc.c (FXM4): Add non-zero optional value.
 261         (TBR): Likewise.
 262         (SXL): Likewise.
 263         (insert_fxm): Handle new default operand value.
 264         (extract_fxm): Likewise.
 265         (insert_tbr): Likewise.
 266         (extract_tbr): Likewise.
 267
 268 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 269
 270         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 271
 272 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 273
 274         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 275
 276 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 277
 278         * ppc-opc.c: Add comment accidentally removed by old commit.
 279         (MTMSRD_L): Delete.
 280
 281 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 282
 283         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 284
 285 2015-06-04  Nick Clifton  <nickc@redhat.com>
 286
 287         PR 18474
 288         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 289
 290 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 291
 292         * arm-dis.c (arm_opcodes): Add "setpan".
 293         (thumb_opcodes): Add "setpan".
 294
 295 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 296
 297         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 298         macros.
 299
 300 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 301
 302         * aarch64-tbl.h (aarch64_feature_rdma): New.
 303         (RDMA): New.
 304         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 305         * aarch64-asm-2.c: Regenerate.
 306         * aarch64-dis-2.c: Regenerate.
 307         * aarch64-opc-2.c: Regenerate.
 308
 309 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 310
 311         * aarch64-tbl.h (aarch64_feature_lor): New.
 312         (LOR): New.
 313         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 314         "stllrb", "stllrh".
 315         * aarch64-asm-2.c: Regenerate.
 316         * aarch64-dis-2.c: Regenerate.
 317         * aarch64-opc-2.c: Regenerate.
 318
 319 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 320
 321         * aarch64-opc.c (F_ARCHEXT): New.
 322         (aarch64_sys_regs): Add "pan".
 323         (aarch64_sys_reg_supported_p): New.
 324         (aarch64_pstatefields): Add "pan".
 325         (aarch64_pstatefield_supported_p): New.
 326
 327 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 328
 329         * i386-tbl.h: Regenerate.
 330
 331 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 332
 333         * i386-dis.c (print_insn): Swap rounding mode specifier and
 334         general purpose register in Intel mode.
 335
 336 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 339         * i386-tbl.h: Regenerate.
 340
 341 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 342
 343         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 344         * i386-init.h: Regenerated.
 345
 346 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 347
 348         PR binutis/18386
 349         * i386-dis.c: Add comments for '@'.
 350         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 351         (enum x86_64_isa): New.
 352         (isa64): Likewise.
 353         (print_i386_disassembler_options): Add amd64 and intel64.
 354         (print_insn): Handle amd64 and intel64.
 355         (putop): Handle '@'.
 356         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 357         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 358         * i386-opc.h (AMD64): New.
 359         (CpuIntel64): Likewise.
 360         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 361         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 362         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 363         * i386-init.h: Regenerated.
 364         * i386-tbl.h: Likewise.
 365
 366 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 367
 368         * ppc-opc.c (IH) New define.
 369         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 370         <tlbie>: Add RS operand for POWER7.
 371         <slbia>: Add IH operand for POWER6.
 372
 373 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 374
 375         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 376         direct branch.
 377         (jmp): Likewise.
 378         * i386-tbl.h: Regenerated.
 379
 380 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 381
 382         * configure.ac: Support bfd_iamcu_arch.
 383         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 384         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 385         CPU_IAMCU_COMPAT_FLAGS.
 386         (cpu_flags): Add CpuIAMCU.
 387         * i386-opc.h (CpuIAMCU): New.
 388         (i386_cpu_flags): Add cpuiamcu.
 389         * configure: Regenerated.
 390         * i386-init.h: Likewise.
 391         * i386-tbl.h: Likewise.
 392
 393 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 394
 395         PR binutis/18386
 396         * i386-dis.c (X86_64_E8): New.
 397         (X86_64_E9): Likewise.
 398         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 399         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 400         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 401         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 402         (putop): Handle '^'.
 403         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 404         REX_W.
 405
 406 2015-04-30  DJ Delorie  <dj@redhat.com>
 407
 408         * disassemble.c (disassembler): Choose suitable disassembler based
 409         on E_ABI.
 410         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 411         it to decode mul/div insns.
 412         * rl78-decode.c: Regenerate.
 413         * rl78-dis.c (print_insn_rl78): Rename to...
 414         (print_insn_rl78_common): ...this, take ISA parameter.
 415         (print_insn_rl78): New.
 416         (print_insn_rl78_g10): New.
 417         (print_insn_rl78_g13): New.
 418         (print_insn_rl78_g14): New.
 419         (rl78_get_disassembler): New.
 420
 421 2015-04-29  Nick Clifton  <nickc@redhat.com>
 422
 423         * po/fr.po: Updated French translation.
 424
 425 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 426
 427         * ppc-opc.c (DCBT_EO): New define.
 428         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 429         <lharx>: Likewise.
 430         <stbcx.>: Likewise.
 431         <sthcx.>: Likewise.
 432         <waitrsv>: Do not enable for POWER7 and later.
 433         <waitimpl>: Likewise.
 434         <dcbt>: Default to the two operand form of the instruction for all
 435         "old" cpus.  For "new" cpus, use the operand ordering that matches
 436         whether the cpu is server or embedded.
 437         <dcbtst>: Likewise.
 438
 439 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 440
 441         * s390-opc.c: New instruction type VV0UU2.
 442         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 443         and WFC.
 444
 445 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 446
 447         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 448         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 449         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 450         (vfpclasspd, vfpclassps): Add %XZ.
 451
 452 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 453
 454         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 455         (PREFIX_UD_REPZ): Likewise.
 456         (PREFIX_UD_REPNZ): Likewise.
 457         (PREFIX_UD_DATA): Likewise.
 458         (PREFIX_UD_ADDR): Likewise.
 459         (PREFIX_UD_LOCK): Likewise.
 460
 461 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 462
 463         * i386-dis.c (prefix_requirement): Removed.
 464         (print_insn): Don't set prefix_requirement.  Check
 465         dp->prefix_requirement instead of prefix_requirement.
 466
 467 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 468
 469         PR binutils/17898
 470         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 471         (PREFIX_MOD_0_0FC7_REG_6): This.
 472         (PREFIX_MOD_3_0FC7_REG_6): New.
 473         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 474         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 475         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 476         PREFIX_MOD_3_0FC7_REG_7.
 477         (mod_table): Replace PREFIX_0FC7_REG_6 with
 478         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 479         PREFIX_MOD_3_0FC7_REG_7.
 480
 481 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 482
 483         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 484         (PREFIX_MANDATORY_REPNZ): Likewise.
 485         (PREFIX_MANDATORY_DATA): Likewise.
 486         (PREFIX_MANDATORY_ADDR): Likewise.
 487         (PREFIX_MANDATORY_LOCK): Likewise.
 488         (PREFIX_MANDATORY): Likewise.
 489         (PREFIX_UD_SHIFT): Set to 8
 490         (PREFIX_UD_REPZ): Updated.
 491         (PREFIX_UD_REPNZ): Likewise.
 492         (PREFIX_UD_DATA): Likewise.
 493         (PREFIX_UD_ADDR): Likewise.
 494         (PREFIX_UD_LOCK): Likewise.
 495         (PREFIX_IGNORED_SHIFT): New.
 496         (PREFIX_IGNORED_REPZ): Likewise.
 497         (PREFIX_IGNORED_REPNZ): Likewise.
 498         (PREFIX_IGNORED_DATA): Likewise.
 499         (PREFIX_IGNORED_ADDR): Likewise.
 500         (PREFIX_IGNORED_LOCK): Likewise.
 501         (PREFIX_OPCODE): Likewise.
 502         (PREFIX_IGNORED): Likewise.
 503         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 504         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 505         (three_byte_table): Likewise.
 506         (mod_table): Likewise.
 507         (mandatory_prefix): Renamed to ...
 508         (prefix_requirement): This.
 509         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 510         Update PREFIX_90 entry.
 511         (get_valid_dis386): Check prefix_requirement to see if a prefix
 512         should be ignored.
 513         (print_insn): Replace mandatory_prefix with prefix_requirement.
 514
 515 2015-04-15  Renlin Li  <renlin.li@arm.com>
 516
 517         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 518         use it for ssat and ssat16.
 519         (print_insn_thumb32): Add handle case for 'D' control code.
 520
 521 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 522             H.J. Lu  <hongjiu.lu@intel.com>
 523
 524         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 525         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 526         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 527         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 528         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 529         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 530         Fill prefix_requirement field.
 531         (struct dis386): Add prefix_requirement field.
 532         (dis386): Fill prefix_requirement field.
 533         (dis386_twobyte): Ditto.
 534         (twobyte_has_mandatory_prefix_: Remove.
 535         (reg_table): Fill prefix_requirement field.
 536         (prefix_table): Ditto.
 537         (x86_64_table): Ditto.
 538         (three_byte_table): Ditto.
 539         (xop_table): Ditto.
 540         (vex_table): Ditto.
 541         (vex_len_table): Ditto.
 542         (vex_w_table): Ditto.
 543         (mod_table): Ditto.
 544         (bad_opcode): Ditto.
 545         (print_insn): Use prefix_requirement.
 546         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 547         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 548         (float_reg): Ditto.
 549
 550 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 551
 552         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 553
 554 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 555
 556         * Makefile.in: Regenerated.
 557
 558 2015-03-25  Anton Blanchard  <anton@samba.org>
 559
 560         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 561         powerpc_opcd_indices and vle_opcd_indices once.
 562
 563 2015-03-25  Anton Blanchard  <anton@samba.org>
 564
 565         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 566
 567 2015-03-24  Terry Guo  <terry.guo@arm.com>
 568
 569         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 570         (opcode16): Likewise.
 571         (coprocessor_opcodes): Replace bit with feature struct.
 572         (neon_opcodes): Likewise.
 573         (arm_opcodes): Likewise.
 574         (thumb_opcodes): Likewise.
 575         (thumb32_opcodes): Likewise.
 576         (print_insn_coprocessor): Likewise.
 577         (print_insn_arm): Likewise.
 578         (select_arm_features): Follow new feature struct.
 579
 580 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 581
 582         * i386-dis.c (rm_table): Add clzero.
 583         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 584         Add CPU_CLZERO_FLAGS.
 585         (cpu_flags): Add CpuCLZERO.
 586         * i386-opc.h: Add CpuCLZERO.
 587         * i386-opc.tbl: Add clzero.
 588         * i386-init.h: Re-generated.
 589         * i386-tbl.h: Re-generated.
 590
 591 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 592
 593         * mips-opc.c (decode_mips_operand): Fix constraint issues
 594         with u and y operands.
 595
 596 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 597
 598         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 599
 600 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 601
 602         * s390-opc.c: Add new IBM z13 instructions.
 603         * s390-opc.txt: Likewise.
 604
 605 2015-03-10  Renlin Li  <renlin.li@arm.com>
 606
 607         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 608         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 609         related alias.
 610         * aarch64-asm-2.c: Regenerate.
 611         * aarch64-dis-2.c: Likewise.
 612         * aarch64-opc-2.c: Likewise.
 613
 614 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 615
 616         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 617
 618 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 619
 620         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 621         arch_sh_up.
 622         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 623         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 624
 625 2015-02-23  Vinay  <Vinay.G@kpit.com>
 626
 627         * rl78-decode.opc (MOV): Added space between two operands for
 628         'mov' instruction in index addressing mode.
 629         * rl78-decode.c: Regenerate.
 630
 631 2015-02-19  Pedro Alves  <palves@redhat.com>
 632
 633         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 634
 635 2015-02-10  Pedro Alves  <palves@redhat.com>
 636             Tom Tromey  <tromey@redhat.com>
 637
 638         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 639         microblaze_and, microblaze_xor.
 640         * microblaze-opc.h (opcodes): Adjust.
 641
 642 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 643
 644         * Makefile.am: Add FT32 files.
 645         * configure.ac: Handle FT32.
 646         * disassemble.c (disassembler): Call print_insn_ft32.
 647         * ft32-dis.c: New file.
 648         * ft32-opc.c: New file.
 649         * Makefile.in: Regenerate.
 650         * configure: Regenerate.
 651         * po/POTFILES.in: Regenerate.
 652
 653 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 654
 655         * nds32-asm.c (keyword_sr): Add new system registers.
 656
 657 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 658
 659         * s390-dis.c (s390_extract_operand): Support vector register
 660         operands.
 661         (s390_print_insn_with_opcode): Support new operands types and add
 662         new handling of optional operands.
 663         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 664         and include opcode/s390.h instead.
 665         (struct op_struct): New field `flags'.
 666         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 667         (dumpTable): Dump flags.
 668         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 669         string.
 670         * s390-opc.c: Add new operands types, instruction formats, and
 671         instruction masks.
 672         (s390_opformats): Add new formats for .insn.
 673         * s390-opc.txt: Add new instructions.
 674
 675 2015-01-01  Alan Modra  <amodra@gmail.com>
 676
 677         Update year range in copyright notice of all files.
 678
 679 For older changes see ChangeLog-2014
 680 \f
 681 Copyright (C) 2015 Free Software Foundation, Inc.
 682
 683 Copying and distribution of this file, with or without modification,
 684 are permitted in any medium without royalty provided the copyright
 685 notice and this notice are preserved.
 686
 687 Local Variables:
 688 mode: change-log
 689 left-margin: 8
 690 fill-column: 74
 691 version-control: never
 692 End: