opcodes/ChangeLog

   1 2021-06-19  Alan Modra  <amodra@gmail.com>
   2
   3         * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
   4         entire buffer.
   5
   6 2021-06-17  Alan Modra  <amodra@gmail.com>
   7
   8         * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
   9         in table.
  10
  11 2021-06-03  Alan Modra  <amodra@gmail.com>
  12
  13         PR 1202
  14         * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
  15         Use unsigned int for inst.
  16
  17 2021-06-02  Shahab Vahedi  <shahab@synopsys.com>
  18
  19         * arc-dis.c (arc_option_arg_t): New enumeration.
  20         (arc_options): New variable.
  21         (disassembler_options_arc): New function.
  22         (print_arc_disassembler_options): Reimplement in terms of
  23         "disassembler_options_arc".
  24
  25 2021-05-29  Alan Modra  <amodra@gmail.com>
  26
  27         * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
  28         Don't special case PPC_OPCODE_RAW.
  29         (lookup_prefix): Likewise.
  30         (lookup_vle, lookup_spe2): Similarly.  Add dialect parameter and..
  31         (print_insn_powerpc): ..update caller.
  32         * ppc-opc.c (EXT): Define.
  33         (powerpc_opcodes): Mark extended mnemonics with EXT.
  34         (prefix_opcodes, vle_opcodes): Likewise.
  35         (XISEL, XISEL_MASK): Add cr field and simplify.
  36         (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
  37         all isel variants to where the base mnemonic belongs.  Sort dstt,
  38         dststt and dssall.
  39
  40 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  41
  42         * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
  43         COP3 opcode instructions.
  44
  45 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  46
  47         * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
  48         "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
  49         "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
  50         "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
  51         "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
  52         "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
  53         "cop2", and "cop3" entries.
  54
  55 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  56
  57         * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
  58         entries and associated comments.
  59
  60 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  61
  62         * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
  63         of "c0".
  64
  65 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  66
  67         * mips-dis.c (mips_cp1_names_mips): New variable.
  68         (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
  69         for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
  70         "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
  71         "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
  72         "r12000", "r14000", "r16000", "mips5", "loongson2e", and
  73         "loongson2f".
  74
  75 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  76
  77         * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
  78         handling code over to...
  79         <OP_REG_CONTROL>: ... this new case.
  80         * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
  81         (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
  82         "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
  83         replacing the `G' operand code with `g'.  Update "cftc1" and
  84         "cftc2" entries replacing the `E' operand code with `y'.
  85         * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
  86         (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
  87         entries replacing the `G' operand code with `g'.
  88
  89 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  90
  91         * mips-dis.c (mips_cp0_names_r3900): New variable.
  92         (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
  93         for "r3900".
  94
  95 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
  96
  97         * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
  98         and "mtthc2" to using the `G' rather than `g' operand code for
  99         the coprocessor control register referred.
 100
 101 2021-05-29  Maciej W. Rozycki  <macro@orcam.me.uk>
 102
 103         * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
 104         entries with each other.
 105
 106 2021-05-27  Peter Bergner  <bergner@linux.ibm.com>
 107
 108         * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
 109
 110 2021-05-25  Alan Modra  <amodra@gmail.com>
 111
 112         * cris-desc.c: Regenerate.
 113         * cris-desc.h: Regenerate.
 114         * cris-opc.h: Regenerate.
 115         * po/POTFILES.in: Regenerate.
 116
 117 2021-05-24  Mike Frysinger  <vapier@gentoo.org>
 118
 119         * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
 120         (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
 121         (CGEN_CPUS): Add cris.
 122         (CRIS_DEPS): Define.
 123         (stamp-cris): New rule.
 124         * cgen.sh: Handle desc action.
 125         * configure.ac (bfd_cris_arch): Add cris-desc.lo.
 126         * Makefile.in, configure: Regenerate.
 127
 128 2021-05-18  Job Noorman  <mtvec@pm.me>
 129
 130         PR 27814
 131         * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
 132         the elf objects.
 133
 134 2021-05-17  Alex Coplan  <alex.coplan@arm.com>
 135
 136         * arm-dis.c (mve_opcodes): Fix disassembly of
 137         MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
 138         (is_mve_encoding_conflict): MVE vector loads should not match
 139         when P = W = 0.
 140         (is_mve_unpredictable): It's not unpredictable to use the same
 141         source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
 142
 143 2021-05-11  Nick Clifton  <nickc@redhat.com>
 144
 145         PR 27840
 146         * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
 147         the end of the code buffer.
 148
 149 2021-05-06  Stafford Horne  <shorne@gmail.com>
 150
 151         PR 21464
 152         * or1k-asm.c: Regenerate.
 153
 154 2021-05-01  Max Filippov  <jcmvbkbc@gmail.com>
 155
 156         * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
 157         info->insn_info_valid.
 158
 159 2021-04-26  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-opc.tbl (lea): Add Optimize.
 162         * opcodes/i386-tbl.h: Re-generate.
 163
 164 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 165
 166         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
 167         of l32r fetch and display referenced literal value.
 168
 169 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
 170
 171         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
 172         to 4 for literal disassembly.
 173
 174 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 175
 176         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
 177         for TLBI instruction.
 178
 179 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 180
 181         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
 182         DC instruction.
 183
 184 2021-04-19  Jan Beulich  <jbeulich@suse.com>
 185
 186         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
 187         "qualifier".
 188         (convert_mov_to_movewide): Add initializer for "value".
 189
 190 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 191
 192         * aarch64-opc.c: Add RME system registers.
 193
 194 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
 195
 196         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
 197         "addi d,CV,z" to "c.mv d,CV".
 198
 199 2021-04-12  Alan Modra  <amodra@gmail.com>
 200
 201         * configure.ac (--enable-checking): Add support.
 202         * config.in: Regenerate.
 203         * configure: Regenerate.
 204
 205 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
 206
 207         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
 208         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
 209
 210 2021-04-09  Alan Modra  <amodra@gmail.com>
 211
 212         * ppc-dis.c (struct dis_private): Add "special".
 213         (POWERPC_DIALECT): Delete.  Replace uses with..
 214         (private_data): ..this.  New inline function.
 215         (disassemble_init_powerpc): Init "special" names.
 216         (skip_optional_operands): Add is_pcrel arg, set when detecting R
 217         field of prefix instructions.
 218         (bsearch_reloc, print_got_plt): New functions.
 219         (print_insn_powerpc): For pcrel instructions, print target address
 220         and symbol if known, and decode plt and got loads too.
 221
 222 2021-04-08  Alan Modra  <amodra@gmail.com>
 223
 224         PR 27684
 225         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
 226
 227 2021-04-08  Alan Modra  <amodra@gmail.com>
 228
 229         PR 27676
 230         * ppc-opc.c (DCBT_EO): Move earlier.
 231         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
 232         (powerpc_operands): Add THCT and THDS entries.
 233         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
 234
 235 2021-04-06  Alan Modra  <amodra@gmail.com>
 236
 237         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
 238         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
 239         symbol_at_address_func.
 240
 241 2021-04-05  Alan Modra  <amodra@gmail.com>
 242
 243         * configure.ac: Don't check for limits.h, string.h, strings.h or
 244         stdlib.h.
 245         (AC_ISC_POSIX): Don't invoke.
 246         * sysdep.h: Include stdlib.h and string.h unconditionally.
 247         * i386-opc.h: Include limits.h unconditionally.
 248         * wasm32-dis.c: Likewise.
 249         * cgen-opc.c: Don't include alloca-conf.h.
 250         * config.in: Regenerate.
 251         * configure: Regenerate.
 252
 253 2021-04-01  Martin Liska  <mliska@suse.cz>
 254
 255         * arm-dis.c (strneq): Remove strneq and use startswith.
 256         * cr16-dis.c (print_insn_cr16): Likewise.
 257         * score-dis.c (streq): Likewise.
 258         (strneq): Likewise.
 259         * score7-dis.c (strneq): Likewise.
 260
 261 2021-04-01  Alan Modra  <amodra@gmail.com>
 262
 263         PR 27675
 264         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 265
 266 2021-03-31  Alan Modra  <amodra@gmail.com>
 267
 268         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 269         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 270         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 271         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 272         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 273         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 274         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 275         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 276         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 277         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 278         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 279         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 280         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 281         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 282         and TRUE with true throughout.
 283
 284 2021-03-31  Alan Modra  <amodra@gmail.com>
 285
 286         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 287         * aarch64-dis.h: Likewise.
 288         * aarch64-opc.c: Likewise.
 289         * avr-dis.c: Likewise.
 290         * csky-dis.c: Likewise.
 291         * nds32-asm.c: Likewise.
 292         * nds32-dis.c: Likewise.
 293         * nfp-dis.c: Likewise.
 294         * riscv-dis.c: Likewise.
 295         * s12z-dis.c: Likewise.
 296         * wasm32-dis.c: Likewise.
 297
 298 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 299
 300         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 301         (i386_seg_prefixes): New.
 302         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 303         (i386_seg_prefixes): Declare.
 304
 305 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 306
 307         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 308
 309 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 312         * i386-reg.tbl (st): Move down.
 313         (st(0)): Delete. Extend comment.
 314         * i386-tbl.h: Re-generate.
 315
 316 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 319         (cmpsd): Move next to cmps.
 320         (movsd): Move next to movs.
 321         (cmpxchg16b): Move to separate section.
 322         (fisttp, fisttpll): Likewise.
 323         (monitor, mwait): Likewise.
 324         * i386-tbl.h: Re-generate.
 325
 326 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 329         (vpsadbw): Add C.
 330         * i386-tbl.h: Re-generate.
 331
 332 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 335         pclmul, gfni): New templates. Use them wherever possible. Move
 336         SSE4.1 pextrw into respective section.
 337         * i386-tbl.h: Re-generate.
 338
 339 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 340
 341         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 342         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 343         "length".
 344         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 345         Convert all of their uses to representation in opcode.
 346
 347 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 350         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 351         value of None. Shrink operands to 3 bits.
 352
 353 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 354
 355         * i386-gen.c (process_i386_opcode_modifier): New parameter
 356         "space".
 357         (output_i386_opcode): New local variable "space". Adjust
 358         process_i386_opcode_modifier() invocation.
 359         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 360         invocation.
 361         * i386-tbl.h: Re-generate.
 362
 363 2021-03-29  Alan Modra  <amodra@gmail.com>
 364
 365         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 366         (fp_qualifier_p, get_data_pattern): Likewise.
 367         (aarch64_get_operand_modifier_from_value): Likewise.
 368         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 369         (operand_variant_qualifier_p): Likewise.
 370         (qualifier_value_in_range_constraint_p): Likewise.
 371         (aarch64_get_qualifier_esize): Likewise.
 372         (aarch64_get_qualifier_nelem): Likewise.
 373         (aarch64_get_qualifier_standard_value): Likewise.
 374         (get_lower_bound, get_upper_bound): Likewise.
 375         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 376         (aarch64_print_operand): Likewise.
 377         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 378         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 379         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 380         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 381         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 382         (print_insn_tic6x): Likewise.
 383
 384 2021-03-29  Alan Modra  <amodra@gmail.com>
 385
 386         * arc-dis.c (extract_operand_value): Correct NULL cast.
 387         * frv-opc.h: Regenerate.
 388
 389 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 390
 391         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 392         MMX form.
 393         * i386-tbl.h: Re-generate.
 394
 395 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 396
 397         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 398         immediate in br.n instruction.
 399
 400 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 401
 402         * i386-dis.c (XMGatherD, VexGatherD): New.
 403         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 404         (print_insn): Check masking for S/G insns.
 405         (OP_E_memory): New local variable check_gather. Extend mandatory
 406         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 407         Extend check for disallowed 16-bit addressing.
 408         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 409         if()s to switch(). Check register conflicts for (VEX-encoded)
 410         gathers. Drop no longer reachable cases.
 411         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 412         vgatherdp*.
 413
 414 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 415
 416         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 417         zeroing-masking without masking.
 418
 419 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 422         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 423         single-operand forms as deprecated.
 424         * i386-tbl.h: Re-generate.
 425
 426 2021-03-25  Alan Modra  <amodra@gmail.com>
 427
 428         PR 27647
 429         * ppc-opc.c (XLOCB_MASK): Delete.
 430         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 431         XLBH_MASK.
 432         (powerpc_opcodes): Accept a BH field on all extended forms of
 433         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 434
 435 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 436
 437         * i386-gen.c (output_i386_opcode): Drop processing of
 438         opcode_length. Calculate length from base_opcode. Adjust prefix
 439         encoding determination.
 440         (process_i386_opcodes): Drop output of fake opcode_length.
 441         * i386-opc.h (struct insn_template): Drop opcode_length field.
 442         * i386-opc.tbl: Drop opcode length field from all templates.
 443         * i386-tbl.h: Re-generate.
 444
 445 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 446
 447         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 448         parameter "prefix". Drop local variable "regular_encoding".
 449         Record prefix setting / check for consistency.
 450         (output_i386_opcode): Parse opcode_length and base_opcode
 451         earlier. Derive prefix encoding. Drop no longer applicable
 452         consistency checking. Adjust process_i386_opcode_modifier()
 453         invocation.
 454         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 455         invocation.
 456         * i386-tbl.h: Re-generate.
 457
 458 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 461         check.
 462         * i386-opc.h (Prefix_*): Move #define-s.
 463         * i386-opc.tbl: Move pseudo prefix enumerator values to
 464         extension opcode field. Introduce pseudopfx template.
 465         * i386-tbl.h: Re-generate.
 466
 467 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 468
 469         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 470         comment.
 471         * i386-tbl.h: Re-generate.
 472
 473 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 474
 475         * i386-opc.h (struct insn_template): Move cpu_flags field past
 476         opcode_modifier one.
 477         * i386-tbl.h: Re-generate.
 478
 479 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 480
 481         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 482         * i386-opc.h (OpcodeSpace): New enumerator.
 483         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 484         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 485         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 486         (struct i386_opcode_modifier): New field opcodespace. Shrink
 487         opcodeprefix field.
 488         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 489         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 490         OpcodePrefix uses.
 491         * i386-tbl.h: Re-generate.
 492
 493 2021-03-22  Martin Liska  <mliska@suse.cz>
 494
 495         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 496         * arc-dis.c (parse_option): Likewise.
 497         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 498         * cris-dis.c (print_with_operands): Likewise.
 499         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 500         * i386-dis.c (print_insn): Likewise.
 501         * ia64-gen.c (fetch_insn_class): Likewise.
 502         (parse_resource_users): Likewise.
 503         (in_iclass): Likewise.
 504         (lookup_specifier): Likewise.
 505         (insert_opcode_dependencies): Likewise.
 506         * mips-dis.c (parse_mips_ase_option): Likewise.
 507         (parse_mips_dis_option): Likewise.
 508         * s390-dis.c (disassemble_init_s390): Likewise.
 509         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 510
 511 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 512
 513         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 514
 515 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 516
 517         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 518         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 519
 520 2021-03-12  Alan Modra  <amodra@gmail.com>
 521
 522         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 523
 524 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 525
 526         * i386-dis.c (OP_XMM): Re-order checks.
 527
 528 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 529
 530         * i386-dis.c (putop): Drop need_vex check when also checking
 531         vex.evex.
 532         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 533         checking vex.b.
 534
 535 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 536
 537         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 538         checks. Move case label past broadcast check.
 539
 540 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 541
 542         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 543         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 544         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 545         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 546         EVEX_W_0F38C7_M_0_L_2): Delete.
 547         (REG_EVEX_0F38C7_M_0_L_2): New.
 548         (intel_operand_size): Handle VEX and EVEX the same for
 549         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 550         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 551         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 552         vex_vsib_q_w_d_mode uses.
 553         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 554         0F38A1, and 0F38A3 entries.
 555         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 556         entry.
 557         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 558         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 559         0F38A3 entries.
 560
 561 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 562
 563         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 564         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 565         MOD_VEX_0FXOP_09_12): Rename to ...
 566         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 567         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 568         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 569         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 570         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 571         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 572         (reg_table): Adjust comments.
 573         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 574         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 575         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 576         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 577         (vex_len_table): Adjust opcode 0A_12 entry.
 578         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 579         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 580         (rm_table): Move hreset entry.
 581
 582 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 583
 584         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 585         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 586         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 587         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 588         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 589         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 590         (get_valid_dis386): Also handle 512-bit vector length when
 591         vectoring into vex_len_table[].
 592         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 593         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 594         entries.
 595         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 596         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 597         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 598         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 599         entries.
 600
 601 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 602
 603         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 604         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 605         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 606         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 607         entries.
 608         * i386-dis-evex-len.h (evex_len_table): Likewise.
 609         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 610
 611 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 612
 613         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 614         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 615         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 616         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 617         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 618         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 619         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 620         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 621         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 622         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 623         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 624         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 625         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 626         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 627         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 628         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 629         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 630         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 631         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 632         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 633         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 634         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 635         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 636         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 637         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 638         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 639         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 640         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 641         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 642         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 643         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 644         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 645         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 646         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 647         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 648         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 649         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 650         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 651         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 652         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 653         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 654         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 655         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 656         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 657         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 658         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 659         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 660         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 661         EVEX_W_0F3A43_L_n): New.
 662         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 663         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 664         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 665         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 666         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 667         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 668         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 669         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 670         0F385B, 0F38C6, and 0F38C7 entries.
 671         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 672         0F38C6 and 0F38C7.
 673         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 674         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 675         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 676         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 677
 678 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 679
 680         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 681         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 682         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 683         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 684         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 685         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 686         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 687         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 688         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 689         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 690         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 691         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 692         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 693         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 694         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 695         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 696         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 697         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 698         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 699         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 700         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 701         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 702         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 703         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 704         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 705         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 706         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 707         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 708         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 709         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 710         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 711         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 712         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 713         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 714         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 715         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 716         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 717         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 718         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 719         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 720         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 721         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 722         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 723         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 724         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 725         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 726         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 727         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 728         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 729         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 730         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 731         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 732         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 733         VEX_W_0F99_P_2_LEN_0): Delete.
 734         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 735         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 736         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 737         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 738         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 739         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 740         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 741         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 742         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 743         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 744         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 745         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 746         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 747         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 748         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 749         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 750         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 751         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 752         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 753         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 754         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 755         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 756         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 757         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 758         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 759         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 760         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 761         (prefix_table): No longer link to vex_len_table[] for opcodes
 762         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 763         0F92, 0F93, 0F98, and 0F99.
 764         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 765         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 766         0F98, and 0F99.
 767         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 768         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 769         0F98, and 0F99.
 770         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 771         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 772         0F98, and 0F99.
 773         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 774         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 775         0F98, and 0F99.
 776
 777 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 778
 779         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 780         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 781         REG_VEX_0F73_M_0 respectively.
 782         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 783         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 784         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 785         MOD_VEX_0F73_REG_7): Delete.
 786         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 787         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 788         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 789         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 790         PREFIX_VEX_0F3AF0_L_0 respectively.
 791         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 792         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 793         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 794         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 795         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 796         VEX_LEN_0F38F7): New.
 797         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 798         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 799         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 800         0F38F3.
 801         (prefix_table): No longer link to vex_len_table[] for opcodes
 802         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 803         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 804         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 805         0F38F6, 0F38F7, and 0F3AF0.
 806         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 807         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 808         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 809         0F73.
 810
 811 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 812
 813         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 814         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 815         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 816         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 817         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 818         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 819         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 820         73.
 821         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 822         0F72, and 0F73.
 823         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 824         0F73.
 825
 826 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 827
 828         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 829         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 830         (reg_table): Don't link to mod_table[] where not needed. Add
 831         PREFIX_IGNORED to nop entries.
 832         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 833         (mod_table): Add nop entries next to prefetch ones. Drop
 834         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 835         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 836         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 837         PREFIX_OPCODE from endbr* entries.
 838         (get_valid_dis386): Also consider entry's name when zapping
 839         vindex.
 840         (print_insn): Handle PREFIX_IGNORED.
 841
 842 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 843
 844         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 845         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 846         element.
 847         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 848         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 849         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 850         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 851         (struct i386_opcode_modifier): Delete notrackprefixok,
 852         islockable, hleprefixok, and repprefixok fields. Add prefixok
 853         field.
 854         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 855         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 856         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 857         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 858         Replace HLEPrefixOk.
 859         * opcodes/i386-tbl.h: Re-generate.
 860
 861 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 862
 863         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 864         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 865         64-bit form.
 866         * opcodes/i386-tbl.h: Re-generate.
 867
 868 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 869
 870         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 871         for {} instead of {0}. Don't look for '0'.
 872         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 873         size specifiers.
 874
 875 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 876
 877         PR 27158
 878         * riscv-dis.c (print_insn_args): Updated encoding macros.
 879         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 880         (match_c_addi16sp): Updated encoding macros.
 881         (match_c_lui): Likewise.
 882         (match_c_lui_with_hint): Likewise.
 883         (match_c_addi4spn): Likewise.
 884         (match_c_slli): Likewise.
 885         (match_slli_as_c_slli): Likewise.
 886         (match_c_slli64): Likewise.
 887         (match_srxi_as_c_srxi): Likewise.
 888         (riscv_insn_types): Added .insn css/cl/cs.
 889
 890 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 891
 892         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 893         (default_priv_spec): Updated type to riscv_spec_class.
 894         (parse_riscv_dis_option): Updated.
 895         * riscv-opc.c: Moved stuff and make the file tidy.
 896
 897 2021-02-17  Alan Modra  <amodra@gmail.com>
 898
 899         * wasm32-dis.c: Include limits.h.
 900         (CHAR_BIT): Provide backup define.
 901         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 902         Correct signed overflow checking.
 903
 904 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 905
 906         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 907         * i386-tbl.h: Re-generate.
 908
 909 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 910
 911         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 912         Oword.
 913         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 914
 915 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 916
 917         * s390-mkopc.c (main): Accept arch14 as cpu string.
 918         * s390-opc.txt: Add new arch14 instructions.
 919
 920 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 921
 922         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 923         favour of LIBINTL.
 924         * configure: Regenerated.
 925
 926 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 927
 928         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 929         * tic54x-opc.c (regs): Rename to ...
 930         (tic54x_regs): ... this.
 931         (mmregs): Rename to ...
 932         (tic54x_mmregs): ... this.
 933         (condition_codes): Rename to ...
 934         (tic54x_condition_codes): ... this.
 935         (cc2_codes): Rename to ...
 936         (tic54x_cc2_codes): ... this.
 937         (cc3_codes): Rename to ...
 938         (tic54x_cc3_codes): ... this.
 939         (status_bits): Rename to ...
 940         (tic54x_status_bits): ... this.
 941         (misc_symbols): Rename to ...
 942         (tic54x_misc_symbols): ... this.
 943
 944 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 945
 946         * riscv-opc.c (MASK_RVB_IMM): Removed.
 947         (riscv_opcodes): Removed zb* instructions.
 948         (riscv_ext_version_table): Removed versions for zb*.
 949
 950 2021-01-26  Alan Modra  <amodra@gmail.com>
 951
 952         * i386-gen.c (parse_template): Ensure entire template_instance
 953         is initialised.
 954
 955 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 956
 957         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 958         (riscv_fpr_names_abi): Likewise.
 959         (riscv_opcodes): Likewise.
 960         (riscv_insn_types): Likewise.
 961
 962 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 963
 964         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 965
 966 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 967
 968         * riscv-dis.c: Comments tidy and improvement.
 969         * riscv-opc.c: Likewise.
 970
 971 2021-01-13  Alan Modra  <amodra@gmail.com>
 972
 973         * Makefile.in: Regenerate.
 974
 975 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 976
 977         PR binutils/26792
 978         * configure.ac: Use GNU_MAKE_JOBSERVER.
 979         * aclocal.m4: Regenerated.
 980         * configure: Likewise.
 981
 982 2021-01-12  Nick Clifton  <nickc@redhat.com>
 983
 984         * po/sr.po: Updated Serbian translation.
 985
 986 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 987
 988         PR ld/27173
 989         * configure: Regenerated.
 990
 991 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 992
 993         * aarch64-asm-2.c: Regenerate.
 994         * aarch64-dis-2.c: Likewise.
 995         * aarch64-opc-2.c: Likewise.
 996         * aarch64-opc.c (aarch64_print_operand):
 997         Delete handling of AARCH64_OPND_CSRE_CSR.
 998         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 999         (CSRE): Likewise.
1000         (_CSRE_INSN): Likewise.
1001         (aarch64_opcode_table): Delete csr.
1002
1003 2021-01-11  Nick Clifton  <nickc@redhat.com>
1004
1005         * po/de.po: Updated German translation.
1006         * po/fr.po: Updated French translation.
1007         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1008         * po/sv.po: Updated Swedish translation.
1009         * po/uk.po: Updated Ukranian translation.
1010
1011 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
1012
1013         * configure: Regenerated.
1014
1015 2021-01-09  Nick Clifton  <nickc@redhat.com>
1016
1017         * configure: Regenerate.
1018         * po/opcodes.pot: Regenerate.
1019
1020 2021-01-09  Nick Clifton  <nickc@redhat.com>
1021
1022         * 2.36 release branch crated.
1023
1024 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
1025
1026         * ppc-opc.c (insert_dw, (extract_dw): New functions.
1027         (DW, (XRC_MASK): Define.
1028         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1029
1030 2021-01-09  Alan Modra  <amodra@gmail.com>
1031
1032         * configure: Regenerate.
1033
1034 2021-01-08  Nick Clifton  <nickc@redhat.com>
1035
1036         * po/sv.po: Updated Swedish translation.
1037
1038 2021-01-08  Nick Clifton  <nickc@redhat.com>
1039
1040         PR 27129
1041         * aarch64-dis.c (determine_disassembling_preference): Move call to
1042         aarch64_match_operands_constraint outside of the assertion.
1043         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1044         Replace with a return of FALSE.
1045
1046         PR 27139
1047         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1048         core system register.
1049
1050 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
1051
1052         * configure: Regenerate.
1053
1054 2021-01-07  Nick Clifton  <nickc@redhat.com>
1055
1056         * po/fr.po: Updated French translation.
1057
1058 2021-01-07  Fredrik Noring  <noring@nocrew.org>
1059
1060         * m68k-opc.c (chkl): Change minimum architecture requirement to
1061         m68020.
1062
1063 2021-01-07  Philipp Tomsich  <prt@gnu.org>
1064
1065         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1066
1067 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
1068             Jim Wilson  <jimw@sifive.com>
1069             Andrew Waterman  <andrew@sifive.com>
1070             Maxim Blinov  <maxim.blinov@embecosm.com>
1071             Kito Cheng  <kito.cheng@sifive.com>
1072             Nelson Chu  <nelson.chu@sifive.com>
1073
1074         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1075         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1076
1077 2021-01-01  Alan Modra  <amodra@gmail.com>
1078
1079         Update year range in copyright notice of all files.
1080
1081 For older changes see ChangeLog-2020
1082 \f
1083 Copyright (C) 2021 Free Software Foundation, Inc.
1084
1085 Copying and distribution of this file, with or without modification,
1086 are permitted in any medium without royalty provided the copyright
1087 notice and this notice are preserved.
1088
1089 Local Variables:
1090 mode: change-log
1091 left-margin: 8
1092 fill-column: 74
1093 version-control: never
1094 End: