opcodes/ChangeLog

   1 2020-02-26  Alan Modra  <amodra@gmail.com>
   2
   3         * aarch64-asm.c: Indent labels correctly.
   4         * aarch64-dis.c: Likewise.
   5         * aarch64-gen.c: Likewise.
   6         * aarch64-opc.c: Likewise.
   7         * alpha-dis.c: Likewise.
   8         * i386-dis.c: Likewise.
   9         * nds32-asm.c: Likewise.
  10         * nfp-dis.c: Likewise.
  11         * visium-dis.c: Likewise.
  12
  13 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
  14
  15         * arc-regs.h (int_vector_base): Make it available for all ARC
  16         CPUs.
  17
  18 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
  19
  20         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
  21         changed.
  22
  23 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
  24
  25         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
  26         c.mv/c.li if rs1 is zero.
  27
  28 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
  29
  30         * i386-gen.c (cpu_flag_init): Replace CpuABM with
  31         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
  32         CPU_POPCNT_FLAGS.
  33         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
  34         * i386-opc.h (CpuABM): Removed.
  35         (CpuPOPCNT): New.
  36         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
  37         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
  38         popcnt.  Remove CpuABM from lzcnt.
  39         * i386-init.h: Regenerated.
  40         * i386-tbl.h: Likewise.
  41
  42 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
  45         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
  46         VexW1 instead of open-coding them.
  47         * i386-tbl.h: Re-generate.
  48
  49 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.tbl (AddrPrefixOpReg): Define.
  52         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
  53         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
  54         templates. Drop NoRex64.
  55         * i386-tbl.h: Re-generate.
  56
  57 2020-02-17  Jan Beulich  <jbeulich@suse.com>
  58
  59         PR gas/6518
  60         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
  61         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
  62         into Intel syntax instance (with Unpsecified) and AT&T one
  63         (without).
  64         (vcvtneps2bf16): Likewise, along with folding the two so far
  65         separate ones.
  66         * i386-tbl.h: Re-generate.
  67
  68 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  69
  70         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
  71         CPU_ANY_SSE4A_FLAGS.
  72
  73 2020-02-17  Alan Modra  <amodra@gmail.com>
  74
  75         * i386-gen.c (cpu_flag_init): Correct last change.
  76
  77 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
  78
  79         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
  80         CPU_ANY_SSE4_FLAGS.
  81
  82 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
  83
  84         * i386-opc.tbl (movsx): Remove Intel syntax comments.
  85         (movzx): Likewise.
  86
  87 2020-02-14  Jan Beulich  <jbeulich@suse.com>
  88
  89         PR gas/25438
  90         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
  91         destination for Cpu64-only variant.
  92         (movzx): Fold patterns.
  93         * i386-tbl.h: Re-generate.
  94
  95 2020-02-13  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
  98         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
  99         CPU_ANY_SSE4_FLAGS entry.
 100         * i386-init.h: Re-generate.
 101
 102 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 103
 104         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 105         with Unspecified, making the present one AT&T syntax only.
 106         * i386-tbl.h: Re-generate.
 107
 108 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 109
 110         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 111         * i386-tbl.h: Re-generate.
 112
 113 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 114
 115         PR gas/24546
 116         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 117         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 118         Amd64 and Intel64 templates.
 119         (call, jmp): Likewise for far indirect variants. Dro
 120         Unspecified.
 121         * i386-tbl.h: Re-generate.
 122
 123 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 126         * i386-opc.h (ShortForm): Delete.
 127         (struct i386_opcode_modifier): Remove shortform field.
 128         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 129         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 130         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 131         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 132         Drop ShortForm.
 133         * i386-tbl.h: Re-generate.
 134
 135 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 136
 137         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 138         fucompi): Drop ShortForm from operand-less templates.
 139         * i386-tbl.h: Re-generate.
 140
 141 2020-02-11  Alan Modra  <amodra@gmail.com>
 142
 143         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 144         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 145         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 146         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 147         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 148
 149 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 150
 151         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 152         (cde_opcodes): Add VCX* instructions.
 153
 154 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 155             Matthew Malcomson  <matthew.malcomson@arm.com>
 156
 157         * arm-dis.c (struct cdeopcode32): New.
 158         (CDE_OPCODE): New macro.
 159         (cde_opcodes): New disassembly table.
 160         (regnames): New option to table.
 161         (cde_coprocs): New global variable.
 162         (print_insn_cde): New
 163         (print_insn_thumb32): Use print_insn_cde.
 164         (parse_arm_disassembler_options): Parse coprocN args.
 165
 166 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 167
 168         PR gas/25516
 169         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 170         with ISA64.
 171         * i386-opc.h (AMD64): Removed.
 172         (Intel64): Likewose.
 173         (AMD64): New.
 174         (INTEL64): Likewise.
 175         (INTEL64ONLY): Likewise.
 176         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 177         * i386-opc.tbl (Amd64): New.
 178         (Intel64): Likewise.
 179         (Intel64Only): Likewise.
 180         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 181         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 182         * i386-tbl.h: Regenerated.
 183
 184 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 185
 186         PR 25469
 187         * z80-dis.c: Add support for GBZ80 opcodes.
 188
 189 2020-02-04  Alan Modra  <amodra@gmail.com>
 190
 191         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 192
 193 2020-02-03  Alan Modra  <amodra@gmail.com>
 194
 195         * m32c-ibld.c: Regenerate.
 196
 197 2020-02-01  Alan Modra  <amodra@gmail.com>
 198
 199         * frv-ibld.c: Regenerate.
 200
 201 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 202
 203         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 204         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 205         (OP_E_memory): Replace xmm_mdq_mode case label by
 206         vex_scalar_w_dq_mode one.
 207         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 208
 209 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 210
 211         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 212         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 213         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 214         (intel_operand_size): Drop vex_w_dq_mode case label.
 215
 216 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 217
 218         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 219         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 220
 221 2020-01-30  Alan Modra  <amodra@gmail.com>
 222
 223         * m32c-ibld.c: Regenerate.
 224
 225 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 226
 227         * bpf-opc.c: Regenerate.
 228
 229 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 230
 231         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 232         (dis386): Use them to replace C2/C3 table entries.
 233         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 234         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 235         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 236         * i386-tbl.h: Re-generate.
 237
 238 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 239
 240         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 241         forms.
 242         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 243         DefaultSize.
 244         * i386-tbl.h: Re-generate.
 245
 246 2020-01-30  Alan Modra  <amodra@gmail.com>
 247
 248         * tic4x-dis.c (tic4x_dp): Make unsigned.
 249
 250 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 251             Jan Beulich  <jbeulich@suse.com>
 252
 253         PR binutils/25445
 254         * i386-dis.c (MOVSXD_Fixup): New function.
 255         (movsxd_mode): New enum.
 256         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 257         (intel_operand_size): Handle movsxd_mode.
 258         (OP_E_register): Likewise.
 259         (OP_G): Likewise.
 260         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 261         register on movsxd.  Add movsxd with 16-bit destination register
 262         for AMD64 and Intel64 ISAs.
 263         * i386-tbl.h: Regenerated.
 264
 265 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 266
 267         PR 25403
 268         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 269         * aarch64-asm-2.c: Regenerate
 270         * aarch64-dis-2.c: Likewise.
 271         * aarch64-opc-2.c: Likewise.
 272
 273 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 274
 275         * i386-opc.tbl (sysret): Drop DefaultSize.
 276         * i386-tbl.h: Re-generate.
 277
 278 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 279
 280         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 281         Dword.
 282         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 283         * i386-tbl.h: Re-generate.
 284
 285 2020-01-20  Nick Clifton  <nickc@redhat.com>
 286
 287         * po/de.po: Updated German translation.
 288         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 289         * po/uk.po: Updated Ukranian translation.
 290
 291 2020-01-20  Alan Modra  <amodra@gmail.com>
 292
 293         * hppa-dis.c (fput_const): Remove useless cast.
 294
 295 2020-01-20  Alan Modra  <amodra@gmail.com>
 296
 297         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 298
 299 2020-01-18  Nick Clifton  <nickc@redhat.com>
 300
 301         * configure: Regenerate.
 302         * po/opcodes.pot: Regenerate.
 303
 304 2020-01-18  Nick Clifton  <nickc@redhat.com>
 305
 306         Binutils 2.34 branch created.
 307
 308 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 309
 310         * opintl.h: Fix spelling error (seperate).
 311
 312 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 313
 314         * i386-opc.tbl: Add {vex} pseudo prefix.
 315         * i386-tbl.h: Regenerated.
 316
 317 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 318
 319         PR 25376
 320         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 321         (neon_opcodes): Likewise.
 322         (select_arm_features): Make sure we enable MVE bits when selecting
 323         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 324         any architecture.
 325
 326 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 327
 328         * i386-opc.tbl: Drop stale comment from XOP section.
 329
 330 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 331
 332         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 333         (extractps): Add VexWIG to SSE2AVX forms.
 334         * i386-tbl.h: Re-generate.
 335
 336 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 337
 338         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 339         Size64 from and use VexW1 on SSE2AVX forms.
 340         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 341         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 342         * i386-tbl.h: Re-generate.
 343
 344 2020-01-15  Alan Modra  <amodra@gmail.com>
 345
 346         * tic4x-dis.c (tic4x_version): Make unsigned long.
 347         (optab, optab_special, registernames): New file scope vars.
 348         (tic4x_print_register): Set up registernames rather than
 349         malloc'd registertable.
 350         (tic4x_disassemble): Delete optable and optable_special.  Use
 351         optab and optab_special instead.  Throw away old optab,
 352         optab_special and registernames when info->mach changes.
 353
 354 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 355
 356         PR 25377
 357         * z80-dis.c (suffix): Use .db instruction to generate double
 358         prefix.
 359
 360 2020-01-14  Alan Modra  <amodra@gmail.com>
 361
 362         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 363         values to unsigned before shifting.
 364
 365 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 366
 367         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 368         flow instructions.
 369         (print_insn_thumb16, print_insn_thumb32): Likewise.
 370         (print_insn): Initialize the insn info.
 371         * i386-dis.c (print_insn): Initialize the insn info fields, and
 372         detect jumps.
 373
 374 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 375
 376         * arc-opc.c (C_NE): Make it required.
 377
 378 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 379
 380         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 381         reserved register name.
 382
 383 2020-01-13  Alan Modra  <amodra@gmail.com>
 384
 385         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 386         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 387
 388 2020-01-13  Alan Modra  <amodra@gmail.com>
 389
 390         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 391         result of wasm_read_leb128 in a uint64_t and check that bits
 392         are not lost when copying to other locals.  Use uint32_t for
 393         most locals.  Use PRId64 when printing int64_t.
 394
 395 2020-01-13  Alan Modra  <amodra@gmail.com>
 396
 397         * score-dis.c: Formatting.
 398         * score7-dis.c: Formatting.
 399
 400 2020-01-13  Alan Modra  <amodra@gmail.com>
 401
 402         * score-dis.c (print_insn_score48): Use unsigned variables for
 403         unsigned values.  Don't left shift negative values.
 404         (print_insn_score32): Likewise.
 405         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 406
 407 2020-01-13  Alan Modra  <amodra@gmail.com>
 408
 409         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 410
 411 2020-01-13  Alan Modra  <amodra@gmail.com>
 412
 413         * fr30-ibld.c: Regenerate.
 414
 415 2020-01-13  Alan Modra  <amodra@gmail.com>
 416
 417         * xgate-dis.c (print_insn): Don't left shift signed value.
 418         (ripBits): Formatting, use 1u.
 419
 420 2020-01-10  Alan Modra  <amodra@gmail.com>
 421
 422         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 423         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 424
 425 2020-01-10  Alan Modra  <amodra@gmail.com>
 426
 427         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 428         and XRREG value earlier to avoid a shift with negative exponent.
 429         * m10200-dis.c (disassemble): Similarly.
 430
 431 2020-01-09  Nick Clifton  <nickc@redhat.com>
 432
 433         PR 25224
 434         * z80-dis.c (ld_ii_ii): Use correct cast.
 435
 436 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 437
 438         PR 25224
 439         * z80-dis.c (ld_ii_ii): Use character constant when checking
 440         opcode byte value.
 441
 442 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 443
 444         * i386-dis.c (SEP_Fixup): New.
 445         (SEP): Define.
 446         (dis386_twobyte): Use it for sysenter/sysexit.
 447         (enum x86_64_isa): Change amd64 enumerator to value 1.
 448         (OP_J): Compare isa64 against intel64 instead of amd64.
 449         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 450         forms.
 451         * i386-tbl.h: Re-generate.
 452
 453 2020-01-08  Alan Modra  <amodra@gmail.com>
 454
 455         * z8k-dis.c: Include libiberty.h
 456         (instr_data_s): Make max_fetched unsigned.
 457         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 458         Don't exceed byte_info bounds.
 459         (output_instr): Make num_bytes unsigned.
 460         (unpack_instr): Likewise for nibl_count and loop.
 461         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 462         idx unsigned.
 463         * z8k-opc.h: Regenerate.
 464
 465 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 466
 467         * arc-tbl.h (llock): Use 'LLOCK' as class.
 468         (llockd): Likewise.
 469         (scond): Use 'SCOND' as class.
 470         (scondd): Likewise.
 471         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 472         (scondd): Likewise.
 473
 474 2020-01-06  Alan Modra  <amodra@gmail.com>
 475
 476         * m32c-ibld.c: Regenerate.
 477
 478 2020-01-06  Alan Modra  <amodra@gmail.com>
 479
 480         PR 25344
 481         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 482         Peek at next byte to prevent recursion on repeated prefix bytes.
 483         Ensure uninitialised "mybuf" is not accessed.
 484         (print_insn_z80): Don't zero n_fetch and n_used here,..
 485         (print_insn_z80_buf): ..do it here instead.
 486
 487 2020-01-04  Alan Modra  <amodra@gmail.com>
 488
 489         * m32r-ibld.c: Regenerate.
 490
 491 2020-01-04  Alan Modra  <amodra@gmail.com>
 492
 493         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 494
 495 2020-01-04  Alan Modra  <amodra@gmail.com>
 496
 497         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 498
 499 2020-01-04  Alan Modra  <amodra@gmail.com>
 500
 501         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 502
 503 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 504
 505         * aarch64-tbl.h (aarch64_opcode_table): Use
 506         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 507
 508 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 509
 510         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 511         forms of SUDOT and USDOT.
 512
 513 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 514
 515         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 516         uzip{1,2}.
 517         * opcodes/aarch64-dis-2.c: Re-generate.
 518
 519 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 520
 521         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 522         FMMLA encoding.
 523         * opcodes/aarch64-dis-2.c: Re-generate.
 524
 525 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 526
 527         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 528
 529 2020-01-01  Alan Modra  <amodra@gmail.com>
 530
 531         Update year range in copyright notice of all files.
 532
 533 For older changes see ChangeLog-2019
 534 \f
 535 Copyright (C) 2020 Free Software Foundation, Inc.
 536
 537 Copying and distribution of this file, with or without modification,
 538 are permitted in any medium without royalty provided the copyright
 539 notice and this notice are preserved.
 540
 541 Local Variables:
 542 mode: change-log
 543 left-margin: 8
 544 fill-column: 74
 545 version-control: never
 546 End: