1 2020-02-12 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
4 * i386-tbl.h: Re-generate.
6 2020-02-12 Jan Beulich <jbeulich@suse.com>
9 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
10 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
11 Amd64 and Intel64 templates.
12 (call, jmp): Likewise for far indirect variants. Dro
14 * i386-tbl.h: Re-generate.
16 2020-02-11 Jan Beulich <jbeulich@suse.com>
18 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
19 * i386-opc.h (ShortForm): Delete.
20 (struct i386_opcode_modifier): Remove shortform field.
21 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
22 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
23 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
24 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
26 * i386-tbl.h: Re-generate.
28 2020-02-11 Jan Beulich <jbeulich@suse.com>
30 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
31 fucompi): Drop ShortForm from operand-less templates.
32 * i386-tbl.h: Re-generate.
34 2020-02-11 Alan Modra <amodra@gmail.com>
36 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
37 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
38 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
39 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
40 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
42 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
44 * arm-dis.c (print_insn_cde): Define 'V' parse character.
45 (cde_opcodes): Add VCX* instructions.
47 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
48 Matthew Malcomson <matthew.malcomson@arm.com>
50 * arm-dis.c (struct cdeopcode32): New.
51 (CDE_OPCODE): New macro.
52 (cde_opcodes): New disassembly table.
53 (regnames): New option to table.
54 (cde_coprocs): New global variable.
56 (print_insn_thumb32): Use print_insn_cde.
57 (parse_arm_disassembler_options): Parse coprocN args.
59 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
62 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
64 * i386-opc.h (AMD64): Removed.
68 (INTEL64ONLY): Likewise.
69 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
70 * i386-opc.tbl (Amd64): New.
72 (Intel64Only): Likewise.
73 Replace AMD64 with Amd64. Update sysenter/sysenter with
74 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
75 * i386-tbl.h: Regenerated.
77 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
80 * z80-dis.c: Add support for GBZ80 opcodes.
82 2020-02-04 Alan Modra <amodra@gmail.com>
84 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
86 2020-02-03 Alan Modra <amodra@gmail.com>
88 * m32c-ibld.c: Regenerate.
90 2020-02-01 Alan Modra <amodra@gmail.com>
92 * frv-ibld.c: Regenerate.
94 2020-01-31 Jan Beulich <jbeulich@suse.com>
96 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
97 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
98 (OP_E_memory): Replace xmm_mdq_mode case label by
99 vex_scalar_w_dq_mode one.
100 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
102 2020-01-31 Jan Beulich <jbeulich@suse.com>
104 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
105 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
106 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
107 (intel_operand_size): Drop vex_w_dq_mode case label.
109 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
111 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
112 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
114 2020-01-30 Alan Modra <amodra@gmail.com>
116 * m32c-ibld.c: Regenerate.
118 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
120 * bpf-opc.c: Regenerate.
122 2020-01-30 Jan Beulich <jbeulich@suse.com>
124 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
125 (dis386): Use them to replace C2/C3 table entries.
126 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
127 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
128 ones. Use Size64 instead of DefaultSize on Intel64 ones.
129 * i386-tbl.h: Re-generate.
131 2020-01-30 Jan Beulich <jbeulich@suse.com>
133 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
135 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
137 * i386-tbl.h: Re-generate.
139 2020-01-30 Alan Modra <amodra@gmail.com>
141 * tic4x-dis.c (tic4x_dp): Make unsigned.
143 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
144 Jan Beulich <jbeulich@suse.com>
147 * i386-dis.c (MOVSXD_Fixup): New function.
148 (movsxd_mode): New enum.
149 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
150 (intel_operand_size): Handle movsxd_mode.
151 (OP_E_register): Likewise.
153 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
154 register on movsxd. Add movsxd with 16-bit destination register
155 for AMD64 and Intel64 ISAs.
156 * i386-tbl.h: Regenerated.
158 2020-01-27 Tamar Christina <tamar.christina@arm.com>
161 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
162 * aarch64-asm-2.c: Regenerate
163 * aarch64-dis-2.c: Likewise.
164 * aarch64-opc-2.c: Likewise.
166 2020-01-21 Jan Beulich <jbeulich@suse.com>
168 * i386-opc.tbl (sysret): Drop DefaultSize.
169 * i386-tbl.h: Re-generate.
171 2020-01-21 Jan Beulich <jbeulich@suse.com>
173 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
175 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
176 * i386-tbl.h: Re-generate.
178 2020-01-20 Nick Clifton <nickc@redhat.com>
180 * po/de.po: Updated German translation.
181 * po/pt_BR.po: Updated Brazilian Portuguese translation.
182 * po/uk.po: Updated Ukranian translation.
184 2020-01-20 Alan Modra <amodra@gmail.com>
186 * hppa-dis.c (fput_const): Remove useless cast.
188 2020-01-20 Alan Modra <amodra@gmail.com>
190 * arm-dis.c (print_insn_arm): Wrap 'T' value.
192 2020-01-18 Nick Clifton <nickc@redhat.com>
194 * configure: Regenerate.
195 * po/opcodes.pot: Regenerate.
197 2020-01-18 Nick Clifton <nickc@redhat.com>
199 Binutils 2.34 branch created.
201 2020-01-17 Christian Biesinger <cbiesinger@google.com>
203 * opintl.h: Fix spelling error (seperate).
205 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
207 * i386-opc.tbl: Add {vex} pseudo prefix.
208 * i386-tbl.h: Regenerated.
210 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
213 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
214 (neon_opcodes): Likewise.
215 (select_arm_features): Make sure we enable MVE bits when selecting
216 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
219 2020-01-16 Jan Beulich <jbeulich@suse.com>
221 * i386-opc.tbl: Drop stale comment from XOP section.
223 2020-01-16 Jan Beulich <jbeulich@suse.com>
225 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
226 (extractps): Add VexWIG to SSE2AVX forms.
227 * i386-tbl.h: Re-generate.
229 2020-01-16 Jan Beulich <jbeulich@suse.com>
231 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
232 Size64 from and use VexW1 on SSE2AVX forms.
233 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
234 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
235 * i386-tbl.h: Re-generate.
237 2020-01-15 Alan Modra <amodra@gmail.com>
239 * tic4x-dis.c (tic4x_version): Make unsigned long.
240 (optab, optab_special, registernames): New file scope vars.
241 (tic4x_print_register): Set up registernames rather than
242 malloc'd registertable.
243 (tic4x_disassemble): Delete optable and optable_special. Use
244 optab and optab_special instead. Throw away old optab,
245 optab_special and registernames when info->mach changes.
247 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
250 * z80-dis.c (suffix): Use .db instruction to generate double
253 2020-01-14 Alan Modra <amodra@gmail.com>
255 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
256 values to unsigned before shifting.
258 2020-01-13 Thomas Troeger <tstroege@gmx.de>
260 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
262 (print_insn_thumb16, print_insn_thumb32): Likewise.
263 (print_insn): Initialize the insn info.
264 * i386-dis.c (print_insn): Initialize the insn info fields, and
267 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
269 * arc-opc.c (C_NE): Make it required.
271 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
273 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
274 reserved register name.
276 2020-01-13 Alan Modra <amodra@gmail.com>
278 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
279 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
281 2020-01-13 Alan Modra <amodra@gmail.com>
283 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
284 result of wasm_read_leb128 in a uint64_t and check that bits
285 are not lost when copying to other locals. Use uint32_t for
286 most locals. Use PRId64 when printing int64_t.
288 2020-01-13 Alan Modra <amodra@gmail.com>
290 * score-dis.c: Formatting.
291 * score7-dis.c: Formatting.
293 2020-01-13 Alan Modra <amodra@gmail.com>
295 * score-dis.c (print_insn_score48): Use unsigned variables for
296 unsigned values. Don't left shift negative values.
297 (print_insn_score32): Likewise.
298 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
300 2020-01-13 Alan Modra <amodra@gmail.com>
302 * tic4x-dis.c (tic4x_print_register): Remove dead code.
304 2020-01-13 Alan Modra <amodra@gmail.com>
306 * fr30-ibld.c: Regenerate.
308 2020-01-13 Alan Modra <amodra@gmail.com>
310 * xgate-dis.c (print_insn): Don't left shift signed value.
311 (ripBits): Formatting, use 1u.
313 2020-01-10 Alan Modra <amodra@gmail.com>
315 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
316 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
318 2020-01-10 Alan Modra <amodra@gmail.com>
320 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
321 and XRREG value earlier to avoid a shift with negative exponent.
322 * m10200-dis.c (disassemble): Similarly.
324 2020-01-09 Nick Clifton <nickc@redhat.com>
327 * z80-dis.c (ld_ii_ii): Use correct cast.
329 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
332 * z80-dis.c (ld_ii_ii): Use character constant when checking
335 2020-01-09 Jan Beulich <jbeulich@suse.com>
337 * i386-dis.c (SEP_Fixup): New.
339 (dis386_twobyte): Use it for sysenter/sysexit.
340 (enum x86_64_isa): Change amd64 enumerator to value 1.
341 (OP_J): Compare isa64 against intel64 instead of amd64.
342 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
344 * i386-tbl.h: Re-generate.
346 2020-01-08 Alan Modra <amodra@gmail.com>
348 * z8k-dis.c: Include libiberty.h
349 (instr_data_s): Make max_fetched unsigned.
350 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
351 Don't exceed byte_info bounds.
352 (output_instr): Make num_bytes unsigned.
353 (unpack_instr): Likewise for nibl_count and loop.
354 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
356 * z8k-opc.h: Regenerate.
358 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
360 * arc-tbl.h (llock): Use 'LLOCK' as class.
362 (scond): Use 'SCOND' as class.
364 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
367 2020-01-06 Alan Modra <amodra@gmail.com>
369 * m32c-ibld.c: Regenerate.
371 2020-01-06 Alan Modra <amodra@gmail.com>
374 * z80-dis.c (suffix): Don't use a local struct buffer copy.
375 Peek at next byte to prevent recursion on repeated prefix bytes.
376 Ensure uninitialised "mybuf" is not accessed.
377 (print_insn_z80): Don't zero n_fetch and n_used here,..
378 (print_insn_z80_buf): ..do it here instead.
380 2020-01-04 Alan Modra <amodra@gmail.com>
382 * m32r-ibld.c: Regenerate.
384 2020-01-04 Alan Modra <amodra@gmail.com>
386 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
388 2020-01-04 Alan Modra <amodra@gmail.com>
390 * crx-dis.c (match_opcode): Avoid shift left of signed value.
392 2020-01-04 Alan Modra <amodra@gmail.com>
394 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
396 2020-01-03 Jan Beulich <jbeulich@suse.com>
398 * aarch64-tbl.h (aarch64_opcode_table): Use
399 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
401 2020-01-03 Jan Beulich <jbeulich@suse.com>
403 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
404 forms of SUDOT and USDOT.
406 2020-01-03 Jan Beulich <jbeulich@suse.com>
408 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
410 * opcodes/aarch64-dis-2.c: Re-generate.
412 2020-01-03 Jan Beulich <jbeulich@suse.com>
414 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
416 * opcodes/aarch64-dis-2.c: Re-generate.
418 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
420 * z80-dis.c: Add support for eZ80 and Z80 instructions.
422 2020-01-01 Alan Modra <amodra@gmail.com>
424 Update year range in copyright notice of all files.
426 For older changes see ChangeLog-2019
428 Copyright (C) 2020 Free Software Foundation, Inc.
430 Copying and distribution of this file, with or without modification,
431 are permitted in any medium without royalty provided the copyright
432 notice and this notice are preserved.
438 version-control: never