opcodes/ChangeLog

   1 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
   2
   3         * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
   4         * aarch64-dis-2.c: Update auto-generated file.
   5
   6 2014-09-03  Jiong Wang  <jiong.wang@arm.com>
   7
   8         * aarch64-tbl.h (QL_R4NIL): New qualifiers.
   9         (aarch64_feature_lse): New feature added.
  10         (LSE): New Added.
  11         (aarch64_opcode_table): New LSE instructions added.  Improve
  12         descriptions for ldarb/ldarh/ldar.
  13         (aarch64_opcode_table): Describe PAIRREG.
  14         * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
  15         * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
  16         (aarch64_print_operand): Recognize PAIRREG.
  17         (operand_general_constraint_met_p): Check reg pair constraints for CASP
  18         instructions.
  19         * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
  20         (do_special_decoding): Recognize F_LSE_SZ.
  21         * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
  22
  23 2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
  24
  25         * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
  26         (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
  27         "sdbbp", "syscall" and "wait".
  28
  29 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
  30             Maciej W. Rozycki  <macro@codesourcery.com>
  31
  32         * arm-dis.c (print_arm_address): Negate the GPR-relative offset
  33         returned if the U bit is set.
  34
  35 2014-08-21  Maciej W. Rozycki  <macro@codesourcery.com>
  36
  37         * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
  38         48-bit "li" encoding.
  39
  40 2014-08-19  Andreas Arnez  <arnez@linux.vnet.ibm.com>
  41
  42         * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
  43         (s390_print_insn_with_opcode, opcode_mask_more_specific): New
  44         static functions, code was moved from...
  45         (print_insn_s390): ...here.
  46         (s390_extract_operand): Adjust comment.  Change type of first
  47         parameter from 'unsigned char *' to 'const bfd_byte *'.
  48         (union operand_value): New.
  49         (s390_extract_operand): Change return type to union operand_value.
  50         Also avoid integer overflow in sign-extension.
  51         (s390_print_insn_with_opcode): Adjust to changed return value from
  52         s390_extract_operand().  Change "%i" printf format to "%u" for
  53         unsigned values.
  54         (init_disasm): Simplify initialization of opc_index[].  This also
  55         fixes an access after the last element of s390_opcodes[].
  56         (print_insn_s390): Simplify the opcode search loop.
  57         Check architecture mask against all searched opcodes, not just the
  58         first matching one.
  59         (s390_print_insn_with_opcode): Drop function pointer dereferences
  60         without effect.
  61         (print_insn_s390): Likewise.
  62         (s390_insn_length): Simplify formula for return value.
  63         (s390_print_insn_with_opcode): Avoid special handling for the
  64         separator before the first operand.  Use new local variable
  65         'flags' in place of 'operand->flags'.
  66
  67 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
  68
  69         * bfin-dis.c (struct private): Change int's to bfd_boolean's.
  70         (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
  71         decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
  72         Change assignment of 1 to priv->comment to TRUE.
  73         (print_insn_bfin): Change legal to a bfd_boolean.  Change
  74         assignment of 0/1 with priv comment and parallel and legal
  75         to FALSE/TRUE.
  76
  77 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
  78
  79         * bfin-dis.c (OUT): Define.
  80         (decode_CC2stat_0): Declare new op_names array.
  81         Replace multiple if statements with a single one.
  82
  83 2014-08-14  Mike Frysinger  <vapier@gentoo.org>
  84
  85         * bfin-dis.c (struct private): Add iw0.
  86         (_print_insn_bfin): Assign iw0 to priv.iw0.
  87         (print_insn_bfin): Drop ifetch and use priv.iw0.
  88
  89 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
  90
  91         * bfin-dis.c (comment, parallel): Move from global scope ...
  92         (struct private): ... to this new struct.
  93         (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
  94         decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
  95         decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
  96         decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
  97         decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
  98         decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
  99         decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
 100         print_insn_bfin): Declare private struct.  Use priv's comment and
 101         parallel members.
 102
 103 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 104
 105         * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
 106         (_print_insn_bfin): Add check for unaligned pc.
 107
 108 2014-08-13  Mike Frysinger  <vapier@gentoo.org>
 109
 110         * bfin-dis.c (ifetch): New function.
 111         (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
 112         -1 when it errors.
 113
 114 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 115
 116         * micromips-opc.c (COD): Rename throughout to...
 117         (CM): New define, update to use INSN_COPROC_MOVE.
 118         (LCD): Rename throughout to...
 119         (LC): New define, update to use INSN_LOAD_COPROC.
 120         * mips-opc.c: Likewise.
 121
 122 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 123
 124         * micromips-opc.c (COD, LCD) New macros.
 125         (cfc1, ctc1): Remove FP_S attribute.
 126         (dmfc1, mfc1, mfhc1): Add LCD attribute.
 127         (dmtc1, mtc1, mthc1): Add COD attribute.
 128         * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
 129
 130 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 131             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 132             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 133             Sergey Lega  <sergey.s.lega@intel.com>
 134             Anna Tikhonova  <anna.tikhonova@intel.com>
 135             Ilya Tocar  <ilya.tocar@intel.com>
 136             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 137             Ilya Verbin  <ilya.verbin@intel.com>
 138             Kirill Yukhin  <kirill.yukhin@intel.com>
 139             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 140
 141         * i386-dis-evex.h: Updated.
 142         * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
 143         PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
 144         PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
 145         PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
 146         PREFIX_EVEX_0F3A67.
 147         (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
 148         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
 149         (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
 150         EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
 151         EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
 152         EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
 153         EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
 154         EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
 155         EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
 156         (prefix_table): Add entries for new instructions.
 157         (vex_len_table): Ditto.
 158         (vex_w_table): Ditto.
 159         (OP_E_memory): Update xmmq_mode handling.
 160         * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
 161         (cpu_flags): Add CpuAVX512DQ.
 162         * i386-init.h: Regenerared.
 163         * i386-opc.h (CpuAVX512DQ): New.
 164         (i386_cpu_flags): Add cpuavx512dq.
 165         * i386-opc.tbl: Add AVX512DQ instructions.
 166         * i386-tbl.h: Regenerate.
 167
 168 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 169             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 170             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 171             Sergey Lega  <sergey.s.lega@intel.com>
 172             Anna Tikhonova  <anna.tikhonova@intel.com>
 173             Ilya Tocar  <ilya.tocar@intel.com>
 174             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 175             Ilya Verbin  <ilya.verbin@intel.com>
 176             Kirill Yukhin  <kirill.yukhin@intel.com>
 177             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 178
 179         * i386-dis-evex.h: Add new instructions (prefixes bellow).
 180         * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
 181         (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
 182         (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
 183         PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
 184         PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
 185         PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
 186         PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
 187         PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
 188         PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
 189         PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
 190         PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
 191         PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
 192         PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
 193         PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
 194         PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
 195         PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
 196         PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
 197         PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
 198         PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
 199         PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
 200         PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
 201         PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
 202         (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
 203         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 204         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
 205         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
 206         VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
 207         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
 208         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 209         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
 210         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
 211         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
 212         VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
 213         (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
 214         EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
 215         EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
 216         EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
 217         EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
 218         EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
 219         EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
 220         (prefix_table): Add entries for new instructions.
 221         (vex_table) : Ditto.
 222         (vex_len_table): Ditto.
 223         (vex_w_table): Ditto.
 224         (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
 225         mask_bd_mode handling.
 226         (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
 227         handling.
 228         (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
 229         handling.
 230         (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
 231         (OP_EX): Add dqw_swap_mode handling.
 232         (OP_VEX): Add mask_bd_mode handling.
 233         (OP_Mask): Add mask_bd_mode handling.
 234         * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
 235         (cpu_flags): Add CpuAVX512BW.
 236         * i386-init.h: Regenerated.
 237         * i386-opc.h (CpuAVX512BW): New.
 238         (i386_cpu_flags): Add cpuavx512bw.
 239         * i386-opc.tbl: Add AVX512BW instructions.
 240         * i386-tbl.h: Regenerate.
 241
 242 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 243             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 244             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 245             Sergey Lega  <sergey.s.lega@intel.com>
 246             Anna Tikhonova  <anna.tikhonova@intel.com>
 247             Ilya Tocar  <ilya.tocar@intel.com>
 248             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 249             Ilya Verbin  <ilya.verbin@intel.com>
 250             Kirill Yukhin  <kirill.yukhin@intel.com>
 251             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 252
 253         * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
 254         * i386-tbl.h: Regenerate.
 255
 256 2014-07-22  Sergey Guriev  <sergey.s.guriev@intel.com>
 257             Alexander Ivchenko  <alexander.ivchenko@intel.com>
 258             Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
 259             Sergey Lega  <sergey.s.lega@intel.com>
 260             Anna Tikhonova  <anna.tikhonova@intel.com>
 261             Ilya Tocar  <ilya.tocar@intel.com>
 262             Andrey Turetskiy  <andrey.turetskiy@intel.com>
 263             Ilya Verbin  <ilya.verbin@intel.com>
 264             Kirill Yukhin  <kirill.yukhin@intel.com>
 265             Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
 266
 267         * i386-dis.c (intel_operand_size): Support 128/256 length in
 268         vex_vsib_q_w_dq_mode.
 269         (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
 270         * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
 271         (cpu_flags): Add CpuAVX512VL.
 272         * i386-init.h: Regenerated.
 273         * i386-opc.h (CpuAVX512VL): New.
 274         (i386_cpu_flags): Add cpuavx512vl.
 275         (BROADCAST_1TO4, BROADCAST_1TO2): Define.
 276         * i386-opc.tbl: Add AVX512VL instructions.
 277         * i386-tbl.h: Regenerate.
 278
 279 2014-07-20  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 280
 281         * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
 282         * or1k-opinst.c: Regenerate.
 283
 284 2014-07-08  Ilya Tocar  <ilya.tocar@intel.com>
 285
 286         * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
 287         (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
 288
 289 2014-07-04  Alan Modra  <amodra@gmail.com>
 290
 291         * configure.ac: Rename from configure.in.
 292         * Makefile.in: Regenerate.
 293         * config.in: Regenerate.
 294
 295 2014-07-04  Alan Modra  <amodra@gmail.com>
 296
 297         * configure.in: Include bfd/version.m4.
 298         (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
 299         (BFD_VERSION): Delete.
 300         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
 301         * configure: Regenerate.
 302         * Makefile.in: Regenerate.
 303
 304 2014-07-01  Barney Stratford   <barney_stratford@fastmail.fm>
 305             Senthil Kumar Selvaraj  <senthil_kumar.selvaraj@atmel.com>
 306             Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 307             Soundararajan  <Sounderarajan.D@atmel.com>
 308
 309         * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
 310         (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
 311         machine is not avrtiny.
 312
 313 2014-06-26  Philippe De Muyter <phdm@macqel.be>
 314
 315         * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
 316         constants.
 317
 318 2014-06-12  Alan Modra  <amodra@gmail.com>
 319
 320         * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
 321         * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
 322
 323 2014-06-10  H.J. Lu  <hongjiu.lu@intel.com>
 324
 325         * i386-dis.c (fwait_prefix): New.
 326         (ckprefix): Set fwait_prefix.
 327         (print_insn): Properly print prefixes before fwait.
 328
 329 2014-06-07  Alan Modra  <amodra@gmail.com>
 330
 331         * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
 332
 333 2014-06-05  Joel Brobecker  <brobecker@adacore.com>
 334
 335         * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
 336         bfd's development.sh.
 337         * Makefile.in, configure: Regenerate.
 338
 339 2014-06-03  Nick Clifton  <nickc@redhat.com>
 340
 341         * msp430-dis.c (msp430_doubleoperand): Use extension_word to
 342         decide when extended addressing is being used.
 343
 344 2014-06-02  Eric Botcazou  <ebotcazou@adacore.com>
 345
 346         * sparc-opc.c (cas): Disable for LEON.
 347         (casl): Likewise.
 348
 349 2014-05-20  Alan Modra  <amodra@gmail.com>
 350
 351         * m68k-dis.c: Don't include setjmp.h.
 352
 353 2014-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 354
 355         * i386-dis.c (ADDR16_PREFIX): Removed.
 356         (ADDR32_PREFIX): Likewise.
 357         (DATA16_PREFIX): Likewise.
 358         (DATA32_PREFIX): Likewise.
 359         (prefix_name): Updated.
 360         (print_insn): Simplify data and address size prefixes processing.
 361
 362 2014-05-08  Stefan Kristiansson  <stefan.kristiansson@saunalahti.fi>
 363
 364         * or1k-desc.c: Regenerated.
 365         * or1k-desc.h: Likewise.
 366         * or1k-opc.c: Likewise.
 367         * or1k-opc.h: Likewise.
 368         * or1k-opinst.c: Likewise.
 369
 370 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 371
 372         * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
 373         (I34): New define.
 374         (I36): New define.
 375         (I66): New define.
 376         (I68): New define.
 377         * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
 378         mips64r5.
 379         (parse_mips_dis_option): Update MSA and virtualization support to
 380         allow mips64r3 and mips64r5.
 381
 382 2014-05-07  Andrew Bennett  <andrew.bennett@imgtec.com>
 383
 384         * mips-opc.c (G3): Remove I4.
 385
 386 2014-05-05  H.J. Lu  <hongjiu.lu@intel.com>
 387
 388         PR binutils/16893
 389         * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
 390         (end_codep): Likewise.
 391         (mandatory_prefix): Likewise.
 392         (active_seg_prefix): Likewise.
 393         (ckprefix): Set active_seg_prefix to the active segment register
 394         prefix.
 395         (seg_prefix): Removed.
 396         (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
 397         for prefix index.  Ignore the index if it is invalid and the
 398         mandatory prefix isn't required.
 399         (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
 400         mandatory.  Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
 401         in used_prefixes here.  Don't print unused prefixes.  Check
 402         active_seg_prefix for the active segment register prefix.
 403         Restore the DFLAG bit in sizeflag if the data size prefix is
 404         unused.  Check the unused mandatory PREFIX_XXX prefixes
 405         (append_seg): Only print the segment register which gets used.
 406         (OP_E_memory): Check active_seg_prefix for the segment register
 407         prefix.
 408         (OP_OFF): Likewise.
 409         (OP_OFF64): Likewise.
 410         (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
 411
 412 2014-05-02  H.J. Lu  <hongjiu.lu@intel.com>
 413
 414         PR binutils/16886
 415         * config.in: Regenerated.
 416         * configure: Likewise.
 417         * configure.in: Check if sigsetjmp is available.
 418         * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 419         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 420         (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
 421         * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 422         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 423         (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
 424         * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 425         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 426         (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
 427         * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
 428         (OPCODES_SIGSETJMP): Likewise.
 429         (OPCODES_SIGLONGJMP): Likewise.
 430         * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 431         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 432         (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
 433         * xtensa-dis.c (dis_private): Replace jmp_buf with
 434         OPCODES_SIGJMP_BUF.
 435         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 436         (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
 437         * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
 438         (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
 439         (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
 440
 441 2014-05-01  H.J. Lu  <hongjiu.lu@intel.com>
 442
 443         PR binutils/16891
 444         * i386-dis.c (print_insn): Handle prefixes before fwait.
 445
 446 2014-04-26  Alan Modra  <amodra@gmail.com>
 447
 448         * po/POTFILES.in: Regenerate.
 449
 450 2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
 451
 452         * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 453         to allow the MIPS XPA ASE.
 454         (parse_mips_dis_option): Process the -Mxpa option.
 455         * mips-opc.c (XPA): New define.
 456         (mips_builtin_opcodes): Add MIPS XPA instructions and move the
 457         locations of the ctc0 and cfc0 instructions.
 458
 459 2014-04-22  Christian Svensson  <blue@cmd.nu>
 460
 461         * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.
 462         * configure.in: Likewise.
 463         * disassemble.c: Likewise.
 464         * or1k-asm.c: New file.
 465         * or1k-desc.c: New file.
 466         * or1k-desc.h: New file.
 467         * or1k-dis.c: New file.
 468         * or1k-ibld.c: New file.
 469         * or1k-opc.c: New file.
 470         * or1k-opc.h: New file.
 471         * or1k-opinst.c: New file.
 472         * Makefile.in: Regenerate.
 473         * configure: Regenerate.
 474         * openrisc-asm.c: Delete.
 475         * openrisc-desc.c: Delete.
 476         * openrisc-desc.h: Delete.
 477         * openrisc-dis.c: Delete.
 478         * openrisc-ibld.c: Delete.
 479         * openrisc-opc.c: Delete.
 480         * openrisc-opc.h: Delete.
 481         * or32-dis.c: Delete.
 482         * or32-opc.c: Delete.
 483
 484 2014-04-04  Ilya Tocar  <ilya.tocar@intel.com>
 485
 486         * i386-dis.c (rm_table): Add encls, enclu.
 487         * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
 488         (cpu_flags): Add CpuSE1.
 489         * i386-opc.h (enum): Add CpuSE1.
 490         (i386_cpu_flags): Add cpuse1.
 491         * i386-opc.tbl: Add encls, enclu.
 492         * i386-init.h: Regenerated.
 493         * i386-tbl.h: Likewise.
 494
 495 2014-04-02  Anthony Green  <green@moxielogic.com>
 496
 497         * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
 498         instructions, sex.b and sex.s.
 499
 500 2014-03-26  Jiong Wang  <jiong.wang@arm.com>
 501
 502         * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
 503         instructions.
 504
 505 2014-03-20  Ilya Tocar  <ilya.tocar@intel.com>
 506
 507         * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
 508         vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
 509         vscatterqps.
 510         * i386-tbl.h: Regenerate.
 511
 512 2014-03-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 513
 514         * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
 515         %hstick_enable added.
 516
 517 2014-03-19  Nick Clifton  <nickc@redhat.com>
 518
 519         * rx-decode.opc (bwl): Allow for bogus instructions with a size
 520         field of 3.
 521         (sbwl, ubwl, SCALE): Likewise.
 522         * rx-decode.c: Regenerate.
 523
 524 2014-03-12  Alan Modra  <amodra@gmail.com>
 525
 526         * Makefile.in: Regenerate.
 527
 528 2014-03-05  Alan Modra  <amodra@gmail.com>
 529
 530         Update copyright years.
 531
 532 2014-03-04  Heiher  <r@hev.cc>
 533
 534         * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
 535
 536 2014-03-04  Richard Sandiford  <rdsandiford@googlemail.com>
 537
 538         * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
 539         so that they come after the Loongson extensions.
 540
 541 2014-03-03  Alan Modra  <amodra@gmail.com>
 542
 543         * i386-gen.c (process_copyright): Emit copyright notice on one line.
 544
 545 2014-02-28  Alan Modra  <amodra@gmail.com>
 546
 547         * msp430-decode.c: Regenerate.
 548
 549 2014-02-27  Jiong Wang  <jiong.wang@arm.com>
 550
 551         * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
 552         FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
 553
 554 2014-02-27  Yufeng Zhang  <yufeng.zhang@arm.com>
 555
 556         * aarch64-opc.c (print_register_offset_address): Call
 557         get_int_reg_name to prepare the register name.
 558
 559 2014-02-25  Ilya Tocar  <ilya.tocar@intel.com>
 560
 561         * i386-opc.tbl: Remove wrong variant of vcvtps2ph
 562         * i386-tbl.h: Regenerate.
 563
 564 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 565
 566         * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
 567         (cpu_flags): Add CpuPREFETCHWT1.
 568         * i386-init.h: Regenerate.
 569         * i386-opc.h (CpuPREFETCHWT1): New.
 570         (i386_cpu_flags): Add cpuprefetchwt1.
 571         * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
 572         * i386-tbl.h: Regenerate.
 573
 574 2014-02-20  Ilya Tocar  <ilya.tocar@intel.com>
 575
 576         * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
 577         to CpuAVX512F.
 578         * i386-tbl.h: Regenerate.
 579
 580 2014-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 581
 582         * i386-gen.c (output_cpu_flags): Don't output trailing space.
 583         (output_opcode_modifier): Likewise.
 584         (output_operand_type): Likewise.
 585         * i386-init.h: Regenerated.
 586         * i386-tbl.h: Likewise.
 587
 588 2014-02-12  Ilya Tocar  <ilya.tocar@intel.com>
 589
 590         * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
 591         MOD_0FC7_REG_5.
 592         (PREFIX enum): Add PREFIX_0FAE_REG_7.
 593         (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
 594         (prefix_table): Add clflusopt.
 595         (mod_table): Add xrstors, xsavec, xsaves.
 596         * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
 597         CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
 598         (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
 599         * i386-init.h: Regenerate.
 600         * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
 601         xsaves64, xsavec, xsavec64.
 602         * i386-tbl.h: Regenerate.
 603
 604 2014-02-10  Alan Modra  <amodra@gmail.com>
 605
 606         * po/POTFILES.in: Regenerate.
 607         * po/opcodes.pot: Regenerate.
 608
 609 2014-01-30  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
 610             Jan Beulich  <jbeulich@suse.com>
 611
 612         PR binutils/16490
 613         * i386-dis.c (OP_E_memory): Fix shift computation for
 614         vex_vsib_q_w_dq_mode.
 615
 616 2014-01-09  Bradley Nelson  <bradnelson@google.com>
 617             Roland McGrath  <mcgrathr@google.com>
 618
 619         * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
 620         last_rex_prefix is -1.
 621
 622 2014-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 623
 624         * i386-gen.c (process_copyright): Update copyright year to 2014.
 625
 626 2014-01-03  Maciej W. Rozycki  <macro@codesourcery.com>
 627
 628         * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
 629
 630 For older changes see ChangeLog-2013
 631 \f
 632 Copyright (C) 2014 Free Software Foundation, Inc.
 633
 634 Copying and distribution of this file, with or without modification,
 635 are permitted in any medium without royalty provided the copyright
 636 notice and this notice are preserved.
 637
 638 Local Variables:
 639 mode: change-log
 640 left-margin: 8
 641 fill-column: 74
 642 version-control: never
 643 End: