opcodes/ChangeLog

   1 2015-12-07  Alan Modra  <amodra@gmail.com>
   2
   3         * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
   4         major opcode/xop.
   5
   6 2015-12-04  Claudiu Zissulescu  <claziss@synopsys.com>
   7
   8         * arc-dis.c (special_flag_p): Match full mnemonic.
   9         * arc-opc.c (print_insn_arc): Check section size to read
  10         appropriate number of bytes. Fix printing.
  11         * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
  12         arguments.
  13
  14 2015-12-02  Andre Vieira  <andre.simoesdiasvieira@arm.com>
  15
  16         * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
  17         <ldah>: ... to this.
  18
  19 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  20
  21         * aarch64-asm-2.c: Regenerate.
  22         * aarch64-dis-2.c: Regenerate.
  23         * aarch64-opc-2.c: Regenerate.
  24         * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
  25         (QL_INT2FP_H, QL_FP2INT_H): New.
  26         (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
  27         (QL_DST_H): New.
  28         (QL_FCCMP_H): New.
  29         (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
  30         fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
  31         fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
  32         fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
  33         frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
  34         fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
  35         fcsel.
  36
  37 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  38
  39         * aarch64-opc.c (half_conv_t): New.
  40         (expand_fp_imm): Replace is_dp flag with the parameter size to
  41         specify the number of bytes for the required expansion.  Treat
  42         a 16-bit expansion like a 32-bit expansion.  Add check for an
  43         unsupported size request.  Update comment.
  44         (aarch64_print_operand): Update to support 16-bit floating point
  45         values.  Update for changes to expand_fp_imm.
  46
  47 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  48
  49         * aarch64-tbl.h (aarch64_feature_fp_f16): New.
  50         (FP_F16): New.
  51
  52 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  53
  54         * aarch64-asm-2.c: Regenerate.
  55         * aarch64-dis-2.c: Regenerate.
  56         * aarch64-opc-2.c: Regenerate.
  57         * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
  58         "rev64".
  59
  60 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  61
  62         * aarch64-asm-2.c: Regenerate.
  63         * aarch64-asm.c (convert_bfc_to_bfm): New.
  64         (convert_to_real): Add case for OP_BFC.
  65         * aarch64-dis-2.c: Regenerate.
  66         * aarch64-dis.c: (convert_bfm_to_bfc): New.
  67         (convert_to_alias): Add case for OP_BFC.
  68         * aarch64-opc-2.c: Regenerate.
  69         * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
  70         to allow width operand in three-operand instructions.
  71         * aarch64-tbl.h (QL_BF1): New.
  72         (aarch64_feature_v8_2): New.
  73         (ARMV8_2): New.
  74         (aarch64_opcode_table): Add "bfc".
  75
  76 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  77
  78         * aarch64-asm-2.c: Regenerate.
  79         * aarch64-dis-2.c: Regenerate.
  80         * aarch64-dis.c: Weaken assert.
  81         * aarch64-gen.c: Include the instruction in the list of its
  82         possible aliases.
  83
  84 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
  85
  86         * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
  87         (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
  88         feature test.
  89
  90 2015-11-23  Tristan Gingold  <gingold@adacore.com>
  91
  92         * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
  93
  94 2015-11-20  Matthew Wahab  <matthew.wahab@arm.com>
  95
  96         * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
  97         sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
  98         tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
  99         amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
 100         cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
 101         cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
 102         cnthv_ctl_el2, cnthv_cval_el2.
 103         (aarch64_sys_reg_supported_p): Update for the new system
 104         registers.
 105
 106 2015-11-20  Nick Clifton  <nickc@redhat.com>
 107
 108         PR binutils/19224
 109         * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
 110
 111 2015-11-20  Nick Clifton  <nickc@redhat.com>
 112
 113         * po/zh_CN.po: Updated simplified Chinese translation.
 114
 115 2015-11-19  Matthew Wahab  <matthew.wahab@arm.com>
 116
 117         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 118         of MSR PAN immediate operand.
 119
 120 2015-11-16  Nick Clifton  <nickc@redhat.com>
 121
 122         * rx-dis.c (condition_names): Replace always and never with
 123         invalid, since the always/never conditions can never be legal.
 124
 125 2015-11-13  Tristan Gingold  <gingold@adacore.com>
 126
 127         * configure: Regenerate.
 128
 129 2015-11-11  Alan Modra  <amodra@gmail.com>
 130             Peter Bergner <bergner@vnet.ibm.com>
 131
 132         * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
 133         Add PPC_OPCODE_VSX3 to the vsx entry.
 134         (powerpc_init_dialect): Set default dialect to power9.
 135         * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
 136         insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
 137         extract_l1 insert_xtq6, extract_xtq6): New static functions.
 138         (insert_esync): Test for illegal L operand value.
 139         (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
 140         XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
 141         XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
 142         XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
 143         PPCVSX3): New defines.
 144         (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
 145         fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
 146         <mcrxr>: Use XBFRARB_MASK.
 147         <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
 148         bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
 149         cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
 150         cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
 151         lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
 152         lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
 153         modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
 154         rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
 155         stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
 156         subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
 157         vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
 158         vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
 159         vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
 160         vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
 161         vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
 162         vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
 163         vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
 164         xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
 165         xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
 166         xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
 167         xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
 168         xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
 169         xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
 170         xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
 171         xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
 172         xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
 173         xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
 174         xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
 175         xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
 176         xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
 177         <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
 178         <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
 179
 180 2015-11-02  Nick Clifton  <nickc@redhat.com>
 181
 182         * rx-decode.opc (rx_decode_opcode): Decode extra NOP
 183         instructions.
 184         * rx-decode.c: Regenerate.
 185
 186 2015-11-02  Nick Clifton  <nickc@redhat.com>
 187
 188         * rx-decode.opc (rx_disp): If the displacement is zero, set the
 189         type to RX_Operand_Zero_Indirect.
 190         * rx-decode.c: Regenerate.
 191         * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
 192
 193 2015-10-28  Yao Qi  <yao.qi@linaro.org>
 194
 195         * aarch64-dis.c (aarch64_decode_insn): Add one argument
 196         noaliases_p.  Update comments.  Pass noaliases_p rather than
 197         no_aliases to aarch64_opcode_decode.
 198         (print_insn_aarch64_word): Pass no_aliases to
 199         aarch64_decode_insn.
 200
 201 2015-10-27  Vinay  <Vinay.G@kpit.com>
 202
 203         PR binutils/19159
 204         * rl78-decode.opc (MOV): Added offset to DE register in index
 205         addressing mode.
 206         * rl78-decode.c: Regenerate.
 207
 208 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 209
 210         PR binutils/19158
 211         * rl78-decode.opc: Add 's' print operator to instructions that
 212         access system registers.
 213         * rl78-decode.c: Regenerate.
 214         * rl78-dis.c (print_insn_rl78_common): Decode all system
 215         registers.
 216
 217 2015-10-27  Vinay Kumar  <vinay.g@kpit.com>
 218
 219         PR binutils/19157
 220         * rl78-decode.opc: Add 'a' print operator to mov instructions
 221         using stack pointer plus index addressing.
 222         * rl78-decode.c: Regenerate.
 223
 224 2015-10-14  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 225
 226         * s390-opc.c: Fix comment.
 227         * s390-opc.txt: Change instruction type for troo, trot, trto, and
 228         trtt to RRF_U0RER since the second parameter does not need to be a
 229         register pair.
 230
 231 2015-10-08  Nick Clifton  <nickc@redhat.com>
 232
 233         * arc-dis.c (print_insn_arc): Initiallise insn array.
 234
 235 2015-10-07  Yao Qi  <yao.qi@linaro.org>
 236
 237         * aarch64-dis.c (aarch64_ext_sysins_op): Access field
 238         'name' rather than 'template'.
 239         * aarch64-opc.c (aarch64_print_operand): Likewise.
 240
 241 2015-10-07  Claudiu Zissulescu <claziss@synopsys.com>
 242
 243         * arc-dis.c: Revamped file for ARC support
 244         * arc-dis.h: Likewise.
 245         * arc-ext.c: Likewise.
 246         * arc-ext.h: Likewise.
 247         * arc-opc.c: Likewise.
 248         * arc-fxi.h: New file.
 249         * arc-regs.h: Likewise.
 250         * arc-tbl.h: Likewise.
 251
 252 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 253
 254         * aarch64-dis.c (disas_aarch64_insn): Remove static.  Change
 255         argument insn type to aarch64_insn.  Rename to ...
 256         (aarch64_decode_insn): ... it.
 257         (print_insn_aarch64_word): Caller updated.
 258
 259 2015-10-02  Yao Qi  <yao.qi@linaro.org>
 260
 261         * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
 262         (print_insn_aarch64_word): Caller updated.
 263
 264 2015-09-29  Dominik Vogt  <vogt@linux.vnet.ibm.com>
 265
 266         * s390-mkopc.c (main): Parse htm and vx flag.
 267         * s390-opc.txt: Mark instructions from the hardware transactional
 268         memory and vector facilities with the "htm"/"vx" flag.
 269
 270 2015-09-28  Nick Clifton  <nickc@redhat.com>
 271
 272         * po/de.po: Updated German translation.
 273
 274 2015-09-28  Tom Rix  <tom@bumblecow.com>
 275
 276         * ppc-opc.c (PPC500): Mark some opcodes as invalid
 277
 278 2015-09-23  Nick Clifton  <nickc@redhat.com>
 279
 280         * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
 281         function.
 282         * tic30-dis.c (print_branch): Likewise.
 283         * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
 284         value before left shifting.
 285         * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
 286         * hppa-dis.c (print_insn_hppa): Likewise.
 287         * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
 288         array.
 289         * msp430-dis.c (msp430_singleoperand): Likewise.
 290         (msp430_doubleoperand): Likewise.
 291         (print_insn_msp430): Likewise.
 292         * nds32-asm.c (parse_operand): Likewise.
 293         * sh-opc.h (MASK): Likewise.
 294         * v850-dis.c (get_operand_value): Likewise.
 295
 296 2015-09-22  Nick Clifton  <nickc@redhat.com>
 297
 298         * rx-decode.opc (bwl): Use RX_Bad_Size.
 299         (sbwl): Likewise.
 300         (ubwl): Likewise.  Rename to ubw.
 301         (uBWL): Rename to uBW.
 302         Replace all references to uBWL with uBW.
 303         * rx-decode.c: Regenerate.
 304         * rx-dis.c (size_names): Add entry for RX_Bad_Size.
 305         (opsize_names): Likewise.
 306         (print_insn_rx): Detect and report RX_Bad_Size.
 307
 308 2015-09-22  Anton Blanchard  <anton@samba.org>
 309
 310         * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
 311
 312 2015-08-25  Jose E. Marchesi  <jose.marchesi@oracle.com>
 313
 314         * sparc-dis.c (print_insn_sparc): Handle the privileged register
 315         %pmcdper.
 316
 317 2015-08-24  Jan Stancek  <jstancek@redhat.com>
 318
 319         * i386-dis.c (print_insn): Fix decoding of three byte operands.
 320
 321 2015-08-21  Alexander Fomin  <alexander.fomin@intel.com>
 322
 323         PR binutils/18257
 324         * i386-dis.c: Use MOD_TABLE for most of mask instructions.
 325         (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
 326         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 327         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 328         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 329         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 330         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 331         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 332         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 333         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 334         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 335         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 336         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 337         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 338         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 339         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 340         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 341         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 342         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 343         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 344         MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
 345         MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
 346         MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
 347         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 348         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 349         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 350         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 351         MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 352         MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 353         MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 354         MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
 355         (vex_w_table): Replace terminals with MOD_TABLE entries for
 356         most of mask instructions.
 357
 358 2015-08-17  Alan Modra  <amodra@gmail.com>
 359
 360         * cgen.sh: Trim trailing space from cgen output.
 361         * ia64-gen.c (print_dependency_table): Don't generate trailing space.
 362         (print_dis_table): Likewise.
 363         * opc2c.c (dump_lines): Likewise.
 364         (orig_filename): Warning fix.
 365         * ia64-asmtab.c: Regenerate.
 366
 367 2015-08-13  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 368
 369         * arm-dis.c (print_insn_arm): Disassembling for all targets V6
 370         and higher with ARM instruction set will now mark the 26-bit
 371         versions of teq,tst,cmn and cmp as UNPREDICTABLE.
 372         (arm_opcodes): Fix for unpredictable nop being recognized as a
 373         teq.
 374
 375 2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>
 376
 377         * micromips-opc.c (micromips_opcodes): Re-order table so that move
 378         based on 'or' is first.
 379         * mips-opc.c (mips_builtin_opcodes): Ditto.
 380
 381 2015-08-11  Nick Clifton  <nickc@redhat.com>
 382
 383         PR 18800
 384         * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
 385         instruction.
 386
 387 2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
 388
 389         * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
 390
 391 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 392
 393         * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
 394         * i386-init.h: Regenerated.
 395
 396 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 397
 398         PR binutils/13571
 399         * i386-dis.c (MOD_0FC3): New.
 400         (PREFIX_0FC3): Renamed to ...
 401         (PREFIX_MOD_0_0FC3): This.
 402         (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
 403         (prefix_table): Replace Ma with Ev on movntiS.
 404         (mod_table): Add MOD_0FC3.
 405
 406 2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>
 407
 408         * configure: Regenerated.
 409
 410 2015-07-23  Alan Modra  <amodra@gmail.com>
 411
 412         PR 18708
 413         * i386-dis.c (get64): Avoid signed integer overflow.
 414
 415 2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>
 416
 417         PR binutils/18631
 418         * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
 419         "EXEvexHalfBcstXmmq" for the second operand.
 420         (EVEX_W_0F79_P_2): Likewise.
 421         (EVEX_W_0F7A_P_2): Likewise.
 422         (EVEX_W_0F7B_P_2): Likewise.
 423
 424 2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>
 425
 426         * arm-dis.c (print_insn_coprocessor): Added support for quarter
 427         float bitfield format.
 428         (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
 429         quarter float bitfield format.
 430
 431 2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 432
 433         * configure: Regenerated.
 434
 435 2015-07-03  Alan Modra  <amodra@gmail.com>
 436
 437         * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
 438         * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
 439         PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.
 440
 441 2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
 442             Cesar Philippidis  <cesar@codesourcery.com>
 443
 444         * nios2-dis.c (nios2_extract_opcode): New.
 445         (nios2_disassembler_state): New.
 446         (nios2_find_opcode_hash): Use mach parameter to select correct
 447         disassembler state.
 448         (nios2_print_insn_arg): Extend to support new R2 argument letters
 449         and formats.
 450         (print_insn_nios2): Check for 16-bit instruction at end of memory.
 451         * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
 452         (NIOS2_NUM_OPCODES): Rename to...
 453         (NIOS2_NUM_R1_OPCODES): This.
 454         (nios2_r2_opcodes): New.
 455         (NIOS2_NUM_R2_OPCODES): New.
 456         (nios2_num_r2_opcodes): New.
 457         (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
 458         (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
 459         (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
 460         (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
 461         (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
 462
 463 2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>
 464
 465         * i386-dis.c (OP_Mwaitx): New.
 466         (rm_table): Add monitorx/mwaitx.
 467         * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
 468         and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
 469         (operand_type_init): Add CpuMWAITX.
 470         * i386-opc.h (CpuMWAITX): New.
 471         (i386_cpu_flags): Add cpumwaitx.
 472         * i386-opc.tbl: Add monitorx and mwaitx.
 473         * i386-init.h: Regenerated.
 474         * i386-tbl.h: Likewise.
 475
 476 2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>
 477
 478         * ppc-opc.c (insert_ls): Test for invalid LS operands.
 479         (insert_esync): New function.
 480         (LS, WC): Use insert_ls.
 481         (ESYNC): Use insert_esync.
 482
 483 2015-06-22  Nick Clifton  <nickc@redhat.com>
 484
 485         * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
 486         requested region lies beyond it.
 487         * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
 488         looking for 32-bit insns.
 489         * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
 490         data.
 491         * sh-dis.c (print_insn_sh): Likewise.
 492         * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
 493         blocks of instructions.
 494         * vax-dis.c (print_insn_vax): Check that the requested address
 495         does not clash with the stop_vma.
 496
 497 2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>
 498
 499         * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
 500         * ppc-opc.c (FXM4): Add non-zero optional value.
 501         (TBR): Likewise.
 502         (SXL): Likewise.
 503         (insert_fxm): Handle new default operand value.
 504         (extract_fxm): Likewise.
 505         (insert_tbr): Likewise.
 506         (extract_tbr): Likewise.
 507
 508 2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>
 509
 510         * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
 511
 512 2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 513
 514         * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
 515
 516 2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>
 517
 518         * ppc-opc.c: Add comment accidentally removed by old commit.
 519         (MTMSRD_L): Delete.
 520
 521 2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>
 522
 523         * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
 524
 525 2015-06-04  Nick Clifton  <nickc@redhat.com>
 526
 527         PR 18474
 528         * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
 529
 530 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 531
 532         * arm-dis.c (arm_opcodes): Add "setpan".
 533         (thumb_opcodes): Add "setpan".
 534
 535 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 536
 537         * arm-dis.c (select_arm_features): Rework to avoid used of redefined
 538         macros.
 539
 540 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 541
 542         * aarch64-tbl.h (aarch64_feature_rdma): New.
 543         (RDMA): New.
 544         (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
 545         * aarch64-asm-2.c: Regenerate.
 546         * aarch64-dis-2.c: Regenerate.
 547         * aarch64-opc-2.c: Regenerate.
 548
 549 2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
 550
 551         * aarch64-tbl.h (aarch64_feature_lor): New.
 552         (LOR): New.
 553         (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
 554         "stllrb", "stllrh".
 555         * aarch64-asm-2.c: Regenerate.
 556         * aarch64-dis-2.c: Regenerate.
 557         * aarch64-opc-2.c: Regenerate.
 558
 559 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 560
 561         * aarch64-opc.c (F_ARCHEXT): New.
 562         (aarch64_sys_regs): Add "pan".
 563         (aarch64_sys_reg_supported_p): New.
 564         (aarch64_pstatefields): Add "pan".
 565         (aarch64_pstatefield_supported_p): New.
 566
 567 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 568
 569         * i386-tbl.h: Regenerate.
 570
 571 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 572
 573         * i386-dis.c (print_insn): Swap rounding mode specifier and
 574         general purpose register in Intel mode.
 575
 576 2015-06-01  Jan Beulich  <jbeulich@suse.com>
 577
 578         * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
 579         * i386-tbl.h: Regenerate.
 580
 581 2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>
 582
 583         * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
 584         * i386-init.h: Regenerated.
 585
 586 2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 587
 588         PR binutis/18386
 589         * i386-dis.c: Add comments for '@'.
 590         (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
 591         (enum x86_64_isa): New.
 592         (isa64): Likewise.
 593         (print_i386_disassembler_options): Add amd64 and intel64.
 594         (print_insn): Handle amd64 and intel64.
 595         (putop): Handle '@'.
 596         (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
 597         * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
 598         * i386-opc.h (AMD64): New.
 599         (CpuIntel64): Likewise.
 600         (i386_cpu_flags): Add cpuamd64 and cpuintel64.
 601         * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
 602         Mark direct call/jmp without Disp16|Disp32 as Intel64.
 603         * i386-init.h: Regenerated.
 604         * i386-tbl.h: Likewise.
 605
 606 2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>
 607
 608         * ppc-opc.c (IH) New define.
 609         (powerpc_opcodes) <wait>: Do not enable for POWER7.
 610         <tlbie>: Add RS operand for POWER7.
 611         <slbia>: Add IH operand for POWER6.
 612
 613 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 614
 615         * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
 616         direct branch.
 617         (jmp): Likewise.
 618         * i386-tbl.h: Regenerated.
 619
 620 2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>
 621
 622         * configure.ac: Support bfd_iamcu_arch.
 623         * disassemble.c (disassembler): Support bfd_iamcu_arch.
 624         * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
 625         CPU_IAMCU_COMPAT_FLAGS.
 626         (cpu_flags): Add CpuIAMCU.
 627         * i386-opc.h (CpuIAMCU): New.
 628         (i386_cpu_flags): Add cpuiamcu.
 629         * configure: Regenerated.
 630         * i386-init.h: Likewise.
 631         * i386-tbl.h: Likewise.
 632
 633 2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>
 634
 635         PR binutis/18386
 636         * i386-dis.c (X86_64_E8): New.
 637         (X86_64_E9): Likewise.
 638         Update comments on 'T', 'U', 'V'.  Add comments for '^'.
 639         (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
 640         (x86_64_table): Add X86_64_E8 and X86_64_E9.
 641         (mod_table): Replace {T|} with ^ on Jcall/Jmp.
 642         (putop): Handle '^'.
 643         (OP_J): Ignore the operand size prefix in 64-bit.  Don't check
 644         REX_W.
 645
 646 2015-04-30  DJ Delorie  <dj@redhat.com>
 647
 648         * disassemble.c (disassembler): Choose suitable disassembler based
 649         on E_ABI.
 650         * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
 651         it to decode mul/div insns.
 652         * rl78-decode.c: Regenerate.
 653         * rl78-dis.c (print_insn_rl78): Rename to...
 654         (print_insn_rl78_common): ...this, take ISA parameter.
 655         (print_insn_rl78): New.
 656         (print_insn_rl78_g10): New.
 657         (print_insn_rl78_g13): New.
 658         (print_insn_rl78_g14): New.
 659         (rl78_get_disassembler): New.
 660
 661 2015-04-29  Nick Clifton  <nickc@redhat.com>
 662
 663         * po/fr.po: Updated French translation.
 664
 665 2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>
 666
 667         * ppc-opc.c (DCBT_EO): New define.
 668         (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
 669         <lharx>: Likewise.
 670         <stbcx.>: Likewise.
 671         <sthcx.>: Likewise.
 672         <waitrsv>: Do not enable for POWER7 and later.
 673         <waitimpl>: Likewise.
 674         <dcbt>: Default to the two operand form of the instruction for all
 675         "old" cpus.  For "new" cpus, use the operand ordering that matches
 676         whether the cpu is server or embedded.
 677         <dcbtst>: Likewise.
 678
 679 2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 680
 681         * s390-opc.c: New instruction type VV0UU2.
 682         * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
 683         and WFC.
 684
 685 2015-04-23  Jan Beulich  <jbeulich@suse.com>
 686
 687         * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
 688         * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
 689         vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
 690         (vfpclasspd, vfpclassps): Add %XZ.
 691
 692 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 693
 694         * i386-dis.c (PREFIX_UD_SHIFT): Removed.
 695         (PREFIX_UD_REPZ): Likewise.
 696         (PREFIX_UD_REPNZ): Likewise.
 697         (PREFIX_UD_DATA): Likewise.
 698         (PREFIX_UD_ADDR): Likewise.
 699         (PREFIX_UD_LOCK): Likewise.
 700
 701 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 702
 703         * i386-dis.c (prefix_requirement): Removed.
 704         (print_insn): Don't set prefix_requirement.  Check
 705         dp->prefix_requirement instead of prefix_requirement.
 706
 707 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 708
 709         PR binutils/17898
 710         * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
 711         (PREFIX_MOD_0_0FC7_REG_6): This.
 712         (PREFIX_MOD_3_0FC7_REG_6): New.
 713         (PREFIX_MOD_3_0FC7_REG_7): Likewise.
 714         (prefix_table): Replace PREFIX_0FC7_REG_6 with
 715         PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
 716         PREFIX_MOD_3_0FC7_REG_7.
 717         (mod_table): Replace PREFIX_0FC7_REG_6 with
 718         PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
 719         PREFIX_MOD_3_0FC7_REG_7.
 720
 721 2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 722
 723         * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
 724         (PREFIX_MANDATORY_REPNZ): Likewise.
 725         (PREFIX_MANDATORY_DATA): Likewise.
 726         (PREFIX_MANDATORY_ADDR): Likewise.
 727         (PREFIX_MANDATORY_LOCK): Likewise.
 728         (PREFIX_MANDATORY): Likewise.
 729         (PREFIX_UD_SHIFT): Set to 8
 730         (PREFIX_UD_REPZ): Updated.
 731         (PREFIX_UD_REPNZ): Likewise.
 732         (PREFIX_UD_DATA): Likewise.
 733         (PREFIX_UD_ADDR): Likewise.
 734         (PREFIX_UD_LOCK): Likewise.
 735         (PREFIX_IGNORED_SHIFT): New.
 736         (PREFIX_IGNORED_REPZ): Likewise.
 737         (PREFIX_IGNORED_REPNZ): Likewise.
 738         (PREFIX_IGNORED_DATA): Likewise.
 739         (PREFIX_IGNORED_ADDR): Likewise.
 740         (PREFIX_IGNORED_LOCK): Likewise.
 741         (PREFIX_OPCODE): Likewise.
 742         (PREFIX_IGNORED): Likewise.
 743         (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
 744         (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 745         (three_byte_table): Likewise.
 746         (mod_table): Likewise.
 747         (mandatory_prefix): Renamed to ...
 748         (prefix_requirement): This.
 749         (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
 750         Update PREFIX_90 entry.
 751         (get_valid_dis386): Check prefix_requirement to see if a prefix
 752         should be ignored.
 753         (print_insn): Replace mandatory_prefix with prefix_requirement.
 754
 755 2015-04-15  Renlin Li  <renlin.li@arm.com>
 756
 757         * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
 758         use it for ssat and ssat16.
 759         (print_insn_thumb32): Add handle case for 'D' control code.
 760
 761 2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
 762             H.J. Lu  <hongjiu.lu@intel.com>
 763
 764         * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
 765         * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
 766         PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
 767         PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
 768         PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
 769         (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
 770         Fill prefix_requirement field.
 771         (struct dis386): Add prefix_requirement field.
 772         (dis386): Fill prefix_requirement field.
 773         (dis386_twobyte): Ditto.
 774         (twobyte_has_mandatory_prefix_: Remove.
 775         (reg_table): Fill prefix_requirement field.
 776         (prefix_table): Ditto.
 777         (x86_64_table): Ditto.
 778         (three_byte_table): Ditto.
 779         (xop_table): Ditto.
 780         (vex_table): Ditto.
 781         (vex_len_table): Ditto.
 782         (vex_w_table): Ditto.
 783         (mod_table): Ditto.
 784         (bad_opcode): Ditto.
 785         (print_insn): Use prefix_requirement.
 786         (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
 787         FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
 788         (float_reg): Ditto.
 789
 790 2015-03-30  Mike Frysinger  <vapier@gentoo.org>
 791
 792         * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
 793
 794 2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 795
 796         * Makefile.in: Regenerated.
 797
 798 2015-03-25  Anton Blanchard  <anton@samba.org>
 799
 800         * ppc-dis.c (disassemble_init_powerpc): Only initialise
 801         powerpc_opcd_indices and vle_opcd_indices once.
 802
 803 2015-03-25  Anton Blanchard  <anton@samba.org>
 804
 805         * ppc-opc.c (powerpc_opcodes): Add slbfee.
 806
 807 2015-03-24  Terry Guo  <terry.guo@arm.com>
 808
 809         * arm-dis.c (opcode32): Updated to use new arm feature struct.
 810         (opcode16): Likewise.
 811         (coprocessor_opcodes): Replace bit with feature struct.
 812         (neon_opcodes): Likewise.
 813         (arm_opcodes): Likewise.
 814         (thumb_opcodes): Likewise.
 815         (thumb32_opcodes): Likewise.
 816         (print_insn_coprocessor): Likewise.
 817         (print_insn_arm): Likewise.
 818         (select_arm_features): Follow new feature struct.
 819
 820 2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>
 821
 822         * i386-dis.c (rm_table): Add clzero.
 823         * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
 824         Add CPU_CLZERO_FLAGS.
 825         (cpu_flags): Add CpuCLZERO.
 826         * i386-opc.h: Add CpuCLZERO.
 827         * i386-opc.tbl: Add clzero.
 828         * i386-init.h: Re-generated.
 829         * i386-tbl.h: Re-generated.
 830
 831 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 832
 833         * mips-opc.c (decode_mips_operand): Fix constraint issues
 834         with u and y operands.
 835
 836 2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>
 837
 838         * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
 839
 840 2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 841
 842         * s390-opc.c: Add new IBM z13 instructions.
 843         * s390-opc.txt: Likewise.
 844
 845 2015-03-10  Renlin Li  <renlin.li@arm.com>
 846
 847         * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
 848         stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
 849         related alias.
 850         * aarch64-asm-2.c: Regenerate.
 851         * aarch64-dis-2.c: Likewise.
 852         * aarch64-opc-2.c: Likewise.
 853
 854 2015-03-03  Jiong Wang  <jiong.wang@arm.com>
 855
 856         * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
 857
 858 2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>
 859
 860         * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
 861         arch_sh_up.
 862         (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
 863         arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
 864
 865 2015-02-23  Vinay  <Vinay.G@kpit.com>
 866
 867         * rl78-decode.opc (MOV): Added space between two operands for
 868         'mov' instruction in index addressing mode.
 869         * rl78-decode.c: Regenerate.
 870
 871 2015-02-19  Pedro Alves  <palves@redhat.com>
 872
 873         * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
 874
 875 2015-02-10  Pedro Alves  <palves@redhat.com>
 876             Tom Tromey  <tromey@redhat.com>
 877
 878         * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
 879         microblaze_and, microblaze_xor.
 880         * microblaze-opc.h (opcodes): Adjust.
 881
 882 2015-01-28  James Bowman  <james.bowman@ftdichip.com>
 883
 884         * Makefile.am: Add FT32 files.
 885         * configure.ac: Handle FT32.
 886         * disassemble.c (disassembler): Call print_insn_ft32.
 887         * ft32-dis.c: New file.
 888         * ft32-opc.c: New file.
 889         * Makefile.in: Regenerate.
 890         * configure: Regenerate.
 891         * po/POTFILES.in: Regenerate.
 892
 893 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
 894
 895         * nds32-asm.c (keyword_sr): Add new system registers.
 896
 897 2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 898
 899         * s390-dis.c (s390_extract_operand): Support vector register
 900         operands.
 901         (s390_print_insn_with_opcode): Support new operands types and add
 902         new handling of optional operands.
 903         * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
 904         and include opcode/s390.h instead.
 905         (struct op_struct): New field `flags'.
 906         (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
 907         (dumpTable): Dump flags.
 908         (main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
 909         string.
 910         * s390-opc.c: Add new operands types, instruction formats, and
 911         instruction masks.
 912         (s390_opformats): Add new formats for .insn.
 913         * s390-opc.txt: Add new instructions.
 914
 915 2015-01-01  Alan Modra  <amodra@gmail.com>
 916
 917         Update year range in copyright notice of all files.
 918
 919 For older changes see ChangeLog-2014
 920 \f
 921 Copyright (C) 2015 Free Software Foundation, Inc.
 922
 923 Copying and distribution of this file, with or without modification,
 924 are permitted in any medium without royalty provided the copyright
 925 notice and this notice are preserved.
 926
 927 Local Variables:
 928 mode: change-log
 929 left-margin: 8
 930 fill-column: 74
 931 version-control: never
 932 End: