opcodes/ChangeLog

   1 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
   2
   3         * micromips-opc.c (WR_mhi): Rename to..
   4         (WR_mh): ...this.
   5         (micromips_opcodes): Update "movep" entry accordingly.  Replace
   6         "mh,mi" with "mh".
   7         * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
   8         (micromips_to_32_reg_h_map1): ...this.
   9         (micromips_to_32_reg_i_map): Rename to...
  10         (micromips_to_32_reg_h_map2): ...this.
  11         (print_micromips_insn): Remove "mi" case.  Print both registers
  12         in the pair for "mh".
  13
  14 2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
  15
  16         * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
  17         * micromips-opc.c (micromips_opcodes): Likewise.
  18         * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
  19         and "+T" handling.  Check for a "0" suffix when deciding whether to
  20         use coprocessor 0 names.  In that case, also check for ",H" selectors.
  21
  22 2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  23
  24         * s390-opc.c (J12_12, J24_24): New macros.
  25         (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
  26         (MASK_MII_UPI): Rename to MASK_MII_UPP.
  27         * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
  28
  29 2013-07-04  Alan Modra  <amodra@gmail.com>
  30
  31         * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
  32
  33 2013-06-26  Nick Clifton  <nickc@redhat.com>
  34
  35         * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
  36         field when checking for type 2 nop.
  37         * rx-decode.c: Regenerate.
  38
  39 2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
  40
  41         * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
  42         and "movep" macros.
  43
  44 2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
  45
  46         * mips-dis.c (is_mips16_plt_tail): New function.
  47         (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
  48         word.
  49         (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
  50
  51 2013-06-21  DJ Delorie  <dj@redhat.com>
  52
  53         * msp430-decode.opc: New.
  54         * msp430-decode.c: New/generated.
  55         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
  56         (MAINTAINER_CLEANFILES): Likewise.
  57         Add rule to build msp430-decode.c frommsp430decode.opc
  58         using the opc2c program.
  59         * Makefile.in: Regenerate.
  60         * configure.in: Add msp430-decode.lo to msp430 architecture files.
  61         * configure: Regenerate.
  62
  63 2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
  64
  65         * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
  66         (SYMTAB_AVAILABLE): Removed.
  67         (#include "elf/aarch64.h): Ditto.
  68
  69 2013-06-17  Catherine Moore  <clm@codesourcery.com>
  70             Maciej W. Rozycki  <macro@codesourcery.com>
  71             Chao-Ying Fu  <fu@mips.com>
  72
  73         * micromips-opc.c (EVA): Define.
  74         (TLBINV): Define.
  75         (micromips_opcodes): Add EVA opcodes.
  76         * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
  77         (print_insn_args): Handle EVA offsets.
  78         (print_insn_micromips): Likewise.
  79         * mips-opc.c (EVA): Define.
  80         (TLBINV): Define.
  81         (mips_builtin_opcodes): Add EVA opcodes.
  82
  83 2013-06-17  Alan Modra  <amodra@gmail.com>
  84
  85         * Makefile.am (mips-opc.lo): Add rules to create automatic
  86         dependency files.  Pass archdefs.
  87         (micromips-opc.lo, mips16-opc.lo): Likewise.
  88         * Makefile.in: Regenerate.
  89
  90 2013-06-14  DJ Delorie  <dj@redhat.com>
  91
  92         * rx-decode.opc (rx_decode_opcode): Bit operations on
  93         registers are 32-bit operations, not 8-bit operations.
  94         * rx-decode.c: Regenerate.
  95
  96 2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
  97
  98         * micromips-opc.c (IVIRT): New define.
  99         (IVIRT64): New define.
 100         (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 101         tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
 102
 103         * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
 104         dmtgc0 to print cp0 names.
 105
 106 2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
 107
 108         * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
 109         argument.
 110
 111 2013-06-08  Catherine Moore  <clm@codesourcery.com>
 112             Richard Sandiford  <rdsandiford@googlemail.com>
 113
 114         * micromips-opc.c (D32, D33, MC): Update definitions.
 115         (micromips_opcodes):  Initialize ase field.
 116         * mips-dis.c (mips_arch_choice): Add ase field.
 117         (mips_arch_choices): Initialize ase field.
 118         (set_default_mips_dis_options): Declare and setup mips_ase.
 119         * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
 120         MT32, MC): Update definitions.
 121         (mips_builtin_opcodes): Initialize ase field.
 122
 123 2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
 124
 125         * s390-opc.txt (flogr): Require a register pair destination.
 126
 127 2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 128
 129         * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
 130         instruction format.
 131
 132 2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
 133
 134         * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
 135
 136 2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
 137
 138         * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
 139         * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
 140         XLS_MASK, PPCVSX2): New defines.
 141         (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
 142         fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
 143         mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
 144         mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
 145         mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
 146         vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
 147         vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
 148         vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
 149         vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
 150         vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
 151         vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
 152         vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
 153         vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
 154         vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
 155         xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
 156         xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
 157         xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
 158         xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
 159         <lxvx, stxvx>: New extended mnemonics.
 160
 161 2013-05-17  Alan Modra  <amodra@gmail.com>
 162
 163         * ia64-raw.tbl: Replace non-ASCII char.
 164         * ia64-waw.tbl: Likewise.
 165         * ia64-asmtab.c: Regenerate.
 166
 167 2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 168
 169         * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
 170         * i386-init.h: Regenerated.
 171
 172 2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
 173
 174         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
 175         * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
 176         check from [0, 255] to [-128, 255].
 177
 178 2013-05-09  Andrew Pinski  <apinski@cavium.com>
 179
 180         * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
 181         Add INSN_VIRT and INSN_VIRT64 to mips64r2.
 182         (parse_mips_dis_option): Handle the virt option.
 183         (print_insn_args): Handle "+J".
 184         (print_mips_disassembler_options): Print out message about virt64.
 185         * mips-opc.c (IVIRT): New define.
 186         (IVIRT64): New define.
 187         (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
 188         tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
 189         Move rfe to the bottom as it conflicts with tlbgp.
 190
 191 2013-05-09  Alan Modra  <amodra@gmail.com>
 192
 193         * ppc-opc.c (extract_vlesi): Properly sign extend.
 194         (extract_vlensi): Likewise.  Comment reason for setting invalid.
 195
 196 2013-05-02  Nick Clifton  <nickc@redhat.com>
 197
 198         * msp430-dis.c: Add support for MSP430X instructions.
 199
 200 2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
 201
 202         * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
 203         to "eccinj".
 204
 205 2013-04-17  Wei-chen Wang  <cole945@gmail.com>
 206
 207         PR binutils/15369
 208         * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
 209         of CGEN_CPU_ENDIAN.
 210         (hash_insns_list): Likewise.
 211
 212 2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
 213
 214         * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
 215         warning workaround.
 216
 217 2013-04-08  Jan Beulich <jbeulich@suse.com>
 218
 219         * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
 220         * i386-tbl.h: Re-generate.
 221
 222 2013-04-06  David S. Miller  <davem@davemloft.net>
 223
 224         * sparc-dis.c (compare_opcodes): When encountering multiple aliases
 225         of an opcode, prefer the one with F_PREFERRED set.
 226         * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
 227         lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
 228         ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
 229         mark existing mnenomics as aliases.  Add "cc" suffix to edge
 230         instructions generating condition codes, mark existing mnenomics
 231         as aliases.  Add "fp" prefix to VIS compare instructions, mark
 232         existing mnenomics as aliases.
 233
 234 2013-04-03  Nick Clifton  <nickc@redhat.com>
 235
 236         * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
 237         destination address by subtracting the operand from the current
 238         address.
 239         * v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
 240         a positive value in the insn.
 241         (extract_u16_loop): Do not negate the returned value.
 242         (D16_LOOP): Add V850_INVERSE_PCREL flag.
 243
 244         (ceilf.sw): Remove duplicate entry.
 245         (cvtf.hs): New entry.
 246         (cvtf.sh): Likewise.
 247         (fmaf.s): Likewise.
 248         (fmsf.s): Likewise.
 249         (fnmaf.s): Likewise.
 250         (fnmsf.s): Likewise.
 251         (maddf.s): Restrict to E3V5 architectures.
 252         (msubf.s): Likewise.
 253         (nmaddf.s): Likewise.
 254         (nmsubf.s): Likewise.
 255
 256 2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
 257
 258         * i386-dis.c (get_sib): Add the sizeflag argument.  Properly
 259         check address mode.
 260         (print_insn): Pass sizeflag to get_sib.
 261
 262 2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
 263
 264         PR binutils/15068
 265         * tic6x-dis.c: Add support for displaying 16-bit insns.
 266
 267 2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
 268
 269         PR gas/15095
 270         * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
 271         individual msb and lsb halves in src1 & src2 fields.  Discard the
 272         src1 (lsb) value and only use src2 (msb), discarding bit 0, to
 273         follow what Ti SDK does in that case as any value in the src1
 274         field yields the same output with SDK disassembler.
 275
 276 2013-03-12  Michael Eager <eager@eagercon.com>
 277
 278         * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
 279
 280 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 281
 282         * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
 283
 284 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 285
 286         * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
 287
 288 2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
 289
 290         * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
 291
 292 2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 293
 294         * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
 295         (thumb32_opcodes): Likewise.
 296         (print_insn_thumb32): Handle 'S' control char.
 297
 298 2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
 299
 300         * lm32-desc.c: Regenerate.
 301
 302 2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 303
 304         * i386-reg.tbl (riz): Add RegRex64.
 305         * i386-tbl.h: Regenerated.
 306
 307 2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
 308
 309         * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
 310         (aarch64_feature_crc): New static.
 311         (CRC): New macro.
 312         (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
 313         crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
 314         * aarch64-asm-2.c: Re-generate.
 315         * aarch64-dis-2.c: Ditto.
 316         * aarch64-opc-2.c: Ditto.
 317
 318 2013-02-27  Alan Modra  <amodra@gmail.com>
 319
 320         * rl78-decode.opc (rl78_decode_opcode): Fix typo.
 321         * rl78-decode.c: Regenerate.
 322
 323 2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
 324
 325         * rl78-decode.opc: Fix encoding of DIVWU insn.
 326         * rl78-decode.c: Regenerate.
 327
 328 2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
 329
 330         PR gas/15159
 331         * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
 332
 333         * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
 334         (cpu_flags): Add CpuSMAP.
 335
 336         * i386-opc.h (CpuSMAP): New.
 337         (i386_cpu_flags): Add cpusmap.
 338
 339         * i386-opc.tbl: Add clac and stac.
 340
 341         * i386-init.h: Regenerated.
 342         * i386-tbl.h: Likewise.
 343
 344 2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
 345
 346         * metag-dis.c: Initialize outf->bytes_per_chunk to 4
 347         which also makes the disassembler output be in little
 348         endian like it should be.
 349
 350 2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
 351
 352         * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
 353         fields to NULL.
 354         (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
 355
 356 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
 357
 358         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
 359         section disassembled.
 360
 361 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 362
 363         * arm-dis.c: Update strht pattern.
 364
 365 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
 366
 367         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
 368         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
 369         trunc.w.s macro for EE.
 370
 371 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
 372             Andrew Jenner <andrew@codesourcery.com>
 373
 374         Based on patches from Altera Corporation.
 375
 376         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
 377         nios2-opc.c.
 378         * Makefile.in: Regenerated.
 379         * configure.in: Add case for bfd_nios2_arch.
 380         * configure: Regenerated.
 381         * disassemble.c (ARCH_nios2): Define.
 382         (disassembler): Add case for bfd_arch_nios2.
 383         * nios2-dis.c: New file.
 384         * nios2-opc.c: New file.
 385
 386 2013-02-04  Alan Modra  <amodra@gmail.com>
 387
 388         * po/POTFILES.in: Regenerate.
 389         * rl78-decode.c: Regenerate.
 390         * rx-decode.c: Regenerate.
 391
 392 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
 393
 394         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
 395         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
 396         * aarch64-asm.c (convert_xtl_to_shll): New function.
 397         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 398         calling convert_xtl_to_shll.
 399         * aarch64-dis.c (convert_shll_to_xtl): New function.
 400         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
 401         calling convert_shll_to_xtl.
 402         * aarch64-gen.c: Update copyright year.
 403         * aarch64-asm-2.c: Re-generate.
 404         * aarch64-dis-2.c: Re-generate.
 405         * aarch64-opc-2.c: Re-generate.
 406
 407 2013-01-24  Nick Clifton  <nickc@redhat.com>
 408
 409         * v850-dis.c: Add support for e3v5 architecture.
 410         * v850-opc.c: Likewise.
 411
 412 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
 413
 414         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
 415         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
 416         * aarch64-opc.c (operand_general_constraint_met_p): For
 417         AARCH64_MOD_LSL, move the range check on the shift amount before the
 418         alignment check; change to call set_sft_amount_out_of_range_error
 419         instead of set_imm_out_of_range_error.
 420         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
 421         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
 422         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
 423         SIMD_IMM_SFT.
 424
 425 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
 426
 427         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
 428
 429         * i386-init.h: Regenerated.
 430         * i386-tbl.h: Likewise.
 431
 432 2013-01-15  Nick Clifton  <nickc@redhat.com>
 433
 434         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
 435         values.
 436         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
 437
 438 2013-01-14  Will Newton <will.newton@imgtec.com>
 439
 440         * metag-dis.c (REG_WIDTH): Increase to 64.
 441
 442 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
 443
 444         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
 445         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
 446         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
 447         (SH6): Update.
 448         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
 449         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
 450         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
 451         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
 452
 453 2013-01-10  Will Newton <will.newton@imgtec.com>
 454
 455         * Makefile.am: Add Meta.
 456         * configure.in: Add Meta.
 457         * disassemble.c: Add Meta support.
 458         * metag-dis.c: New file.
 459         * Makefile.in: Regenerate.
 460         * configure: Regenerate.
 461
 462 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 463
 464         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 465         (match_opcode): Rename to cr16_match_opcode.
 466
 467 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 468
 469         * mips-dis.c: Add names for CP0 registers of r5900.
 470         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 471         instructions sq and lq.
 472         Add support for MIPS r5900 CPU.
 473         Add support for 128 bit MMI (Multimedia Instructions).
 474         Add support for EE instructions (Emotion Engine).
 475         Disable unsupported floating point instructions (64 bit and
 476         undefined compare operations).
 477         Enable instructions of MIPS ISA IV which are supported by r5900.
 478         Disable 64 bit co processor instructions.
 479         Disable 64 bit multiplication and division instructions.
 480         Disable instructions for co-processor 2 and 3, because these are
 481         not supported (preparation for later VU0 support (Vector Unit)).
 482         Disable cvt.w.s because this behaves like trunc.w.s and the
 483         correct execution can't be ensured on r5900.
 484         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 485         will confuse less developers and compilers.
 486
 487 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 488
 489         * aarch64-opc.c (aarch64_print_operand): Change to print
 490         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 491         in comment.
 492         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 493         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 494         OP_MOV_IMM_WIDE.
 495
 496 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 497
 498         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 499         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 500
 501 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 502
 503         * i386-gen.c (process_copyright): Update copyright year to 2013.
 504
 505 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 506
 507         * cr16-dis.c (match_opcode,make_instruction): Remove static
 508         declaration.
 509         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 510         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 511
 512 For older changes see ChangeLog-2012
 513 \f
 514 Copyright (C) 2013 Free Software Foundation, Inc.
 515
 516 Copying and distribution of this file, with or without modification,
 517 are permitted in any medium without royalty provided the copyright
 518 notice and this notice are preserved.
 519
 520 Local Variables:
 521 mode: change-log
 522 left-margin: 8
 523 fill-column: 74
 524 version-control: never
 525 End: