1 2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
3 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
4 (cgen_put_insn_value): Likewise.
5 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
6 * cgen-dis.in (print_insn): Likewise.
7 * cgen-ibld.in (insert_1): Likewise.
9 (insert_insn_normal): Likewise.
10 (extract_1): Likewise.
11 * bpf-dis.c: Regenerate.
12 * bpf-ibld.c: Likewise.
13 * bpf-ibld.c: Likewise.
14 * cgen-dis.in: Likewise.
15 * cgen-ibld.in: Likewise.
16 * cgen-opc.c: Likewise.
17 * epiphany-dis.c: Likewise.
18 * epiphany-ibld.c: Likewise.
19 * fr30-dis.c: Likewise.
20 * fr30-ibld.c: Likewise.
21 * frv-dis.c: Likewise.
22 * frv-ibld.c: Likewise.
23 * ip2k-dis.c: Likewise.
24 * ip2k-ibld.c: Likewise.
25 * iq2000-dis.c: Likewise.
26 * iq2000-ibld.c: Likewise.
27 * lm32-dis.c: Likewise.
28 * lm32-ibld.c: Likewise.
29 * m32c-dis.c: Likewise.
30 * m32c-ibld.c: Likewise.
31 * m32r-dis.c: Likewise.
32 * m32r-ibld.c: Likewise.
33 * mep-dis.c: Likewise.
34 * mep-ibld.c: Likewise.
36 * mt-ibld.c: Likewise.
37 * or1k-dis.c: Likewise.
38 * or1k-ibld.c: Likewise.
39 * xc16x-dis.c: Likewise.
40 * xc16x-ibld.c: Likewise.
41 * xstormy16-dis.c: Likewise.
42 * xstormy16-ibld.c: Likewise.
44 2020-06-04 Jose E. Marchesi <jemarch@gnu.org>
46 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
47 (print_insn_): Handle instruction endian.
48 * bpf-dis.c: Regenerate.
49 * bpf-desc.c: Regenerate.
50 * epiphany-dis.c: Likewise.
51 * epiphany-desc.c: Likewise.
52 * fr30-dis.c: Likewise.
53 * fr30-desc.c: Likewise.
54 * frv-dis.c: Likewise.
55 * frv-desc.c: Likewise.
56 * ip2k-dis.c: Likewise.
57 * ip2k-desc.c: Likewise.
58 * iq2000-dis.c: Likewise.
59 * iq2000-desc.c: Likewise.
60 * lm32-dis.c: Likewise.
61 * lm32-desc.c: Likewise.
62 * m32c-dis.c: Likewise.
63 * m32c-desc.c: Likewise.
64 * m32r-dis.c: Likewise.
65 * m32r-desc.c: Likewise.
66 * mep-dis.c: Likewise.
67 * mep-desc.c: Likewise.
69 * mt-desc.c: Likewise.
70 * or1k-dis.c: Likewise.
71 * or1k-desc.c: Likewise.
72 * xc16x-dis.c: Likewise.
73 * xc16x-desc.c: Likewise.
74 * xstormy16-dis.c: Likewise.
75 * xstormy16-desc.c: Likewise.
77 2020-06-03 Nick Clifton <nickc@redhat.com>
79 * po/sr.po: Updated Serbian translation.
81 2020-06-03 Nelson Chu <nelson.chu@sifive.com>
83 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
84 (riscv_get_priv_spec_class): Likewise.
86 2020-06-01 Alan Modra <amodra@gmail.com>
88 * bpf-desc.c: Regenerate.
90 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
91 David Faust <david.faust@oracle.com>
93 * bpf-desc.c: Regenerate.
94 * bpf-opc.h: Likewise.
95 * bpf-opc.c: Likewise.
96 * bpf-dis.c: Likewise.
98 2020-05-28 Alan Modra <amodra@gmail.com>
100 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
103 2020-05-28 Alan Modra <amodra@gmail.com>
105 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
107 (print_insn_ns32k): Revert last change.
109 2020-05-28 Nick Clifton <nickc@redhat.com>
111 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
114 2020-05-26 Sandra Loosemore <sandra@codesourcery.com>
116 Fix extraction of signed constants in nios2 disassembler (again).
118 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
119 extractions of signed fields.
121 2020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
123 * s390-opc.txt: Relocate vector load/store instructions with
124 additional alignment parameter and change architecture level
125 constraint from z14 to z13.
127 2020-05-21 Alan Modra <amodra@gmail.com>
129 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
130 * sparc-dis.c: Likewise.
131 * tic4x-dis.c: Likewise.
132 * xtensa-dis.c: Likewise.
133 * bpf-desc.c: Regenerate.
134 * epiphany-desc.c: Regenerate.
135 * fr30-desc.c: Regenerate.
136 * frv-desc.c: Regenerate.
137 * ip2k-desc.c: Regenerate.
138 * iq2000-desc.c: Regenerate.
139 * lm32-desc.c: Regenerate.
140 * m32c-desc.c: Regenerate.
141 * m32r-desc.c: Regenerate.
142 * mep-asm.c: Regenerate.
143 * mep-desc.c: Regenerate.
144 * mt-desc.c: Regenerate.
145 * or1k-desc.c: Regenerate.
146 * xc16x-desc.c: Regenerate.
147 * xstormy16-desc.c: Regenerate.
149 2020-05-20 Nelson Chu <nelson.chu@sifive.com>
151 * riscv-opc.c (riscv_ext_version_table): The table used to store
152 all information about the supported spec and the corresponding ISA
153 versions. Currently, only Zicsr is supported to verify the
154 correctness of Z sub extension settings. Others will be supported
155 in the future patches.
156 (struct isa_spec_t, isa_specs): List for all supported ISA spec
157 classes and the corresponding strings.
158 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
159 spec class by giving a ISA spec string.
160 * riscv-opc.c (struct priv_spec_t): New structure.
161 (struct priv_spec_t priv_specs): List for all supported privilege spec
162 classes and the corresponding strings.
163 (riscv_get_priv_spec_class): New function. Get the corresponding
164 privilege spec class by giving a spec string.
165 (riscv_get_priv_spec_name): New function. Get the corresponding
166 privilege spec string by giving a CSR version class.
167 * riscv-dis.c: Updated since DECLARE_CSR is changed.
168 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
169 according to the chosen version. Build a hash table riscv_csr_hash to
170 store the valid CSR for the chosen pirv verison. Dump the direct
171 CSR address rather than it's name if it is invalid.
172 (parse_riscv_dis_option_without_args): New function. Parse the options
174 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
175 parse the options without arguments first, and then handle the options
176 with arguments. Add the new option -Mpriv-spec, which has argument.
177 * riscv-dis.c (print_riscv_disassembler_options): Add description
178 about the new OBJDUMP option.
180 2020-05-19 Peter Bergner <bergner@linux.ibm.com>
182 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
183 WC values on POWER10 sync, dcbf and wait instructions.
184 (insert_pl, extract_pl): New functions.
185 (L2OPT, LS, WC): Use insert_ls and extract_ls.
186 (LS3): New , 3-bit L for sync.
187 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
188 (SC2, PL): New, 2-bit SC and PL for sync and wait.
189 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
190 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
191 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
192 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
193 <wait>: Enable PL operand on POWER10.
194 <dcbf>: Enable L3OPT operand on POWER10.
195 <sync>: Enable SC2 operand on POWER10.
197 2020-05-19 Stafford Horne <shorne@gmail.com>
200 * or1k-asm.c: Regenerate.
201 * or1k-desc.c: Regenerate.
202 * or1k-desc.h: Regenerate.
203 * or1k-dis.c: Regenerate.
204 * or1k-ibld.c: Regenerate.
205 * or1k-opc.c: Regenerate.
206 * or1k-opc.h: Regenerate.
207 * or1k-opinst.c: Regenerate.
209 2020-05-11 Alan Modra <amodra@gmail.com>
211 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
214 2020-05-11 Alan Modra <amodra@gmail.com>
216 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
217 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
219 2020-05-11 Alan Modra <amodra@gmail.com>
221 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
223 2020-05-11 Alan Modra <amodra@gmail.com>
225 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
226 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
228 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
230 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
233 2020-05-11 Alan Modra <amodra@gmail.com>
235 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
236 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
237 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
238 (prefix_opcodes): Add xxeval.
240 2020-05-11 Alan Modra <amodra@gmail.com>
242 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
243 xxgenpcvwm, xxgenpcvdm.
245 2020-05-11 Alan Modra <amodra@gmail.com>
247 * ppc-opc.c (MP, VXVAM_MASK): Define.
248 (VXVAPS_MASK): Use VXVA_MASK.
249 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
250 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
251 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
252 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
254 2020-05-11 Alan Modra <amodra@gmail.com>
255 Peter Bergner <bergner@linux.ibm.com>
257 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
259 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
260 YMSK2, XA6a, XA6ap, XB6a entries.
261 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
262 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
264 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
265 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
266 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
267 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
268 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
269 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
270 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
271 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
272 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
273 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
274 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
275 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
276 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
277 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
279 2020-05-11 Alan Modra <amodra@gmail.com>
281 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
282 (insert_xts, extract_xts): New functions.
283 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
284 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
285 (VXRC_MASK, VXSH_MASK): Define.
286 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
287 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
288 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
289 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
290 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
291 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
292 xxblendvh, xxblendvw, xxblendvd, xxpermx.
294 2020-05-11 Alan Modra <amodra@gmail.com>
296 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
297 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
298 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
299 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
300 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
302 2020-05-11 Alan Modra <amodra@gmail.com>
304 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
305 (XTP, DQXP, DQXP_MASK): Define.
306 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
307 (prefix_opcodes): Add plxvp and pstxvp.
309 2020-05-11 Alan Modra <amodra@gmail.com>
311 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
312 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
313 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
315 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
317 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
319 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
321 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
323 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
325 2020-05-11 Peter Bergner <bergner@linux.ibm.com>
327 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
329 2020-05-11 Alan Modra <amodra@gmail.com>
331 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
333 2020-05-11 Alan Modra <amodra@gmail.com>
335 * ppc-dis.c (ppc_opts): Add "power10" entry.
336 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
337 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
339 2020-05-11 Nick Clifton <nickc@redhat.com>
341 * po/fr.po: Updated French translation.
343 2020-04-30 Alex Coplan <alex.coplan@arm.com>
345 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
346 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
347 (operand_general_constraint_met_p): validate
348 AARCH64_OPND_UNDEFINED.
349 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
351 * aarch64-asm-2.c: Regenerated.
352 * aarch64-dis-2.c: Regenerated.
353 * aarch64-opc-2.c: Regenerated.
355 2020-04-29 Nick Clifton <nickc@redhat.com>
358 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
361 2020-04-29 Nick Clifton <nickc@redhat.com>
363 * po/sv.po: Updated Swedish translation.
365 2020-04-29 Nick Clifton <nickc@redhat.com>
368 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
369 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
370 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
373 2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
376 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
377 cmpi only on m68020up and cpu32.
379 2020-04-20 Sudakshina Das <sudi.das@arm.com>
381 * aarch64-asm.c (aarch64_ins_none): New.
382 * aarch64-asm.h (ins_none): New declaration.
383 * aarch64-dis.c (aarch64_ext_none): New.
384 * aarch64-dis.h (ext_none): New declaration.
385 * aarch64-opc.c (aarch64_print_operand): Update case for
386 AARCH64_OPND_BARRIER_PSB.
387 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
388 (AARCH64_OPERANDS): Update inserter/extracter for
389 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
390 * aarch64-asm-2.c: Regenerated.
391 * aarch64-dis-2.c: Regenerated.
392 * aarch64-opc-2.c: Regenerated.
394 2020-04-20 Sudakshina Das <sudi.das@arm.com>
396 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
397 (aarch64_feature_ras, RAS): Likewise.
398 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
399 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
400 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
401 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
402 * aarch64-asm-2.c: Regenerated.
403 * aarch64-dis-2.c: Regenerated.
404 * aarch64-opc-2.c: Regenerated.
406 2020-04-17 Fredrik Strupe <fredrik@strupe.net>
408 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
409 (print_insn_neon): Support disassembly of conditional
412 2020-02-16 David Faust <david.faust@oracle.com>
414 * bpf-desc.c: Regenerate.
415 * bpf-desc.h: Likewise.
416 * bpf-opc.c: Regenerate.
417 * bpf-opc.h: Likewise.
419 2020-04-07 Lili Cui <lili.cui@intel.com>
421 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
422 (prefix_table): New instructions (see prefixes above).
424 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
425 CPU_ANY_TSXLDTRK_FLAGS.
426 (cpu_flags): Add CpuTSXLDTRK.
427 * i386-opc.h (enum): Add CpuTSXLDTRK.
428 (i386_cpu_flags): Add cputsxldtrk.
429 * i386-opc.tbl: Add XSUSPLDTRK insns.
430 * i386-init.h: Regenerate.
431 * i386-tbl.h: Likewise.
433 2020-04-02 Lili Cui <lili.cui@intel.com>
435 * i386-dis.c (prefix_table): New instructions serialize.
436 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
437 CPU_ANY_SERIALIZE_FLAGS.
438 (cpu_flags): Add CpuSERIALIZE.
439 * i386-opc.h (enum): Add CpuSERIALIZE.
440 (i386_cpu_flags): Add cpuserialize.
441 * i386-opc.tbl: Add SERIALIZE insns.
442 * i386-init.h: Regenerate.
443 * i386-tbl.h: Likewise.
445 2020-03-26 Alan Modra <amodra@gmail.com>
447 * disassemble.h (opcodes_assert): Declare.
448 (OPCODES_ASSERT): Define.
449 * disassemble.c: Don't include assert.h. Include opintl.h.
450 (opcodes_assert): New function.
451 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
452 (bfd_h8_disassemble): Reduce size of data array. Correctly
453 calculate maxlen. Omit insn decoding when insn length exceeds
454 maxlen. Exit from nibble loop when looking for E, before
455 accessing next data byte. Move processing of E outside loop.
456 Replace tests of maxlen in loop with assertions.
458 2020-03-26 Alan Modra <amodra@gmail.com>
460 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
462 2020-03-25 Alan Modra <amodra@gmail.com>
464 * z80-dis.c (suffix): Init mybuf.
466 2020-03-22 Alan Modra <amodra@gmail.com>
468 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
469 successflly read from section.
471 2020-03-22 Alan Modra <amodra@gmail.com>
473 * arc-dis.c (find_format): Use ISO C string concatenation rather
474 than line continuation within a string. Don't access needs_limm
475 before testing opcode != NULL.
477 2020-03-22 Alan Modra <amodra@gmail.com>
479 * ns32k-dis.c (print_insn_arg): Update comment.
480 (print_insn_ns32k): Reduce size of index_offset array, and
481 initialize, passing -1 to print_insn_arg for args that are not
482 an index. Don't exit arg loop early. Abort on bad arg number.
484 2020-03-22 Alan Modra <amodra@gmail.com>
486 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
487 * s12z-opc.c: Formatting.
488 (operands_f): Return an int.
489 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
490 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
491 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
492 (exg_sex_discrim): Likewise.
493 (create_immediate_operand, create_bitfield_operand),
494 (create_register_operand_with_size, create_register_all_operand),
495 (create_register_all16_operand, create_simple_memory_operand),
496 (create_memory_operand, create_memory_auto_operand): Don't
497 segfault on malloc failure.
498 (z_ext24_decode): Return an int status, negative on fail, zero
500 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
501 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
502 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
503 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
504 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
505 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
506 (loop_primitive_decode, shift_decode, psh_pul_decode),
507 (bit_field_decode): Similarly.
508 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
509 to return value, update callers.
510 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
511 Don't segfault on NULL operand.
512 (decode_operation): Return OP_INVALID on first fail.
513 (decode_s12z): Check all reads, returning -1 on fail.
515 2020-03-20 Alan Modra <amodra@gmail.com>
517 * metag-dis.c (print_insn_metag): Don't ignore status from
520 2020-03-20 Alan Modra <amodra@gmail.com>
522 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
523 Initialize parts of buffer not written when handling a possible
524 2-byte insn at end of section. Don't attempt decoding of such
525 an insn by the 4-byte machinery.
527 2020-03-20 Alan Modra <amodra@gmail.com>
529 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
530 partially filled buffer. Prevent lookup of 4-byte insns when
531 only VLE 2-byte insns are possible due to section size. Print
532 ".word" rather than ".long" for 2-byte leftovers.
534 2020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
537 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
539 2020-03-13 Jan Beulich <jbeulich@suse.com>
541 * i386-dis.c (X86_64_0D): Rename to ...
542 (X86_64_0E): ... this.
544 2020-03-09 H.J. Lu <hongjiu.lu@intel.com>
546 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
547 * Makefile.in: Regenerated.
549 2020-03-09 Jan Beulich <jbeulich@suse.com>
551 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
553 * i386-tbl.h: Re-generate.
555 2020-03-09 Jan Beulich <jbeulich@suse.com>
557 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
558 vprot*, vpsha*, and vpshl*.
559 * i386-tbl.h: Re-generate.
561 2020-03-09 Jan Beulich <jbeulich@suse.com>
563 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
564 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
565 * i386-tbl.h: Re-generate.
567 2020-03-09 Jan Beulich <jbeulich@suse.com>
569 * i386-gen.c (set_bitfield): Ignore zero-length field names.
570 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
571 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
572 * i386-tbl.h: Re-generate.
574 2020-03-09 Jan Beulich <jbeulich@suse.com>
576 * i386-gen.c (struct template_arg, struct template_instance,
577 struct template_param, struct template, templates,
578 parse_template, expand_templates): New.
579 (process_i386_opcodes): Various local variables moved to
580 expand_templates. Call parse_template and expand_templates.
581 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
582 * i386-tbl.h: Re-generate.
584 2020-03-06 Jan Beulich <jbeulich@suse.com>
586 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
587 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
588 register and memory source templates. Replace VexW= by VexW*
590 * i386-tbl.h: Re-generate.
592 2020-03-06 Jan Beulich <jbeulich@suse.com>
594 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
595 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
596 * i386-tbl.h: Re-generate.
598 2020-03-06 Jan Beulich <jbeulich@suse.com>
600 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
601 * i386-tbl.h: Re-generate.
603 2020-03-06 Jan Beulich <jbeulich@suse.com>
605 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
606 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
607 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
608 VexW0 on SSE2AVX variants.
609 (vmovq): Drop NoRex64 from XMM/XMM variants.
610 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
611 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
612 applicable use VexW0.
613 * i386-tbl.h: Re-generate.
615 2020-03-06 Jan Beulich <jbeulich@suse.com>
617 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
618 * i386-opc.h (Rex64): Delete.
619 (struct i386_opcode_modifier): Remove rex64 field.
620 * i386-opc.tbl (crc32): Drop Rex64.
621 Replace Rex64 with Size64 everywhere else.
622 * i386-tbl.h: Re-generate.
624 2020-03-06 Jan Beulich <jbeulich@suse.com>
626 * i386-dis.c (OP_E_memory): Exclude recording of used address
627 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
628 addressed memory operands for MPX insns.
630 2020-03-06 Jan Beulich <jbeulich@suse.com>
632 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
633 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
634 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
635 (ptwrite): Split into non-64-bit and 64-bit forms.
636 * i386-tbl.h: Re-generate.
638 2020-03-06 Jan Beulich <jbeulich@suse.com>
640 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
642 * i386-tbl.h: Re-generate.
644 2020-03-04 Jan Beulich <jbeulich@suse.com>
646 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
647 (prefix_table): Move vmmcall here. Add vmgexit.
648 (rm_table): Replace vmmcall entry by prefix_table[] escape.
649 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
650 (cpu_flags): Add CpuSEV_ES entry.
651 * i386-opc.h (CpuSEV_ES): New.
652 (union i386_cpu_flags): Add cpusev_es field.
653 * i386-opc.tbl (vmgexit): New.
654 * i386-init.h, i386-tbl.h: Re-generate.
656 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
658 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
660 * i386-opc.h (IGNORESIZE): New.
661 (DEFAULTSIZE): Likewise.
662 (IgnoreSize): Removed.
663 (DefaultSize): Likewise.
665 (i386_opcode_modifier): Replace ignoresize/defaultsize with
667 * i386-opc.tbl (IgnoreSize): New.
668 (DefaultSize): Likewise.
669 * i386-tbl.h: Regenerated.
671 2020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
674 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
677 2020-03-03 H.J. Lu <hongjiu.lu@intel.com>
680 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
681 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
682 * i386-tbl.h: Regenerated.
684 2020-02-26 Alan Modra <amodra@gmail.com>
686 * aarch64-asm.c: Indent labels correctly.
687 * aarch64-dis.c: Likewise.
688 * aarch64-gen.c: Likewise.
689 * aarch64-opc.c: Likewise.
690 * alpha-dis.c: Likewise.
691 * i386-dis.c: Likewise.
692 * nds32-asm.c: Likewise.
693 * nfp-dis.c: Likewise.
694 * visium-dis.c: Likewise.
696 2020-02-25 Claudiu Zissulescu <claziss@gmail.com>
698 * arc-regs.h (int_vector_base): Make it available for all ARC
701 2020-02-20 Nelson Chu <nelson.chu@sifive.com>
703 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
706 2020-02-19 Nelson Chu <nelson.chu@sifive.com>
708 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
709 c.mv/c.li if rs1 is zero.
711 2020-02-17 H.J. Lu <hongjiu.lu@intel.com>
713 * i386-gen.c (cpu_flag_init): Replace CpuABM with
714 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
716 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
717 * i386-opc.h (CpuABM): Removed.
719 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
720 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
721 popcnt. Remove CpuABM from lzcnt.
722 * i386-init.h: Regenerated.
723 * i386-tbl.h: Likewise.
725 2020-02-17 Jan Beulich <jbeulich@suse.com>
727 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
728 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
729 VexW1 instead of open-coding them.
730 * i386-tbl.h: Re-generate.
732 2020-02-17 Jan Beulich <jbeulich@suse.com>
734 * i386-opc.tbl (AddrPrefixOpReg): Define.
735 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
736 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
737 templates. Drop NoRex64.
738 * i386-tbl.h: Re-generate.
740 2020-02-17 Jan Beulich <jbeulich@suse.com>
743 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
744 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
745 into Intel syntax instance (with Unpsecified) and AT&T one
747 (vcvtneps2bf16): Likewise, along with folding the two so far
749 * i386-tbl.h: Re-generate.
751 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
753 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
756 2020-02-17 Alan Modra <amodra@gmail.com>
758 * i386-gen.c (cpu_flag_init): Correct last change.
760 2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
762 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
765 2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
767 * i386-opc.tbl (movsx): Remove Intel syntax comments.
770 2020-02-14 Jan Beulich <jbeulich@suse.com>
773 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
774 destination for Cpu64-only variant.
775 (movzx): Fold patterns.
776 * i386-tbl.h: Re-generate.
778 2020-02-13 Jan Beulich <jbeulich@suse.com>
780 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
781 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
782 CPU_ANY_SSE4_FLAGS entry.
783 * i386-init.h: Re-generate.
785 2020-02-12 Jan Beulich <jbeulich@suse.com>
787 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
788 with Unspecified, making the present one AT&T syntax only.
789 * i386-tbl.h: Re-generate.
791 2020-02-12 Jan Beulich <jbeulich@suse.com>
793 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
794 * i386-tbl.h: Re-generate.
796 2020-02-12 Jan Beulich <jbeulich@suse.com>
799 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
800 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
801 Amd64 and Intel64 templates.
802 (call, jmp): Likewise for far indirect variants. Dro
804 * i386-tbl.h: Re-generate.
806 2020-02-11 Jan Beulich <jbeulich@suse.com>
808 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
809 * i386-opc.h (ShortForm): Delete.
810 (struct i386_opcode_modifier): Remove shortform field.
811 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
812 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
813 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
814 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
816 * i386-tbl.h: Re-generate.
818 2020-02-11 Jan Beulich <jbeulich@suse.com>
820 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
821 fucompi): Drop ShortForm from operand-less templates.
822 * i386-tbl.h: Re-generate.
824 2020-02-11 Alan Modra <amodra@gmail.com>
826 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
827 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
828 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
829 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
830 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
832 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
834 * arm-dis.c (print_insn_cde): Define 'V' parse character.
835 (cde_opcodes): Add VCX* instructions.
837 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
838 Matthew Malcomson <matthew.malcomson@arm.com>
840 * arm-dis.c (struct cdeopcode32): New.
841 (CDE_OPCODE): New macro.
842 (cde_opcodes): New disassembly table.
843 (regnames): New option to table.
844 (cde_coprocs): New global variable.
845 (print_insn_cde): New
846 (print_insn_thumb32): Use print_insn_cde.
847 (parse_arm_disassembler_options): Parse coprocN args.
849 2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
852 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
854 * i386-opc.h (AMD64): Removed.
858 (INTEL64ONLY): Likewise.
859 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
860 * i386-opc.tbl (Amd64): New.
862 (Intel64Only): Likewise.
863 Replace AMD64 with Amd64. Update sysenter/sysenter with
864 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
865 * i386-tbl.h: Regenerated.
867 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
870 * z80-dis.c: Add support for GBZ80 opcodes.
872 2020-02-04 Alan Modra <amodra@gmail.com>
874 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
876 2020-02-03 Alan Modra <amodra@gmail.com>
878 * m32c-ibld.c: Regenerate.
880 2020-02-01 Alan Modra <amodra@gmail.com>
882 * frv-ibld.c: Regenerate.
884 2020-01-31 Jan Beulich <jbeulich@suse.com>
886 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
887 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
888 (OP_E_memory): Replace xmm_mdq_mode case label by
889 vex_scalar_w_dq_mode one.
890 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
892 2020-01-31 Jan Beulich <jbeulich@suse.com>
894 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
895 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
896 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
897 (intel_operand_size): Drop vex_w_dq_mode case label.
899 2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
901 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
902 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
904 2020-01-30 Alan Modra <amodra@gmail.com>
906 * m32c-ibld.c: Regenerate.
908 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
910 * bpf-opc.c: Regenerate.
912 2020-01-30 Jan Beulich <jbeulich@suse.com>
914 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
915 (dis386): Use them to replace C2/C3 table entries.
916 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
917 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
918 ones. Use Size64 instead of DefaultSize on Intel64 ones.
919 * i386-tbl.h: Re-generate.
921 2020-01-30 Jan Beulich <jbeulich@suse.com>
923 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
925 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
927 * i386-tbl.h: Re-generate.
929 2020-01-30 Alan Modra <amodra@gmail.com>
931 * tic4x-dis.c (tic4x_dp): Make unsigned.
933 2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
934 Jan Beulich <jbeulich@suse.com>
937 * i386-dis.c (MOVSXD_Fixup): New function.
938 (movsxd_mode): New enum.
939 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
940 (intel_operand_size): Handle movsxd_mode.
941 (OP_E_register): Likewise.
943 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
944 register on movsxd. Add movsxd with 16-bit destination register
945 for AMD64 and Intel64 ISAs.
946 * i386-tbl.h: Regenerated.
948 2020-01-27 Tamar Christina <tamar.christina@arm.com>
951 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
952 * aarch64-asm-2.c: Regenerate
953 * aarch64-dis-2.c: Likewise.
954 * aarch64-opc-2.c: Likewise.
956 2020-01-21 Jan Beulich <jbeulich@suse.com>
958 * i386-opc.tbl (sysret): Drop DefaultSize.
959 * i386-tbl.h: Re-generate.
961 2020-01-21 Jan Beulich <jbeulich@suse.com>
963 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
965 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
966 * i386-tbl.h: Re-generate.
968 2020-01-20 Nick Clifton <nickc@redhat.com>
970 * po/de.po: Updated German translation.
971 * po/pt_BR.po: Updated Brazilian Portuguese translation.
972 * po/uk.po: Updated Ukranian translation.
974 2020-01-20 Alan Modra <amodra@gmail.com>
976 * hppa-dis.c (fput_const): Remove useless cast.
978 2020-01-20 Alan Modra <amodra@gmail.com>
980 * arm-dis.c (print_insn_arm): Wrap 'T' value.
982 2020-01-18 Nick Clifton <nickc@redhat.com>
984 * configure: Regenerate.
985 * po/opcodes.pot: Regenerate.
987 2020-01-18 Nick Clifton <nickc@redhat.com>
989 Binutils 2.34 branch created.
991 2020-01-17 Christian Biesinger <cbiesinger@google.com>
993 * opintl.h: Fix spelling error (seperate).
995 2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
997 * i386-opc.tbl: Add {vex} pseudo prefix.
998 * i386-tbl.h: Regenerated.
1000 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1003 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1004 (neon_opcodes): Likewise.
1005 (select_arm_features): Make sure we enable MVE bits when selecting
1006 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1009 2020-01-16 Jan Beulich <jbeulich@suse.com>
1011 * i386-opc.tbl: Drop stale comment from XOP section.
1013 2020-01-16 Jan Beulich <jbeulich@suse.com>
1015 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1016 (extractps): Add VexWIG to SSE2AVX forms.
1017 * i386-tbl.h: Re-generate.
1019 2020-01-16 Jan Beulich <jbeulich@suse.com>
1021 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1022 Size64 from and use VexW1 on SSE2AVX forms.
1023 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1024 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1025 * i386-tbl.h: Re-generate.
1027 2020-01-15 Alan Modra <amodra@gmail.com>
1029 * tic4x-dis.c (tic4x_version): Make unsigned long.
1030 (optab, optab_special, registernames): New file scope vars.
1031 (tic4x_print_register): Set up registernames rather than
1032 malloc'd registertable.
1033 (tic4x_disassemble): Delete optable and optable_special. Use
1034 optab and optab_special instead. Throw away old optab,
1035 optab_special and registernames when info->mach changes.
1037 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1040 * z80-dis.c (suffix): Use .db instruction to generate double
1043 2020-01-14 Alan Modra <amodra@gmail.com>
1045 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1046 values to unsigned before shifting.
1048 2020-01-13 Thomas Troeger <tstroege@gmx.de>
1050 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1052 (print_insn_thumb16, print_insn_thumb32): Likewise.
1053 (print_insn): Initialize the insn info.
1054 * i386-dis.c (print_insn): Initialize the insn info fields, and
1057 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1059 * arc-opc.c (C_NE): Make it required.
1061 2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1063 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1064 reserved register name.
1066 2020-01-13 Alan Modra <amodra@gmail.com>
1068 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1069 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1071 2020-01-13 Alan Modra <amodra@gmail.com>
1073 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1074 result of wasm_read_leb128 in a uint64_t and check that bits
1075 are not lost when copying to other locals. Use uint32_t for
1076 most locals. Use PRId64 when printing int64_t.
1078 2020-01-13 Alan Modra <amodra@gmail.com>
1080 * score-dis.c: Formatting.
1081 * score7-dis.c: Formatting.
1083 2020-01-13 Alan Modra <amodra@gmail.com>
1085 * score-dis.c (print_insn_score48): Use unsigned variables for
1086 unsigned values. Don't left shift negative values.
1087 (print_insn_score32): Likewise.
1088 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1090 2020-01-13 Alan Modra <amodra@gmail.com>
1092 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1094 2020-01-13 Alan Modra <amodra@gmail.com>
1096 * fr30-ibld.c: Regenerate.
1098 2020-01-13 Alan Modra <amodra@gmail.com>
1100 * xgate-dis.c (print_insn): Don't left shift signed value.
1101 (ripBits): Formatting, use 1u.
1103 2020-01-10 Alan Modra <amodra@gmail.com>
1105 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1106 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1108 2020-01-10 Alan Modra <amodra@gmail.com>
1110 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1111 and XRREG value earlier to avoid a shift with negative exponent.
1112 * m10200-dis.c (disassemble): Similarly.
1114 2020-01-09 Nick Clifton <nickc@redhat.com>
1117 * z80-dis.c (ld_ii_ii): Use correct cast.
1119 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1122 * z80-dis.c (ld_ii_ii): Use character constant when checking
1125 2020-01-09 Jan Beulich <jbeulich@suse.com>
1127 * i386-dis.c (SEP_Fixup): New.
1129 (dis386_twobyte): Use it for sysenter/sysexit.
1130 (enum x86_64_isa): Change amd64 enumerator to value 1.
1131 (OP_J): Compare isa64 against intel64 instead of amd64.
1132 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1134 * i386-tbl.h: Re-generate.
1136 2020-01-08 Alan Modra <amodra@gmail.com>
1138 * z8k-dis.c: Include libiberty.h
1139 (instr_data_s): Make max_fetched unsigned.
1140 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1141 Don't exceed byte_info bounds.
1142 (output_instr): Make num_bytes unsigned.
1143 (unpack_instr): Likewise for nibl_count and loop.
1144 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1146 * z8k-opc.h: Regenerate.
1148 2020-01-07 Shahab Vahedi <shahab@synopsys.com>
1150 * arc-tbl.h (llock): Use 'LLOCK' as class.
1152 (scond): Use 'SCOND' as class.
1154 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1157 2020-01-06 Alan Modra <amodra@gmail.com>
1159 * m32c-ibld.c: Regenerate.
1161 2020-01-06 Alan Modra <amodra@gmail.com>
1164 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1165 Peek at next byte to prevent recursion on repeated prefix bytes.
1166 Ensure uninitialised "mybuf" is not accessed.
1167 (print_insn_z80): Don't zero n_fetch and n_used here,..
1168 (print_insn_z80_buf): ..do it here instead.
1170 2020-01-04 Alan Modra <amodra@gmail.com>
1172 * m32r-ibld.c: Regenerate.
1174 2020-01-04 Alan Modra <amodra@gmail.com>
1176 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1178 2020-01-04 Alan Modra <amodra@gmail.com>
1180 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1182 2020-01-04 Alan Modra <amodra@gmail.com>
1184 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1186 2020-01-03 Jan Beulich <jbeulich@suse.com>
1188 * aarch64-tbl.h (aarch64_opcode_table): Use
1189 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1191 2020-01-03 Jan Beulich <jbeulich@suse.com>
1193 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1194 forms of SUDOT and USDOT.
1196 2020-01-03 Jan Beulich <jbeulich@suse.com>
1198 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1200 * opcodes/aarch64-dis-2.c: Re-generate.
1202 2020-01-03 Jan Beulich <jbeulich@suse.com>
1204 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1206 * opcodes/aarch64-dis-2.c: Re-generate.
1208 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1210 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1212 2020-01-01 Alan Modra <amodra@gmail.com>
1214 Update year range in copyright notice of all files.
1216 For older changes see ChangeLog-2019
1218 Copyright (C) 2020 Free Software Foundation, Inc.
1220 Copying and distribution of this file, with or without modification,
1221 are permitted in any medium without royalty provided the copyright
1222 notice and this notice are preserved.
1228 version-control: never