opcodes/ChangeLog

   1 2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
   2
   3         * mips-dis.c (is_compressed_mode_p): Only match symbols from the
   4         section disassembled.
   5
   6 2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
   7
   8         * arm-dis.c: Update strht pattern.
   9
  10 2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
  11
  12         * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
  13         single-float.  Disable ll, lld, sc and scd for EE.  Disable the
  14         trunc.w.s macro for EE.
  15
  16 2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
  17             Andrew Jenner <andrew@codesourcery.com>
  18
  19         Based on patches from Altera Corporation.
  20
  21         * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
  22         nios2-opc.c.
  23         * Makefile.in: Regenerated.
  24         * configure.in: Add case for bfd_nios2_arch.
  25         * configure: Regenerated.
  26         * disassemble.c (ARCH_nios2): Define.
  27         (disassembler): Add case for bfd_arch_nios2.
  28         * nios2-dis.c: New file.
  29         * nios2-opc.c: New file.
  30
  31 2013-02-04  Alan Modra  <amodra@gmail.com>
  32
  33         * po/POTFILES.in: Regenerate.
  34         * rl78-decode.c: Regenerate.
  35         * rx-decode.c: Regenerate.
  36
  37 2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
  38
  39         * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
  40         ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
  41         * aarch64-asm.c (convert_xtl_to_shll): New function.
  42         (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  43         calling convert_xtl_to_shll.
  44         * aarch64-dis.c (convert_shll_to_xtl): New function.
  45         (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
  46         calling convert_shll_to_xtl.
  47         * aarch64-gen.c: Update copyright year.
  48         * aarch64-asm-2.c: Re-generate.
  49         * aarch64-dis-2.c: Re-generate.
  50         * aarch64-opc-2.c: Re-generate.
  51
  52 2013-01-24  Nick Clifton  <nickc@redhat.com>
  53
  54         * v850-dis.c: Add support for e3v5 architecture.
  55         * v850-opc.c: Likewise.
  56
  57 2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
  58
  59         * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
  60         * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
  61         * aarch64-opc.c (operand_general_constraint_met_p): For
  62         AARCH64_MOD_LSL, move the range check on the shift amount before the
  63         alignment check; change to call set_sft_amount_out_of_range_error
  64         instead of set_imm_out_of_range_error.
  65         * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
  66         (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
  67         8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
  68         SIMD_IMM_SFT.
  69
  70 2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
  73
  74         * i386-init.h: Regenerated.
  75         * i386-tbl.h: Likewise.
  76
  77 2013-01-15  Nick Clifton  <nickc@redhat.com>
  78
  79         * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
  80         values.
  81         * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
  82
  83 2013-01-14  Will Newton <will.newton@imgtec.com>
  84
  85         * metag-dis.c (REG_WIDTH): Increase to 64.
  86
  87 2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
  88
  89         * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
  90         * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
  91         XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
  92         (SH6): Update.
  93         <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
  94         "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
  95         "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
  96         <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
  97
  98 2013-01-10  Will Newton <will.newton@imgtec.com>
  99
 100         * Makefile.am: Add Meta.
 101         * configure.in: Add Meta.
 102         * disassemble.c: Add Meta support.
 103         * metag-dis.c: New file.
 104         * Makefile.in: Regenerate.
 105         * configure: Regenerate.
 106
 107 2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 108
 109         * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
 110         (match_opcode): Rename to cr16_match_opcode.
 111
 112 2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
 113
 114         * mips-dis.c: Add names for CP0 registers of r5900.
 115         * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
 116         instructions sq and lq.
 117         Add support for MIPS r5900 CPU.
 118         Add support for 128 bit MMI (Multimedia Instructions).
 119         Add support for EE instructions (Emotion Engine).
 120         Disable unsupported floating point instructions (64 bit and
 121         undefined compare operations).
 122         Enable instructions of MIPS ISA IV which are supported by r5900.
 123         Disable 64 bit co processor instructions.
 124         Disable 64 bit multiplication and division instructions.
 125         Disable instructions for co-processor 2 and 3, because these are
 126         not supported (preparation for later VU0 support (Vector Unit)).
 127         Disable cvt.w.s because this behaves like trunc.w.s and the
 128         correct execution can't be ensured on r5900.
 129         Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
 130         will confuse less developers and compilers.
 131
 132 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 133
 134         * aarch64-opc.c (aarch64_print_operand): Change to print
 135         AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
 136         in comment.
 137         * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
 138         from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
 139         OP_MOV_IMM_WIDE.
 140
 141 2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
 142
 143         * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
 144         PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
 145
 146 2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
 147
 148         * i386-gen.c (process_copyright): Update copyright year to 2013.
 149
 150 2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
 151
 152         * cr16-dis.c (match_opcode,make_instruction): Remove static
 153         declaration.
 154         (dwordU,wordU): Moved typedefs to opcode/cr16.h
 155         (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
 156
 157 For older changes see ChangeLog-2012
 158 \f
 159 Copyright (C) 2013 Free Software Foundation, Inc.
 160
 161 Copying and distribution of this file, with or without modification,
 162 are permitted in any medium without royalty provided the copyright
 163 notice and this notice are preserved.
 164
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