opcodes/ChangeLog

   1 2020-05-28  Alan Modra  <amodra@gmail.com>
   2
   3         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
   4         values.
   5
   6 2020-05-28  Alan Modra  <amodra@gmail.com>
   7
   8         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
   9         immediates.
  10         (print_insn_ns32k): Revert last change.
  11
  12 2020-05-28  Nick Clifton  <nickc@redhat.com>
  13
  14         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
  15         static.
  16
  17 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
  18
  19         Fix extraction of signed constants in nios2 disassembler (again).
  20
  21         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
  22         extractions of signed fields.
  23
  24 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
  25
  26         * s390-opc.txt: Relocate vector load/store instructions with
  27         additional alignment parameter and change architecture level
  28         constraint from z14 to z13.
  29
  30 2020-05-21  Alan Modra  <amodra@gmail.com>
  31
  32         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
  33         * sparc-dis.c: Likewise.
  34         * tic4x-dis.c: Likewise.
  35         * xtensa-dis.c: Likewise.
  36         * bpf-desc.c: Regenerate.
  37         * epiphany-desc.c: Regenerate.
  38         * fr30-desc.c: Regenerate.
  39         * frv-desc.c: Regenerate.
  40         * ip2k-desc.c: Regenerate.
  41         * iq2000-desc.c: Regenerate.
  42         * lm32-desc.c: Regenerate.
  43         * m32c-desc.c: Regenerate.
  44         * m32r-desc.c: Regenerate.
  45         * mep-asm.c: Regenerate.
  46         * mep-desc.c: Regenerate.
  47         * mt-desc.c: Regenerate.
  48         * or1k-desc.c: Regenerate.
  49         * xc16x-desc.c: Regenerate.
  50         * xstormy16-desc.c: Regenerate.
  51
  52 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
  53
  54         * riscv-opc.c (riscv_ext_version_table): The table used to store
  55         all information about the supported spec and the corresponding ISA
  56         versions.  Currently, only Zicsr is supported to verify the
  57         correctness of Z sub extension settings.  Others will be supported
  58         in the future patches.
  59         (struct isa_spec_t, isa_specs): List for all supported ISA spec
  60         classes and the corresponding strings.
  61         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
  62         spec class by giving a ISA spec string.
  63         * riscv-opc.c (struct priv_spec_t): New structure.
  64         (struct priv_spec_t priv_specs): List for all supported privilege spec
  65         classes and the corresponding strings.
  66         (riscv_get_priv_spec_class): New function.  Get the corresponding
  67         privilege spec class by giving a spec string.
  68         (riscv_get_priv_spec_name): New function.  Get the corresponding
  69         privilege spec string by giving a CSR version class.
  70         * riscv-dis.c: Updated since DECLARE_CSR is changed.
  71         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
  72         according to the chosen version.  Build a hash table riscv_csr_hash to
  73         store the valid CSR for the chosen pirv verison.  Dump the direct
  74         CSR address rather than it's name if it is invalid.
  75         (parse_riscv_dis_option_without_args): New function.  Parse the options
  76         without arguments.
  77         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
  78         parse the options without arguments first, and then handle the options
  79         with arguments.  Add the new option -Mpriv-spec, which has argument.
  80         * riscv-dis.c (print_riscv_disassembler_options): Add description
  81         about the new OBJDUMP option.
  82
  83 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
  84
  85         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
  86         WC values on POWER10 sync, dcbf  and wait instructions.
  87         (insert_pl, extract_pl): New functions.
  88         (L2OPT, LS, WC): Use insert_ls and extract_ls.
  89         (LS3): New , 3-bit L for sync.
  90         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
  91         (SC2, PL): New, 2-bit SC and PL for sync and wait.
  92         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
  93         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
  94         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
  95         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
  96         <wait>: Enable PL operand on POWER10.
  97         <dcbf>: Enable L3OPT operand on POWER10.
  98         <sync>: Enable SC2 operand on POWER10.
  99
 100 2020-05-19  Stafford Horne  <shorne@gmail.com>
 101
 102         PR 25184
 103         * or1k-asm.c: Regenerate.
 104         * or1k-desc.c: Regenerate.
 105         * or1k-desc.h: Regenerate.
 106         * or1k-dis.c: Regenerate.
 107         * or1k-ibld.c: Regenerate.
 108         * or1k-opc.c: Regenerate.
 109         * or1k-opc.h: Regenerate.
 110         * or1k-opinst.c: Regenerate.
 111
 112 2020-05-11  Alan Modra  <amodra@gmail.com>
 113
 114         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 115         xsmaxcqp, xsmincqp.
 116
 117 2020-05-11  Alan Modra  <amodra@gmail.com>
 118
 119         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 120         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 121
 122 2020-05-11  Alan Modra  <amodra@gmail.com>
 123
 124         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 125
 126 2020-05-11  Alan Modra  <amodra@gmail.com>
 127
 128         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 129         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 130
 131 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 132
 133         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 134         mnemonics.
 135
 136 2020-05-11  Alan Modra  <amodra@gmail.com>
 137
 138         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 139         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 140         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 141         (prefix_opcodes): Add xxeval.
 142
 143 2020-05-11  Alan Modra  <amodra@gmail.com>
 144
 145         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 146         xxgenpcvwm, xxgenpcvdm.
 147
 148 2020-05-11  Alan Modra  <amodra@gmail.com>
 149
 150         * ppc-opc.c (MP, VXVAM_MASK): Define.
 151         (VXVAPS_MASK): Use VXVA_MASK.
 152         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 153         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 154         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 155         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 156
 157 2020-05-11  Alan Modra  <amodra@gmail.com>
 158             Peter Bergner  <bergner@linux.ibm.com>
 159
 160         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 161         New functions.
 162         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 163         YMSK2, XA6a, XA6ap, XB6a entries.
 164         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 165         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 166         (PPCVSX4): Define.
 167         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 168         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 169         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 170         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 171         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 172         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 173         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 174         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 175         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 176         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 177         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 178         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 179         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 180         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 181
 182 2020-05-11  Alan Modra  <amodra@gmail.com>
 183
 184         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 185         (insert_xts, extract_xts): New functions.
 186         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 187         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 188         (VXRC_MASK, VXSH_MASK): Define.
 189         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 190         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 191         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 192         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 193         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 194         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 195         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 196
 197 2020-05-11  Alan Modra  <amodra@gmail.com>
 198
 199         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 200         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 201         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 202         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 203         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 204
 205 2020-05-11  Alan Modra  <amodra@gmail.com>
 206
 207         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 208         (XTP, DQXP, DQXP_MASK): Define.
 209         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 210         (prefix_opcodes): Add plxvp and pstxvp.
 211
 212 2020-05-11  Alan Modra  <amodra@gmail.com>
 213
 214         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 215         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 216         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 217
 218 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 219
 220         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 221
 222 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 223
 224         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 225         (L1OPT): Define.
 226         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 227
 228 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 229
 230         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 231
 232 2020-05-11  Alan Modra  <amodra@gmail.com>
 233
 234         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 235
 236 2020-05-11  Alan Modra  <amodra@gmail.com>
 237
 238         * ppc-dis.c (ppc_opts): Add "power10" entry.
 239         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 240         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 241
 242 2020-05-11  Nick Clifton  <nickc@redhat.com>
 243
 244         * po/fr.po: Updated French translation.
 245
 246 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 247
 248         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 249         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 250         (operand_general_constraint_met_p): validate
 251         AARCH64_OPND_UNDEFINED.
 252         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 253         for FLD_imm16_2.
 254         * aarch64-asm-2.c: Regenerated.
 255         * aarch64-dis-2.c: Regenerated.
 256         * aarch64-opc-2.c: Regenerated.
 257
 258 2020-04-29  Nick Clifton  <nickc@redhat.com>
 259
 260         PR 22699
 261         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 262         and SETRC insns.
 263
 264 2020-04-29  Nick Clifton  <nickc@redhat.com>
 265
 266         * po/sv.po: Updated Swedish translation.
 267
 268 2020-04-29  Nick Clifton  <nickc@redhat.com>
 269
 270         PR 22699
 271         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 272         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 273         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 274         IMM0_8U case.
 275
 276 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 277
 278         PR 25848
 279         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 280         cmpi only on m68020up and cpu32.
 281
 282 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 283
 284         * aarch64-asm.c (aarch64_ins_none): New.
 285         * aarch64-asm.h (ins_none): New declaration.
 286         * aarch64-dis.c (aarch64_ext_none): New.
 287         * aarch64-dis.h (ext_none): New declaration.
 288         * aarch64-opc.c (aarch64_print_operand): Update case for
 289         AARCH64_OPND_BARRIER_PSB.
 290         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 291         (AARCH64_OPERANDS): Update inserter/extracter for
 292         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 293         * aarch64-asm-2.c: Regenerated.
 294         * aarch64-dis-2.c: Regenerated.
 295         * aarch64-opc-2.c: Regenerated.
 296
 297 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 298
 299         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 300         (aarch64_feature_ras, RAS): Likewise.
 301         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 302         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 303         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 304         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 305         * aarch64-asm-2.c: Regenerated.
 306         * aarch64-dis-2.c: Regenerated.
 307         * aarch64-opc-2.c: Regenerated.
 308
 309 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 310
 311         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 312         (print_insn_neon): Support disassembly of conditional
 313         instructions.
 314
 315 2020-02-16  David Faust  <david.faust@oracle.com>
 316
 317         * bpf-desc.c: Regenerate.
 318         * bpf-desc.h: Likewise.
 319         * bpf-opc.c: Regenerate.
 320         * bpf-opc.h: Likewise.
 321
 322 2020-04-07  Lili Cui  <lili.cui@intel.com>
 323
 324         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 325         (prefix_table): New instructions (see prefixes above).
 326         (rm_table): Likewise
 327         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 328         CPU_ANY_TSXLDTRK_FLAGS.
 329         (cpu_flags): Add CpuTSXLDTRK.
 330         * i386-opc.h (enum): Add CpuTSXLDTRK.
 331         (i386_cpu_flags): Add cputsxldtrk.
 332         * i386-opc.tbl: Add XSUSPLDTRK insns.
 333         * i386-init.h: Regenerate.
 334         * i386-tbl.h: Likewise.
 335
 336 2020-04-02  Lili Cui  <lili.cui@intel.com>
 337
 338         * i386-dis.c (prefix_table): New instructions serialize.
 339         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 340         CPU_ANY_SERIALIZE_FLAGS.
 341         (cpu_flags): Add CpuSERIALIZE.
 342         * i386-opc.h (enum): Add CpuSERIALIZE.
 343         (i386_cpu_flags): Add cpuserialize.
 344         * i386-opc.tbl: Add SERIALIZE insns.
 345         * i386-init.h: Regenerate.
 346         * i386-tbl.h: Likewise.
 347
 348 2020-03-26  Alan Modra  <amodra@gmail.com>
 349
 350         * disassemble.h (opcodes_assert): Declare.
 351         (OPCODES_ASSERT): Define.
 352         * disassemble.c: Don't include assert.h.  Include opintl.h.
 353         (opcodes_assert): New function.
 354         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 355         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 356         calculate maxlen.  Omit insn decoding when insn length exceeds
 357         maxlen.  Exit from nibble loop when looking for E, before
 358         accessing next data byte.  Move processing of E outside loop.
 359         Replace tests of maxlen in loop with assertions.
 360
 361 2020-03-26  Alan Modra  <amodra@gmail.com>
 362
 363         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 364
 365 2020-03-25  Alan Modra  <amodra@gmail.com>
 366
 367         * z80-dis.c (suffix): Init mybuf.
 368
 369 2020-03-22  Alan Modra  <amodra@gmail.com>
 370
 371         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 372         successflly read from section.
 373
 374 2020-03-22  Alan Modra  <amodra@gmail.com>
 375
 376         * arc-dis.c (find_format): Use ISO C string concatenation rather
 377         than line continuation within a string.  Don't access needs_limm
 378         before testing opcode != NULL.
 379
 380 2020-03-22  Alan Modra  <amodra@gmail.com>
 381
 382         * ns32k-dis.c (print_insn_arg): Update comment.
 383         (print_insn_ns32k): Reduce size of index_offset array, and
 384         initialize, passing -1 to print_insn_arg for args that are not
 385         an index.  Don't exit arg loop early.  Abort on bad arg number.
 386
 387 2020-03-22  Alan Modra  <amodra@gmail.com>
 388
 389         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 390         * s12z-opc.c: Formatting.
 391         (operands_f): Return an int.
 392         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 393         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 394         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 395         (exg_sex_discrim): Likewise.
 396         (create_immediate_operand, create_bitfield_operand),
 397         (create_register_operand_with_size, create_register_all_operand),
 398         (create_register_all16_operand, create_simple_memory_operand),
 399         (create_memory_operand, create_memory_auto_operand): Don't
 400         segfault on malloc failure.
 401         (z_ext24_decode): Return an int status, negative on fail, zero
 402         on success.
 403         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 404         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 405         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 406         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 407         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 408         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 409         (loop_primitive_decode, shift_decode, psh_pul_decode),
 410         (bit_field_decode): Similarly.
 411         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 412         to return value, update callers.
 413         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 414         Don't segfault on NULL operand.
 415         (decode_operation): Return OP_INVALID on first fail.
 416         (decode_s12z): Check all reads, returning -1 on fail.
 417
 418 2020-03-20  Alan Modra  <amodra@gmail.com>
 419
 420         * metag-dis.c (print_insn_metag): Don't ignore status from
 421         read_memory_func.
 422
 423 2020-03-20  Alan Modra  <amodra@gmail.com>
 424
 425         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 426         Initialize parts of buffer not written when handling a possible
 427         2-byte insn at end of section.  Don't attempt decoding of such
 428         an insn by the 4-byte machinery.
 429
 430 2020-03-20  Alan Modra  <amodra@gmail.com>
 431
 432         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 433         partially filled buffer.  Prevent lookup of 4-byte insns when
 434         only VLE 2-byte insns are possible due to section size.  Print
 435         ".word" rather than ".long" for 2-byte leftovers.
 436
 437 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 438
 439         PR 25641
 440         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 441
 442 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 443
 444         * i386-dis.c (X86_64_0D): Rename to ...
 445         (X86_64_0E): ... this.
 446
 447 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 448
 449         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 450         * Makefile.in: Regenerated.
 451
 452 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 453
 454         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 455         3-operand pseudos.
 456         * i386-tbl.h: Re-generate.
 457
 458 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 461         vprot*, vpsha*, and vpshl*.
 462         * i386-tbl.h: Re-generate.
 463
 464 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 465
 466         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 467         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 468         * i386-tbl.h: Re-generate.
 469
 470 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 473         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 474         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 475         * i386-tbl.h: Re-generate.
 476
 477 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 478
 479         * i386-gen.c (struct template_arg, struct template_instance,
 480         struct template_param, struct template, templates,
 481         parse_template, expand_templates): New.
 482         (process_i386_opcodes): Various local variables moved to
 483         expand_templates. Call parse_template and expand_templates.
 484         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 485         * i386-tbl.h: Re-generate.
 486
 487 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 488
 489         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 490         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 491         register and memory source templates. Replace VexW= by VexW*
 492         where applicable.
 493         * i386-tbl.h: Re-generate.
 494
 495 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 498         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 499         * i386-tbl.h: Re-generate.
 500
 501 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 504         * i386-tbl.h: Re-generate.
 505
 506 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 509         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 510         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 511         VexW0 on SSE2AVX variants.
 512         (vmovq): Drop NoRex64 from XMM/XMM variants.
 513         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 514         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 515         applicable use VexW0.
 516         * i386-tbl.h: Re-generate.
 517
 518 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 519
 520         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 521         * i386-opc.h (Rex64): Delete.
 522         (struct i386_opcode_modifier): Remove rex64 field.
 523         * i386-opc.tbl (crc32): Drop Rex64.
 524         Replace Rex64 with Size64 everywhere else.
 525         * i386-tbl.h: Re-generate.
 526
 527 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 528
 529         * i386-dis.c (OP_E_memory): Exclude recording of used address
 530         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 531         addressed memory operands for MPX insns.
 532
 533 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 534
 535         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 536         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 537         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 538         (ptwrite): Split into non-64-bit and 64-bit forms.
 539         * i386-tbl.h: Re-generate.
 540
 541 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 544         template.
 545         * i386-tbl.h: Re-generate.
 546
 547 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 548
 549         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 550         (prefix_table): Move vmmcall here. Add vmgexit.
 551         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 552         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 553         (cpu_flags): Add CpuSEV_ES entry.
 554         * i386-opc.h (CpuSEV_ES): New.
 555         (union i386_cpu_flags): Add cpusev_es field.
 556         * i386-opc.tbl (vmgexit): New.
 557         * i386-init.h, i386-tbl.h: Re-generate.
 558
 559 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 560
 561         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 562         with MnemonicSize.
 563         * i386-opc.h (IGNORESIZE): New.
 564         (DEFAULTSIZE): Likewise.
 565         (IgnoreSize): Removed.
 566         (DefaultSize): Likewise.
 567         (MnemonicSize): New.
 568         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 569         mnemonicsize.
 570         * i386-opc.tbl (IgnoreSize): New.
 571         (DefaultSize): Likewise.
 572         * i386-tbl.h: Regenerated.
 573
 574 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 575
 576         PR 25627
 577         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 578         instructions.
 579
 580 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 581
 582         PR gas/25622
 583         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 584         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 585         * i386-tbl.h: Regenerated.
 586
 587 2020-02-26  Alan Modra  <amodra@gmail.com>
 588
 589         * aarch64-asm.c: Indent labels correctly.
 590         * aarch64-dis.c: Likewise.
 591         * aarch64-gen.c: Likewise.
 592         * aarch64-opc.c: Likewise.
 593         * alpha-dis.c: Likewise.
 594         * i386-dis.c: Likewise.
 595         * nds32-asm.c: Likewise.
 596         * nfp-dis.c: Likewise.
 597         * visium-dis.c: Likewise.
 598
 599 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 600
 601         * arc-regs.h (int_vector_base): Make it available for all ARC
 602         CPUs.
 603
 604 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 605
 606         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 607         changed.
 608
 609 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 610
 611         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 612         c.mv/c.li if rs1 is zero.
 613
 614 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 615
 616         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 617         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 618         CPU_POPCNT_FLAGS.
 619         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 620         * i386-opc.h (CpuABM): Removed.
 621         (CpuPOPCNT): New.
 622         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 623         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 624         popcnt.  Remove CpuABM from lzcnt.
 625         * i386-init.h: Regenerated.
 626         * i386-tbl.h: Likewise.
 627
 628 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 629
 630         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 631         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 632         VexW1 instead of open-coding them.
 633         * i386-tbl.h: Re-generate.
 634
 635 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 636
 637         * i386-opc.tbl (AddrPrefixOpReg): Define.
 638         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 639         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 640         templates. Drop NoRex64.
 641         * i386-tbl.h: Re-generate.
 642
 643 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 644
 645         PR gas/6518
 646         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 647         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 648         into Intel syntax instance (with Unpsecified) and AT&T one
 649         (without).
 650         (vcvtneps2bf16): Likewise, along with folding the two so far
 651         separate ones.
 652         * i386-tbl.h: Re-generate.
 653
 654 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 655
 656         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 657         CPU_ANY_SSE4A_FLAGS.
 658
 659 2020-02-17  Alan Modra  <amodra@gmail.com>
 660
 661         * i386-gen.c (cpu_flag_init): Correct last change.
 662
 663 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 664
 665         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 666         CPU_ANY_SSE4_FLAGS.
 667
 668 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 669
 670         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 671         (movzx): Likewise.
 672
 673 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 674
 675         PR gas/25438
 676         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 677         destination for Cpu64-only variant.
 678         (movzx): Fold patterns.
 679         * i386-tbl.h: Re-generate.
 680
 681 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 684         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 685         CPU_ANY_SSE4_FLAGS entry.
 686         * i386-init.h: Re-generate.
 687
 688 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 689
 690         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 691         with Unspecified, making the present one AT&T syntax only.
 692         * i386-tbl.h: Re-generate.
 693
 694 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 695
 696         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 697         * i386-tbl.h: Re-generate.
 698
 699 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 700
 701         PR gas/24546
 702         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 703         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 704         Amd64 and Intel64 templates.
 705         (call, jmp): Likewise for far indirect variants. Dro
 706         Unspecified.
 707         * i386-tbl.h: Re-generate.
 708
 709 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 710
 711         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 712         * i386-opc.h (ShortForm): Delete.
 713         (struct i386_opcode_modifier): Remove shortform field.
 714         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 715         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 716         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 717         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 718         Drop ShortForm.
 719         * i386-tbl.h: Re-generate.
 720
 721 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 722
 723         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 724         fucompi): Drop ShortForm from operand-less templates.
 725         * i386-tbl.h: Re-generate.
 726
 727 2020-02-11  Alan Modra  <amodra@gmail.com>
 728
 729         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 730         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 731         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 732         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 733         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 734
 735 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 736
 737         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 738         (cde_opcodes): Add VCX* instructions.
 739
 740 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 741             Matthew Malcomson  <matthew.malcomson@arm.com>
 742
 743         * arm-dis.c (struct cdeopcode32): New.
 744         (CDE_OPCODE): New macro.
 745         (cde_opcodes): New disassembly table.
 746         (regnames): New option to table.
 747         (cde_coprocs): New global variable.
 748         (print_insn_cde): New
 749         (print_insn_thumb32): Use print_insn_cde.
 750         (parse_arm_disassembler_options): Parse coprocN args.
 751
 752 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 753
 754         PR gas/25516
 755         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 756         with ISA64.
 757         * i386-opc.h (AMD64): Removed.
 758         (Intel64): Likewose.
 759         (AMD64): New.
 760         (INTEL64): Likewise.
 761         (INTEL64ONLY): Likewise.
 762         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 763         * i386-opc.tbl (Amd64): New.
 764         (Intel64): Likewise.
 765         (Intel64Only): Likewise.
 766         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 767         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 768         * i386-tbl.h: Regenerated.
 769
 770 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 771
 772         PR 25469
 773         * z80-dis.c: Add support for GBZ80 opcodes.
 774
 775 2020-02-04  Alan Modra  <amodra@gmail.com>
 776
 777         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 778
 779 2020-02-03  Alan Modra  <amodra@gmail.com>
 780
 781         * m32c-ibld.c: Regenerate.
 782
 783 2020-02-01  Alan Modra  <amodra@gmail.com>
 784
 785         * frv-ibld.c: Regenerate.
 786
 787 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 788
 789         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 790         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 791         (OP_E_memory): Replace xmm_mdq_mode case label by
 792         vex_scalar_w_dq_mode one.
 793         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 794
 795 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 798         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 799         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 800         (intel_operand_size): Drop vex_w_dq_mode case label.
 801
 802 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 803
 804         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 805         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 806
 807 2020-01-30  Alan Modra  <amodra@gmail.com>
 808
 809         * m32c-ibld.c: Regenerate.
 810
 811 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 812
 813         * bpf-opc.c: Regenerate.
 814
 815 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 816
 817         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 818         (dis386): Use them to replace C2/C3 table entries.
 819         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 820         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 821         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 822         * i386-tbl.h: Re-generate.
 823
 824 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 825
 826         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 827         forms.
 828         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 829         DefaultSize.
 830         * i386-tbl.h: Re-generate.
 831
 832 2020-01-30  Alan Modra  <amodra@gmail.com>
 833
 834         * tic4x-dis.c (tic4x_dp): Make unsigned.
 835
 836 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 837             Jan Beulich  <jbeulich@suse.com>
 838
 839         PR binutils/25445
 840         * i386-dis.c (MOVSXD_Fixup): New function.
 841         (movsxd_mode): New enum.
 842         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 843         (intel_operand_size): Handle movsxd_mode.
 844         (OP_E_register): Likewise.
 845         (OP_G): Likewise.
 846         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 847         register on movsxd.  Add movsxd with 16-bit destination register
 848         for AMD64 and Intel64 ISAs.
 849         * i386-tbl.h: Regenerated.
 850
 851 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 852
 853         PR 25403
 854         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 855         * aarch64-asm-2.c: Regenerate
 856         * aarch64-dis-2.c: Likewise.
 857         * aarch64-opc-2.c: Likewise.
 858
 859 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 860
 861         * i386-opc.tbl (sysret): Drop DefaultSize.
 862         * i386-tbl.h: Re-generate.
 863
 864 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 865
 866         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 867         Dword.
 868         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 869         * i386-tbl.h: Re-generate.
 870
 871 2020-01-20  Nick Clifton  <nickc@redhat.com>
 872
 873         * po/de.po: Updated German translation.
 874         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 875         * po/uk.po: Updated Ukranian translation.
 876
 877 2020-01-20  Alan Modra  <amodra@gmail.com>
 878
 879         * hppa-dis.c (fput_const): Remove useless cast.
 880
 881 2020-01-20  Alan Modra  <amodra@gmail.com>
 882
 883         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 884
 885 2020-01-18  Nick Clifton  <nickc@redhat.com>
 886
 887         * configure: Regenerate.
 888         * po/opcodes.pot: Regenerate.
 889
 890 2020-01-18  Nick Clifton  <nickc@redhat.com>
 891
 892         Binutils 2.34 branch created.
 893
 894 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 895
 896         * opintl.h: Fix spelling error (seperate).
 897
 898 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 899
 900         * i386-opc.tbl: Add {vex} pseudo prefix.
 901         * i386-tbl.h: Regenerated.
 902
 903 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 904
 905         PR 25376
 906         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 907         (neon_opcodes): Likewise.
 908         (select_arm_features): Make sure we enable MVE bits when selecting
 909         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 910         any architecture.
 911
 912 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 913
 914         * i386-opc.tbl: Drop stale comment from XOP section.
 915
 916 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 917
 918         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 919         (extractps): Add VexWIG to SSE2AVX forms.
 920         * i386-tbl.h: Re-generate.
 921
 922 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 923
 924         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 925         Size64 from and use VexW1 on SSE2AVX forms.
 926         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 927         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 928         * i386-tbl.h: Re-generate.
 929
 930 2020-01-15  Alan Modra  <amodra@gmail.com>
 931
 932         * tic4x-dis.c (tic4x_version): Make unsigned long.
 933         (optab, optab_special, registernames): New file scope vars.
 934         (tic4x_print_register): Set up registernames rather than
 935         malloc'd registertable.
 936         (tic4x_disassemble): Delete optable and optable_special.  Use
 937         optab and optab_special instead.  Throw away old optab,
 938         optab_special and registernames when info->mach changes.
 939
 940 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 941
 942         PR 25377
 943         * z80-dis.c (suffix): Use .db instruction to generate double
 944         prefix.
 945
 946 2020-01-14  Alan Modra  <amodra@gmail.com>
 947
 948         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 949         values to unsigned before shifting.
 950
 951 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 952
 953         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 954         flow instructions.
 955         (print_insn_thumb16, print_insn_thumb32): Likewise.
 956         (print_insn): Initialize the insn info.
 957         * i386-dis.c (print_insn): Initialize the insn info fields, and
 958         detect jumps.
 959
 960 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 961
 962         * arc-opc.c (C_NE): Make it required.
 963
 964 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 965
 966         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 967         reserved register name.
 968
 969 2020-01-13  Alan Modra  <amodra@gmail.com>
 970
 971         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 972         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 973
 974 2020-01-13  Alan Modra  <amodra@gmail.com>
 975
 976         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 977         result of wasm_read_leb128 in a uint64_t and check that bits
 978         are not lost when copying to other locals.  Use uint32_t for
 979         most locals.  Use PRId64 when printing int64_t.
 980
 981 2020-01-13  Alan Modra  <amodra@gmail.com>
 982
 983         * score-dis.c: Formatting.
 984         * score7-dis.c: Formatting.
 985
 986 2020-01-13  Alan Modra  <amodra@gmail.com>
 987
 988         * score-dis.c (print_insn_score48): Use unsigned variables for
 989         unsigned values.  Don't left shift negative values.
 990         (print_insn_score32): Likewise.
 991         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 992
 993 2020-01-13  Alan Modra  <amodra@gmail.com>
 994
 995         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 996
 997 2020-01-13  Alan Modra  <amodra@gmail.com>
 998
 999         * fr30-ibld.c: Regenerate.
1000
1001 2020-01-13  Alan Modra  <amodra@gmail.com>
1002
1003         * xgate-dis.c (print_insn): Don't left shift signed value.
1004         (ripBits): Formatting, use 1u.
1005
1006 2020-01-10  Alan Modra  <amodra@gmail.com>
1007
1008         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1009         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1010
1011 2020-01-10  Alan Modra  <amodra@gmail.com>
1012
1013         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1014         and XRREG value earlier to avoid a shift with negative exponent.
1015         * m10200-dis.c (disassemble): Similarly.
1016
1017 2020-01-09  Nick Clifton  <nickc@redhat.com>
1018
1019         PR 25224
1020         * z80-dis.c (ld_ii_ii): Use correct cast.
1021
1022 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1023
1024         PR 25224
1025         * z80-dis.c (ld_ii_ii): Use character constant when checking
1026         opcode byte value.
1027
1028 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1029
1030         * i386-dis.c (SEP_Fixup): New.
1031         (SEP): Define.
1032         (dis386_twobyte): Use it for sysenter/sysexit.
1033         (enum x86_64_isa): Change amd64 enumerator to value 1.
1034         (OP_J): Compare isa64 against intel64 instead of amd64.
1035         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1036         forms.
1037         * i386-tbl.h: Re-generate.
1038
1039 2020-01-08  Alan Modra  <amodra@gmail.com>
1040
1041         * z8k-dis.c: Include libiberty.h
1042         (instr_data_s): Make max_fetched unsigned.
1043         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1044         Don't exceed byte_info bounds.
1045         (output_instr): Make num_bytes unsigned.
1046         (unpack_instr): Likewise for nibl_count and loop.
1047         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1048         idx unsigned.
1049         * z8k-opc.h: Regenerate.
1050
1051 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1052
1053         * arc-tbl.h (llock): Use 'LLOCK' as class.
1054         (llockd): Likewise.
1055         (scond): Use 'SCOND' as class.
1056         (scondd): Likewise.
1057         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1058         (scondd): Likewise.
1059
1060 2020-01-06  Alan Modra  <amodra@gmail.com>
1061
1062         * m32c-ibld.c: Regenerate.
1063
1064 2020-01-06  Alan Modra  <amodra@gmail.com>
1065
1066         PR 25344
1067         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1068         Peek at next byte to prevent recursion on repeated prefix bytes.
1069         Ensure uninitialised "mybuf" is not accessed.
1070         (print_insn_z80): Don't zero n_fetch and n_used here,..
1071         (print_insn_z80_buf): ..do it here instead.
1072
1073 2020-01-04  Alan Modra  <amodra@gmail.com>
1074
1075         * m32r-ibld.c: Regenerate.
1076
1077 2020-01-04  Alan Modra  <amodra@gmail.com>
1078
1079         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1080
1081 2020-01-04  Alan Modra  <amodra@gmail.com>
1082
1083         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1084
1085 2020-01-04  Alan Modra  <amodra@gmail.com>
1086
1087         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1088
1089 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1090
1091         * aarch64-tbl.h (aarch64_opcode_table): Use
1092         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1093
1094 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1095
1096         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1097         forms of SUDOT and USDOT.
1098
1099 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1100
1101         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1102         uzip{1,2}.
1103         * opcodes/aarch64-dis-2.c: Re-generate.
1104
1105 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1106
1107         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1108         FMMLA encoding.
1109         * opcodes/aarch64-dis-2.c: Re-generate.
1110
1111 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1112
1113         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1114
1115 2020-01-01  Alan Modra  <amodra@gmail.com>
1116
1117         Update year range in copyright notice of all files.
1118
1119 For older changes see ChangeLog-2019
1120 \f
1121 Copyright (C) 2020 Free Software Foundation, Inc.
1122
1123 Copying and distribution of this file, with or without modification,
1124 are permitted in any medium without royalty provided the copyright
1125 notice and this notice are preserved.
1126
1127 Local Variables:
1128 mode: change-log
1129 left-margin: 8
1130 fill-column: 74
1131 version-control: never
1132 End: