opcodes/ChangeLog

   1 2018-07-11  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.h: Rename OTMax to OTNum.
   4         (OTNumOfUints): Adjust calculation.
   5         (OTUnused): Directly alias to OTNum.
   6
   7 2018-07-09  Maciej W. Rozycki  <macro@mips.com>
   8
   9         * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
  10         `reg_xys'.
  11         (lea_reg_xys): Likewise.
  12         (print_insn_loop_primitive): Rename `reg' local variable to
  13         `reg_dxy'.
  14
  15 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
  16
  17         PR binutils/23242
  18         * aarch64-tbl.h (ldarh): Fix disassembly mask.
  19
  20 2018-07-06  Tamar Christina  <tamar.christina@arm.com>
  21
  22         PR binutils/23369
  23         * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
  24         vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
  25
  26 2018-07-02  Maciej W. Rozycki  <macro@mips.com>
  27
  28         PR tdep/8282
  29         * mips-dis.c (mips_option_arg_t): New enumeration.
  30         (mips_options): New variable.
  31         (disassembler_options_mips): New function.
  32         (print_mips_disassembler_options): Reimplement in terms of
  33         `disassembler_options_mips'.
  34         * arm-dis.c (disassembler_options_arm): Adapt to using the
  35         `disasm_options_and_args_t' structure.
  36         * ppc-dis.c (disassembler_options_powerpc): Likewise.
  37         * s390-dis.c (disassembler_options_s390): Likewise.
  38
  39 2018-07-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  40
  41         * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
  42         expected result.
  43         * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
  44         * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
  45         * testsuite/ld-arm/tls-longplt.d: Likewise.
  46
  47 2018-06-29  Tamar Christina  <tamar.christina@arm.com>
  48
  49         PR binutils/23192
  50         * aarch64-asm-2.c: Regenerate.
  51         * aarch64-dis-2.c: Likewise.
  52         * aarch64-opc-2.c: Likewise.
  53         * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
  54         * aarch64-opc.c (operand_general_constraint_met_p,
  55         aarch64_print_operand): Likewise.
  56         * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
  57         smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
  58         fmlal2, fmlsl2.
  59         (AARCH64_OPERANDS): Add Em2.
  60
  61 2018-06-26  Nick Clifton  <nickc@redhat.com>
  62
  63         * po/uk.po: Updated Ukranian translation.
  64         * po/de.po: Updated German translation.
  65         * po/pt_BR.po: Updated Brazilian Portuguese translation.
  66
  67 2018-06-26  Nick Clifton  <nickc@redhat.com>
  68
  69         * nfp-dis.c: Fix spelling mistake.
  70
  71 2018-06-24  Nick Clifton  <nickc@redhat.com>
  72
  73         * configure: Regenerate.
  74         * po/opcodes.pot: Regenerate.
  75
  76 2018-06-24  Nick Clifton  <nickc@redhat.com>
  77
  78         2.31 branch created.
  79
  80 2018-06-19  Tamar Christina  <tamar.christina@arm.com>
  81
  82         * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
  83         * aarch64-asm-2.c: Regenerate.
  84         * aarch64-dis-2.c: Likewise.
  85
  86 2018-06-21  Maciej W. Rozycki  <macro@mips.com>
  87
  88         * mips-dis.c (print_mips_disassembler_options): Fix a typo in
  89         `-M ginv' option description.
  90
  91 2018-06-20  Sebastian Huber  <sebastian.huber@embedded-brains.de>
  92
  93         PR gas/23305
  94         * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
  95         la and lla.
  96
  97 2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
  98
  99         * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
 100         * configure.ac: Remove AC_PREREQ.
 101         * Makefile.in: Re-generate.
 102         * aclocal.m4: Re-generate.
 103         * configure: Re-generate.
 104
 105 2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 106
 107         * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
 108         mips64r6 descriptors.
 109         (parse_mips_ase_option): Handle -Mginv option.
 110         (print_mips_disassembler_options): Document -Mginv.
 111         * mips-opc.c (decode_mips_operand) <+\>: New operand format.
 112         (GINV): New macro.
 113         (mips_opcodes): Define ginvi and ginvt.
 114
 115 2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
 116             Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
 117
 118         * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
 119         * mips-opc.c (CRC, CRC64): New macros.
 120         (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
 121         crc32cb, crc32ch and crc32cw for CRC.  Define crc32d and
 122         crc32cd for CRC64.
 123
 124 2018-06-08  Egeyar Bagcioglu  <egeyar.bagcioglu@oracle.com>
 125
 126         PR 20319
 127         * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 128         (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
 129
 130 2018-06-06  Alan Modra  <amodra@gmail.com>
 131
 132         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
 133         setjmp.  Move init for some other vars later too.
 134
 135 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
 136
 137         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
 138         (dis_private): Add new fields for property section tracking.
 139         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
 140         (xtensa_instruction_fits): New functions.
 141         (fetch_data): Bump minimal fetch size to 4.
 142         (print_insn_xtensa): Make struct dis_private static.
 143         Load and prepare property table on section change.
 144         Don't disassemble literals. Don't disassemble instructions that
 145         cross property table boundaries.
 146
 147 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
 148
 149         * configure: Regenerated.
 150
 151 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
 154         * i386-tbl.h: Re-generate.
 155
 156 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 157
 158         * i386-opc.tbl (sldt, str): Add NoRex64.
 159         * i386-tbl.h: Re-generate.
 160
 161 2018-06-01  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-opc.tbl (invpcid): Add Oword.
 164         * i386-tbl.h: Re-generate.
 165
 166 2018-06-01  Alan Modra  <amodra@gmail.com>
 167
 168         * sysdep.h (_bfd_error_handler): Don't declare.
 169         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
 170         * rl78-decode.opc: Likewise.
 171         * msp430-decode.c: Regenerate.
 172         * rl78-decode.c: Regenerate.
 173
 174 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
 175
 176         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
 177         * i386-init.h : Regenerated.
 178
 179 2018-05-25  Alan Modra  <amodra@gmail.com>
 180
 181         * Makefile.in: Regenerate.
 182         * po/POTFILES.in: Regenerate.
 183
 184 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
 185
 186         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
 187         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
 188         (insert_bab, extract_bab, insert_btab, extract_btab,
 189         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
 190         (BAT, BBA VBA RBS XB6S): Delete macros.
 191         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
 192         (BB, BD, RBX, XC6): Update for new macros.
 193         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
 194         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
 195         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
 196         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
 197
 198 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
 199
 200         * Makefile.am: Add support for s12z architecture.
 201         * configure.ac: Likewise.
 202         * disassemble.c: Likewise.
 203         * disassemble.h: Likewise.
 204         * Makefile.in: Regenerate.
 205         * configure: Regenerate.
 206         * s12z-dis.c: New file.
 207         * s12z.h: New file.
 208
 209 2018-05-18  Alan Modra  <amodra@gmail.com>
 210
 211         * nfp-dis.c: Don't #include libbfd.h.
 212         (init_nfp3200_priv): Use bfd_get_section_contents.
 213         (nit_nfp6000_mecsr_sec): Likewise.
 214
 215 2018-05-17  Nick Clifton  <nickc@redhat.com>
 216
 217         * po/zh_CN.po: Updated simplified Chinese translation.
 218
 219 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
 220
 221         PR binutils/23109
 222         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
 223         * aarch64-dis-2.c: Regenerate.
 224
 225 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 226
 227         PR binutils/21446
 228         * aarch64-asm.c (opintl.h): Include.
 229         (aarch64_ins_sysreg): Enforce read/write constraints.
 230         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 231         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 232         (F_REG_READ, F_REG_WRITE): New.
 233         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 234         AARCH64_OPND_SYSREG.
 235         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 236         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 237         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 238         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 239         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 240         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 241         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 242         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 243         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 244         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 245         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 246         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 247         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 248         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 249         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 250         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 251         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 252
 253 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 254
 255         PR binutils/21446
 256         * aarch64-dis.c (no_notes: New.
 257         (parse_aarch64_dis_option): Support notes.
 258         (aarch64_decode_insn, print_operands): Likewise.
 259         (print_aarch64_disassembler_options): Document notes.
 260         * aarch64-opc.c (aarch64_print_operand): Support notes.
 261
 262 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 263
 264         PR binutils/21446
 265         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 266         and take error struct.
 267         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 268         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 269         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 270         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 271         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 272         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 273         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 274         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 275         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 276         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 277         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 278         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 279         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 280         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 281         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 282         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 283         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 284         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 285         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 286         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 287         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 288         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 289         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 290         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 291         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 292         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 293         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 294         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 295         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 296         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 297         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 298         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 299         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 300         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 301         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 302         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 303         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 304         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 305         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 306         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 307         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 308         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 309         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 310         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 311         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 312         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 313         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 314         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 315         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 316         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 317         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 318         (determine_disassembling_preference, aarch64_decode_insn,
 319         print_insn_aarch64_word, print_insn_data): Take errors struct.
 320         (print_insn_aarch64): Use errors.
 321         * aarch64-asm-2.c: Regenerate.
 322         * aarch64-dis-2.c: Regenerate.
 323         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 324         boolean in aarch64_insert_operan.
 325         (print_operand_extractor): Likewise.
 326         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 327
 328 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 329
 330         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 331
 332 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 333
 334         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 335
 336 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 337
 338         * cr16-opc.c (cr16_instruction): Comment typo fix.
 339         * hppa-dis.c (print_insn_hppa): Likewise.
 340
 341 2018-05-08  Jim Wilson  <jimw@sifive.com>
 342
 343         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 344         (match_c_slli64, match_srxi_as_c_srxi): New.
 345         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 346         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 347         <c.slli, c.srli, c.srai>: Use match_s_slli.
 348         <c.slli64, c.srli64, c.srai64>: New.
 349
 350 2018-05-08  Alan Modra  <amodra@gmail.com>
 351
 352         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 353         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 354         partition opcode space for index lookup.
 355
 356 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 357
 358         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 359         <insn_length>: ...with this.  Update usage.
 360         Remove duplicate call to *info->memory_error_func.
 361
 362 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 363             H.J. Lu  <hongjiu.lu@intel.com>
 364
 365         * i386-dis.c (Gva): New.
 366         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 367         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 368         (prefix_table): New instructions (see prefix above).
 369         (mod_table): New instructions (see prefix above).
 370         (OP_G): Handle va_mode.
 371         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 372         CPU_MOVDIR64B_FLAGS.
 373         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 374         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 375         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 376         * i386-opc.tbl: Add movidir{i,64b}.
 377         * i386-init.h: Regenerated.
 378         * i386-tbl.h: Likewise.
 379
 380 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 381
 382         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 383         AddrPrefixOpReg.
 384         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 385         (AddrPrefixOpReg): This.
 386         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 387         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 388
 389 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 390
 391         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 392         (vle_num_opcodes): Likewise.
 393         (spe2_num_opcodes): Likewise.
 394         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 395         initialization loop.
 396         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 397         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 398         only once.
 399
 400 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 401
 402         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 403
 404 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 405
 406         Makefile.am: Added nfp-dis.c.
 407         configure.ac: Added bfd_nfp_arch.
 408         disassemble.h: Added print_insn_nfp prototype.
 409         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 410         nfp-dis.c: New, for NFP support.
 411         po/POTFILES.in: Added nfp-dis.c to the list.
 412         Makefile.in: Regenerate.
 413         configure: Regenerate.
 414
 415 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 416
 417         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 418         templates into their base ones.
 419         * i386-tlb.h: Re-generate.
 420
 421 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 422
 423         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 424         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 425         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 426         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 427         * i386-init.h: Re-generate.
 428
 429 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 430
 431         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 432         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 433         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 434         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 435         comment.
 436         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 437         and CpuRegMask.
 438         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 439         CpuRegMask: Delete.
 440         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 441         cpuregzmm, and cpuregmask.
 442         * i386-init.h: Re-generate.
 443         * i386-tbl.h: Re-generate.
 444
 445 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 446
 447         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 448         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 449         * i386-init.h: Re-generate.
 450
 451 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 452
 453         * i386-gen.c (VexImmExt): Delete.
 454         * i386-opc.h (VexImmExt, veximmext): Delete.
 455         * i386-opc.tbl: Drop all VexImmExt uses.
 456         * i386-tlb.h: Re-generate.
 457
 458 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 459
 460         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 461         register-only forms.
 462         * i386-tlb.h: Re-generate.
 463
 464 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 465
 466         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 467
 468 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 469
 470         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 471         PREFIX_0F1C.
 472         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 473         (cpu_flags): Add CpuCLDEMOTE.
 474         * i386-init.h: Regenerate.
 475         * i386-opc.h (enum): Add CpuCLDEMOTE,
 476         (i386_cpu_flags): Add cpucldemote.
 477         * i386-opc.tbl: Add cldemote.
 478         * i386-tbl.h: Regenerate.
 479
 480 2018-04-16  Alan Modra  <amodra@gmail.com>
 481
 482         * Makefile.am: Remove sh5 and sh64 support.
 483         * configure.ac: Likewise.
 484         * disassemble.c: Likewise.
 485         * disassemble.h: Likewise.
 486         * sh-dis.c: Likewise.
 487         * sh64-dis.c: Delete.
 488         * sh64-opc.c: Delete.
 489         * sh64-opc.h: Delete.
 490         * Makefile.in: Regenerate.
 491         * configure: Regenerate.
 492         * po/POTFILES.in: Regenerate.
 493
 494 2018-04-16  Alan Modra  <amodra@gmail.com>
 495
 496         * Makefile.am: Remove w65 support.
 497         * configure.ac: Likewise.
 498         * disassemble.c: Likewise.
 499         * disassemble.h: Likewise.
 500         * w65-dis.c: Delete.
 501         * w65-opc.h: Delete.
 502         * Makefile.in: Regenerate.
 503         * configure: Regenerate.
 504         * po/POTFILES.in: Regenerate.
 505
 506 2018-04-16  Alan Modra  <amodra@gmail.com>
 507
 508         * configure.ac: Remove we32k support.
 509         * configure: Regenerate.
 510
 511 2018-04-16  Alan Modra  <amodra@gmail.com>
 512
 513         * Makefile.am: Remove m88k support.
 514         * configure.ac: Likewise.
 515         * disassemble.c: Likewise.
 516         * disassemble.h: Likewise.
 517         * m88k-dis.c: Delete.
 518         * Makefile.in: Regenerate.
 519         * configure: Regenerate.
 520         * po/POTFILES.in: Regenerate.
 521
 522 2018-04-16  Alan Modra  <amodra@gmail.com>
 523
 524         * Makefile.am: Remove i370 support.
 525         * configure.ac: Likewise.
 526         * disassemble.c: Likewise.
 527         * disassemble.h: Likewise.
 528         * i370-dis.c: Delete.
 529         * i370-opc.c: Delete.
 530         * Makefile.in: Regenerate.
 531         * configure: Regenerate.
 532         * po/POTFILES.in: Regenerate.
 533
 534 2018-04-16  Alan Modra  <amodra@gmail.com>
 535
 536         * Makefile.am: Remove h8500 support.
 537         * configure.ac: Likewise.
 538         * disassemble.c: Likewise.
 539         * disassemble.h: Likewise.
 540         * h8500-dis.c: Delete.
 541         * h8500-opc.h: Delete.
 542         * Makefile.in: Regenerate.
 543         * configure: Regenerate.
 544         * po/POTFILES.in: Regenerate.
 545
 546 2018-04-16  Alan Modra  <amodra@gmail.com>
 547
 548         * configure.ac: Remove tahoe support.
 549         * configure: Regenerate.
 550
 551 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 552
 553         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 554         umwait.
 555         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 556         64-bit mode.
 557         * i386-tbl.h: Regenerated.
 558
 559 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 560
 561         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 562         PREFIX_MOD_1_0FAE_REG_6.
 563         (va_mode): New.
 564         (OP_E_register): Use va_mode.
 565         * i386-dis-evex.h (prefix_table):
 566         New instructions (see prefixes above).
 567         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 568         (cpu_flags): Likewise.
 569         * i386-opc.h (enum): Likewise.
 570         (i386_cpu_flags): Likewise.
 571         * i386-opc.tbl: Add umonitor, umwait, tpause.
 572         * i386-init.h: Regenerate.
 573         * i386-tbl.h: Likewise.
 574
 575 2018-04-11  Alan Modra  <amodra@gmail.com>
 576
 577         * opcodes/i860-dis.c: Delete.
 578         * opcodes/i960-dis.c: Delete.
 579         * Makefile.am: Remove i860 and i960 support.
 580         * configure.ac: Likewise.
 581         * disassemble.c: Likewise.
 582         * disassemble.h: Likewise.
 583         * Makefile.in: Regenerate.
 584         * configure: Regenerate.
 585         * po/POTFILES.in: Regenerate.
 586
 587 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 588
 589         PR binutils/23025
 590         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 591         to 0.
 592         (print_insn): Clear vex instead of vex.evex.
 593
 594 2018-04-04  Nick Clifton  <nickc@redhat.com>
 595
 596         * po/es.po: Updated Spanish translation.
 597
 598 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 599
 600         * i386-gen.c (opcode_modifiers): Delete VecESize.
 601         * i386-opc.h (VecESize): Delete.
 602         (struct i386_opcode_modifier): Delete vecesize.
 603         * i386-opc.tbl: Drop VecESize.
 604         * i386-tlb.h: Re-generate.
 605
 606 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 607
 608         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 609         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 610         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 611         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 612         * i386-tlb.h: Re-generate.
 613
 614 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 615
 616         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 617         Fold AVX512 forms
 618         * i386-tlb.h: Re-generate.
 619
 620 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 621
 622         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 623         (vex_len_table): Drop Y for vcvt*2si.
 624         (putop): Replace plain 'Y' handling by abort().
 625
 626 2018-03-28  Nick Clifton  <nickc@redhat.com>
 627
 628         PR 22988
 629         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 630         instructions with only a base address register.
 631         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 632         handle AARHC64_OPND_SVE_ADDR_R.
 633         (aarch64_print_operand): Likewise.
 634         * aarch64-asm-2.c: Regenerate.
 635         * aarch64_dis-2.c: Regenerate.
 636         * aarch64-opc-2.c: Regenerate.
 637
 638 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-opc.tbl: Drop VecESize from register only insn forms and
 641         memory forms not allowing broadcast.
 642         * i386-tlb.h: Re-generate.
 643
 644 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 645
 646         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 647         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 648         sha256*): Drop Disp<N>.
 649
 650 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 651
 652         * i386-dis.c (EbndS, bnd_swap_mode): New.
 653         (prefix_table): Use EbndS.
 654         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 655         * i386-opc.tbl (bndmov): Move misplaced Load.
 656         * i386-tlb.h: Re-generate.
 657
 658 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 659
 660         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 661         templates allowing memory operands and folded ones for register
 662         only flavors.
 663         * i386-tlb.h: Re-generate.
 664
 665 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 666
 667         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 668         256-bit templates. Drop redundant leftover Disp<N>.
 669         * i386-tlb.h: Re-generate.
 670
 671 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 672
 673         * riscv-opc.c (riscv_insn_types): New.
 674
 675 2018-03-13  Nick Clifton  <nickc@redhat.com>
 676
 677         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 678
 679 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 680
 681         * i386-opc.tbl: Add Optimize to clr.
 682         * i386-tbl.h: Regenerated.
 683
 684 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 685
 686         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 687         * i386-opc.h (OldGcc): Removed.
 688         (i386_opcode_modifier): Remove oldgcc.
 689         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 690         instructions for old (<= 2.8.1) versions of gcc.
 691         * i386-tbl.h: Regenerated.
 692
 693 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 694
 695         * i386-opc.h (EVEXDYN): New.
 696         * i386-opc.tbl: Fold various AVX512VL templates.
 697         * i386-tlb.h: Re-generate.
 698
 699 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 700
 701         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 702         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 703         vpexpandd, vpexpandq): Fold AFX512VF templates.
 704         * i386-tlb.h: Re-generate.
 705
 706 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 707
 708         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 709         Fold 128- and 256-bit VEX-encoded templates.
 710         * i386-tlb.h: Re-generate.
 711
 712 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 713
 714         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 715         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 716         vpexpandd, vpexpandq): Fold AVX512F templates.
 717         * i386-tlb.h: Re-generate.
 718
 719 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 720
 721         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 722         64-bit templates. Drop Disp<N>.
 723         * i386-tlb.h: Re-generate.
 724
 725 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 726
 727         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 728         and 256-bit templates.
 729         * i386-tlb.h: Re-generate.
 730
 731 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 732
 733         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 734         * i386-tlb.h: Re-generate.
 735
 736 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 737
 738         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 739         Drop NoAVX.
 740         * i386-tlb.h: Re-generate.
 741
 742 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 743
 744         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 745         * i386-tlb.h: Re-generate.
 746
 747 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 748
 749         * i386-gen.c (opcode_modifiers): Delete FloatD.
 750         * i386-opc.h (FloatD): Delete.
 751         (struct i386_opcode_modifier): Delete floatd.
 752         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 753         FloatD by D.
 754         * i386-tlb.h: Re-generate.
 755
 756 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 757
 758         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 759
 760 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 761
 762         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 763         * i386-tlb.h: Re-generate.
 764
 765 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 766
 767         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 768         forms.
 769         * i386-tlb.h: Re-generate.
 770
 771 2018-03-07  Alan Modra  <amodra@gmail.com>
 772
 773         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 774         bfd_arch_rs6000.
 775         * disassemble.h (print_insn_rs6000): Delete.
 776         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 777         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 778         (print_insn_rs6000): Delete.
 779
 780 2018-03-03  Alan Modra  <amodra@gmail.com>
 781
 782         * sysdep.h (opcodes_error_handler): Define.
 783         (_bfd_error_handler): Declare.
 784         * Makefile.am: Remove stray #.
 785         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 786         EDIT" comment.
 787         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 788         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 789         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 790         opcodes_error_handler to print errors.  Standardize error messages.
 791         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 792         and include opintl.h.
 793         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 794         * i386-gen.c: Standardize error messages.
 795         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 796         * Makefile.in: Regenerate.
 797         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 798         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 799         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 800         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 801         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 802         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 803         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 804         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 805         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 806         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 807         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 808         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 809         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 810
 811 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 812
 813         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 814         vpsub[bwdq] instructions.
 815         * i386-tbl.h: Regenerated.
 816
 817 2018-03-01  Alan Modra  <amodra@gmail.com>
 818
 819         * configure.ac (ALL_LINGUAS): Sort.
 820         * configure: Regenerate.
 821
 822 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 823
 824         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 825         macro by assignements.
 826
 827 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 828
 829         PR gas/22871
 830         * i386-gen.c (opcode_modifiers): Add Optimize.
 831         * i386-opc.h (Optimize): New enum.
 832         (i386_opcode_modifier): Add optimize.
 833         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 834         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 835         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 836         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 837         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 838         vpxord and vpxorq.
 839         * i386-tbl.h: Regenerated.
 840
 841 2018-02-26  Alan Modra  <amodra@gmail.com>
 842
 843         * crx-dis.c (getregliststring): Allocate a large enough buffer
 844         to silence false positive gcc8 warning.
 845
 846 2018-02-22  Shea Levy <shea@shealevy.com>
 847
 848         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 849
 850 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 851
 852         * i386-opc.tbl: Add {rex},
 853         * i386-tbl.h: Regenerated.
 854
 855 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 856
 857         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 858         (mips16_opcodes): Replace `M' with `m' for "restore".
 859
 860 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 861
 862         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 863
 864 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 865
 866         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 867         variable to `function_index'.
 868
 869 2018-02-13  Nick Clifton  <nickc@redhat.com>
 870
 871         PR 22823
 872         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 873         about truncation of printing.
 874
 875 2018-02-12  Henry Wong <henry@stuffedcow.net>
 876
 877         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 878
 879 2018-02-05  Nick Clifton  <nickc@redhat.com>
 880
 881         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 882
 883 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 884
 885         * i386-dis.c (enum): Add pconfig.
 886         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 887         (cpu_flags): Add CpuPCONFIG.
 888         * i386-opc.h (enum): Add CpuPCONFIG.
 889         (i386_cpu_flags): Add cpupconfig.
 890         * i386-opc.tbl: Add PCONFIG instruction.
 891         * i386-init.h: Regenerate.
 892         * i386-tbl.h: Likewise.
 893
 894 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 895
 896         * i386-dis.c (enum): Add PREFIX_0F09.
 897         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 898         (cpu_flags): Add CpuWBNOINVD.
 899         * i386-opc.h (enum): Add CpuWBNOINVD.
 900         (i386_cpu_flags): Add cpuwbnoinvd.
 901         * i386-opc.tbl: Add WBNOINVD instruction.
 902         * i386-init.h: Regenerate.
 903         * i386-tbl.h: Likewise.
 904
 905 2018-01-17  Jim Wilson  <jimw@sifive.com>
 906
 907         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 908
 909 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 910
 911         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 912         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 913         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 914         (cpu_flags): Add CpuIBT, CpuSHSTK.
 915         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 916         (i386_cpu_flags): Add cpuibt, cpushstk.
 917         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 918         * i386-init.h: Regenerate.
 919         * i386-tbl.h: Likewise.
 920
 921 2018-01-16  Nick Clifton  <nickc@redhat.com>
 922
 923         * po/pt_BR.po: Updated Brazilian Portugese translation.
 924         * po/de.po: Updated German translation.
 925
 926 2018-01-15  Jim Wilson  <jimw@sifive.com>
 927
 928         * riscv-opc.c (match_c_nop): New.
 929         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 930
 931 2018-01-15  Nick Clifton  <nickc@redhat.com>
 932
 933         * po/uk.po: Updated Ukranian translation.
 934
 935 2018-01-13  Nick Clifton  <nickc@redhat.com>
 936
 937         * po/opcodes.pot: Regenerated.
 938
 939 2018-01-13  Nick Clifton  <nickc@redhat.com>
 940
 941         * configure: Regenerate.
 942
 943 2018-01-13  Nick Clifton  <nickc@redhat.com>
 944
 945         2.30 branch created.
 946
 947 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 948
 949         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 950         * i386-tbl.h: Regenerate.
 951
 952 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 953
 954         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 955         * i386-tbl.h: Re-generate.
 956
 957 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 958
 959         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 960         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 961         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 962         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 963         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 964         Disp8MemShift of AVX512VL forms.
 965         * i386-tbl.h: Re-generate.
 966
 967 2018-01-09  Jim Wilson  <jimw@sifive.com>
 968
 969         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 970         then the hi_addr value is zero.
 971
 972 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 973
 974         * arm-dis.c (arm_opcodes): Add csdb.
 975         (thumb32_opcodes): Add csdb.
 976
 977 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 978
 979         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 980         * aarch64-asm-2.c: Regenerate.
 981         * aarch64-dis-2.c: Regenerate.
 982         * aarch64-opc-2.c: Regenerate.
 983
 984 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 985
 986         PR gas/22681
 987         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 988         Remove AVX512 vmovd with 64-bit operands.
 989         * i386-tbl.h: Regenerated.
 990
 991 2018-01-05  Jim Wilson  <jimw@sifive.com>
 992
 993         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 994         jalr.
 995
 996 2018-01-03  Alan Modra  <amodra@gmail.com>
 997
 998         Update year range in copyright notice of all files.
 999
1000 2018-01-02  Jan Beulich  <jbeulich@suse.com>
1001
1002         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1003         and OPERAND_TYPE_REGZMM entries.
1004
1005 For older changes see ChangeLog-2017
1006 \f
1007 Copyright (C) 2018 Free Software Foundation, Inc.
1008
1009 Copying and distribution of this file, with or without modification,
1010 are permitted in any medium without royalty provided the copyright
1011 notice and this notice are preserved.
1012
1013 Local Variables:
1014 mode: change-log
1015 left-margin: 8
1016 fill-column: 74
1017 version-control: never
1018 End: