1 2018-07-06 Tamar Christina <tamar.christina@arm.com>
4 * aarch64-tbl.h (ldarh): Fix disassembly mask.
6 2018-07-06 Tamar Christina <tamar.christina@arm.com>
9 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
10 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
12 2018-07-02 Maciej W. Rozycki <macro@mips.com>
15 * mips-dis.c (mips_option_arg_t): New enumeration.
16 (mips_options): New variable.
17 (disassembler_options_mips): New function.
18 (print_mips_disassembler_options): Reimplement in terms of
19 `disassembler_options_mips'.
20 * arm-dis.c (disassembler_options_arm): Adapt to using the
21 `disasm_options_and_args_t' structure.
22 * ppc-dis.c (disassembler_options_powerpc): Likewise.
23 * s390-dis.c (disassembler_options_s390): Likewise.
25 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
27 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
29 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
30 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
31 * testsuite/ld-arm/tls-longplt.d: Likewise.
33 2018-06-29 Tamar Christina <tamar.christina@arm.com>
36 * aarch64-asm-2.c: Regenerate.
37 * aarch64-dis-2.c: Likewise.
38 * aarch64-opc-2.c: Likewise.
39 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
40 * aarch64-opc.c (operand_general_constraint_met_p,
41 aarch64_print_operand): Likewise.
42 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
43 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
45 (AARCH64_OPERANDS): Add Em2.
47 2018-06-26 Nick Clifton <nickc@redhat.com>
49 * po/uk.po: Updated Ukranian translation.
50 * po/de.po: Updated German translation.
51 * po/pt_BR.po: Updated Brazilian Portuguese translation.
53 2018-06-26 Nick Clifton <nickc@redhat.com>
55 * nfp-dis.c: Fix spelling mistake.
57 2018-06-24 Nick Clifton <nickc@redhat.com>
59 * configure: Regenerate.
60 * po/opcodes.pot: Regenerate.
62 2018-06-24 Nick Clifton <nickc@redhat.com>
66 2018-06-19 Tamar Christina <tamar.christina@arm.com>
68 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
69 * aarch64-asm-2.c: Regenerate.
70 * aarch64-dis-2.c: Likewise.
72 2018-06-21 Maciej W. Rozycki <macro@mips.com>
74 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
75 `-M ginv' option description.
77 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
80 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
83 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
85 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
86 * configure.ac: Remove AC_PREREQ.
87 * Makefile.in: Re-generate.
88 * aclocal.m4: Re-generate.
89 * configure: Re-generate.
91 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
93 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
95 (parse_mips_ase_option): Handle -Mginv option.
96 (print_mips_disassembler_options): Document -Mginv.
97 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
99 (mips_opcodes): Define ginvi and ginvt.
101 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
102 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
104 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
105 * mips-opc.c (CRC, CRC64): New macros.
106 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
107 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
110 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
113 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
114 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
116 2018-06-06 Alan Modra <amodra@gmail.com>
118 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
119 setjmp. Move init for some other vars later too.
121 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
123 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
124 (dis_private): Add new fields for property section tracking.
125 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
126 (xtensa_instruction_fits): New functions.
127 (fetch_data): Bump minimal fetch size to 4.
128 (print_insn_xtensa): Make struct dis_private static.
129 Load and prepare property table on section change.
130 Don't disassemble literals. Don't disassemble instructions that
131 cross property table boundaries.
133 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
135 * configure: Regenerated.
137 2018-06-01 Jan Beulich <jbeulich@suse.com>
139 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
140 * i386-tbl.h: Re-generate.
142 2018-06-01 Jan Beulich <jbeulich@suse.com>
144 * i386-opc.tbl (sldt, str): Add NoRex64.
145 * i386-tbl.h: Re-generate.
147 2018-06-01 Jan Beulich <jbeulich@suse.com>
149 * i386-opc.tbl (invpcid): Add Oword.
150 * i386-tbl.h: Re-generate.
152 2018-06-01 Alan Modra <amodra@gmail.com>
154 * sysdep.h (_bfd_error_handler): Don't declare.
155 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
156 * rl78-decode.opc: Likewise.
157 * msp430-decode.c: Regenerate.
158 * rl78-decode.c: Regenerate.
160 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
162 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
163 * i386-init.h : Regenerated.
165 2018-05-25 Alan Modra <amodra@gmail.com>
167 * Makefile.in: Regenerate.
168 * po/POTFILES.in: Regenerate.
170 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
172 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
173 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
174 (insert_bab, extract_bab, insert_btab, extract_btab,
175 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
176 (BAT, BBA VBA RBS XB6S): Delete macros.
177 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
178 (BB, BD, RBX, XC6): Update for new macros.
179 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
180 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
181 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
182 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
184 2018-05-18 John Darrington <john@darrington.wattle.id.au>
186 * Makefile.am: Add support for s12z architecture.
187 * configure.ac: Likewise.
188 * disassemble.c: Likewise.
189 * disassemble.h: Likewise.
190 * Makefile.in: Regenerate.
191 * configure: Regenerate.
192 * s12z-dis.c: New file.
195 2018-05-18 Alan Modra <amodra@gmail.com>
197 * nfp-dis.c: Don't #include libbfd.h.
198 (init_nfp3200_priv): Use bfd_get_section_contents.
199 (nit_nfp6000_mecsr_sec): Likewise.
201 2018-05-17 Nick Clifton <nickc@redhat.com>
203 * po/zh_CN.po: Updated simplified Chinese translation.
205 2018-05-16 Tamar Christina <tamar.christina@arm.com>
208 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
209 * aarch64-dis-2.c: Regenerate.
211 2018-05-15 Tamar Christina <tamar.christina@arm.com>
214 * aarch64-asm.c (opintl.h): Include.
215 (aarch64_ins_sysreg): Enforce read/write constraints.
216 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
217 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
218 (F_REG_READ, F_REG_WRITE): New.
219 * aarch64-opc.c (aarch64_print_operand): Generate notes for
221 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
222 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
223 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
224 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
225 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
226 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
227 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
228 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
229 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
230 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
231 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
232 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
233 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
234 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
235 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
236 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
237 msr (F_SYS_WRITE), mrs (F_SYS_READ).
239 2018-05-15 Tamar Christina <tamar.christina@arm.com>
242 * aarch64-dis.c (no_notes: New.
243 (parse_aarch64_dis_option): Support notes.
244 (aarch64_decode_insn, print_operands): Likewise.
245 (print_aarch64_disassembler_options): Document notes.
246 * aarch64-opc.c (aarch64_print_operand): Support notes.
248 2018-05-15 Tamar Christina <tamar.christina@arm.com>
251 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
252 and take error struct.
253 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
254 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
255 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
256 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
257 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
258 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
259 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
260 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
261 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
262 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
263 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
264 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
265 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
266 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
267 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
268 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
269 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
270 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
271 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
272 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
273 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
274 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
275 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
276 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
277 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
278 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
279 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
280 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
281 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
282 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
283 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
284 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
285 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
286 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
287 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
288 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
289 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
290 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
291 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
292 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
293 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
294 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
295 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
296 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
297 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
298 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
299 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
300 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
301 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
302 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
303 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
304 (determine_disassembling_preference, aarch64_decode_insn,
305 print_insn_aarch64_word, print_insn_data): Take errors struct.
306 (print_insn_aarch64): Use errors.
307 * aarch64-asm-2.c: Regenerate.
308 * aarch64-dis-2.c: Regenerate.
309 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
310 boolean in aarch64_insert_operan.
311 (print_operand_extractor): Likewise.
312 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
314 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
316 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
318 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
320 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
322 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
324 * cr16-opc.c (cr16_instruction): Comment typo fix.
325 * hppa-dis.c (print_insn_hppa): Likewise.
327 2018-05-08 Jim Wilson <jimw@sifive.com>
329 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
330 (match_c_slli64, match_srxi_as_c_srxi): New.
331 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
332 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
333 <c.slli, c.srli, c.srai>: Use match_s_slli.
334 <c.slli64, c.srli64, c.srai64>: New.
336 2018-05-08 Alan Modra <amodra@gmail.com>
338 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
339 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
340 partition opcode space for index lookup.
342 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
344 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
345 <insn_length>: ...with this. Update usage.
346 Remove duplicate call to *info->memory_error_func.
348 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
349 H.J. Lu <hongjiu.lu@intel.com>
351 * i386-dis.c (Gva): New.
352 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
353 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
354 (prefix_table): New instructions (see prefix above).
355 (mod_table): New instructions (see prefix above).
356 (OP_G): Handle va_mode.
357 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
359 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
360 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
361 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
362 * i386-opc.tbl: Add movidir{i,64b}.
363 * i386-init.h: Regenerated.
364 * i386-tbl.h: Likewise.
366 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
368 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
370 * i386-opc.h (AddrPrefixOp0): Renamed to ...
371 (AddrPrefixOpReg): This.
372 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
373 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
375 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
377 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
378 (vle_num_opcodes): Likewise.
379 (spe2_num_opcodes): Likewise.
380 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
382 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
383 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
386 2018-05-01 Tamar Christina <tamar.christina@arm.com>
388 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
390 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
392 Makefile.am: Added nfp-dis.c.
393 configure.ac: Added bfd_nfp_arch.
394 disassemble.h: Added print_insn_nfp prototype.
395 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
396 nfp-dis.c: New, for NFP support.
397 po/POTFILES.in: Added nfp-dis.c to the list.
398 Makefile.in: Regenerate.
399 configure: Regenerate.
401 2018-04-26 Jan Beulich <jbeulich@suse.com>
403 * i386-opc.tbl: Fold various non-memory operand AVX512VL
404 templates into their base ones.
405 * i386-tlb.h: Re-generate.
407 2018-04-26 Jan Beulich <jbeulich@suse.com>
409 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
410 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
411 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
412 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
413 * i386-init.h: Re-generate.
415 2018-04-26 Jan Beulich <jbeulich@suse.com>
417 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
418 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
419 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
420 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
422 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
424 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
426 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
427 cpuregzmm, and cpuregmask.
428 * i386-init.h: Re-generate.
429 * i386-tbl.h: Re-generate.
431 2018-04-26 Jan Beulich <jbeulich@suse.com>
433 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
434 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
435 * i386-init.h: Re-generate.
437 2018-04-26 Jan Beulich <jbeulich@suse.com>
439 * i386-gen.c (VexImmExt): Delete.
440 * i386-opc.h (VexImmExt, veximmext): Delete.
441 * i386-opc.tbl: Drop all VexImmExt uses.
442 * i386-tlb.h: Re-generate.
444 2018-04-25 Jan Beulich <jbeulich@suse.com>
446 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
448 * i386-tlb.h: Re-generate.
450 2018-04-25 Tamar Christina <tamar.christina@arm.com>
452 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
454 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
456 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
458 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
459 (cpu_flags): Add CpuCLDEMOTE.
460 * i386-init.h: Regenerate.
461 * i386-opc.h (enum): Add CpuCLDEMOTE,
462 (i386_cpu_flags): Add cpucldemote.
463 * i386-opc.tbl: Add cldemote.
464 * i386-tbl.h: Regenerate.
466 2018-04-16 Alan Modra <amodra@gmail.com>
468 * Makefile.am: Remove sh5 and sh64 support.
469 * configure.ac: Likewise.
470 * disassemble.c: Likewise.
471 * disassemble.h: Likewise.
472 * sh-dis.c: Likewise.
473 * sh64-dis.c: Delete.
474 * sh64-opc.c: Delete.
475 * sh64-opc.h: Delete.
476 * Makefile.in: Regenerate.
477 * configure: Regenerate.
478 * po/POTFILES.in: Regenerate.
480 2018-04-16 Alan Modra <amodra@gmail.com>
482 * Makefile.am: Remove w65 support.
483 * configure.ac: Likewise.
484 * disassemble.c: Likewise.
485 * disassemble.h: Likewise.
488 * Makefile.in: Regenerate.
489 * configure: Regenerate.
490 * po/POTFILES.in: Regenerate.
492 2018-04-16 Alan Modra <amodra@gmail.com>
494 * configure.ac: Remove we32k support.
495 * configure: Regenerate.
497 2018-04-16 Alan Modra <amodra@gmail.com>
499 * Makefile.am: Remove m88k support.
500 * configure.ac: Likewise.
501 * disassemble.c: Likewise.
502 * disassemble.h: Likewise.
503 * m88k-dis.c: Delete.
504 * Makefile.in: Regenerate.
505 * configure: Regenerate.
506 * po/POTFILES.in: Regenerate.
508 2018-04-16 Alan Modra <amodra@gmail.com>
510 * Makefile.am: Remove i370 support.
511 * configure.ac: Likewise.
512 * disassemble.c: Likewise.
513 * disassemble.h: Likewise.
514 * i370-dis.c: Delete.
515 * i370-opc.c: Delete.
516 * Makefile.in: Regenerate.
517 * configure: Regenerate.
518 * po/POTFILES.in: Regenerate.
520 2018-04-16 Alan Modra <amodra@gmail.com>
522 * Makefile.am: Remove h8500 support.
523 * configure.ac: Likewise.
524 * disassemble.c: Likewise.
525 * disassemble.h: Likewise.
526 * h8500-dis.c: Delete.
527 * h8500-opc.h: Delete.
528 * Makefile.in: Regenerate.
529 * configure: Regenerate.
530 * po/POTFILES.in: Regenerate.
532 2018-04-16 Alan Modra <amodra@gmail.com>
534 * configure.ac: Remove tahoe support.
535 * configure: Regenerate.
537 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
539 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
541 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
543 * i386-tbl.h: Regenerated.
545 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
547 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
548 PREFIX_MOD_1_0FAE_REG_6.
550 (OP_E_register): Use va_mode.
551 * i386-dis-evex.h (prefix_table):
552 New instructions (see prefixes above).
553 * i386-gen.c (cpu_flag_init): Add WAITPKG.
554 (cpu_flags): Likewise.
555 * i386-opc.h (enum): Likewise.
556 (i386_cpu_flags): Likewise.
557 * i386-opc.tbl: Add umonitor, umwait, tpause.
558 * i386-init.h: Regenerate.
559 * i386-tbl.h: Likewise.
561 2018-04-11 Alan Modra <amodra@gmail.com>
563 * opcodes/i860-dis.c: Delete.
564 * opcodes/i960-dis.c: Delete.
565 * Makefile.am: Remove i860 and i960 support.
566 * configure.ac: Likewise.
567 * disassemble.c: Likewise.
568 * disassemble.h: Likewise.
569 * Makefile.in: Regenerate.
570 * configure: Regenerate.
571 * po/POTFILES.in: Regenerate.
573 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
576 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
578 (print_insn): Clear vex instead of vex.evex.
580 2018-04-04 Nick Clifton <nickc@redhat.com>
582 * po/es.po: Updated Spanish translation.
584 2018-03-28 Jan Beulich <jbeulich@suse.com>
586 * i386-gen.c (opcode_modifiers): Delete VecESize.
587 * i386-opc.h (VecESize): Delete.
588 (struct i386_opcode_modifier): Delete vecesize.
589 * i386-opc.tbl: Drop VecESize.
590 * i386-tlb.h: Re-generate.
592 2018-03-28 Jan Beulich <jbeulich@suse.com>
594 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
595 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
596 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
597 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
598 * i386-tlb.h: Re-generate.
600 2018-03-28 Jan Beulich <jbeulich@suse.com>
602 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
604 * i386-tlb.h: Re-generate.
606 2018-03-28 Jan Beulich <jbeulich@suse.com>
608 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
609 (vex_len_table): Drop Y for vcvt*2si.
610 (putop): Replace plain 'Y' handling by abort().
612 2018-03-28 Nick Clifton <nickc@redhat.com>
615 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
616 instructions with only a base address register.
617 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
618 handle AARHC64_OPND_SVE_ADDR_R.
619 (aarch64_print_operand): Likewise.
620 * aarch64-asm-2.c: Regenerate.
621 * aarch64_dis-2.c: Regenerate.
622 * aarch64-opc-2.c: Regenerate.
624 2018-03-22 Jan Beulich <jbeulich@suse.com>
626 * i386-opc.tbl: Drop VecESize from register only insn forms and
627 memory forms not allowing broadcast.
628 * i386-tlb.h: Re-generate.
630 2018-03-22 Jan Beulich <jbeulich@suse.com>
632 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
633 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
634 sha256*): Drop Disp<N>.
636 2018-03-22 Jan Beulich <jbeulich@suse.com>
638 * i386-dis.c (EbndS, bnd_swap_mode): New.
639 (prefix_table): Use EbndS.
640 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
641 * i386-opc.tbl (bndmov): Move misplaced Load.
642 * i386-tlb.h: Re-generate.
644 2018-03-22 Jan Beulich <jbeulich@suse.com>
646 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
647 templates allowing memory operands and folded ones for register
649 * i386-tlb.h: Re-generate.
651 2018-03-22 Jan Beulich <jbeulich@suse.com>
653 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
654 256-bit templates. Drop redundant leftover Disp<N>.
655 * i386-tlb.h: Re-generate.
657 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
659 * riscv-opc.c (riscv_insn_types): New.
661 2018-03-13 Nick Clifton <nickc@redhat.com>
663 * po/pt_BR.po: Updated Brazilian Portuguese translation.
665 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
667 * i386-opc.tbl: Add Optimize to clr.
668 * i386-tbl.h: Regenerated.
670 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
672 * i386-gen.c (opcode_modifiers): Remove OldGcc.
673 * i386-opc.h (OldGcc): Removed.
674 (i386_opcode_modifier): Remove oldgcc.
675 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
676 instructions for old (<= 2.8.1) versions of gcc.
677 * i386-tbl.h: Regenerated.
679 2018-03-08 Jan Beulich <jbeulich@suse.com>
681 * i386-opc.h (EVEXDYN): New.
682 * i386-opc.tbl: Fold various AVX512VL templates.
683 * i386-tlb.h: Re-generate.
685 2018-03-08 Jan Beulich <jbeulich@suse.com>
687 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
688 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
689 vpexpandd, vpexpandq): Fold AFX512VF templates.
690 * i386-tlb.h: Re-generate.
692 2018-03-08 Jan Beulich <jbeulich@suse.com>
694 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
695 Fold 128- and 256-bit VEX-encoded templates.
696 * i386-tlb.h: Re-generate.
698 2018-03-08 Jan Beulich <jbeulich@suse.com>
700 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
701 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
702 vpexpandd, vpexpandq): Fold AVX512F templates.
703 * i386-tlb.h: Re-generate.
705 2018-03-08 Jan Beulich <jbeulich@suse.com>
707 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
708 64-bit templates. Drop Disp<N>.
709 * i386-tlb.h: Re-generate.
711 2018-03-08 Jan Beulich <jbeulich@suse.com>
713 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
714 and 256-bit templates.
715 * i386-tlb.h: Re-generate.
717 2018-03-08 Jan Beulich <jbeulich@suse.com>
719 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
720 * i386-tlb.h: Re-generate.
722 2018-03-08 Jan Beulich <jbeulich@suse.com>
724 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
726 * i386-tlb.h: Re-generate.
728 2018-03-08 Jan Beulich <jbeulich@suse.com>
730 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
731 * i386-tlb.h: Re-generate.
733 2018-03-08 Jan Beulich <jbeulich@suse.com>
735 * i386-gen.c (opcode_modifiers): Delete FloatD.
736 * i386-opc.h (FloatD): Delete.
737 (struct i386_opcode_modifier): Delete floatd.
738 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
740 * i386-tlb.h: Re-generate.
742 2018-03-08 Jan Beulich <jbeulich@suse.com>
744 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
746 2018-03-08 Jan Beulich <jbeulich@suse.com>
748 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
749 * i386-tlb.h: Re-generate.
751 2018-03-08 Jan Beulich <jbeulich@suse.com>
753 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
755 * i386-tlb.h: Re-generate.
757 2018-03-07 Alan Modra <amodra@gmail.com>
759 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
761 * disassemble.h (print_insn_rs6000): Delete.
762 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
763 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
764 (print_insn_rs6000): Delete.
766 2018-03-03 Alan Modra <amodra@gmail.com>
768 * sysdep.h (opcodes_error_handler): Define.
769 (_bfd_error_handler): Declare.
770 * Makefile.am: Remove stray #.
771 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
773 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
774 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
775 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
776 opcodes_error_handler to print errors. Standardize error messages.
777 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
778 and include opintl.h.
779 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
780 * i386-gen.c: Standardize error messages.
781 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
782 * Makefile.in: Regenerate.
783 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
784 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
785 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
786 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
787 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
788 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
789 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
790 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
791 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
792 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
793 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
794 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
795 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
797 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
799 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
800 vpsub[bwdq] instructions.
801 * i386-tbl.h: Regenerated.
803 2018-03-01 Alan Modra <amodra@gmail.com>
805 * configure.ac (ALL_LINGUAS): Sort.
806 * configure: Regenerate.
808 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
810 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
811 macro by assignements.
813 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
816 * i386-gen.c (opcode_modifiers): Add Optimize.
817 * i386-opc.h (Optimize): New enum.
818 (i386_opcode_modifier): Add optimize.
819 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
820 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
821 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
822 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
823 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
825 * i386-tbl.h: Regenerated.
827 2018-02-26 Alan Modra <amodra@gmail.com>
829 * crx-dis.c (getregliststring): Allocate a large enough buffer
830 to silence false positive gcc8 warning.
832 2018-02-22 Shea Levy <shea@shealevy.com>
834 * disassemble.c (ARCH_riscv): Define if ARCH_all.
836 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
838 * i386-opc.tbl: Add {rex},
839 * i386-tbl.h: Regenerated.
841 2018-02-20 Maciej W. Rozycki <macro@mips.com>
843 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
844 (mips16_opcodes): Replace `M' with `m' for "restore".
846 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
848 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
850 2018-02-13 Maciej W. Rozycki <macro@mips.com>
852 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
853 variable to `function_index'.
855 2018-02-13 Nick Clifton <nickc@redhat.com>
858 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
859 about truncation of printing.
861 2018-02-12 Henry Wong <henry@stuffedcow.net>
863 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
865 2018-02-05 Nick Clifton <nickc@redhat.com>
867 * po/pt_BR.po: Updated Brazilian Portuguese translation.
869 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
871 * i386-dis.c (enum): Add pconfig.
872 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
873 (cpu_flags): Add CpuPCONFIG.
874 * i386-opc.h (enum): Add CpuPCONFIG.
875 (i386_cpu_flags): Add cpupconfig.
876 * i386-opc.tbl: Add PCONFIG instruction.
877 * i386-init.h: Regenerate.
878 * i386-tbl.h: Likewise.
880 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
882 * i386-dis.c (enum): Add PREFIX_0F09.
883 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
884 (cpu_flags): Add CpuWBNOINVD.
885 * i386-opc.h (enum): Add CpuWBNOINVD.
886 (i386_cpu_flags): Add cpuwbnoinvd.
887 * i386-opc.tbl: Add WBNOINVD instruction.
888 * i386-init.h: Regenerate.
889 * i386-tbl.h: Likewise.
891 2018-01-17 Jim Wilson <jimw@sifive.com>
893 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
895 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
897 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
898 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
899 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
900 (cpu_flags): Add CpuIBT, CpuSHSTK.
901 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
902 (i386_cpu_flags): Add cpuibt, cpushstk.
903 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
904 * i386-init.h: Regenerate.
905 * i386-tbl.h: Likewise.
907 2018-01-16 Nick Clifton <nickc@redhat.com>
909 * po/pt_BR.po: Updated Brazilian Portugese translation.
910 * po/de.po: Updated German translation.
912 2018-01-15 Jim Wilson <jimw@sifive.com>
914 * riscv-opc.c (match_c_nop): New.
915 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
917 2018-01-15 Nick Clifton <nickc@redhat.com>
919 * po/uk.po: Updated Ukranian translation.
921 2018-01-13 Nick Clifton <nickc@redhat.com>
923 * po/opcodes.pot: Regenerated.
925 2018-01-13 Nick Clifton <nickc@redhat.com>
927 * configure: Regenerate.
929 2018-01-13 Nick Clifton <nickc@redhat.com>
933 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
935 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
936 * i386-tbl.h: Regenerate.
938 2018-01-10 Jan Beulich <jbeulich@suse.com>
940 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
941 * i386-tbl.h: Re-generate.
943 2018-01-10 Jan Beulich <jbeulich@suse.com>
945 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
946 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
947 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
948 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
949 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
950 Disp8MemShift of AVX512VL forms.
951 * i386-tbl.h: Re-generate.
953 2018-01-09 Jim Wilson <jimw@sifive.com>
955 * riscv-dis.c (maybe_print_address): If base_reg is zero,
956 then the hi_addr value is zero.
958 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
960 * arm-dis.c (arm_opcodes): Add csdb.
961 (thumb32_opcodes): Add csdb.
963 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
965 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
966 * aarch64-asm-2.c: Regenerate.
967 * aarch64-dis-2.c: Regenerate.
968 * aarch64-opc-2.c: Regenerate.
970 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
973 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
974 Remove AVX512 vmovd with 64-bit operands.
975 * i386-tbl.h: Regenerated.
977 2018-01-05 Jim Wilson <jimw@sifive.com>
979 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
982 2018-01-03 Alan Modra <amodra@gmail.com>
984 Update year range in copyright notice of all files.
986 2018-01-02 Jan Beulich <jbeulich@suse.com>
988 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
989 and OPERAND_TYPE_REGZMM entries.
991 For older changes see ChangeLog-2017
993 Copyright (C) 2018 Free Software Foundation, Inc.
995 Copying and distribution of this file, with or without modification,
996 are permitted in any medium without royalty provided the copyright
997 notice and this notice are preserved.
1003 version-control: never