1 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
3 * arm-dis.c (WORD_ADDRESS): Define.
4 (print_insn): Use it. Correct big-endian end-of-section handling.
6 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
7 Vineet Sharma <vineets@noida.hcltech.com>
9 * maxq-dis.c: New file.
10 * disassemble.c (ARCH_maxq): Define.
11 (disassembler): Add 'print_insn_maxq_little' for handling maxq
13 * configure.in: Add case for bfd_maxq_arch.
14 * configure: Regenerate.
15 * Makefile.am: Add support for maxq-dis.c
16 * Makefile.in: Regenerate.
17 * aclocal.m4: Regenerate.
19 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
21 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
23 * crx-dis.c: Likewise.
25 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
27 Generally, handle CRISv32.
28 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
29 (struct cris_disasm_data): New type.
30 (format_reg, format_hex, cris_constraint, print_flags)
31 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
33 (format_sup_reg, print_insn_crisv32_with_register_prefix)
34 (print_insn_crisv32_without_register_prefix)
35 (print_insn_crisv10_v32_with_register_prefix)
36 (print_insn_crisv10_v32_without_register_prefix)
37 (cris_parse_disassembler_options): New functions.
38 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
39 parameter. All callers changed.
40 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
42 (cris_constraint) <case 'Y', 'U'>: New cases.
43 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
45 (print_with_operands) <case 'Y'>: New case.
46 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
47 <case 'N', 'Y', 'Q'>: New cases.
48 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
49 (print_insn_cris_with_register_prefix)
50 (print_insn_cris_without_register_prefix): Call
51 cris_parse_disassembler_options.
52 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
53 for CRISv32 and the size of immediate operands. New v32-only
54 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
55 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
56 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
57 Change brp to be v3..v10.
58 (cris_support_regs): New vector.
59 (cris_opcodes): Update head comment. New format characters '[',
60 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
61 Add new opcodes for v32 and adjust existing opcodes to accommodate
62 differences to earlier variants.
63 (cris_cond15s): New vector.
65 2004-11-04 Jan Beulich <jbeulich@novell.com>
67 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
69 (Mp): Use f_mode rather than none at all.
70 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
71 replaces what previously was x_mode; x_mode now means 128-bit SSE
73 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
74 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
75 pinsrw's second operand is Edqw.
76 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
77 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
78 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
79 mode when an operand size override is present or always suffixing.
80 More instructions will need to be added to this group.
81 (putop): Handle new macro chars 'C' (short/long suffix selector),
82 'I' (Intel mode override for following macro char), and 'J' (for
83 adding the 'l' prefix to far branches in AT&T mode). When an
84 alternative was specified in the template, honor macro character when
85 specified for Intel mode.
86 (OP_E): Handle new *_mode values. Correct pointer specifications for
87 memory operands. Consolidate output of index register.
88 (OP_G): Handle new *_mode values.
89 (OP_I): Handle const_1_mode.
90 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
91 respective opcode prefix bits have been consumed.
92 (OP_EM, OP_EX): Provide some default handling for generating pointer
95 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
97 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
100 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
102 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
103 (getregliststring): Support HI/LO and user registers.
104 * crx-opc.c (crx_instruction): Update data structure according to the
105 rearrangement done in CRX opcode header file.
106 (crx_regtab): Likewise.
107 (crx_optab): Likewise.
108 (crx_instruction): Reorder load/stor instructions, remove unsupported
110 support new Co-Processor instruction 'cpi'.
112 2004-10-27 Nick Clifton <nickc@redhat.com>
114 * opcodes/iq2000-asm.c: Regenerate.
115 * opcodes/iq2000-desc.c: Regenerate.
116 * opcodes/iq2000-desc.h: Regenerate.
117 * opcodes/iq2000-dis.c: Regenerate.
118 * opcodes/iq2000-ibld.c: Regenerate.
119 * opcodes/iq2000-opc.c: Regenerate.
120 * opcodes/iq2000-opc.h: Regenerate.
122 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
124 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
125 us4, us5 (respectively).
126 Remove unsupported 'popa' instruction.
127 Reverse operands order in store co-processor instructions.
129 2004-10-15 Alan Modra <amodra@bigpond.net.au>
131 * Makefile.am: Run "make dep-am"
132 * Makefile.in: Regenerate.
134 2004-10-12 Bob Wilson <bob.wilson@acm.org>
136 * xtensa-dis.c: Use ISO C90 formatting.
138 2004-10-09 Alan Modra <amodra@bigpond.net.au>
140 * ppc-opc.c: Revert 2004-09-09 change.
142 2004-10-07 Bob Wilson <bob.wilson@acm.org>
144 * xtensa-dis.c (state_names): Delete.
145 (fetch_data): Use xtensa_isa_maxlength.
146 (print_xtensa_operand): Replace operand parameter with opcode/operand
147 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
148 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
149 instruction bundles. Use xmalloc instead of malloc.
151 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
153 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
156 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
158 * crx-opc.c (crx_instruction): Support Co-processor insns.
159 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
160 (getregliststring): Change function to use the above enum.
161 (print_arg): Handle CO-Processor insns.
162 (crx_cinvs): Add 'b' option to invalidate the branch-target
165 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
167 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
168 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
169 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
170 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
171 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
173 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
175 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
178 2004-09-30 Paul Brook <paul@codesourcery.com>
180 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
181 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
183 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
185 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
186 (CONFIG_STATUS_DEPENDENCIES): New.
188 (config.status): Likewise.
189 * Makefile.in: Regenerated.
191 2004-09-17 Alan Modra <amodra@bigpond.net.au>
193 * Makefile.am: Run "make dep-am".
194 * Makefile.in: Regenerate.
195 * aclocal.m4: Regenerate.
196 * configure: Regenerate.
197 * po/POTFILES.in: Regenerate.
198 * po/opcodes.pot: Regenerate.
200 2004-09-11 Andreas Schwab <schwab@suse.de>
202 * configure: Rebuild.
204 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
206 * ppc-opc.c (L): Make this field not optional.
208 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
210 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
211 Fix parameter to 'm[t|f]csr' insns.
213 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
215 * configure.in: Autoupdate to autoconf 2.59.
216 * aclocal.m4: Rebuild with aclocal 1.4p6.
217 * configure: Rebuild with autoconf 2.59.
218 * Makefile.in: Rebuild with automake 1.4p6 (picking up
219 bfd changes for autoconf 2.59 on the way).
220 * config.in: Rebuild with autoheader 2.59.
222 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
224 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
226 2004-07-30 Michal Ludvig <mludvig@suse.cz>
228 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
229 (GRPPADLCK2): New define.
230 (twobyte_has_modrm): True for 0xA6.
231 (grps): GRPPADLCK2 for opcode 0xA6.
233 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
235 Introduce SH2a support.
236 * sh-opc.h (arch_sh2a_base): Renumber.
237 (arch_sh2a_nofpu_base): Remove.
238 (arch_sh_base_mask): Adjust.
239 (arch_opann_mask): New.
240 (arch_sh2a, arch_sh2a_nofpu): Adjust.
241 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
242 (sh_table): Adjust whitespace.
243 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
244 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
245 instruction list throughout.
246 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
247 of arch_sh2a in instruction list throughout.
248 (arch_sh2e_up): Accomodate above changes.
249 (arch_sh2_up): Ditto.
250 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
251 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
252 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
253 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
254 * sh-opc.h (arch_sh2a_nofpu): New.
255 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
256 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
258 2004-01-20 DJ Delorie <dj@redhat.com>
259 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
260 2003-12-29 DJ Delorie <dj@redhat.com>
261 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
262 sh_opcode_info, sh_table): Add sh2a support.
263 (arch_op32): New, to tag 32-bit opcodes.
264 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
265 2003-12-02 Michael Snyder <msnyder@redhat.com>
266 * sh-opc.h (arch_sh2a): Add.
267 * sh-dis.c (arch_sh2a): Handle.
268 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
270 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
272 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
274 2004-07-22 Nick Clifton <nickc@redhat.com>
277 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
278 insns - this is done by objdump itself.
279 * h8500-dis.c (print_insn_h8500): Likewise.
281 2004-07-21 Jan Beulich <jbeulich@novell.com>
283 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
284 regardless of address size prefix in effect.
285 (ptr_reg): Size or address registers does not depend on rex64, but
286 on the presence of an address size override.
287 (OP_MMX): Use rex.x only for xmm registers.
288 (OP_EM): Use rex.z only for xmm registers.
290 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
292 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
293 move/branch operations to the bottom so that VR5400 multimedia
294 instructions take precedence in disassembly.
296 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
298 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
299 ISA-specific "break" encoding.
301 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
303 * arm-opc.h: Fix typo in comment.
305 2004-07-11 Andreas Schwab <schwab@suse.de>
307 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
309 2004-07-09 Andreas Schwab <schwab@suse.de>
311 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
313 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
315 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
316 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
317 (crx-dis.lo): New target.
318 (crx-opc.lo): Likewise.
319 * Makefile.in: Regenerate.
320 * configure.in: Handle bfd_crx_arch.
321 * configure: Regenerate.
322 * crx-dis.c: New file.
323 * crx-opc.c: New file.
324 * disassemble.c (ARCH_crx): Define.
325 (disassembler): Handle ARCH_crx.
327 2004-06-29 James E Wilson <wilson@specifixinc.com>
329 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
330 * ia64-asmtab.c: Regnerate.
332 2004-06-28 Alan Modra <amodra@bigpond.net.au>
334 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
335 (extract_fxm): Don't test dialect.
336 (XFXFXM_MASK): Include the power4 bit.
337 (XFXM): Add p4 param.
338 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
340 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
342 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
343 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
345 2004-06-26 Alan Modra <amodra@bigpond.net.au>
347 * ppc-opc.c (BH, XLBH_MASK): Define.
348 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
350 2004-06-24 Alan Modra <amodra@bigpond.net.au>
352 * i386-dis.c (x_mode): Comment.
353 (two_source_ops): File scope.
354 (float_mem): Correct fisttpll and fistpll.
355 (float_mem_mode): New table.
357 (OP_E): Correct intel mode PTR output.
358 (ptr_reg): Use open_char and close_char.
359 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
360 operands. Set two_source_ops.
362 2004-06-15 Alan Modra <amodra@bigpond.net.au>
364 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
365 instead of _raw_size.
367 2004-06-08 Jakub Jelinek <jakub@redhat.com>
369 * ia64-gen.c (in_iclass): Handle more postinc st
371 * ia64-asmtab.c: Rebuilt.
373 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
375 * s390-opc.txt: Correct architecture mask for some opcodes.
376 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
377 in the esa mode as well.
379 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
381 * sh-dis.c (target_arch): Make unsigned.
382 (print_insn_sh): Replace (most of) switch with a call to
383 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
384 * sh-opc.h: Redefine architecture flags values.
385 Add sh3-nommu architecture.
386 Reorganise <arch>_up macros so they make more visual sense.
387 (SH_MERGE_ARCH_SET): Define new macro.
388 (SH_VALID_BASE_ARCH_SET): Likewise.
389 (SH_VALID_MMU_ARCH_SET): Likewise.
390 (SH_VALID_CO_ARCH_SET): Likewise.
391 (SH_VALID_ARCH_SET): Likewise.
392 (SH_MERGE_ARCH_SET_VALID): Likewise.
393 (SH_ARCH_SET_HAS_FPU): Likewise.
394 (SH_ARCH_SET_HAS_DSP): Likewise.
395 (SH_ARCH_UNKNOWN_ARCH): Likewise.
396 (sh_get_arch_from_bfd_mach): Add prototype.
397 (sh_get_arch_up_from_bfd_mach): Likewise.
398 (sh_get_bfd_mach_from_arch_set): Likewise.
399 (sh_merge_bfd_arc): Likewise.
401 2004-05-24 Peter Barada <peter@the-baradas.com>
403 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
404 into new match_insn_m68k function. Loop over canidate
405 matches and select first that completely matches.
406 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
407 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
408 to verify addressing for MAC/EMAC.
409 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
410 reigster halves since 'fpu' and 'spl' look misleading.
411 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
412 * m68k-opc.c: Rearragne mac/emac cases to use longest for
413 first, tighten up match masks.
414 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
415 'size' from special case code in print_insn_m68k to
416 determine decode size of insns.
418 2004-05-19 Alan Modra <amodra@bigpond.net.au>
420 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
421 well as when -mpower4.
423 2004-05-13 Nick Clifton <nickc@redhat.com>
425 * po/fr.po: Updated French translation.
427 2004-05-05 Peter Barada <peter@the-baradas.com>
429 * m68k-dis.c(print_insn_m68k): Add new chips, use core
430 variants in arch_mask. Only set m68881/68851 for 68k chips.
431 * m68k-op.c: Switch from ColdFire chips to core variants.
433 2004-05-05 Alan Modra <amodra@bigpond.net.au>
436 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
438 2004-04-29 Ben Elliston <bje@au.ibm.com>
440 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
441 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
443 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
445 * sh-dis.c (print_insn_sh): Print the value in constant pool
446 as a symbol if it looks like a symbol.
448 2004-04-22 Peter Barada <peter@the-baradas.com>
450 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
451 appropriate ColdFire architectures.
452 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
454 Add EMAC instructions, fix MAC instructions. Remove
455 macmw/macml/msacmw/msacml instructions since mask addressing now
458 2004-04-20 Jakub Jelinek <jakub@redhat.com>
460 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
461 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
462 suffix. Use fmov*x macros, create all 3 fpsize variants in one
463 macro. Adjust all users.
465 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
467 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
470 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
472 * m32r-asm.c: Regenerate.
474 2004-03-29 Stan Shebs <shebs@apple.com>
476 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
479 2004-03-19 Alan Modra <amodra@bigpond.net.au>
481 * aclocal.m4: Regenerate.
482 * config.in: Regenerate.
483 * configure: Regenerate.
484 * po/POTFILES.in: Regenerate.
485 * po/opcodes.pot: Regenerate.
487 2004-03-16 Alan Modra <amodra@bigpond.net.au>
489 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
491 * ppc-opc.c (RA0): Define.
492 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
493 (RAOPT): Rename from RAO. Update all uses.
494 (powerpc_opcodes): Use RA0 as appropriate.
496 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
498 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
500 2004-03-15 Alan Modra <amodra@bigpond.net.au>
502 * sparc-dis.c (print_insn_sparc): Update getword prototype.
504 2004-03-12 Michal Ludvig <mludvig@suse.cz>
506 * i386-dis.c (GRPPLOCK): Delete.
507 (grps): Delete GRPPLOCK entry.
509 2004-03-12 Alan Modra <amodra@bigpond.net.au>
511 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
513 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
515 (dis386): Use NOP_Fixup on "nop".
516 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
517 (twobyte_has_modrm): Set for 0xa7.
518 (padlock_table): Delete. Move to..
519 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
521 (print_insn): Revert PADLOCK_SPECIAL code.
522 (OP_E): Delete sfence, lfence, mfence checks.
524 2004-03-12 Jakub Jelinek <jakub@redhat.com>
526 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
527 (INVLPG_Fixup): New function.
528 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
530 2004-03-12 Michal Ludvig <mludvig@suse.cz>
532 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
533 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
534 (padlock_table): New struct with PadLock instructions.
535 (print_insn): Handle PADLOCK_SPECIAL.
537 2004-03-12 Alan Modra <amodra@bigpond.net.au>
539 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
540 (OP_E): Twiddle clflush to sfence here.
542 2004-03-08 Nick Clifton <nickc@redhat.com>
544 * po/de.po: Updated German translation.
546 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
548 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
549 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
550 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
553 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
555 * frv-asm.c: Regenerate.
556 * frv-desc.c: Regenerate.
557 * frv-desc.h: Regenerate.
558 * frv-dis.c: Regenerate.
559 * frv-ibld.c: Regenerate.
560 * frv-opc.c: Regenerate.
561 * frv-opc.h: Regenerate.
563 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
565 * frv-desc.c, frv-opc.c: Regenerate.
567 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
569 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
571 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
573 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
574 Also correct mistake in the comment.
576 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
578 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
579 ensure that double registers have even numbers.
580 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
581 that reserved instruction 0xfffd does not decode the same
583 * sh-opc.h: Add REG_N_D nibble type and use it whereever
584 REG_N refers to a double register.
585 Add REG_N_B01 nibble type and use it instead of REG_NM
587 Adjust the bit patterns in a few comments.
589 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
591 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
593 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
595 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
597 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
599 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
601 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
603 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
604 mtivor32, mtivor33, mtivor34.
606 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
608 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
610 2004-02-10 Petko Manolov <petkan@nucleusys.com>
612 * arm-opc.h Maverick accumulator register opcode fixes.
614 2004-02-13 Ben Elliston <bje@wasabisystems.com>
616 * m32r-dis.c: Regenerate.
618 2004-01-27 Michael Snyder <msnyder@redhat.com>
620 * sh-opc.h (sh_table): "fsrra", not "fssra".
622 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
624 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
627 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
629 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
631 2004-01-19 Alan Modra <amodra@bigpond.net.au>
633 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
634 1. Don't print scale factor on AT&T mode when index missing.
636 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
638 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
639 when loaded into XR registers.
641 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
643 * frv-desc.h: Regenerate.
644 * frv-desc.c: Regenerate.
645 * frv-opc.c: Regenerate.
647 2004-01-13 Michael Snyder <msnyder@redhat.com>
649 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
651 2004-01-09 Paul Brook <paul@codesourcery.com>
653 * arm-opc.h (arm_opcodes): Move generic mcrr after known
656 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
658 * Makefile.am (libopcodes_la_DEPENDENCIES)
659 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
660 comment about the problem.
661 * Makefile.in: Regenerate.
663 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
665 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
666 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
667 cut&paste errors in shifting/truncating numerical operands.
668 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
669 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
670 (parse_uslo16): Likewise.
671 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
672 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
673 (parse_s12): Likewise.
674 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
675 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
676 (parse_uslo16): Likewise.
677 (parse_uhi16): Parse gothi and gotfuncdeschi.
678 (parse_d12): Parse got12 and gotfuncdesc12.
679 (parse_s12): Likewise.
681 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
683 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
684 instruction which looks similar to an 'rla' instruction.
686 For older changes see ChangeLog-0203
692 version-control: never