opcodes/ChangeLog

   1 2018-06-06  Alan Modra  <amodra@gmail.com>
   2
   3         * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
   4         setjmp.  Move init for some other vars later too.
   5
   6 2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
   7
   8         * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
   9         (dis_private): Add new fields for property section tracking.
  10         (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
  11         (xtensa_instruction_fits): New functions.
  12         (fetch_data): Bump minimal fetch size to 4.
  13         (print_insn_xtensa): Make struct dis_private static.
  14         Load and prepare property table on section change.
  15         Don't disassemble literals. Don't disassemble instructions that
  16         cross property table boundaries.
  17
  18 2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
  19
  20         * configure: Regenerated.
  21
  22 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
  25         * i386-tbl.h: Re-generate.
  26
  27 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  28
  29         * i386-opc.tbl (sldt, str): Add NoRex64.
  30         * i386-tbl.h: Re-generate.
  31
  32 2018-06-01  Jan Beulich  <jbeulich@suse.com>
  33
  34         * i386-opc.tbl (invpcid): Add Oword.
  35         * i386-tbl.h: Re-generate.
  36
  37 2018-06-01  Alan Modra  <amodra@gmail.com>
  38
  39         * sysdep.h (_bfd_error_handler): Don't declare.
  40         * msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
  41         * rl78-decode.opc: Likewise.
  42         * msp430-decode.c: Regenerate.
  43         * rl78-decode.c: Regenerate.
  44
  45 2018-05-30  Amit Pawar <Amit.Pawar@amd.com>
  46
  47         * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
  48         * i386-init.h : Regenerated.
  49
  50 2018-05-25  Alan Modra  <amodra@gmail.com>
  51
  52         * Makefile.in: Regenerate.
  53         * po/POTFILES.in: Regenerate.
  54
  55 2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
  56
  57         * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
  58         insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
  59         (insert_bab, extract_bab, insert_btab, extract_btab,
  60         insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
  61         (BAT, BBA VBA RBS XB6S): Delete macros.
  62         (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
  63         (BB, BD, RBX, XC6): Update for new macros.
  64         (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
  65         crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
  66         e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
  67         * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
  68
  69 2018-05-18  John Darrington  <john@darrington.wattle.id.au>
  70
  71         * Makefile.am: Add support for s12z architecture.
  72         * configure.ac: Likewise.
  73         * disassemble.c: Likewise.
  74         * disassemble.h: Likewise.
  75         * Makefile.in: Regenerate.
  76         * configure: Regenerate.
  77         * s12z-dis.c: New file.
  78         * s12z.h: New file.
  79
  80 2018-05-18  Alan Modra  <amodra@gmail.com>
  81
  82         * nfp-dis.c: Don't #include libbfd.h.
  83         (init_nfp3200_priv): Use bfd_get_section_contents.
  84         (nit_nfp6000_mecsr_sec): Likewise.
  85
  86 2018-05-17  Nick Clifton  <nickc@redhat.com>
  87
  88         * po/zh_CN.po: Updated simplified Chinese translation.
  89
  90 2018-05-16  Tamar Christina  <tamar.christina@arm.com>
  91
  92         PR binutils/23109
  93         * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
  94         * aarch64-dis-2.c: Regenerate.
  95
  96 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
  97
  98         PR binutils/21446
  99         * aarch64-asm.c (opintl.h): Include.
 100         (aarch64_ins_sysreg): Enforce read/write constraints.
 101         * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
 102         * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
 103         (F_REG_READ, F_REG_WRITE): New.
 104         * aarch64-opc.c (aarch64_print_operand): Generate notes for
 105         AARCH64_OPND_SYSREG.
 106         (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
 107         (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
 108         mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
 109         id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
 110         id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
 111         id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
 112         mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
 113         id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
 114         id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
 115         id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
 116         csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
 117         rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
 118         mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
 119         mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
 120         pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
 121         * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
 122         msr (F_SYS_WRITE), mrs (F_SYS_READ).
 123
 124 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 125
 126         PR binutils/21446
 127         * aarch64-dis.c (no_notes: New.
 128         (parse_aarch64_dis_option): Support notes.
 129         (aarch64_decode_insn, print_operands): Likewise.
 130         (print_aarch64_disassembler_options): Document notes.
 131         * aarch64-opc.c (aarch64_print_operand): Support notes.
 132
 133 2018-05-15  Tamar Christina  <tamar.christina@arm.com>
 134
 135         PR binutils/21446
 136         * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
 137         and take error struct.
 138         * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
 139         aarch64_ins_reglist, aarch64_ins_ldst_reglist,
 140         aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
 141         aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
 142         aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
 143         aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
 144         aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
 145         aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
 146         aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
 147         aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
 148         aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
 149         aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
 150         aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
 151         aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
 152         aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
 153         aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
 154         aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
 155         aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 156         aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
 157         aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
 158         aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
 159         aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
 160         aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
 161         aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
 162         aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
 163         * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
 164         * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
 165         aarch64_ext_reglist, aarch64_ext_ldst_reglist,
 166         aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
 167         aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
 168         aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
 169         aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
 170         aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
 171         aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
 172         aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
 173         aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
 174         aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
 175         aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
 176         aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
 177         aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
 178         aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
 179         aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
 180         aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
 181         aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
 182         aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
 183         aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
 184         aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
 185         aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
 186         aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
 187         aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
 188         aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
 189         (determine_disassembling_preference, aarch64_decode_insn,
 190         print_insn_aarch64_word, print_insn_data): Take errors struct.
 191         (print_insn_aarch64): Use errors.
 192         * aarch64-asm-2.c: Regenerate.
 193         * aarch64-dis-2.c: Regenerate.
 194         * aarch64-gen.c (print_operand_inserter): Use errors and change type to
 195         boolean in aarch64_insert_operan.
 196         (print_operand_extractor): Likewise.
 197         * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
 198
 199 2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
 200
 201         * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
 202
 203 2018-05-09  H.J. Lu  <hongjiu.lu@intel.com>
 204
 205         * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
 206
 207 2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
 208
 209         * cr16-opc.c (cr16_instruction): Comment typo fix.
 210         * hppa-dis.c (print_insn_hppa): Likewise.
 211
 212 2018-05-08  Jim Wilson  <jimw@sifive.com>
 213
 214         * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
 215         (match_c_slli64, match_srxi_as_c_srxi): New.
 216         (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
 217         <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
 218         <c.slli, c.srli, c.srai>: Use match_s_slli.
 219         <c.slli64, c.srli64, c.srai64>: New.
 220
 221 2018-05-08  Alan Modra  <amodra@gmail.com>
 222
 223         * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
 224         (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
 225         partition opcode space for index lookup.
 226
 227 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 228
 229         * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
 230         <insn_length>: ...with this.  Update usage.
 231         Remove duplicate call to *info->memory_error_func.
 232
 233 2018-05-07  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 234             H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * i386-dis.c (Gva): New.
 237         (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
 238         MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
 239         (prefix_table): New instructions (see prefix above).
 240         (mod_table): New instructions (see prefix above).
 241         (OP_G): Handle va_mode.
 242         * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
 243         CPU_MOVDIR64B_FLAGS.
 244         (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
 245         * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
 246         (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
 247         * i386-opc.tbl: Add movidir{i,64b}.
 248         * i386-init.h: Regenerated.
 249         * i386-tbl.h: Likewise.
 250
 251 2018-05-07  H.J. Lu  <hongjiu.lu@intel.com>
 252
 253         * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
 254         AddrPrefixOpReg.
 255         * i386-opc.h (AddrPrefixOp0): Renamed to ...
 256         (AddrPrefixOpReg): This.
 257         (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
 258         * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
 259
 260 2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
 261
 262         * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
 263         (vle_num_opcodes): Likewise.
 264         (spe2_num_opcodes): Likewise.
 265         * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
 266         initialization loop.
 267         (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
 268         (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise.  Initialize
 269         only once.
 270
 271 2018-05-01  Tamar Christina  <tamar.christina@arm.com>
 272
 273         * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
 274
 275 2018-04-30  Francois H. Theron <francois.theron@netronome.com>
 276
 277         Makefile.am: Added nfp-dis.c.
 278         configure.ac: Added bfd_nfp_arch.
 279         disassemble.h: Added print_insn_nfp prototype.
 280         disassemble.c: Added ARCH_nfp and call to print_insn_nfp
 281         nfp-dis.c: New, for NFP support.
 282         po/POTFILES.in: Added nfp-dis.c to the list.
 283         Makefile.in: Regenerate.
 284         configure: Regenerate.
 285
 286 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 287
 288         * i386-opc.tbl: Fold various non-memory operand AVX512VL
 289         templates into their base ones.
 290         * i386-tlb.h: Re-generate.
 291
 292 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 293
 294         * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
 295         CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
 296         CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
 297         CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
 298         * i386-init.h: Re-generate.
 299
 300 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
 303         CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
 304         CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
 305         Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
 306         comment.
 307         (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 308         and CpuRegMask.
 309         * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
 310         CpuRegMask: Delete.
 311         (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
 312         cpuregzmm, and cpuregmask.
 313         * i386-init.h: Re-generate.
 314         * i386-tbl.h: Re-generate.
 315
 316 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 317
 318         * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
 319         CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
 320         * i386-init.h: Re-generate.
 321
 322 2018-04-26  Jan Beulich  <jbeulich@suse.com>
 323
 324         * i386-gen.c (VexImmExt): Delete.
 325         * i386-opc.h (VexImmExt, veximmext): Delete.
 326         * i386-opc.tbl: Drop all VexImmExt uses.
 327         * i386-tlb.h: Re-generate.
 328
 329 2018-04-25  Jan Beulich  <jbeulich@suse.com>
 330
 331         * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
 332         register-only forms.
 333         * i386-tlb.h: Re-generate.
 334
 335 2018-04-25  Tamar Christina  <tamar.christina@arm.com>
 336
 337         * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
 338
 339 2018-04-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 340
 341         * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
 342         PREFIX_0F1C.
 343         * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
 344         (cpu_flags): Add CpuCLDEMOTE.
 345         * i386-init.h: Regenerate.
 346         * i386-opc.h (enum): Add CpuCLDEMOTE,
 347         (i386_cpu_flags): Add cpucldemote.
 348         * i386-opc.tbl: Add cldemote.
 349         * i386-tbl.h: Regenerate.
 350
 351 2018-04-16  Alan Modra  <amodra@gmail.com>
 352
 353         * Makefile.am: Remove sh5 and sh64 support.
 354         * configure.ac: Likewise.
 355         * disassemble.c: Likewise.
 356         * disassemble.h: Likewise.
 357         * sh-dis.c: Likewise.
 358         * sh64-dis.c: Delete.
 359         * sh64-opc.c: Delete.
 360         * sh64-opc.h: Delete.
 361         * Makefile.in: Regenerate.
 362         * configure: Regenerate.
 363         * po/POTFILES.in: Regenerate.
 364
 365 2018-04-16  Alan Modra  <amodra@gmail.com>
 366
 367         * Makefile.am: Remove w65 support.
 368         * configure.ac: Likewise.
 369         * disassemble.c: Likewise.
 370         * disassemble.h: Likewise.
 371         * w65-dis.c: Delete.
 372         * w65-opc.h: Delete.
 373         * Makefile.in: Regenerate.
 374         * configure: Regenerate.
 375         * po/POTFILES.in: Regenerate.
 376
 377 2018-04-16  Alan Modra  <amodra@gmail.com>
 378
 379         * configure.ac: Remove we32k support.
 380         * configure: Regenerate.
 381
 382 2018-04-16  Alan Modra  <amodra@gmail.com>
 383
 384         * Makefile.am: Remove m88k support.
 385         * configure.ac: Likewise.
 386         * disassemble.c: Likewise.
 387         * disassemble.h: Likewise.
 388         * m88k-dis.c: Delete.
 389         * Makefile.in: Regenerate.
 390         * configure: Regenerate.
 391         * po/POTFILES.in: Regenerate.
 392
 393 2018-04-16  Alan Modra  <amodra@gmail.com>
 394
 395         * Makefile.am: Remove i370 support.
 396         * configure.ac: Likewise.
 397         * disassemble.c: Likewise.
 398         * disassemble.h: Likewise.
 399         * i370-dis.c: Delete.
 400         * i370-opc.c: Delete.
 401         * Makefile.in: Regenerate.
 402         * configure: Regenerate.
 403         * po/POTFILES.in: Regenerate.
 404
 405 2018-04-16  Alan Modra  <amodra@gmail.com>
 406
 407         * Makefile.am: Remove h8500 support.
 408         * configure.ac: Likewise.
 409         * disassemble.c: Likewise.
 410         * disassemble.h: Likewise.
 411         * h8500-dis.c: Delete.
 412         * h8500-opc.h: Delete.
 413         * Makefile.in: Regenerate.
 414         * configure: Regenerate.
 415         * po/POTFILES.in: Regenerate.
 416
 417 2018-04-16  Alan Modra  <amodra@gmail.com>
 418
 419         * configure.ac: Remove tahoe support.
 420         * configure: Regenerate.
 421
 422 2018-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 423
 424         * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
 425         umwait.
 426         * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
 427         64-bit mode.
 428         * i386-tbl.h: Regenerated.
 429
 430 2018-04-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 431
 432         * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
 433         PREFIX_MOD_1_0FAE_REG_6.
 434         (va_mode): New.
 435         (OP_E_register): Use va_mode.
 436         * i386-dis-evex.h (prefix_table):
 437         New instructions (see prefixes above).
 438         * i386-gen.c (cpu_flag_init): Add WAITPKG.
 439         (cpu_flags): Likewise.
 440         * i386-opc.h (enum): Likewise.
 441         (i386_cpu_flags): Likewise.
 442         * i386-opc.tbl: Add umonitor, umwait, tpause.
 443         * i386-init.h: Regenerate.
 444         * i386-tbl.h: Likewise.
 445
 446 2018-04-11  Alan Modra  <amodra@gmail.com>
 447
 448         * opcodes/i860-dis.c: Delete.
 449         * opcodes/i960-dis.c: Delete.
 450         * Makefile.am: Remove i860 and i960 support.
 451         * configure.ac: Likewise.
 452         * disassemble.c: Likewise.
 453         * disassemble.h: Likewise.
 454         * Makefile.in: Regenerate.
 455         * configure: Regenerate.
 456         * po/POTFILES.in: Regenerate.
 457
 458 2018-04-04  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         PR binutils/23025
 461         * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
 462         to 0.
 463         (print_insn): Clear vex instead of vex.evex.
 464
 465 2018-04-04  Nick Clifton  <nickc@redhat.com>
 466
 467         * po/es.po: Updated Spanish translation.
 468
 469 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 470
 471         * i386-gen.c (opcode_modifiers): Delete VecESize.
 472         * i386-opc.h (VecESize): Delete.
 473         (struct i386_opcode_modifier): Delete vecesize.
 474         * i386-opc.tbl: Drop VecESize.
 475         * i386-tlb.h: Re-generate.
 476
 477 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 478
 479         * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
 480         BROADCAST_1TO4, BROADCAST_1TO2): Delete.
 481         (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
 482         * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
 483         * i386-tlb.h: Re-generate.
 484
 485 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
 488         Fold AVX512 forms
 489         * i386-tlb.h: Re-generate.
 490
 491 2018-03-28  Jan Beulich  <jbeulich@suse.com>
 492
 493         * i386-dis.c (prefix_table): Drop Y for cvt*2si.
 494         (vex_len_table): Drop Y for vcvt*2si.
 495         (putop): Replace plain 'Y' handling by abort().
 496
 497 2018-03-28  Nick Clifton  <nickc@redhat.com>
 498
 499         PR 22988
 500         * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
 501         instructions with only a base address register.
 502         * aarch64-opc.c (operand_general_constraint_met_p): Add code to
 503         handle AARHC64_OPND_SVE_ADDR_R.
 504         (aarch64_print_operand): Likewise.
 505         * aarch64-asm-2.c: Regenerate.
 506         * aarch64_dis-2.c: Regenerate.
 507         * aarch64-opc-2.c: Regenerate.
 508
 509 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 510
 511         * i386-opc.tbl: Drop VecESize from register only insn forms and
 512         memory forms not allowing broadcast.
 513         * i386-tlb.h: Re-generate.
 514
 515 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 516
 517         * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
 518         vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
 519         sha256*): Drop Disp<N>.
 520
 521 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 522
 523         * i386-dis.c (EbndS, bnd_swap_mode): New.
 524         (prefix_table): Use EbndS.
 525         (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
 526         * i386-opc.tbl (bndmov): Move misplaced Load.
 527         * i386-tlb.h: Re-generate.
 528
 529 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 530
 531         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
 532         templates allowing memory operands and folded ones for register
 533         only flavors.
 534         * i386-tlb.h: Re-generate.
 535
 536 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 537
 538         * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
 539         256-bit templates. Drop redundant leftover Disp<N>.
 540         * i386-tlb.h: Re-generate.
 541
 542 2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
 543
 544         * riscv-opc.c (riscv_insn_types): New.
 545
 546 2018-03-13  Nick Clifton  <nickc@redhat.com>
 547
 548         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 549
 550 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 551
 552         * i386-opc.tbl: Add Optimize to clr.
 553         * i386-tbl.h: Regenerated.
 554
 555 2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
 556
 557         * i386-gen.c (opcode_modifiers): Remove OldGcc.
 558         * i386-opc.h (OldGcc): Removed.
 559         (i386_opcode_modifier): Remove oldgcc.
 560         * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
 561         instructions for old (<= 2.8.1) versions of gcc.
 562         * i386-tbl.h: Regenerated.
 563
 564 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 565
 566         * i386-opc.h (EVEXDYN): New.
 567         * i386-opc.tbl: Fold various AVX512VL templates.
 568         * i386-tlb.h: Re-generate.
 569
 570 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 571
 572         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 573         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 574         vpexpandd, vpexpandq): Fold AFX512VF templates.
 575         * i386-tlb.h: Re-generate.
 576
 577 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 578
 579         * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
 580         Fold 128- and 256-bit VEX-encoded templates.
 581         * i386-tlb.h: Re-generate.
 582
 583 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 584
 585         * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
 586         vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
 587         vpexpandd, vpexpandq): Fold AVX512F templates.
 588         * i386-tlb.h: Re-generate.
 589
 590 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 591
 592         * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
 593         64-bit templates. Drop Disp<N>.
 594         * i386-tlb.h: Re-generate.
 595
 596 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 597
 598         * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
 599         and 256-bit templates.
 600         * i386-tlb.h: Re-generate.
 601
 602 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 603
 604         * i386-opc.tbl (cmpxchg8b): Add NoRex64.
 605         * i386-tlb.h: Re-generate.
 606
 607 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 608
 609         * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
 610         Drop NoAVX.
 611         * i386-tlb.h: Re-generate.
 612
 613 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 614
 615         * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
 616         * i386-tlb.h: Re-generate.
 617
 618 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 619
 620         * i386-gen.c (opcode_modifiers): Delete FloatD.
 621         * i386-opc.h (FloatD): Delete.
 622         (struct i386_opcode_modifier): Delete floatd.
 623         * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
 624         FloatD by D.
 625         * i386-tlb.h: Re-generate.
 626
 627 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 628
 629         * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
 630
 631 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 632
 633         * i386-opc.tbl (vmovd): Disallow Qword memory operands.
 634         * i386-tlb.h: Re-generate.
 635
 636 2018-03-08  Jan Beulich  <jbeulich@suse.com>
 637
 638         * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
 639         forms.
 640         * i386-tlb.h: Re-generate.
 641
 642 2018-03-07  Alan Modra  <amodra@gmail.com>
 643
 644         * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
 645         bfd_arch_rs6000.
 646         * disassemble.h (print_insn_rs6000): Delete.
 647         * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
 648         (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
 649         (print_insn_rs6000): Delete.
 650
 651 2018-03-03  Alan Modra  <amodra@gmail.com>
 652
 653         * sysdep.h (opcodes_error_handler): Define.
 654         (_bfd_error_handler): Declare.
 655         * Makefile.am: Remove stray #.
 656         * opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
 657         EDIT" comment.
 658         * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
 659         * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
 660         * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
 661         opcodes_error_handler to print errors.  Standardize error messages.
 662         * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
 663         and include opintl.h.
 664         * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
 665         * i386-gen.c: Standardize error messages.
 666         * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
 667         * Makefile.in: Regenerate.
 668         * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
 669         * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
 670         * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
 671         * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
 672         * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
 673         * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
 674         * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
 675         * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
 676         * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
 677         * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
 678         * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
 679         * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
 680         * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 681
 682 2018-03-01  H.J. Lu  <hongjiu.lu@intel.com>
 683
 684         * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
 685         vpsub[bwdq] instructions.
 686         * i386-tbl.h: Regenerated.
 687
 688 2018-03-01  Alan Modra  <amodra@gmail.com>
 689
 690         * configure.ac (ALL_LINGUAS): Sort.
 691         * configure: Regenerate.
 692
 693 2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 694
 695         * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
 696         macro by assignements.
 697
 698 2018-02-27  H.J. Lu  <hongjiu.lu@intel.com>
 699
 700         PR gas/22871
 701         * i386-gen.c (opcode_modifiers): Add Optimize.
 702         * i386-opc.h (Optimize): New enum.
 703         (i386_opcode_modifier): Add optimize.
 704         * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
 705         "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
 706         "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
 707         "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
 708         vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
 709         vpxord and vpxorq.
 710         * i386-tbl.h: Regenerated.
 711
 712 2018-02-26  Alan Modra  <amodra@gmail.com>
 713
 714         * crx-dis.c (getregliststring): Allocate a large enough buffer
 715         to silence false positive gcc8 warning.
 716
 717 2018-02-22  Shea Levy <shea@shealevy.com>
 718
 719         * disassemble.c (ARCH_riscv): Define if ARCH_all.
 720
 721 2018-02-22  H.J. Lu  <hongjiu.lu@intel.com>
 722
 723         * i386-opc.tbl: Add {rex},
 724         * i386-tbl.h: Regenerated.
 725
 726 2018-02-20  Maciej W. Rozycki  <macro@mips.com>
 727
 728         * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
 729         (mips16_opcodes): Replace `M' with `m' for "restore".
 730
 731 2018-02-19  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 732
 733         * arm-dis.c (thumb_opcodes): Fix BXNS mask.
 734
 735 2018-02-13  Maciej W. Rozycki  <macro@mips.com>
 736
 737         * wasm32-dis.c (print_insn_wasm32): Rename `index' local
 738         variable to `function_index'.
 739
 740 2018-02-13  Nick Clifton  <nickc@redhat.com>
 741
 742         PR 22823
 743         * metag-dis.c (print_fmmov): Double buffer size to avoid warning
 744         about truncation of printing.
 745
 746 2018-02-12  Henry Wong <henry@stuffedcow.net>
 747
 748         * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
 749
 750 2018-02-05  Nick Clifton  <nickc@redhat.com>
 751
 752         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 753
 754 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 755
 756         * i386-dis.c (enum): Add pconfig.
 757         * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
 758         (cpu_flags): Add CpuPCONFIG.
 759         * i386-opc.h (enum): Add CpuPCONFIG.
 760         (i386_cpu_flags): Add cpupconfig.
 761         * i386-opc.tbl: Add PCONFIG instruction.
 762         * i386-init.h: Regenerate.
 763         * i386-tbl.h: Likewise.
 764
 765 2018-01-23  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 766
 767         * i386-dis.c (enum): Add PREFIX_0F09.
 768         * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
 769         (cpu_flags): Add CpuWBNOINVD.
 770         * i386-opc.h (enum): Add CpuWBNOINVD.
 771         (i386_cpu_flags): Add cpuwbnoinvd.
 772         * i386-opc.tbl: Add WBNOINVD instruction.
 773         * i386-init.h: Regenerate.
 774         * i386-tbl.h: Likewise.
 775
 776 2018-01-17  Jim Wilson  <jimw@sifive.com>
 777
 778         * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
 779
 780 2018-01-17  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 781
 782         * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
 783         Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
 784         CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
 785         (cpu_flags): Add CpuIBT, CpuSHSTK.
 786         * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
 787         (i386_cpu_flags): Add cpuibt, cpushstk.
 788         * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
 789         * i386-init.h: Regenerate.
 790         * i386-tbl.h: Likewise.
 791
 792 2018-01-16  Nick Clifton  <nickc@redhat.com>
 793
 794         * po/pt_BR.po: Updated Brazilian Portugese translation.
 795         * po/de.po: Updated German translation.
 796
 797 2018-01-15  Jim Wilson  <jimw@sifive.com>
 798
 799         * riscv-opc.c (match_c_nop): New.
 800         (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
 801
 802 2018-01-15  Nick Clifton  <nickc@redhat.com>
 803
 804         * po/uk.po: Updated Ukranian translation.
 805
 806 2018-01-13  Nick Clifton  <nickc@redhat.com>
 807
 808         * po/opcodes.pot: Regenerated.
 809
 810 2018-01-13  Nick Clifton  <nickc@redhat.com>
 811
 812         * configure: Regenerate.
 813
 814 2018-01-13  Nick Clifton  <nickc@redhat.com>
 815
 816         2.30 branch created.
 817
 818 2018-01-11  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 819
 820         * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
 821         * i386-tbl.h: Regenerate.
 822
 823 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 824
 825         * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
 826         * i386-tbl.h: Re-generate.
 827
 828 2018-01-10  Jan Beulich  <jbeulich@suse.com>
 829
 830         * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
 831         vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
 832         vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
 833         vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
 834         vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
 835         Disp8MemShift of AVX512VL forms.
 836         * i386-tbl.h: Re-generate.
 837
 838 2018-01-09  Jim Wilson  <jimw@sifive.com>
 839
 840         * riscv-dis.c (maybe_print_address): If base_reg is zero,
 841         then the hi_addr value is zero.
 842
 843 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 844
 845         * arm-dis.c (arm_opcodes): Add csdb.
 846         (thumb32_opcodes): Add csdb.
 847
 848 2018-01-09  James Greenhalgh  <james.greenhalgh@arm.com>
 849
 850         * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
 851         * aarch64-asm-2.c: Regenerate.
 852         * aarch64-dis-2.c: Regenerate.
 853         * aarch64-opc-2.c: Regenerate.
 854
 855 2018-01-08  H.J. Lu  <hongjiu.lu@intel.com>
 856
 857         PR gas/22681
 858         * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
 859         Remove AVX512 vmovd with 64-bit operands.
 860         * i386-tbl.h: Regenerated.
 861
 862 2018-01-05  Jim Wilson  <jimw@sifive.com>
 863
 864         * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
 865         jalr.
 866
 867 2018-01-03  Alan Modra  <amodra@gmail.com>
 868
 869         Update year range in copyright notice of all files.
 870
 871 2018-01-02  Jan Beulich  <jbeulich@suse.com>
 872
 873         * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
 874         and OPERAND_TYPE_REGZMM entries.
 875
 876 For older changes see ChangeLog-2017
 877 \f
 878 Copyright (C) 2018 Free Software Foundation, Inc.
 879
 880 Copying and distribution of this file, with or without modification,
 881 are permitted in any medium without royalty provided the copyright
 882 notice and this notice are preserved.
 883
 884 Local Variables:
 885 mode: change-log
 886 left-margin: 8
 887 fill-column: 74
 888 version-control: never
 889 End: