opcodes/ChangeLog

   1 2021-04-26  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-opc.tbl (lea): Add Optimize.
   4         * opcodes/i386-tbl.h: Re-generate.
   5
   6 2020-04-23  Max Filippov  <jcmvbkbc@gmail.com>
   7
   8         * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
   9         of l32r fetch and display referenced literal value.
  10
  11 2021-04-23  Max Filippov  <jcmvbkbc@gmail.com>
  12
  13         * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
  14         to 4 for literal disassembly.
  15
  16 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  17
  18         * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
  19         for TLBI instruction.
  20
  21 2021-04-19  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  22
  23         * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
  24         DC instruction.
  25
  26 2021-04-19  Jan Beulich  <jbeulich@suse.com>
  27
  28         * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
  29         "qualifier".
  30         (convert_mov_to_movewide): Add initializer for "value".
  31
  32 2021-04-16  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
  33
  34         * aarch64-opc.c: Add RME system registers.
  35
  36 2021-04-16  Lifang Xia <lifang_xia@c-sky.com>
  37
  38         * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
  39         "addi d,CV,z" to "c.mv d,CV".
  40
  41 2021-04-12  Alan Modra  <amodra@gmail.com>
  42
  43         * configure.ac (--enable-checking): Add support.
  44         * config.in: Regenerate.
  45         * configure: Regenerate.
  46
  47 2021-04-09  Tejas Belagod  <tejas.belagod@arm.com>
  48
  49         * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
  50         LD64/ST64 instructions to lse_atomic instead of ldstexcl.
  51
  52 2021-04-09  Alan Modra  <amodra@gmail.com>
  53
  54         * ppc-dis.c (struct dis_private): Add "special".
  55         (POWERPC_DIALECT): Delete.  Replace uses with..
  56         (private_data): ..this.  New inline function.
  57         (disassemble_init_powerpc): Init "special" names.
  58         (skip_optional_operands): Add is_pcrel arg, set when detecting R
  59         field of prefix instructions.
  60         (bsearch_reloc, print_got_plt): New functions.
  61         (print_insn_powerpc): For pcrel instructions, print target address
  62         and symbol if known, and decode plt and got loads too.
  63
  64 2021-04-08  Alan Modra  <amodra@gmail.com>
  65
  66         PR 27684
  67         * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
  68
  69 2021-04-08  Alan Modra  <amodra@gmail.com>
  70
  71         PR 27676
  72         * ppc-opc.c (DCBT_EO): Move earlier.
  73         (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
  74         (powerpc_operands): Add THCT and THDS entries.
  75         (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
  76
  77 2021-04-06  Alan Modra  <amodra@gmail.com>
  78
  79         * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
  80         * s12z-dis.c (decode_possible_symbol): Use symbol returned from
  81         symbol_at_address_func.
  82
  83 2021-04-05  Alan Modra  <amodra@gmail.com>
  84
  85         * configure.ac: Don't check for limits.h, string.h, strings.h or
  86         stdlib.h.
  87         (AC_ISC_POSIX): Don't invoke.
  88         * sysdep.h: Include stdlib.h and string.h unconditionally.
  89         * i386-opc.h: Include limits.h unconditionally.
  90         * wasm32-dis.c: Likewise.
  91         * cgen-opc.c: Don't include alloca-conf.h.
  92         * config.in: Regenerate.
  93         * configure: Regenerate.
  94
  95 2021-04-01  Martin Liska  <mliska@suse.cz>
  96
  97         * arm-dis.c (strneq): Remove strneq and use startswith.
  98         * cr16-dis.c (print_insn_cr16): Likewise.
  99         * score-dis.c (streq): Likewise.
 100         (strneq): Likewise.
 101         * score7-dis.c (strneq): Likewise.
 102
 103 2021-04-01  Alan Modra  <amodra@gmail.com>
 104
 105         PR 27675
 106         * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
 107
 108 2021-03-31  Alan Modra  <amodra@gmail.com>
 109
 110         * sysdep.h (POISON_BFD_BOOLEAN): Define.
 111         * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
 112         * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
 113         * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
 114         * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
 115         * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
 116         * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
 117         * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
 118         * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
 119         * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
 120         * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
 121         * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
 122         * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
 123         * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
 124         and TRUE with true throughout.
 125
 126 2021-03-31  Alan Modra  <amodra@gmail.com>
 127
 128         * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
 129         * aarch64-dis.h: Likewise.
 130         * aarch64-opc.c: Likewise.
 131         * avr-dis.c: Likewise.
 132         * csky-dis.c: Likewise.
 133         * nds32-asm.c: Likewise.
 134         * nds32-dis.c: Likewise.
 135         * nfp-dis.c: Likewise.
 136         * riscv-dis.c: Likewise.
 137         * s12z-dis.c: Likewise.
 138         * wasm32-dis.c: Likewise.
 139
 140 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
 143         (i386_seg_prefixes): New.
 144         * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
 145         (i386_seg_prefixes): Declare.
 146
 147 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 148
 149         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
 150
 151 2021-03-30  Jan Beulich  <jbeulich@suse.com>
 152
 153         * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
 154         * i386-reg.tbl (st): Move down.
 155         (st(0)): Delete. Extend comment.
 156         * i386-tbl.h: Re-generate.
 157
 158 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 159
 160         * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
 161         (cmpsd): Move next to cmps.
 162         (movsd): Move next to movs.
 163         (cmpxchg16b): Move to separate section.
 164         (fisttp, fisttpll): Likewise.
 165         (monitor, mwait): Likewise.
 166         * i386-tbl.h: Re-generate.
 167
 168 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 169
 170         * i386-opc.tbl (psadbw): Add <sse2:comm>.
 171         (vpsadbw): Add C.
 172         * i386-tbl.h: Re-generate.
 173
 174 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
 177         pclmul, gfni): New templates. Use them wherever possible. Move
 178         SSE4.1 pextrw into respective section.
 179         * i386-tbl.h: Re-generate.
 180
 181 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 182
 183         * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
 184         strtoull(). Bump upper loop bound. Widen masks. Sanity check
 185         "length".
 186         * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
 187         Convert all of their uses to representation in opcode.
 188
 189 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-opc.h (struct insn_template): Shrink base_opcode to 16
 192         bits. Shrink extension_opcode to 9 bits. Make it signed. Change
 193         value of None. Shrink operands to 3 bits.
 194
 195 2021-03-29  Jan Beulich  <jbeulich@suse.com>
 196
 197         * i386-gen.c (process_i386_opcode_modifier): New parameter
 198         "space".
 199         (output_i386_opcode): New local variable "space". Adjust
 200         process_i386_opcode_modifier() invocation.
 201         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 202         invocation.
 203         * i386-tbl.h: Re-generate.
 204
 205 2021-03-29  Alan Modra  <amodra@gmail.com>
 206
 207         * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
 208         (fp_qualifier_p, get_data_pattern): Likewise.
 209         (aarch64_get_operand_modifier_from_value): Likewise.
 210         (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
 211         (operand_variant_qualifier_p): Likewise.
 212         (qualifier_value_in_range_constraint_p): Likewise.
 213         (aarch64_get_qualifier_esize): Likewise.
 214         (aarch64_get_qualifier_nelem): Likewise.
 215         (aarch64_get_qualifier_standard_value): Likewise.
 216         (get_lower_bound, get_upper_bound): Likewise.
 217         (aarch64_find_best_match, match_operands_qualifier): Likewise.
 218         (aarch64_print_operand): Likewise.
 219         * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
 220         (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
 221         (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
 222         * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
 223         * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
 224         (print_insn_tic6x): Likewise.
 225
 226 2021-03-29  Alan Modra  <amodra@gmail.com>
 227
 228         * arc-dis.c (extract_operand_value): Correct NULL cast.
 229         * frv-opc.h: Regenerate.
 230
 231 2021-03-26  Jan Beulich  <jbeulich@suse.com>
 232
 233         * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
 234         MMX form.
 235         * i386-tbl.h: Re-generate.
 236
 237 2021-03-25  Abid Qadeer  <abidh@codesourcery.com>
 238
 239         * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
 240         immediate in br.n instruction.
 241
 242 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 243
 244         * i386-dis.c (XMGatherD, VexGatherD): New.
 245         (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
 246         (print_insn): Check masking for S/G insns.
 247         (OP_E_memory): New local variable check_gather. Extend mandatory
 248         SIB check. Check register conflicts for (EVEX-encoded) gathers.
 249         Extend check for disallowed 16-bit addressing.
 250         (OP_VEX): New local variables modrm_reg and sib_index. Convert
 251         if()s to switch(). Check register conflicts for (VEX-encoded)
 252         gathers. Drop no longer reachable cases.
 253         * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
 254         vgatherdp*.
 255
 256 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
 259         zeroing-masking without masking.
 260
 261 2021-03-25  Jan Beulich  <jbeulich@suse.com>
 262
 263         * i386-opc.tbl (invlpgb): Fix multi-operand form.
 264         (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
 265         single-operand forms as deprecated.
 266         * i386-tbl.h: Re-generate.
 267
 268 2021-03-25  Alan Modra  <amodra@gmail.com>
 269
 270         PR 27647
 271         * ppc-opc.c (XLOCB_MASK): Delete.
 272         (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
 273         XLBH_MASK.
 274         (powerpc_opcodes): Accept a BH field on all extended forms of
 275         bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
 276
 277 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 278
 279         * i386-gen.c (output_i386_opcode): Drop processing of
 280         opcode_length. Calculate length from base_opcode. Adjust prefix
 281         encoding determination.
 282         (process_i386_opcodes): Drop output of fake opcode_length.
 283         * i386-opc.h (struct insn_template): Drop opcode_length field.
 284         * i386-opc.tbl: Drop opcode length field from all templates.
 285         * i386-tbl.h: Re-generate.
 286
 287 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 288
 289         * i386-gen.c (process_i386_opcode_modifier): Return void. New
 290         parameter "prefix". Drop local variable "regular_encoding".
 291         Record prefix setting / check for consistency.
 292         (output_i386_opcode): Parse opcode_length and base_opcode
 293         earlier. Derive prefix encoding. Drop no longer applicable
 294         consistency checking. Adjust process_i386_opcode_modifier()
 295         invocation.
 296         (process_i386_opcodes): Adjust process_i386_opcode_modifier()
 297         invocation.
 298         * i386-tbl.h: Re-generate.
 299
 300 2021-03-24  Jan Beulich  <jbeulich@suse.com>
 301
 302         * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
 303         check.
 304         * i386-opc.h (Prefix_*): Move #define-s.
 305         * i386-opc.tbl: Move pseudo prefix enumerator values to
 306         extension opcode field. Introduce pseudopfx template.
 307         * i386-tbl.h: Re-generate.
 308
 309 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 310
 311         * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
 312         comment.
 313         * i386-tbl.h: Re-generate.
 314
 315 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 316
 317         * i386-opc.h (struct insn_template): Move cpu_flags field past
 318         opcode_modifier one.
 319         * i386-tbl.h: Re-generate.
 320
 321 2021-03-23  Jan Beulich  <jbeulich@suse.com>
 322
 323         * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
 324         * i386-opc.h (OpcodeSpace): New enumerator.
 325         (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
 326         (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
 327         SPACE_XOP09, SPACE_XOP0A): ... respectively.
 328         (struct i386_opcode_modifier): New field opcodespace. Shrink
 329         opcodeprefix field.
 330         i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
 331         SpaceXOP09, SpaceXOP0A): Define. Use them to replace
 332         OpcodePrefix uses.
 333         * i386-tbl.h: Re-generate.
 334
 335 2021-03-22  Martin Liska  <mliska@suse.cz>
 336
 337         * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
 338         * arc-dis.c (parse_option): Likewise.
 339         * arm-dis.c (parse_arm_disassembler_options): Likewise.
 340         * cris-dis.c (print_with_operands): Likewise.
 341         * h8300-dis.c (bfd_h8_disassemble): Likewise.
 342         * i386-dis.c (print_insn): Likewise.
 343         * ia64-gen.c (fetch_insn_class): Likewise.
 344         (parse_resource_users): Likewise.
 345         (in_iclass): Likewise.
 346         (lookup_specifier): Likewise.
 347         (insert_opcode_dependencies): Likewise.
 348         * mips-dis.c (parse_mips_ase_option): Likewise.
 349         (parse_mips_dis_option): Likewise.
 350         * s390-dis.c (disassemble_init_s390): Likewise.
 351         * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
 352
 353 2021-03-16  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
 354
 355         * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
 356
 357 2021-03-12  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>
 358
 359         * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
 360         icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
 361
 362 2021-03-12  Alan Modra  <amodra@gmail.com>
 363
 364         * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
 365
 366 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 367
 368         * i386-dis.c (OP_XMM): Re-order checks.
 369
 370 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-dis.c (putop): Drop need_vex check when also checking
 373         vex.evex.
 374         (intel_operand_size, OP_E_memory): Drop vex.evex check when also
 375         checking vex.b.
 376
 377 2021-03-11  Jan Beulich  <jbeulich@suse.com>
 378
 379         * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
 380         checks. Move case label past broadcast check.
 381
 382 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 383
 384         * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
 385         vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
 386         REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
 387         EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
 388         EVEX_W_0F38C7_M_0_L_2): Delete.
 389         (REG_EVEX_0F38C7_M_0_L_2): New.
 390         (intel_operand_size): Handle VEX and EVEX the same for
 391         vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
 392         vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
 393         (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
 394         vex_vsib_q_w_d_mode uses.
 395         * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
 396         0F38A1, and 0F38A3 entries.
 397         * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
 398         entry.
 399         * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
 400         * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
 401         0F38A3 entries.
 402
 403 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 404
 405         * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
 406         REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
 407         MOD_VEX_0FXOP_09_12): Rename to ...
 408         (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
 409         REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
 410         (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
 411         RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
 412         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 413         X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
 414         (reg_table): Adjust comments.
 415         (x86_64_table): Move X86_64_0F24, X86_64_0F26,
 416         X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
 417         X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
 418         (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
 419         (vex_len_table): Adjust opcode 0A_12 entry.
 420         (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
 421         MOD_C5_32BIT, and MOD_XOP_09_12 entries.
 422         (rm_table): Move hreset entry.
 423
 424 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 425
 426         * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
 427         EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
 428         EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
 429         EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
 430         EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
 431         (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
 432         (get_valid_dis386): Also handle 512-bit vector length when
 433         vectoring into vex_len_table[].
 434         * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
 435         0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
 436         entries.
 437         * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
 438         0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
 439         * i386-dis-evex-prefix.h: Adjust 0F7E entry.
 440         * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
 441         entries.
 442
 443 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 444
 445         * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
 446         Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
 447         EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
 448         * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
 449         entries.
 450         * i386-dis-evex-len.h (evex_len_table): Likewise.
 451         * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
 452
 453 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 454
 455         * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
 456         MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
 457         MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
 458         MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
 459         MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
 460         MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
 461         MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
 462         MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
 463         EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
 464         EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
 465         EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
 466         EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
 467         EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
 468         EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
 469         EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
 470         EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
 471         EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
 472         EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
 473         EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
 474         EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
 475         EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
 476         EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
 477         EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
 478         EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
 479         EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
 480         EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
 481         EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
 482         EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
 483         EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
 484         EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
 485         EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
 486         EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
 487         REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
 488         REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
 489         MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
 490         MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
 491         EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
 492         EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
 493         EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
 494         EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
 495         EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
 496         EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
 497         EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
 498         EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
 499         EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
 500         EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
 501         EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
 502         EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
 503         EVEX_W_0F3A43_L_n): New.
 504         * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
 505         0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
 506         0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
 507         * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
 508         for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
 509         0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
 510         0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
 511         * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
 512         0F385B, 0F38C6, and 0F38C7 entries.
 513         * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
 514         0F38C6 and 0F38C7.
 515         * i386-dis-evex-w.h: No longer link to evex_len_table[] for
 516         opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
 517         0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
 518         evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
 519
 520 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 521
 522         * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
 523         MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
 524         MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
 525         MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
 526         MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
 527         MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
 528         MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
 529         MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
 530         MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
 531         MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
 532         MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
 533         MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
 534         MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
 535         MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
 536         MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
 537         MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
 538         MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
 539         MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
 540         MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
 541         MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
 542         MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
 543         MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
 544         MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
 545         MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
 546         MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
 547         PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
 548         PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
 549         PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
 550         PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
 551         PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
 552         VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
 553         VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
 554         VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
 555         VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
 556         VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
 557         VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
 558         VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
 559         VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
 560         VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
 561         VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
 562         VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
 563         VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
 564         VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
 565         VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
 566         VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
 567         VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
 568         VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
 569         VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
 570         VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
 571         VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
 572         VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
 573         VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
 574         VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
 575         VEX_W_0F99_P_2_LEN_0): Delete.
 576         MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
 577         MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
 578         MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
 579         MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
 580         MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
 581         PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
 582         PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
 583         PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
 584         PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
 585         PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
 586         PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
 587         PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
 588         PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
 589         PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
 590         PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
 591         PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
 592         PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
 593         PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
 594         PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
 595         VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
 596         VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
 597         VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
 598         VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
 599         VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
 600         VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
 601         VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
 602         VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
 603         (prefix_table): No longer link to vex_len_table[] for opcodes
 604         0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
 605         0F92, 0F93, 0F98, and 0F99.
 606         (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
 607         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 608         0F98, and 0F99.
 609         (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
 610         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 611         0F98, and 0F99.
 612         (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
 613         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 614         0F98, and 0F99.
 615         (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
 616         0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
 617         0F98, and 0F99.
 618
 619 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 620
 621         * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
 622         Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
 623         REG_VEX_0F73_M_0 respectively.
 624         (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
 625         MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
 626         MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
 627         MOD_VEX_0F73_REG_7): Delete.
 628         (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
 629         (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
 630         PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
 631         PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
 632         PREFIX_VEX_0F3AF0_L_0 respectively.
 633         (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
 634         VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
 635         VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
 636         VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
 637         (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
 638         VEX_LEN_0F38F7): New.
 639         (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
 640         (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
 641         0F72, and 0F73. No longer link to vex_len_table[] for opcode
 642         0F38F3.
 643         (prefix_table): No longer link to vex_len_table[] for opcodes
 644         0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 645         (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
 646         0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
 647         0F38F6, 0F38F7, and 0F3AF0.
 648         (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
 649         prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
 650         (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
 651         0F73.
 652
 653 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 654
 655         * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
 656         REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
 657         (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
 658         MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
 659         MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
 660         (MOD_0F71, MOD_0F72, MOD_0F73): New.
 661         (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
 662         73.
 663         (reg_table): No longer link to mod_table[] for opcodes 0F71,
 664         0F72, and 0F73.
 665         (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
 666         0F73.
 667
 668 2021-03-10  Jan Beulich  <jbeulich@suse.com>
 669
 670         * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
 671         MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
 672         (reg_table): Don't link to mod_table[] where not needed. Add
 673         PREFIX_IGNORED to nop entries.
 674         (prefix_table): Replace PREFIX_OPCODE in nop entries.
 675         (mod_table): Add nop entries next to prefetch ones. Drop
 676         MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
 677         MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
 678         (rm_table): Add PREFIX_IGNORED to nop entries. Drop
 679         PREFIX_OPCODE from endbr* entries.
 680         (get_valid_dis386): Also consider entry's name when zapping
 681         vindex.
 682         (print_insn): Handle PREFIX_IGNORED.
 683
 684 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 685
 686         * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
 687         IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
 688         element.
 689         * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
 690         HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
 691         (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
 692         PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
 693         (struct i386_opcode_modifier): Delete notrackprefixok,
 694         islockable, hleprefixok, and repprefixok fields. Add prefixok
 695         field.
 696         * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
 697         HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
 698         (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
 699         not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
 700         Replace HLEPrefixOk.
 701         * opcodes/i386-tbl.h: Re-generate.
 702
 703 2021-03-09  Jan Beulich  <jbeulich@suse.com>
 704
 705         * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
 706         * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
 707         64-bit form.
 708         * opcodes/i386-tbl.h: Re-generate.
 709
 710 2021-03-03  Jan Beulich  <jbeulich@suse.com>
 711
 712         * i386-gen.c (output_i386_opcode): Don't get operand count. Look
 713         for {} instead of {0}. Don't look for '0'.
 714         * i386-opc.tbl: Drop operand count field. Drop redundant operand
 715         size specifiers.
 716
 717 2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
 718
 719         PR 27158
 720         * riscv-dis.c (print_insn_args): Updated encoding macros.
 721         * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
 722         (match_c_addi16sp): Updated encoding macros.
 723         (match_c_lui): Likewise.
 724         (match_c_lui_with_hint): Likewise.
 725         (match_c_addi4spn): Likewise.
 726         (match_c_slli): Likewise.
 727         (match_slli_as_c_slli): Likewise.
 728         (match_c_slli64): Likewise.
 729         (match_srxi_as_c_srxi): Likewise.
 730         (riscv_insn_types): Added .insn css/cl/cs.
 731
 732 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 733
 734         * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
 735         (default_priv_spec): Updated type to riscv_spec_class.
 736         (parse_riscv_dis_option): Updated.
 737         * riscv-opc.c: Moved stuff and make the file tidy.
 738
 739 2021-02-17  Alan Modra  <amodra@gmail.com>
 740
 741         * wasm32-dis.c: Include limits.h.
 742         (CHAR_BIT): Provide backup define.
 743         (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
 744         Correct signed overflow checking.
 745
 746 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 747
 748         * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
 749         * i386-tbl.h: Re-generate.
 750
 751 2021-02-16  Jan Beulich  <jbeulich@suse.com>
 752
 753         * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
 754         Oword.
 755         * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
 756
 757 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 758
 759         * s390-mkopc.c (main): Accept arch14 as cpu string.
 760         * s390-opc.txt: Add new arch14 instructions.
 761
 762 2021-02-04  Nick Alcock  <nick.alcock@oracle.com>
 763
 764         * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
 765         favour of LIBINTL.
 766         * configure: Regenerated.
 767
 768 2021-02-08  Mike Frysinger  <vapier@gentoo.org>
 769
 770         * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
 771         * tic54x-opc.c (regs): Rename to ...
 772         (tic54x_regs): ... this.
 773         (mmregs): Rename to ...
 774         (tic54x_mmregs): ... this.
 775         (condition_codes): Rename to ...
 776         (tic54x_condition_codes): ... this.
 777         (cc2_codes): Rename to ...
 778         (tic54x_cc2_codes): ... this.
 779         (cc3_codes): Rename to ...
 780         (tic54x_cc3_codes): ... this.
 781         (status_bits): Rename to ...
 782         (tic54x_status_bits): ... this.
 783         (misc_symbols): Rename to ...
 784         (tic54x_misc_symbols): ... this.
 785
 786 2021-02-04  Nelson Chu  <nelson.chu@sifive.com>
 787
 788         * riscv-opc.c (MASK_RVB_IMM): Removed.
 789         (riscv_opcodes): Removed zb* instructions.
 790         (riscv_ext_version_table): Removed versions for zb*.
 791
 792 2021-01-26  Alan Modra  <amodra@gmail.com>
 793
 794         * i386-gen.c (parse_template): Ensure entire template_instance
 795         is initialised.
 796
 797 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 798
 799         * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
 800         (riscv_fpr_names_abi): Likewise.
 801         (riscv_opcodes): Likewise.
 802         (riscv_insn_types): Likewise.
 803
 804 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 805
 806         * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
 807
 808 2021-01-15  Nelson Chu  <nelson.chu@sifive.com>
 809
 810         * riscv-dis.c: Comments tidy and improvement.
 811         * riscv-opc.c: Likewise.
 812
 813 2021-01-13  Alan Modra  <amodra@gmail.com>
 814
 815         * Makefile.in: Regenerate.
 816
 817 2021-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 818
 819         PR binutils/26792
 820         * configure.ac: Use GNU_MAKE_JOBSERVER.
 821         * aclocal.m4: Regenerated.
 822         * configure: Likewise.
 823
 824 2021-01-12  Nick Clifton  <nickc@redhat.com>
 825
 826         * po/sr.po: Updated Serbian translation.
 827
 828 2021-01-11  H.J. Lu  <hongjiu.lu@intel.com>
 829
 830         PR ld/27173
 831         * configure: Regenerated.
 832
 833 2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 834
 835         * aarch64-asm-2.c: Regenerate.
 836         * aarch64-dis-2.c: Likewise.
 837         * aarch64-opc-2.c: Likewise.
 838         * aarch64-opc.c (aarch64_print_operand):
 839         Delete handling of AARCH64_OPND_CSRE_CSR.
 840         * aarch64-tbl.h (aarch64_feature_csre): Delete.
 841         (CSRE): Likewise.
 842         (_CSRE_INSN): Likewise.
 843         (aarch64_opcode_table): Delete csr.
 844
 845 2021-01-11  Nick Clifton  <nickc@redhat.com>
 846
 847         * po/de.po: Updated German translation.
 848         * po/fr.po: Updated French translation.
 849         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 850         * po/sv.po: Updated Swedish translation.
 851         * po/uk.po: Updated Ukranian translation.
 852
 853 2021-01-09  H.J. Lu  <hongjiu.lu@intel.com>
 854
 855         * configure: Regenerated.
 856
 857 2021-01-09  Nick Clifton  <nickc@redhat.com>
 858
 859         * configure: Regenerate.
 860         * po/opcodes.pot: Regenerate.
 861
 862 2021-01-09  Nick Clifton  <nickc@redhat.com>
 863
 864         * 2.36 release branch crated.
 865
 866 2021-01-08  Peter Bergner  <bergner@linux.ibm.com>
 867
 868         * ppc-opc.c (insert_dw, (extract_dw): New functions.
 869         (DW, (XRC_MASK): Define.
 870         (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
 871
 872 2021-01-09  Alan Modra  <amodra@gmail.com>
 873
 874         * configure: Regenerate.
 875
 876 2021-01-08  Nick Clifton  <nickc@redhat.com>
 877
 878         * po/sv.po: Updated Swedish translation.
 879
 880 2021-01-08  Nick Clifton  <nickc@redhat.com>
 881
 882         PR 27129
 883         * aarch64-dis.c (determine_disassembling_preference): Move call to
 884         aarch64_match_operands_constraint outside of the assertion.
 885         * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
 886         Replace with a return of FALSE.
 887
 888         PR 27139
 889         * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
 890         core system register.
 891
 892 2021-01-07  Samuel Thibault  <samuel.thibault@gnu.org>
 893
 894         * configure: Regenerate.
 895
 896 2021-01-07  Nick Clifton  <nickc@redhat.com>
 897
 898         * po/fr.po: Updated French translation.
 899
 900 2021-01-07  Fredrik Noring  <noring@nocrew.org>
 901
 902         * m68k-opc.c (chkl): Change minimum architecture requirement to
 903         m68020.
 904
 905 2021-01-07  Philipp Tomsich  <prt@gnu.org>
 906
 907         * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
 908
 909 2021-01-07  Claire Xenia Wolf  <claire@symbioticeda.com>
 910             Jim Wilson  <jimw@sifive.com>
 911             Andrew Waterman  <andrew@sifive.com>
 912             Maxim Blinov  <maxim.blinov@embecosm.com>
 913             Kito Cheng  <kito.cheng@sifive.com>
 914             Nelson Chu  <nelson.chu@sifive.com>
 915
 916         * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
 917         (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
 918
 919 2021-01-01  Alan Modra  <amodra@gmail.com>
 920
 921         Update year range in copyright notice of all files.
 922
 923 For older changes see ChangeLog-2020
 924 \f
 925 Copyright (C) 2021 Free Software Foundation, Inc.
 926
 927 Copying and distribution of this file, with or without modification,
 928 are permitted in any medium without royalty provided the copyright
 929 notice and this notice are preserved.
 930
 931 Local Variables:
 932 mode: change-log
 933 left-margin: 8
 934 fill-column: 74
 935 version-control: never
 936 End: