opcodes/ChangeLog

   1 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
   2
   3         * configure: Regenerated.
   4
   5 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
   6
   7         * arc-dis.c (skipclass): New structure.
   8         (decodelist): New variable.
   9         (is_compatible_p): New function.
  10         (new_element): Likewise.
  11         (skip_class_p): Likewise.
  12         (find_format_from_table): Use skip_class_p function.
  13         (find_format): Decode first the extension instructions.
  14         (print_insn_arc): Select either ARCEM or ARCHS based on elf
  15         e_flags.
  16         (parse_option): New function.
  17         (parse_disassembler_options): Likewise.
  18         (print_arc_disassembler_options): Likewise.
  19         (print_insn_arc): Use parse_disassembler_options function.  Proper
  20         select ARCv2 cpu variant.
  21         * disassemble.c (disassembler_usage): Add ARC disassembler
  22         options.
  23
  24 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
  25
  26         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
  27         annotation from the "nal" entry and reorder it beyond "bltzal".
  28
  29 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
  30
  31         * sparc-opc.c (ldtxa): New macro.
  32         (sparc_opcodes): Use the macro defined above to add entries for
  33         the LDTXA instructions.
  34         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
  35         instruction.
  36
  37 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
  38
  39         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
  40         and "jmpc".
  41
  42 2016-07-01  Jan Beulich  <jbeulich@suse.com>
  43
  44         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
  45         (movzb): Adjust to cover all permitted suffixes.
  46         (movzw): New.
  47         * i386-tbl.h: Re-generate.
  48
  49 2016-07-01  Jan Beulich  <jbeulich@suse.com>
  50
  51         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
  52         (lgdt): Remove Tbyte from non-64-bit variant.
  53         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
  54         xsaves64, xsavec64): Remove Disp16.
  55         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
  56         Remove Disp32S from non-64-bit variants. Remove Disp16 from
  57         64-bit variants.
  58         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
  59         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
  60         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
  61         64-bit variants.
  62         * i386-tbl.h: Re-generate.
  63
  64 2016-07-01  Jan Beulich  <jbeulich@suse.com>
  65
  66         * i386-opc.tbl (xlat): Remove RepPrefixOk.
  67         * i386-tbl.h: Re-generate.
  68
  69 2016-06-30  Yao Qi  <yao.qi@linaro.org>
  70
  71         * arm-dis.c (print_insn): Fix typo in comment.
  72
  73 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
  74
  75         * aarch64-opc.c (operand_general_constraint_met_p): Check the
  76         range of ldst_elemlist operands.
  77         (print_register_list): Use PRIi64 to print the index.
  78         (aarch64_print_operand): Likewise.
  79
  80 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
  81
  82         * mcore-opc.h: Remove sentinal.
  83         * mcore-dis.c (print_insn_mcore): Adjust.
  84
  85 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
  86
  87         * arc-opc.c: Correct description of availability of NPS400
  88         features.
  89
  90 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
  91
  92         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
  93         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
  94         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
  95         xor3>: New mnemonics.
  96         <setb>: Change to a VX form instruction.
  97         (insert_sh6): Add support for rldixor.
  98         (extract_sh6): Likewise.
  99
 100 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 101
 102         * arc-ext.h: Wrap in extern C.
 103
 104 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
 105
 106         * arc-dis.c (arc_insn_length): Add comment on instruction length.
 107         Use same method for determining instruction length on ARC700 and
 108         NPS-400.
 109         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
 110         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
 111         with the NPS400 subclass.
 112         * arc-opc.c: Likewise.
 113
 114 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 115
 116         * sparc-opc.c (rdasr): New macro.
 117         (wrasr): Likewise.
 118         (rdpr): Likewise.
 119         (wrpr): Likewise.
 120         (rdhpr): Likewise.
 121         (wrhpr): Likewise.
 122         (sparc_opcodes): Use the macros above to fix and expand the
 123         definition of read/write instructions from/to
 124         asr/privileged/hyperprivileged instructions.
 125         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
 126         %hva_mask_nz.  Prefer softint_set and softint_clear over
 127         set_softint and clear_softint.
 128         (print_insn_sparc): Support %ver in Rd.
 129
 130 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 131
 132         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
 133         architecture according to the hardware capabilities they require.
 134
 135 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 136
 137         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
 138         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
 139         bfd_mach_sparc_v9{c,d,e,v,m}.
 140         * sparc-opc.c (MASK_V9C): Define.
 141         (MASK_V9D): Likewise.
 142         (MASK_V9E): Likewise.
 143         (MASK_V9V): Likewise.
 144         (MASK_V9M): Likewise.
 145         (v6): Add MASK_V9{C,D,E,V,M}.
 146         (v6notlet): Likewise.
 147         (v7): Likewise.
 148         (v8): Likewise.
 149         (v9): Likewise.
 150         (v9andleon): Likewise.
 151         (v9a): Likewise.
 152         (v9b): Likewise.
 153         (v9c): Define.
 154         (v9d): Likewise.
 155         (v9e): Likewise.
 156         (v9v): Likewise.
 157         (v9m): Likewise.
 158         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
 159
 160 2016-06-15  Nick Clifton  <nickc@redhat.com>
 161
 162         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
 163         constants to match expected behaviour.
 164         (nds32_parse_opcode): Likewise.  Also for whitespace.
 165
 166 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
 167
 168         * arc-opc.c (extract_rhv1): Extract value from insn.
 169
 170 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 171
 172         * arc-nps400-tbl.h: Add ldbit instruction.
 173         * arc-opc.c: Add flag classes required for ldbit.
 174
 175 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 176
 177         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
 178         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 179         support the above instructions.
 180
 181 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
 182
 183         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
 184         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
 185         csma, cbba, zncv, and hofs.
 186         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
 187         support the above instructions.
 188
 189 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 190
 191         * arc-nps400-tbl.h: Add andab and orab instructions.
 192
 193 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 194
 195         * arc-nps400-tbl.h: Add addl-like instructions.
 196
 197 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 198
 199         * arc-nps400-tbl.h: Add mxb and imxb instructions.
 200
 201 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
 202
 203         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
 204         instructions.
 205
 206 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 207
 208         * s390-dis.c (option_use_insn_len_bits_p): New file scope
 209         variable.
 210         (init_disasm): Handle new command line option "insnlength".
 211         (print_s390_disassembler_options): Mention new option in help
 212         output.
 213         (print_insn_s390): Use the encoded insn length when dumping
 214         unknown instructions.
 215
 216 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
 217
 218         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
 219          to the address and set as symbol address for LDS/ STS immediate operands.
 220
 221 2016-06-07  Alan Modra  <amodra@gmail.com>
 222
 223         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
 224         cpu for "vle" to e500.
 225         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
 226         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
 227         (PPCNONE): Delete, substitute throughout.
 228         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
 229         except for major opcode 4 and 31.
 230         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
 231
 232 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
 233
 234         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
 235         ARM_EXT_RAS in relevant entries.
 236
 237 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
 238
 239         PR binutils/20196
 240         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
 241         opcodes for E6500.
 242
 243 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         PR binutis/18386
 246         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
 247         (indir_v_mode): New.
 248         Add comments for '&'.
 249         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
 250         (putop): Handle '&'.
 251         (intel_operand_size): Handle indir_v_mode.
 252         (OP_E_register): Likewise.
 253         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
 254         64-bit indirect call/jmp for AMD64.
 255         * i386-tbl.h: Regenerated
 256
 257 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 258
 259         * arc-dis.c (struct arc_operand_iterator): New structure.
 260         (find_format_from_table): All the old content from find_format,
 261         with some minor adjustments, and parameter renaming.
 262         (find_format_long_instructions): New function.
 263         (find_format): Rewritten.
 264         (arc_insn_length): Add LSB parameter.
 265         (extract_operand_value): New function.
 266         (operand_iterator_next): New function.
 267         (print_insn_arc): Use new functions to find opcode, and iterator
 268         over operands.
 269         * arc-opc.c (insert_nps_3bit_dst_short): New function.
 270         (extract_nps_3bit_dst_short): New function.
 271         (insert_nps_3bit_src2_short): New function.
 272         (extract_nps_3bit_src2_short): New function.
 273         (insert_nps_bitop1_size): New function.
 274         (extract_nps_bitop1_size): New function.
 275         (insert_nps_bitop2_size): New function.
 276         (extract_nps_bitop2_size): New function.
 277         (insert_nps_bitop_mod4_msb): New function.
 278         (extract_nps_bitop_mod4_msb): New function.
 279         (insert_nps_bitop_mod4_lsb): New function.
 280         (extract_nps_bitop_mod4_lsb): New function.
 281         (insert_nps_bitop_dst_pos3_pos4): New function.
 282         (extract_nps_bitop_dst_pos3_pos4): New function.
 283         (insert_nps_bitop_ins_ext): New function.
 284         (extract_nps_bitop_ins_ext): New function.
 285         (arc_operands): Add new operands.
 286         (arc_long_opcodes): New global array.
 287         (arc_num_long_opcodes): New global.
 288         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
 289
 290 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 291
 292         * nds32-asm.h: Add extern "C".
 293         * sh-opc.h: Likewise.
 294
 295 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
 296
 297         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
 298         0,b,limm to the rflt instruction.
 299
 300 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 301
 302         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
 303         constant.
 304
 305 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
 306
 307         PR gas/20145
 308         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
 309         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
 310         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
 311         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
 312         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
 313         * i386-init.h: Regenerated.
 314
 315 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 316
 317         PR gas/20145
 318         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
 319         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
 320         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
 321         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
 322         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
 323         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
 324         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
 325         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
 326         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
 327         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
 328         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
 329         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
 330         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
 331         CpuRegMask for AVX512.
 332         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
 333         and CpuRegMask.
 334         (set_bitfield_from_cpu_flag_init): New function.
 335         (set_bitfield): Remove const on f.  Call
 336         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
 337         * i386-opc.h (CpuRegMMX): New.
 338         (CpuRegXMM): Likewise.
 339         (CpuRegYMM): Likewise.
 340         (CpuRegZMM): Likewise.
 341         (CpuRegMask): Likewise.
 342         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
 343         and cpuregmask.
 344         * i386-init.h: Regenerated.
 345         * i386-tbl.h: Likewise.
 346
 347 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 348
 349         PR gas/20154
 350         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
 351         (opcode_modifiers): Add AMD64 and Intel64.
 352         (main): Properly verify CpuMax.
 353         * i386-opc.h (CpuAMD64): Removed.
 354         (CpuIntel64): Likewise.
 355         (CpuMax): Set to CpuNo64.
 356         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
 357         (AMD64): New.
 358         (Intel64): Likewise.
 359         (i386_opcode_modifier): Add amd64 and intel64.
 360         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
 361         on call and jmp.
 362         * i386-init.h: Regenerated.
 363         * i386-tbl.h: Likewise.
 364
 365 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
 366
 367         PR gas/20154
 368         * i386-gen.c (main): Fail if CpuMax is incorrect.
 369         * i386-opc.h (CpuMax): Set to CpuIntel64.
 370         * i386-tbl.h: Regenerated.
 371
 372 2016-05-27  Nick Clifton  <nickc@redhat.com>
 373
 374         PR target/20150
 375         * msp430-dis.c (msp430dis_read_two_bytes): New function.
 376         (msp430dis_opcode_unsigned): New function.
 377         (msp430dis_opcode_signed): New function.
 378         (msp430_singleoperand): Use the new opcode reading functions.
 379         Only disassenmble bytes if they were successfully read.
 380         (msp430_doubleoperand): Likewise.
 381         (msp430_branchinstr): Likewise.
 382         (msp430x_callx_instr): Likewise.
 383         (print_insn_msp430): Check that it is safe to read bytes before
 384         attempting disassembly.  Use the new opcode reading functions.
 385
 386 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
 387
 388         * ppc-opc.c (CY): New define.  Document it.
 389         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
 390
 391 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 392
 393         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
 394         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
 395         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
 396         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
 397         CPU_ANY_AVX_FLAGS.
 398         * i386-init.h: Regenerated.
 399
 400 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 401
 402         PR gas/20141
 403         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
 404         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
 405         * i386-init.h: Regenerated.
 406
 407 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
 408
 409         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
 410         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
 411         * i386-init.h: Regenerated.
 412
 413 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 414
 415         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
 416         information.
 417         (print_insn_arc): Set insn_type information.
 418         * arc-opc.c (C_CC): Add F_CLASS_COND.
 419         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
 420         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
 421         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
 422         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
 423         (brne, brne_s, jeq_s, jne_s): Likewise.
 424
 425 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
 426
 427         * arc-tbl.h (neg): New instruction variant.
 428
 429 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
 430
 431         * arc-dis.c (find_format, find_format, get_auxreg)
 432         (print_insn_arc): Changed.
 433         * arc-ext.h (INSERT_XOP): Likewise.
 434
 435 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 436
 437         * tic54x-dis.c (sprint_mmr): Adjust.
 438         * tic54x-opc.c: Likewise.
 439
 440 2016-05-19  Alan Modra  <amodra@gmail.com>
 441
 442         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
 443
 444 2016-05-19  Alan Modra  <amodra@gmail.com>
 445
 446         * ppc-opc.c: Formatting.
 447         (NSISIGNOPT): Define.
 448         (powerpc_opcodes <subis>): Use NSISIGNOPT.
 449
 450 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
 451
 452         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
 453         replacing references to `micromips_ase' throughout.
 454         (_print_insn_mips): Don't use file-level microMIPS annotation to
 455         determine the disassembly mode with the symbol table.
 456
 457 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
 458
 459         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
 460
 461 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
 462
 463         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
 464         mips64r6.
 465         * mips-opc.c (D34): New macro.
 466         (mips_builtin_opcodes): Define bposge32c for DSPr3.
 467
 468 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
 469
 470         * i386-dis.c (prefix_table): Add RDPID instruction.
 471         * i386-gen.c (cpu_flag_init): Add RDPID flag.
 472         (cpu_flags): Add RDPID bitfield.
 473         * i386-opc.h (enum): Add RDPID element.
 474         (i386_cpu_flags): Add RDPID field.
 475         * i386-opc.tbl: Add RDPID instruction.
 476         * i386-init.h: Regenerate.
 477         * i386-tbl.h: Regenerate.
 478
 479 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 480
 481         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
 482         branch type of a symbol.
 483         (print_insn): Likewise.
 484
 485 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 486
 487         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
 488         Mainline Security Extensions instructions.
 489         (thumb_opcodes): Add entries for narrow ARMv8-M Security
 490         Extensions instructions.
 491         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
 492         instructions.
 493         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
 494         special registers.
 495
 496 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 497
 498         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
 499
 500 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
 501
 502         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
 503         (arcExtMap_genOpcode): Likewise.
 504         * arc-opc.c (arg_32bit_rc): Define new variable.
 505         (arg_32bit_u6): Likewise.
 506         (arg_32bit_limm): Likewise.
 507
 508 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 509
 510         * aarch64-gen.c (VERIFIER): Define.
 511         * aarch64-opc.c (VERIFIER): Define.
 512         (verify_ldpsw): Use static linkage.
 513         * aarch64-opc.h (verify_ldpsw): Remove.
 514         * aarch64-tbl.h: Use VERIFIER for verifiers.
 515
 516 2016-04-28  Nick Clifton  <nickc@redhat.com>
 517
 518         PR target/19722
 519         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
 520         * aarch64-opc.c (verify_ldpsw): New function.
 521         * aarch64-opc.h (verify_ldpsw): New prototype.
 522         * aarch64-tbl.h: Add initialiser for verifier field.
 523         (LDPSW): Set verifier to verify_ldpsw.
 524
 525 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
 526
 527         PR binutils/19983
 528         PR binutils/19984
 529         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 530         smaller than address size.
 531
 532 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 533
 534         * alpha-dis.c: Regenerate.
 535         * crx-dis.c: Likewise.
 536         * disassemble.c: Likewise.
 537         * epiphany-opc.c: Likewise.
 538         * fr30-opc.c: Likewise.
 539         * frv-opc.c: Likewise.
 540         * ip2k-opc.c: Likewise.
 541         * iq2000-opc.c: Likewise.
 542         * lm32-opc.c: Likewise.
 543         * lm32-opinst.c: Likewise.
 544         * m32c-opc.c: Likewise.
 545         * m32r-opc.c: Likewise.
 546         * m32r-opinst.c: Likewise.
 547         * mep-opc.c: Likewise.
 548         * mt-opc.c: Likewise.
 549         * or1k-opc.c: Likewise.
 550         * or1k-opinst.c: Likewise.
 551         * tic80-opc.c: Likewise.
 552         * xc16x-opc.c: Likewise.
 553         * xstormy16-opc.c: Likewise.
 554
 555 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 556
 557         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 558         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 559         calcsd, and calcxd instructions.
 560         * arc-opc.c (insert_nps_bitop_size): Delete.
 561         (extract_nps_bitop_size): Delete.
 562         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 563         (extract_nps_qcmp_m3): Define.
 564         (extract_nps_qcmp_m2): Define.
 565         (extract_nps_qcmp_m1): Define.
 566         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 567         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 568         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 569         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 570         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 571         NPS_QCMP_M3.
 572
 573 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 574
 575         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 576
 577 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 578
 579         * Makefile.in: Regenerated with automake 1.11.6.
 580         * aclocal.m4: Likewise.
 581
 582 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 583
 584         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 585         instructions.
 586         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 587         (extract_nps_cmem_uimm16): New function.
 588         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 589
 590 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 591
 592         * arc-dis.c (arc_insn_length): New function.
 593         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 594         (find_format): Change insnLen parameter to unsigned.
 595
 596 2016-04-13  Nick Clifton  <nickc@redhat.com>
 597
 598         PR target/19937
 599         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 600         the LD.B and LD.BU instructions.
 601
 602 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 603
 604         * arc-dis.c (find_format): Check for extension flags.
 605         (print_flags): New function.
 606         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 607         .extAuxRegister.
 608         * arc-ext.c (arcExtMap_coreRegName): Use
 609         LAST_EXTENSION_CORE_REGISTER.
 610         (arcExtMap_coreReadWrite): Likewise.
 611         (dump_ARC_extmap): Update printing.
 612         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 613         (arc_aux_regs): Add cpu field.
 614         * arc-regs.h: Add cpu field, lower case name aux registers.
 615
 616 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 617
 618         * arc-tbl.h: Add rtsc, sleep with no arguments.
 619
 620 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 621
 622         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 623         Initialize.
 624         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 625         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 626         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 627         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 628         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 629         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 630         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 631         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 632         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 633         (arc_opcode arc_opcodes): Null terminate the array.
 634         (arc_num_opcodes): Remove.
 635         * arc-ext.h (INSERT_XOP): Define.
 636         (extInstruction_t): Likewise.
 637         (arcExtMap_instName): Delete.
 638         (arcExtMap_insn): New function.
 639         (arcExtMap_genOpcode): Likewise.
 640         * arc-ext.c (ExtInstruction): Remove.
 641         (create_map): Zero initialize instruction fields.
 642         (arcExtMap_instName): Remove.
 643         (arcExtMap_insn): New function.
 644         (dump_ARC_extmap): More info while debuging.
 645         (arcExtMap_genOpcode): New function.
 646         * arc-dis.c (find_format): New function.
 647         (print_insn_arc): Use find_format.
 648         (arc_get_disassembler): Enable dump_ARC_extmap only when
 649         debugging.
 650
 651 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 652
 653         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 654         instruction bits out.
 655
 656 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 657
 658         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 659         * arc-opc.c (arc_flag_operands): Add new flags.
 660         (arc_flag_classes): Add new classes.
 661
 662 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 663
 664         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 665
 666 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 667
 668         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 669         encode1, rflt, crc16, and crc32 instructions.
 670         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 671         (arc_flag_classes): Add C_NPS_R.
 672         (insert_nps_bitop_size_2b): New function.
 673         (extract_nps_bitop_size_2b): Likewise.
 674         (insert_nps_bitop_uimm8): Likewise.
 675         (extract_nps_bitop_uimm8): Likewise.
 676         (arc_operands): Add new operand entries.
 677
 678 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 679
 680         * arc-regs.h: Add a new subclass field.  Add double assist
 681         accumulator register values.
 682         * arc-tbl.h: Use DPA subclass to mark the double assist
 683         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 684         * arc-opc.c (RSP): Define instead of SP.
 685         (arc_aux_regs): Add the subclass field.
 686
 687 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 688
 689         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 690
 691 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 692
 693         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 694         NPS_R_SRC1.
 695
 696 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 697
 698         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 699         issues.  No functional changes.
 700
 701 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 702
 703         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 704         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 705         (RTT): Remove duplicate.
 706         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 707         (PCT_CONFIG*): Remove.
 708         (D1L, D1H, D2H, D2L): Define.
 709
 710 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 711
 712         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 713
 714 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 715
 716         * arc-tbl.h (invld07): Remove.
 717         * arc-ext-tbl.h: New file.
 718         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 719         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 720
 721 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 722
 723         Fix -Wstack-usage warnings.
 724         * aarch64-dis.c (print_operands): Substitute size.
 725         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 726
 727 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 728
 729         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 730         to get a proper diagnostic when an invalid ASR register is used.
 731
 732 2016-03-22  Nick Clifton  <nickc@redhat.com>
 733
 734         * configure: Regenerate.
 735
 736 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 737
 738         * arc-nps400-tbl.h: New file.
 739         * arc-opc.c: Add top level comment.
 740         (insert_nps_3bit_dst): New function.
 741         (extract_nps_3bit_dst): New function.
 742         (insert_nps_3bit_src2): New function.
 743         (extract_nps_3bit_src2): New function.
 744         (insert_nps_bitop_size): New function.
 745         (extract_nps_bitop_size): New function.
 746         (arc_flag_operands): Add nps400 entries.
 747         (arc_flag_classes): Add nps400 entries.
 748         (arc_operands): Add nps400 entries.
 749         (arc_opcodes): Add nps400 include.
 750
 751 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 752
 753         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 754         the new class enum values.
 755
 756 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 757
 758         * arc-dis.c (print_insn_arc): Handle nps400.
 759
 760 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 761
 762         * arc-opc.c (BASE): Delete.
 763
 764 2016-03-18  Nick Clifton  <nickc@redhat.com>
 765
 766         PR target/19721
 767         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 768         of MOV insn that aliases an ORR insn.
 769
 770 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 771
 772         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 773
 774 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 775
 776         * mcore-opc.h: Add const qualifiers.
 777         * microblaze-opc.h (struct op_code_struct): Likewise.
 778         * sh-opc.h: Likewise.
 779         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 780         (tic4x_print_op): Likewise.
 781
 782 2016-03-02  Alan Modra  <amodra@gmail.com>
 783
 784         * or1k-desc.h: Regenerate.
 785         * fr30-ibld.c: Regenerate.
 786         * rl78-decode.c: Regenerate.
 787
 788 2016-03-01  Nick Clifton  <nickc@redhat.com>
 789
 790         PR target/19747
 791         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 792
 793 2016-02-24  Renlin Li  <renlin.li@arm.com>
 794
 795         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 796         (print_insn_coprocessor): Support fp16 instructions.
 797
 798 2016-02-24  Renlin Li  <renlin.li@arm.com>
 799
 800         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 801         vminnm, vrint(mpna).
 802
 803 2016-02-24  Renlin Li  <renlin.li@arm.com>
 804
 805         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 806         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 807
 808 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 809
 810         * i386-dis.c (print_insn): Parenthesize expression to prevent
 811         truncated addresses.
 812         (OP_J): Likewise.
 813
 814 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 815             Janek van Oirschot  <jvanoirs@synopsys.com>
 816
 817         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 818         variable.
 819
 820 2016-02-04  Nick Clifton  <nickc@redhat.com>
 821
 822         PR target/19561
 823         * msp430-dis.c (print_insn_msp430): Add a special case for
 824         decoding an RRC instruction with the ZC bit set in the extension
 825         word.
 826
 827 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 828
 829         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 830         * epiphany-ibld.c: Regenerate.
 831         * fr30-ibld.c: Regenerate.
 832         * frv-ibld.c: Regenerate.
 833         * ip2k-ibld.c: Regenerate.
 834         * iq2000-ibld.c: Regenerate.
 835         * lm32-ibld.c: Regenerate.
 836         * m32c-ibld.c: Regenerate.
 837         * m32r-ibld.c: Regenerate.
 838         * mep-ibld.c: Regenerate.
 839         * mt-ibld.c: Regenerate.
 840         * or1k-ibld.c: Regenerate.
 841         * xc16x-ibld.c: Regenerate.
 842         * xstormy16-ibld.c: Regenerate.
 843
 844 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 845
 846         * epiphany-dis.c: Regenerated from latest cpu files.
 847
 848 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 849
 850         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 851         test bit.
 852
 853 2016-01-25  Renlin Li  <renlin.li@arm.com>
 854
 855         * arm-dis.c (mapping_symbol_for_insn): New function.
 856         (find_ifthen_state): Call mapping_symbol_for_insn().
 857
 858 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 859
 860         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 861         of MSR UAO immediate operand.
 862
 863 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 864
 865         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 866         instruction support.
 867
 868 2016-01-17  Alan Modra  <amodra@gmail.com>
 869
 870         * configure: Regenerate.
 871
 872 2016-01-14  Nick Clifton  <nickc@redhat.com>
 873
 874         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 875         instructions that can support stack pointer operations.
 876         * rl78-decode.c: Regenerate.
 877         * rl78-dis.c: Fix display of stack pointer in MOVW based
 878         instructions.
 879
 880 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 881
 882         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 883         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 884         erxtatus_el1 and erxaddr_el1.
 885
 886 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 887
 888         * arm-dis.c (arm_opcodes): Add "esb".
 889         (thumb_opcodes): Likewise.
 890
 891 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 892
 893         * ppc-opc.c <xscmpnedp>: Delete.
 894         <xvcmpnedp>: Likewise.
 895         <xvcmpnedp.>: Likewise.
 896         <xvcmpnesp>: Likewise.
 897         <xvcmpnesp.>: Likewise.
 898
 899 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 900
 901         PR gas/13050
 902         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 903         addition to ISA_A.
 904
 905 2016-01-01  Alan Modra  <amodra@gmail.com>
 906
 907         Update year range in copyright notice of all files.
 908
 909 For older changes see ChangeLog-2015
 910 \f
 911 Copyright (C) 2016 Free Software Foundation, Inc.
 912
 913 Copying and distribution of this file, with or without modification,
 914 are permitted in any medium without royalty provided the copyright
 915 notice and this notice are preserved.
 916
 917 Local Variables:
 918 mode: change-log
 919 left-margin: 8
 920 fill-column: 74
 921 version-control: never
 922 End: