1 /* aarch64-dis.c -- AArch64 disassembler.
2 Copyright (C) 2009-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
22 #include "bfd_stdint.h"
24 #include "libiberty.h"
26 #include "aarch64-dis.h"
36 /* Cached mapping symbol state. */
43 static enum map_type last_type
;
44 static int last_mapping_sym
= -1;
45 static bfd_vma last_mapping_addr
= 0;
48 static int no_aliases
= 0; /* If set disassemble as most general inst. */
52 set_default_aarch64_dis_options (struct disassemble_info
*info ATTRIBUTE_UNUSED
)
57 parse_aarch64_dis_option (const char *option
, unsigned int len ATTRIBUTE_UNUSED
)
59 /* Try to match options that are simple flags */
60 if (CONST_STRNEQ (option
, "no-aliases"))
66 if (CONST_STRNEQ (option
, "aliases"))
73 if (CONST_STRNEQ (option
, "debug_dump"))
78 #endif /* DEBUG_AARCH64 */
81 fprintf (stderr
, _("Unrecognised disassembler option: %s\n"), option
);
85 parse_aarch64_dis_options (const char *options
)
87 const char *option_end
;
92 while (*options
!= '\0')
94 /* Skip empty options. */
101 /* We know that *options is neither NUL or a comma. */
102 option_end
= options
+ 1;
103 while (*option_end
!= ',' && *option_end
!= '\0')
106 parse_aarch64_dis_option (options
, option_end
- options
);
108 /* Go on to the next one. If option_end points to a comma, it
109 will be skipped above. */
110 options
= option_end
;
114 /* Functions doing the instruction disassembling. */
116 /* The unnamed arguments consist of the number of fields and information about
117 these fields where the VALUE will be extracted from CODE and returned.
118 MASK can be zero or the base mask of the opcode.
120 N.B. the fields are required to be in such an order than the most signficant
121 field for VALUE comes the first, e.g. the <index> in
122 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
123 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
124 the order of H, L, M. */
127 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...)
130 const aarch64_field
*field
;
131 enum aarch64_field_kind kind
;
135 num
= va_arg (va
, uint32_t);
137 aarch64_insn value
= 0x0;
140 kind
= va_arg (va
, enum aarch64_field_kind
);
141 field
= &fields
[kind
];
142 value
<<= field
->width
;
143 value
|= extract_field (kind
, code
, mask
);
148 /* Extract the value of all fields in SELF->fields from instruction CODE.
149 The least significant bit comes from the final field. */
152 extract_all_fields (const aarch64_operand
*self
, aarch64_insn code
)
156 enum aarch64_field_kind kind
;
159 for (i
= 0; i
< ARRAY_SIZE (self
->fields
) && self
->fields
[i
] != FLD_NIL
; ++i
)
161 kind
= self
->fields
[i
];
162 value
<<= fields
[kind
].width
;
163 value
|= extract_field (kind
, code
, 0);
168 /* Sign-extend bit I of VALUE. */
169 static inline int32_t
170 sign_extend (aarch64_insn value
, unsigned i
)
172 uint32_t ret
= value
;
175 if ((value
>> i
) & 0x1)
177 uint32_t val
= (uint32_t)(-1) << i
;
180 return (int32_t) ret
;
183 /* N.B. the following inline helpfer functions create a dependency on the
184 order of operand qualifier enumerators. */
186 /* Given VALUE, return qualifier for a general purpose register. */
187 static inline enum aarch64_opnd_qualifier
188 get_greg_qualifier_from_value (aarch64_insn value
)
190 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_W
+ value
;
192 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
196 /* Given VALUE, return qualifier for a vector register. This does not support
197 decoding instructions that accept the 2H vector type. */
199 static inline enum aarch64_opnd_qualifier
200 get_vreg_qualifier_from_value (aarch64_insn value
)
202 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_V_8B
+ value
;
204 /* Instructions using vector type 2H should not call this function. Skip over
206 if (qualifier
>= AARCH64_OPND_QLF_V_2H
)
210 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
214 /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
215 static inline enum aarch64_opnd_qualifier
216 get_sreg_qualifier_from_value (aarch64_insn value
)
218 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_S_B
+ value
;
221 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
225 /* Given the instruction in *INST which is probably half way through the
226 decoding and our caller wants to know the expected qualifier for operand
227 I. Return such a qualifier if we can establish it; otherwise return
228 AARCH64_OPND_QLF_NIL. */
230 static aarch64_opnd_qualifier_t
231 get_expected_qualifier (const aarch64_inst
*inst
, int i
)
233 aarch64_opnd_qualifier_seq_t qualifiers
;
234 /* Should not be called if the qualifier is known. */
235 assert (inst
->operands
[i
].qualifier
== AARCH64_OPND_QLF_NIL
);
236 if (aarch64_find_best_match (inst
, inst
->opcode
->qualifiers_list
,
238 return qualifiers
[i
];
240 return AARCH64_OPND_QLF_NIL
;
243 /* Operand extractors. */
246 aarch64_ext_regno (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
247 const aarch64_insn code
,
248 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
250 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
255 aarch64_ext_regno_pair (const aarch64_operand
*self ATTRIBUTE_UNUSED
, aarch64_opnd_info
*info
,
256 const aarch64_insn code ATTRIBUTE_UNUSED
,
257 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
259 assert (info
->idx
== 1
261 info
->reg
.regno
= inst
->operands
[info
->idx
- 1].reg
.regno
+ 1;
265 /* e.g. IC <ic_op>{, <Xt>}. */
267 aarch64_ext_regrt_sysins (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
268 const aarch64_insn code
,
269 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
271 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
272 assert (info
->idx
== 1
273 && (aarch64_get_operand_class (inst
->operands
[0].type
)
274 == AARCH64_OPND_CLASS_SYSTEM
));
275 /* This will make the constraint checking happy and more importantly will
276 help the disassembler determine whether this operand is optional or
278 info
->present
= aarch64_sys_ins_reg_has_xt (inst
->operands
[0].sysins_op
);
283 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
285 aarch64_ext_reglane (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
286 const aarch64_insn code
,
287 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
290 info
->reglane
.regno
= extract_field (self
->fields
[0], code
,
293 /* Index and/or type. */
294 if (inst
->opcode
->iclass
== asisdone
295 || inst
->opcode
->iclass
== asimdins
)
297 if (info
->type
== AARCH64_OPND_En
298 && inst
->opcode
->operands
[0] == AARCH64_OPND_Ed
)
301 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
302 assert (info
->idx
== 1); /* Vn */
303 aarch64_insn value
= extract_field (FLD_imm4
, code
, 0);
304 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
305 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
306 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
307 info
->reglane
.index
= value
>> shift
;
311 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
319 aarch64_insn value
= extract_field (FLD_imm5
, code
, 0);
320 while (++pos
<= 3 && (value
& 0x1) == 0)
324 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
325 info
->reglane
.index
= (unsigned) (value
>> 1);
330 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
331 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
333 /* Need information in other operand(s) to help decoding. */
334 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
335 switch (info
->qualifier
)
337 case AARCH64_OPND_QLF_S_H
:
339 info
->reglane
.index
= extract_fields (code
, 0, 3, FLD_H
, FLD_L
,
341 info
->reglane
.regno
&= 0xf;
343 case AARCH64_OPND_QLF_S_S
:
345 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
347 case AARCH64_OPND_QLF_S_D
:
349 info
->reglane
.index
= extract_field (FLD_H
, code
, 0);
360 aarch64_ext_reglist (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
361 const aarch64_insn code
,
362 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
365 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
367 info
->reglist
.num_regs
= extract_field (FLD_len
, code
, 0) + 1;
371 /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
373 aarch64_ext_ldst_reglist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
374 aarch64_opnd_info
*info
, const aarch64_insn code
,
375 const aarch64_inst
*inst
)
378 /* Number of elements in each structure to be loaded/stored. */
379 unsigned expected_num
= get_opcode_dependent_value (inst
->opcode
);
383 unsigned is_reserved
;
385 unsigned num_elements
;
401 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
403 value
= extract_field (FLD_opcode
, code
, 0);
404 if (expected_num
!= data
[value
].num_elements
|| data
[value
].is_reserved
)
406 info
->reglist
.num_regs
= data
[value
].num_regs
;
411 /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
412 lanes instructions. */
414 aarch64_ext_ldst_reglist_r (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
415 aarch64_opnd_info
*info
, const aarch64_insn code
,
416 const aarch64_inst
*inst
)
421 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
423 value
= extract_field (FLD_S
, code
, 0);
425 /* Number of registers is equal to the number of elements in
426 each structure to be loaded/stored. */
427 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
428 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
430 /* Except when it is LD1R. */
431 if (info
->reglist
.num_regs
== 1 && value
== (aarch64_insn
) 1)
432 info
->reglist
.num_regs
= 2;
437 /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
438 load/store single element instructions. */
440 aarch64_ext_ldst_elemlist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
441 aarch64_opnd_info
*info
, const aarch64_insn code
,
442 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
444 aarch64_field field
= {0, 0};
445 aarch64_insn QSsize
; /* fields Q:S:size. */
446 aarch64_insn opcodeh2
; /* opcode<2:1> */
449 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
451 /* Decode the index, opcode<2:1> and size. */
452 gen_sub_field (FLD_asisdlso_opcode
, 1, 2, &field
);
453 opcodeh2
= extract_field_2 (&field
, code
, 0);
454 QSsize
= extract_fields (code
, 0, 3, FLD_Q
, FLD_S
, FLD_vldst_size
);
458 info
->qualifier
= AARCH64_OPND_QLF_S_B
;
459 /* Index encoded in "Q:S:size". */
460 info
->reglist
.index
= QSsize
;
466 info
->qualifier
= AARCH64_OPND_QLF_S_H
;
467 /* Index encoded in "Q:S:size<1>". */
468 info
->reglist
.index
= QSsize
>> 1;
471 if ((QSsize
>> 1) & 0x1)
474 if ((QSsize
& 0x1) == 0)
476 info
->qualifier
= AARCH64_OPND_QLF_S_S
;
477 /* Index encoded in "Q:S". */
478 info
->reglist
.index
= QSsize
>> 2;
482 if (extract_field (FLD_S
, code
, 0))
485 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
486 /* Index encoded in "Q". */
487 info
->reglist
.index
= QSsize
>> 3;
494 info
->reglist
.has_index
= 1;
495 info
->reglist
.num_regs
= 0;
496 /* Number of registers is equal to the number of elements in
497 each structure to be loaded/stored. */
498 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
499 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
504 /* Decode fields immh:immb and/or Q for e.g.
505 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
506 or SSHR <V><d>, <V><n>, #<shift>. */
509 aarch64_ext_advsimd_imm_shift (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
510 aarch64_opnd_info
*info
, const aarch64_insn code
,
511 const aarch64_inst
*inst
)
514 aarch64_insn Q
, imm
, immh
;
515 enum aarch64_insn_class iclass
= inst
->opcode
->iclass
;
517 immh
= extract_field (FLD_immh
, code
, 0);
520 imm
= extract_fields (code
, 0, 2, FLD_immh
, FLD_immb
);
522 /* Get highest set bit in immh. */
523 while (--pos
>= 0 && (immh
& 0x8) == 0)
526 assert ((iclass
== asimdshf
|| iclass
== asisdshf
)
527 && (info
->type
== AARCH64_OPND_IMM_VLSR
528 || info
->type
== AARCH64_OPND_IMM_VLSL
));
530 if (iclass
== asimdshf
)
532 Q
= extract_field (FLD_Q
, code
, 0);
534 0000 x SEE AdvSIMD modified immediate
544 get_vreg_qualifier_from_value ((pos
<< 1) | (int) Q
);
547 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
549 if (info
->type
== AARCH64_OPND_IMM_VLSR
)
551 0000 SEE AdvSIMD modified immediate
552 0001 (16-UInt(immh:immb))
553 001x (32-UInt(immh:immb))
554 01xx (64-UInt(immh:immb))
555 1xxx (128-UInt(immh:immb)) */
556 info
->imm
.value
= (16 << pos
) - imm
;
560 0000 SEE AdvSIMD modified immediate
561 0001 (UInt(immh:immb)-8)
562 001x (UInt(immh:immb)-16)
563 01xx (UInt(immh:immb)-32)
564 1xxx (UInt(immh:immb)-64) */
565 info
->imm
.value
= imm
- (8 << pos
);
570 /* Decode shift immediate for e.g. sshr (imm). */
572 aarch64_ext_shll_imm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
573 aarch64_opnd_info
*info
, const aarch64_insn code
,
574 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
578 val
= extract_field (FLD_size
, code
, 0);
581 case 0: imm
= 8; break;
582 case 1: imm
= 16; break;
583 case 2: imm
= 32; break;
586 info
->imm
.value
= imm
;
590 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
591 value in the field(s) will be extracted as unsigned immediate value. */
593 aarch64_ext_imm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
594 const aarch64_insn code
,
595 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
599 imm
= extract_all_fields (self
, code
);
601 if (operand_need_sign_extension (self
))
602 imm
= sign_extend (imm
, get_operand_fields_width (self
) - 1);
604 if (operand_need_shift_by_two (self
))
607 if (info
->type
== AARCH64_OPND_ADDR_ADRP
)
610 info
->imm
.value
= imm
;
614 /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
616 aarch64_ext_imm_half (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
617 const aarch64_insn code
,
618 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
620 aarch64_ext_imm (self
, info
, code
, inst
);
621 info
->shifter
.kind
= AARCH64_MOD_LSL
;
622 info
->shifter
.amount
= extract_field (FLD_hw
, code
, 0) << 4;
626 /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
627 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
629 aarch64_ext_advsimd_imm_modified (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
630 aarch64_opnd_info
*info
,
631 const aarch64_insn code
,
632 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
635 enum aarch64_opnd_qualifier opnd0_qualifier
= inst
->operands
[0].qualifier
;
636 aarch64_field field
= {0, 0};
638 assert (info
->idx
== 1);
640 if (info
->type
== AARCH64_OPND_SIMD_FPIMM
)
643 /* a:b:c:d:e:f:g:h */
644 imm
= extract_fields (code
, 0, 2, FLD_abc
, FLD_defgh
);
645 if (!info
->imm
.is_fp
&& aarch64_get_qualifier_esize (opnd0_qualifier
) == 8)
647 /* Either MOVI <Dd>, #<imm>
648 or MOVI <Vd>.2D, #<imm>.
649 <imm> is a 64-bit immediate
650 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
651 encoded in "a:b:c:d:e:f:g:h". */
653 unsigned abcdefgh
= imm
;
654 for (imm
= 0ull, i
= 0; i
< 8; i
++)
655 if (((abcdefgh
>> i
) & 0x1) != 0)
656 imm
|= 0xffull
<< (8 * i
);
658 info
->imm
.value
= imm
;
661 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
662 switch (info
->qualifier
)
664 case AARCH64_OPND_QLF_NIL
:
666 info
->shifter
.kind
= AARCH64_MOD_NONE
;
668 case AARCH64_OPND_QLF_LSL
:
670 info
->shifter
.kind
= AARCH64_MOD_LSL
;
671 switch (aarch64_get_qualifier_esize (opnd0_qualifier
))
673 case 4: gen_sub_field (FLD_cmode
, 1, 2, &field
); break; /* per word */
674 case 2: gen_sub_field (FLD_cmode
, 1, 1, &field
); break; /* per half */
675 case 1: gen_sub_field (FLD_cmode
, 1, 0, &field
); break; /* per byte */
676 default: assert (0); return 0;
678 /* 00: 0; 01: 8; 10:16; 11:24. */
679 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) << 3;
681 case AARCH64_OPND_QLF_MSL
:
683 info
->shifter
.kind
= AARCH64_MOD_MSL
;
684 gen_sub_field (FLD_cmode
, 0, 1, &field
); /* per word */
685 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) ? 16 : 8;
695 /* Decode an 8-bit floating-point immediate. */
697 aarch64_ext_fpimm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
698 const aarch64_insn code
,
699 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
701 info
->imm
.value
= extract_all_fields (self
, code
);
706 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
708 aarch64_ext_fbits (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
709 aarch64_opnd_info
*info
, const aarch64_insn code
,
710 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
712 info
->imm
.value
= 64- extract_field (FLD_scale
, code
, 0);
716 /* Decode arithmetic immediate for e.g.
717 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
719 aarch64_ext_aimm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
720 aarch64_opnd_info
*info
, const aarch64_insn code
,
721 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
725 info
->shifter
.kind
= AARCH64_MOD_LSL
;
727 value
= extract_field (FLD_shift
, code
, 0);
730 info
->shifter
.amount
= value
? 12 : 0;
731 /* imm12 (unsigned) */
732 info
->imm
.value
= extract_field (FLD_imm12
, code
, 0);
737 /* Return true if VALUE is a valid logical immediate encoding, storing the
738 decoded value in *RESULT if so. ESIZE is the number of bytes in the
739 decoded immediate. */
741 decode_limm (uint32_t esize
, aarch64_insn value
, int64_t *result
)
747 /* value is N:immr:imms. */
749 R
= (value
>> 6) & 0x3f;
750 N
= (value
>> 12) & 0x1;
752 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
753 (in other words, right rotated by R), then replicated. */
757 mask
= 0xffffffffffffffffull
;
763 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size
= 32; break;
764 case 0x20 ... 0x2f: /* 10xxxx */ simd_size
= 16; S
&= 0xf; break;
765 case 0x30 ... 0x37: /* 110xxx */ simd_size
= 8; S
&= 0x7; break;
766 case 0x38 ... 0x3b: /* 1110xx */ simd_size
= 4; S
&= 0x3; break;
767 case 0x3c ... 0x3d: /* 11110x */ simd_size
= 2; S
&= 0x1; break;
770 mask
= (1ull << simd_size
) - 1;
771 /* Top bits are IGNORED. */
775 if (simd_size
> esize
* 8)
778 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
779 if (S
== simd_size
- 1)
781 /* S+1 consecutive bits to 1. */
782 /* NOTE: S can't be 63 due to detection above. */
783 imm
= (1ull << (S
+ 1)) - 1;
784 /* Rotate to the left by simd_size - R. */
786 imm
= ((imm
<< (simd_size
- R
)) & mask
) | (imm
>> R
);
787 /* Replicate the value according to SIMD size. */
790 case 2: imm
= (imm
<< 2) | imm
;
792 case 4: imm
= (imm
<< 4) | imm
;
794 case 8: imm
= (imm
<< 8) | imm
;
796 case 16: imm
= (imm
<< 16) | imm
;
798 case 32: imm
= (imm
<< 32) | imm
;
801 default: assert (0); return 0;
804 *result
= imm
& ~((uint64_t) -1 << (esize
* 4) << (esize
* 4));
809 /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
811 aarch64_ext_limm (const aarch64_operand
*self
,
812 aarch64_opnd_info
*info
, const aarch64_insn code
,
813 const aarch64_inst
*inst
)
818 value
= extract_fields (code
, 0, 3, self
->fields
[0], self
->fields
[1],
820 esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
821 return decode_limm (esize
, value
, &info
->imm
.value
);
824 /* Decode a logical immediate for the BIC alias of AND (etc.). */
826 aarch64_ext_inv_limm (const aarch64_operand
*self
,
827 aarch64_opnd_info
*info
, const aarch64_insn code
,
828 const aarch64_inst
*inst
)
830 if (!aarch64_ext_limm (self
, info
, code
, inst
))
832 info
->imm
.value
= ~info
->imm
.value
;
836 /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
837 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
839 aarch64_ext_ft (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
840 aarch64_opnd_info
*info
,
841 const aarch64_insn code
, const aarch64_inst
*inst
)
846 info
->reg
.regno
= extract_field (FLD_Rt
, code
, 0);
849 value
= extract_field (FLD_ldst_size
, code
, 0);
850 if (inst
->opcode
->iclass
== ldstpair_indexed
851 || inst
->opcode
->iclass
== ldstnapair_offs
852 || inst
->opcode
->iclass
== ldstpair_off
853 || inst
->opcode
->iclass
== loadlit
)
855 enum aarch64_opnd_qualifier qualifier
;
858 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
859 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
860 case 2: qualifier
= AARCH64_OPND_QLF_S_Q
; break;
863 info
->qualifier
= qualifier
;
868 value
= extract_fields (code
, 0, 2, FLD_opc1
, FLD_ldst_size
);
871 info
->qualifier
= get_sreg_qualifier_from_value (value
);
877 /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
879 aarch64_ext_addr_simple (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
880 aarch64_opnd_info
*info
,
882 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
885 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
889 /* Decode the address operand for e.g.
890 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
892 aarch64_ext_addr_regoff (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
893 aarch64_opnd_info
*info
,
894 aarch64_insn code
, const aarch64_inst
*inst
)
896 aarch64_insn S
, value
;
899 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
901 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
903 value
= extract_field (FLD_option
, code
, 0);
905 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
906 /* Fix-up the shifter kind; although the table-driven approach is
907 efficient, it is slightly inflexible, thus needing this fix-up. */
908 if (info
->shifter
.kind
== AARCH64_MOD_UXTX
)
909 info
->shifter
.kind
= AARCH64_MOD_LSL
;
911 S
= extract_field (FLD_S
, code
, 0);
914 info
->shifter
.amount
= 0;
915 info
->shifter
.amount_present
= 0;
920 /* Need information in other operand(s) to help achieve the decoding
922 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
923 /* Get the size of the data element that is accessed, which may be
924 different from that of the source register size, e.g. in strb/ldrb. */
925 size
= aarch64_get_qualifier_esize (info
->qualifier
);
926 info
->shifter
.amount
= get_logsz (size
);
927 info
->shifter
.amount_present
= 1;
933 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
935 aarch64_ext_addr_simm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
936 aarch64_insn code
, const aarch64_inst
*inst
)
939 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
942 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
943 /* simm (imm9 or imm7) */
944 imm
= extract_field (self
->fields
[0], code
, 0);
945 info
->addr
.offset
.imm
= sign_extend (imm
, fields
[self
->fields
[0]].width
- 1);
946 if (self
->fields
[0] == FLD_imm7
)
947 /* scaled immediate in ld/st pair instructions. */
948 info
->addr
.offset
.imm
*= aarch64_get_qualifier_esize (info
->qualifier
);
950 if (inst
->opcode
->iclass
== ldst_unscaled
951 || inst
->opcode
->iclass
== ldstnapair_offs
952 || inst
->opcode
->iclass
== ldstpair_off
953 || inst
->opcode
->iclass
== ldst_unpriv
)
954 info
->addr
.writeback
= 0;
957 /* pre/post- index */
958 info
->addr
.writeback
= 1;
959 if (extract_field (self
->fields
[1], code
, 0) == 1)
960 info
->addr
.preind
= 1;
962 info
->addr
.postind
= 1;
968 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
970 aarch64_ext_addr_uimm12 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
972 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
975 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
976 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
978 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
980 info
->addr
.offset
.imm
= extract_field (self
->fields
[1], code
, 0) << shift
;
984 /* Decode the address operand for e.g.
985 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
987 aarch64_ext_simd_addr_post (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
988 aarch64_opnd_info
*info
,
989 aarch64_insn code
, const aarch64_inst
*inst
)
991 /* The opcode dependent area stores the number of elements in
992 each structure to be loaded/stored. */
993 int is_ld1r
= get_opcode_dependent_value (inst
->opcode
) == 1;
996 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
998 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
999 if (info
->addr
.offset
.regno
== 31)
1001 if (inst
->opcode
->operands
[0] == AARCH64_OPND_LVt_AL
)
1002 /* Special handling of loading single structure to all lane. */
1003 info
->addr
.offset
.imm
= (is_ld1r
? 1
1004 : inst
->operands
[0].reglist
.num_regs
)
1005 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1007 info
->addr
.offset
.imm
= inst
->operands
[0].reglist
.num_regs
1008 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
)
1009 * aarch64_get_qualifier_nelem (inst
->operands
[0].qualifier
);
1012 info
->addr
.offset
.is_reg
= 1;
1013 info
->addr
.writeback
= 1;
1018 /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
1020 aarch64_ext_cond (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1021 aarch64_opnd_info
*info
,
1022 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1026 value
= extract_field (FLD_cond
, code
, 0);
1027 info
->cond
= get_cond_from_value (value
);
1031 /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
1033 aarch64_ext_sysreg (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1034 aarch64_opnd_info
*info
,
1036 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1038 /* op0:op1:CRn:CRm:op2 */
1039 info
->sysreg
= extract_fields (code
, 0, 5, FLD_op0
, FLD_op1
, FLD_CRn
,
1044 /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
1046 aarch64_ext_pstatefield (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1047 aarch64_opnd_info
*info
, aarch64_insn code
,
1048 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1052 info
->pstatefield
= extract_fields (code
, 0, 2, FLD_op1
, FLD_op2
);
1053 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
1054 if (aarch64_pstatefields
[i
].value
== (aarch64_insn
)info
->pstatefield
)
1056 /* Reserved value in <pstatefield>. */
1060 /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
1062 aarch64_ext_sysins_op (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1063 aarch64_opnd_info
*info
,
1065 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1069 const aarch64_sys_ins_reg
*sysins_ops
;
1070 /* op0:op1:CRn:CRm:op2 */
1071 value
= extract_fields (code
, 0, 5,
1072 FLD_op0
, FLD_op1
, FLD_CRn
,
1077 case AARCH64_OPND_SYSREG_AT
: sysins_ops
= aarch64_sys_regs_at
; break;
1078 case AARCH64_OPND_SYSREG_DC
: sysins_ops
= aarch64_sys_regs_dc
; break;
1079 case AARCH64_OPND_SYSREG_IC
: sysins_ops
= aarch64_sys_regs_ic
; break;
1080 case AARCH64_OPND_SYSREG_TLBI
: sysins_ops
= aarch64_sys_regs_tlbi
; break;
1081 default: assert (0); return 0;
1084 for (i
= 0; sysins_ops
[i
].name
!= NULL
; ++i
)
1085 if (sysins_ops
[i
].value
== value
)
1087 info
->sysins_op
= sysins_ops
+ i
;
1088 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1089 info
->sysins_op
->name
,
1090 (unsigned)info
->sysins_op
->value
,
1091 aarch64_sys_ins_reg_has_xt (info
->sysins_op
), i
);
1098 /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
1101 aarch64_ext_barrier (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1102 aarch64_opnd_info
*info
,
1104 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1107 info
->barrier
= aarch64_barrier_options
+ extract_field (FLD_CRm
, code
, 0);
1111 /* Decode the prefetch operation option operand for e.g.
1112 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
1115 aarch64_ext_prfop (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1116 aarch64_opnd_info
*info
,
1117 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1120 info
->prfop
= aarch64_prfops
+ extract_field (FLD_Rt
, code
, 0);
1124 /* Decode the hint number for an alias taking an operand. Set info->hint_option
1125 to the matching name/value pair in aarch64_hint_options. */
1128 aarch64_ext_hint (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1129 aarch64_opnd_info
*info
,
1131 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1134 unsigned hint_number
;
1137 hint_number
= extract_fields (code
, 0, 2, FLD_CRm
, FLD_op2
);
1139 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
1141 if (hint_number
== aarch64_hint_options
[i
].value
)
1143 info
->hint_option
= &(aarch64_hint_options
[i
]);
1151 /* Decode the extended register operand for e.g.
1152 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1154 aarch64_ext_reg_extended (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1155 aarch64_opnd_info
*info
,
1157 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1162 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1164 value
= extract_field (FLD_option
, code
, 0);
1165 info
->shifter
.kind
=
1166 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
1168 info
->shifter
.amount
= extract_field (FLD_imm3
, code
, 0);
1170 /* This makes the constraint checking happy. */
1171 info
->shifter
.operator_present
= 1;
1173 /* Assume inst->operands[0].qualifier has been resolved. */
1174 assert (inst
->operands
[0].qualifier
!= AARCH64_OPND_QLF_NIL
);
1175 info
->qualifier
= AARCH64_OPND_QLF_W
;
1176 if (inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_X
1177 && (info
->shifter
.kind
== AARCH64_MOD_UXTX
1178 || info
->shifter
.kind
== AARCH64_MOD_SXTX
))
1179 info
->qualifier
= AARCH64_OPND_QLF_X
;
1184 /* Decode the shifted register operand for e.g.
1185 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
1187 aarch64_ext_reg_shifted (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1188 aarch64_opnd_info
*info
,
1190 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1195 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1197 value
= extract_field (FLD_shift
, code
, 0);
1198 info
->shifter
.kind
=
1199 aarch64_get_operand_modifier_from_value (value
, FALSE
/* extend_p */);
1200 if (info
->shifter
.kind
== AARCH64_MOD_ROR
1201 && inst
->opcode
->iclass
!= log_shift
)
1202 /* ROR is not available for the shifted register operand in arithmetic
1206 info
->shifter
.amount
= extract_field (FLD_imm6
, code
, 0);
1208 /* This makes the constraint checking happy. */
1209 info
->shifter
.operator_present
= 1;
1214 /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
1215 where <offset> is given by the OFFSET parameter and where <factor> is
1216 1 plus SELF's operand-dependent value. fields[0] specifies the field
1217 that holds <base>. */
1219 aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand
*self
,
1220 aarch64_opnd_info
*info
, aarch64_insn code
,
1223 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1224 info
->addr
.offset
.imm
= offset
* (1 + get_operand_specific_data (self
));
1225 info
->addr
.offset
.is_reg
= FALSE
;
1226 info
->addr
.writeback
= FALSE
;
1227 info
->addr
.preind
= TRUE
;
1229 info
->shifter
.kind
= AARCH64_MOD_MUL_VL
;
1230 info
->shifter
.amount
= 1;
1231 info
->shifter
.operator_present
= (info
->addr
.offset
.imm
!= 0);
1232 info
->shifter
.amount_present
= FALSE
;
1236 /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
1237 where <simm4> is a 4-bit signed value and where <factor> is 1 plus
1238 SELF's operand-dependent value. fields[0] specifies the field that
1239 holds <base>. <simm4> is encoded in the SVE_imm4 field. */
1241 aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand
*self
,
1242 aarch64_opnd_info
*info
, aarch64_insn code
,
1243 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1247 offset
= extract_field (FLD_SVE_imm4
, code
, 0);
1248 offset
= ((offset
+ 8) & 15) - 8;
1249 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1252 /* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
1253 where <simm6> is a 6-bit signed value and where <factor> is 1 plus
1254 SELF's operand-dependent value. fields[0] specifies the field that
1255 holds <base>. <simm6> is encoded in the SVE_imm6 field. */
1257 aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand
*self
,
1258 aarch64_opnd_info
*info
, aarch64_insn code
,
1259 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1263 offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1264 offset
= (((offset
+ 32) & 63) - 32);
1265 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1268 /* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
1269 where <simm9> is a 9-bit signed value and where <factor> is 1 plus
1270 SELF's operand-dependent value. fields[0] specifies the field that
1271 holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
1272 and imm3 fields, with imm3 being the less-significant part. */
1274 aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand
*self
,
1275 aarch64_opnd_info
*info
,
1277 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1281 offset
= extract_fields (code
, 0, 2, FLD_SVE_imm6
, FLD_imm3
);
1282 offset
= (((offset
+ 256) & 511) - 256);
1283 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1286 /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
1287 is given by the OFFSET parameter and where <shift> is SELF's operand-
1288 dependent value. fields[0] specifies the base register field <base>. */
1290 aarch64_ext_sve_addr_reg_imm (const aarch64_operand
*self
,
1291 aarch64_opnd_info
*info
, aarch64_insn code
,
1294 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1295 info
->addr
.offset
.imm
= offset
* (1 << get_operand_specific_data (self
));
1296 info
->addr
.offset
.is_reg
= FALSE
;
1297 info
->addr
.writeback
= FALSE
;
1298 info
->addr
.preind
= TRUE
;
1299 info
->shifter
.operator_present
= FALSE
;
1300 info
->shifter
.amount_present
= FALSE
;
1304 /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1305 is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1306 value. fields[0] specifies the base register field. */
1308 aarch64_ext_sve_addr_ri_u6 (const aarch64_operand
*self
,
1309 aarch64_opnd_info
*info
, aarch64_insn code
,
1310 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1312 int offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1313 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1316 /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1317 is SELF's operand-dependent value. fields[0] specifies the base
1318 register field and fields[1] specifies the offset register field. */
1320 aarch64_ext_sve_addr_rr_lsl (const aarch64_operand
*self
,
1321 aarch64_opnd_info
*info
, aarch64_insn code
,
1322 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1326 index_regno
= extract_field (self
->fields
[1], code
, 0);
1327 if (index_regno
== 31 && (self
->flags
& OPD_F_NO_ZR
) != 0)
1330 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1331 info
->addr
.offset
.regno
= index_regno
;
1332 info
->addr
.offset
.is_reg
= TRUE
;
1333 info
->addr
.writeback
= FALSE
;
1334 info
->addr
.preind
= TRUE
;
1335 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1336 info
->shifter
.amount
= get_operand_specific_data (self
);
1337 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1338 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1342 /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1343 <shift> is SELF's operand-dependent value. fields[0] specifies the
1344 base register field, fields[1] specifies the offset register field and
1345 fields[2] is a single-bit field that selects SXTW over UXTW. */
1347 aarch64_ext_sve_addr_rz_xtw (const aarch64_operand
*self
,
1348 aarch64_opnd_info
*info
, aarch64_insn code
,
1349 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1351 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1352 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1353 info
->addr
.offset
.is_reg
= TRUE
;
1354 info
->addr
.writeback
= FALSE
;
1355 info
->addr
.preind
= TRUE
;
1356 if (extract_field (self
->fields
[2], code
, 0))
1357 info
->shifter
.kind
= AARCH64_MOD_SXTW
;
1359 info
->shifter
.kind
= AARCH64_MOD_UXTW
;
1360 info
->shifter
.amount
= get_operand_specific_data (self
);
1361 info
->shifter
.operator_present
= TRUE
;
1362 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1366 /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1367 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1368 fields[0] specifies the base register field. */
1370 aarch64_ext_sve_addr_zi_u5 (const aarch64_operand
*self
,
1371 aarch64_opnd_info
*info
, aarch64_insn code
,
1372 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1374 int offset
= extract_field (FLD_imm5
, code
, 0);
1375 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1378 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1379 where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
1380 number. fields[0] specifies the base register field and fields[1]
1381 specifies the offset register field. */
1383 aarch64_ext_sve_addr_zz (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1384 aarch64_insn code
, enum aarch64_modifier_kind kind
)
1386 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1387 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1388 info
->addr
.offset
.is_reg
= TRUE
;
1389 info
->addr
.writeback
= FALSE
;
1390 info
->addr
.preind
= TRUE
;
1391 info
->shifter
.kind
= kind
;
1392 info
->shifter
.amount
= extract_field (FLD_SVE_msz
, code
, 0);
1393 info
->shifter
.operator_present
= (kind
!= AARCH64_MOD_LSL
1394 || info
->shifter
.amount
!= 0);
1395 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1399 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1400 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1401 field and fields[1] specifies the offset register field. */
1403 aarch64_ext_sve_addr_zz_lsl (const aarch64_operand
*self
,
1404 aarch64_opnd_info
*info
, aarch64_insn code
,
1405 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1407 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_LSL
);
1410 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1411 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1412 field and fields[1] specifies the offset register field. */
1414 aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand
*self
,
1415 aarch64_opnd_info
*info
, aarch64_insn code
,
1416 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1418 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_SXTW
);
1421 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1422 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1423 field and fields[1] specifies the offset register field. */
1425 aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand
*self
,
1426 aarch64_opnd_info
*info
, aarch64_insn code
,
1427 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1429 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_UXTW
);
1432 /* Finish decoding an SVE arithmetic immediate, given that INFO already
1433 has the raw field value and that the low 8 bits decode to VALUE. */
1435 decode_sve_aimm (aarch64_opnd_info
*info
, int64_t value
)
1437 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1438 info
->shifter
.amount
= 0;
1439 if (info
->imm
.value
& 0x100)
1442 /* Decode 0x100 as #0, LSL #8. */
1443 info
->shifter
.amount
= 8;
1447 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1448 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1449 info
->imm
.value
= value
;
1453 /* Decode an SVE ADD/SUB immediate. */
1455 aarch64_ext_sve_aimm (const aarch64_operand
*self
,
1456 aarch64_opnd_info
*info
, const aarch64_insn code
,
1457 const aarch64_inst
*inst
)
1459 return (aarch64_ext_imm (self
, info
, code
, inst
)
1460 && decode_sve_aimm (info
, (uint8_t) info
->imm
.value
));
1463 /* Decode an SVE CPY/DUP immediate. */
1465 aarch64_ext_sve_asimm (const aarch64_operand
*self
,
1466 aarch64_opnd_info
*info
, const aarch64_insn code
,
1467 const aarch64_inst
*inst
)
1469 return (aarch64_ext_imm (self
, info
, code
, inst
)
1470 && decode_sve_aimm (info
, (int8_t) info
->imm
.value
));
1473 /* Decode a single-bit immediate that selects between #0.5 and #1.0.
1474 The fields array specifies which field to use. */
1476 aarch64_ext_sve_float_half_one (const aarch64_operand
*self
,
1477 aarch64_opnd_info
*info
, aarch64_insn code
,
1478 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1480 if (extract_field (self
->fields
[0], code
, 0))
1481 info
->imm
.value
= 0x3f800000;
1483 info
->imm
.value
= 0x3f000000;
1484 info
->imm
.is_fp
= TRUE
;
1488 /* Decode a single-bit immediate that selects between #0.5 and #2.0.
1489 The fields array specifies which field to use. */
1491 aarch64_ext_sve_float_half_two (const aarch64_operand
*self
,
1492 aarch64_opnd_info
*info
, aarch64_insn code
,
1493 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1495 if (extract_field (self
->fields
[0], code
, 0))
1496 info
->imm
.value
= 0x40000000;
1498 info
->imm
.value
= 0x3f000000;
1499 info
->imm
.is_fp
= TRUE
;
1503 /* Decode a single-bit immediate that selects between #0.0 and #1.0.
1504 The fields array specifies which field to use. */
1506 aarch64_ext_sve_float_zero_one (const aarch64_operand
*self
,
1507 aarch64_opnd_info
*info
, aarch64_insn code
,
1508 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1510 if (extract_field (self
->fields
[0], code
, 0))
1511 info
->imm
.value
= 0x3f800000;
1513 info
->imm
.value
= 0x0;
1514 info
->imm
.is_fp
= TRUE
;
1518 /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
1519 array specifies which field to use for Zn. MM is encoded in the
1520 concatenation of imm5 and SVE_tszh, with imm5 being the less
1521 significant part. */
1523 aarch64_ext_sve_index (const aarch64_operand
*self
,
1524 aarch64_opnd_info
*info
, aarch64_insn code
,
1525 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1529 info
->reglane
.regno
= extract_field (self
->fields
[0], code
, 0);
1530 val
= extract_fields (code
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1531 if ((val
& 15) == 0)
1533 while ((val
& 1) == 0)
1535 info
->reglane
.index
= val
/ 2;
1539 /* Decode a logical immediate for the MOV alias of SVE DUPM. */
1541 aarch64_ext_sve_limm_mov (const aarch64_operand
*self
,
1542 aarch64_opnd_info
*info
, const aarch64_insn code
,
1543 const aarch64_inst
*inst
)
1545 int esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1546 return (aarch64_ext_limm (self
, info
, code
, inst
)
1547 && aarch64_sve_dupm_mov_immediate_p (info
->imm
.value
, esize
));
1550 /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
1551 to use for Zn. The opcode-dependent value specifies the number
1552 of registers in the list. */
1554 aarch64_ext_sve_reglist (const aarch64_operand
*self
,
1555 aarch64_opnd_info
*info
, aarch64_insn code
,
1556 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1558 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
1559 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
1563 /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
1564 fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
1567 aarch64_ext_sve_scale (const aarch64_operand
*self
,
1568 aarch64_opnd_info
*info
, aarch64_insn code
,
1569 const aarch64_inst
*inst
)
1573 if (!aarch64_ext_imm (self
, info
, code
, inst
))
1575 val
= extract_field (FLD_SVE_imm4
, code
, 0);
1576 info
->shifter
.kind
= AARCH64_MOD_MUL
;
1577 info
->shifter
.amount
= val
+ 1;
1578 info
->shifter
.operator_present
= (val
!= 0);
1579 info
->shifter
.amount_present
= (val
!= 0);
1583 /* Return the top set bit in VALUE, which is expected to be relatively
1586 get_top_bit (uint64_t value
)
1588 while ((value
& -value
) != value
)
1589 value
-= value
& -value
;
1593 /* Decode an SVE shift-left immediate. */
1595 aarch64_ext_sve_shlimm (const aarch64_operand
*self
,
1596 aarch64_opnd_info
*info
, const aarch64_insn code
,
1597 const aarch64_inst
*inst
)
1599 if (!aarch64_ext_imm (self
, info
, code
, inst
)
1600 || info
->imm
.value
== 0)
1603 info
->imm
.value
-= get_top_bit (info
->imm
.value
);
1607 /* Decode an SVE shift-right immediate. */
1609 aarch64_ext_sve_shrimm (const aarch64_operand
*self
,
1610 aarch64_opnd_info
*info
, const aarch64_insn code
,
1611 const aarch64_inst
*inst
)
1613 if (!aarch64_ext_imm (self
, info
, code
, inst
)
1614 || info
->imm
.value
== 0)
1617 info
->imm
.value
= get_top_bit (info
->imm
.value
) * 2 - info
->imm
.value
;
1621 /* Bitfields that are commonly used to encode certain operands' information
1622 may be partially used as part of the base opcode in some instructions.
1623 For example, the bit 1 of the field 'size' in
1624 FCVTXN <Vb><d>, <Va><n>
1625 is actually part of the base opcode, while only size<0> is available
1626 for encoding the register type. Another example is the AdvSIMD
1627 instruction ORR (register), in which the field 'size' is also used for
1628 the base opcode, leaving only the field 'Q' available to encode the
1629 vector register arrangement specifier '8B' or '16B'.
1631 This function tries to deduce the qualifier from the value of partially
1632 constrained field(s). Given the VALUE of such a field or fields, the
1633 qualifiers CANDIDATES and the MASK (indicating which bits are valid for
1634 operand encoding), the function returns the matching qualifier or
1635 AARCH64_OPND_QLF_NIL if nothing matches.
1637 N.B. CANDIDATES is a group of possible qualifiers that are valid for
1638 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
1639 may end with AARCH64_OPND_QLF_NIL. */
1641 static enum aarch64_opnd_qualifier
1642 get_qualifier_from_partial_encoding (aarch64_insn value
,
1643 const enum aarch64_opnd_qualifier
* \
1648 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value
, (int)mask
);
1649 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1651 aarch64_insn standard_value
;
1652 if (candidates
[i
] == AARCH64_OPND_QLF_NIL
)
1654 standard_value
= aarch64_get_qualifier_standard_value (candidates
[i
]);
1655 if ((standard_value
& mask
) == (value
& mask
))
1656 return candidates
[i
];
1658 return AARCH64_OPND_QLF_NIL
;
1661 /* Given a list of qualifier sequences, return all possible valid qualifiers
1662 for operand IDX in QUALIFIERS.
1663 Assume QUALIFIERS is an array whose length is large enough. */
1666 get_operand_possible_qualifiers (int idx
,
1667 const aarch64_opnd_qualifier_seq_t
*list
,
1668 enum aarch64_opnd_qualifier
*qualifiers
)
1671 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1672 if ((qualifiers
[i
] = list
[i
][idx
]) == AARCH64_OPND_QLF_NIL
)
1676 /* Decode the size Q field for e.g. SHADD.
1677 We tag one operand with the qualifer according to the code;
1678 whether the qualifier is valid for this opcode or not, it is the
1679 duty of the semantic checking. */
1682 decode_sizeq (aarch64_inst
*inst
)
1685 enum aarch64_opnd_qualifier qualifier
;
1687 aarch64_insn value
, mask
;
1688 enum aarch64_field_kind fld_sz
;
1689 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1691 if (inst
->opcode
->iclass
== asisdlse
1692 || inst
->opcode
->iclass
== asisdlsep
1693 || inst
->opcode
->iclass
== asisdlso
1694 || inst
->opcode
->iclass
== asisdlsop
)
1695 fld_sz
= FLD_vldst_size
;
1700 value
= extract_fields (code
, inst
->opcode
->mask
, 2, fld_sz
, FLD_Q
);
1701 /* Obtain the info that which bits of fields Q and size are actually
1702 available for operand encoding. Opcodes like FMAXNM and FMLA have
1703 size[1] unavailable. */
1704 mask
= extract_fields (~inst
->opcode
->mask
, 0, 2, fld_sz
, FLD_Q
);
1706 /* The index of the operand we are going to tag a qualifier and the qualifer
1707 itself are reasoned from the value of the size and Q fields and the
1708 possible valid qualifier lists. */
1709 idx
= aarch64_select_operand_for_sizeq_field_coding (inst
->opcode
);
1710 DEBUG_TRACE ("key idx: %d", idx
);
1712 /* For most related instruciton, size:Q are fully available for operand
1716 inst
->operands
[idx
].qualifier
= get_vreg_qualifier_from_value (value
);
1720 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1722 #ifdef DEBUG_AARCH64
1726 for (i
= 0; candidates
[i
] != AARCH64_OPND_QLF_NIL
1727 && i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1728 DEBUG_TRACE ("qualifier %d: %s", i
,
1729 aarch64_get_qualifier_name(candidates
[i
]));
1730 DEBUG_TRACE ("%d, %d", (int)value
, (int)mask
);
1732 #endif /* DEBUG_AARCH64 */
1734 qualifier
= get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1736 if (qualifier
== AARCH64_OPND_QLF_NIL
)
1739 inst
->operands
[idx
].qualifier
= qualifier
;
1743 /* Decode size[0]:Q, i.e. bit 22 and bit 30, for
1744 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1747 decode_asimd_fcvt (aarch64_inst
*inst
)
1749 aarch64_field field
= {0, 0};
1751 enum aarch64_opnd_qualifier qualifier
;
1753 gen_sub_field (FLD_size
, 0, 1, &field
);
1754 value
= extract_field_2 (&field
, inst
->value
, 0);
1755 qualifier
= value
== 0 ? AARCH64_OPND_QLF_V_4S
1756 : AARCH64_OPND_QLF_V_2D
;
1757 switch (inst
->opcode
->op
)
1761 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1762 inst
->operands
[1].qualifier
= qualifier
;
1766 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
1767 inst
->operands
[0].qualifier
= qualifier
;
1777 /* Decode size[0], i.e. bit 22, for
1778 e.g. FCVTXN <Vb><d>, <Va><n>. */
1781 decode_asisd_fcvtxn (aarch64_inst
*inst
)
1783 aarch64_field field
= {0, 0};
1784 gen_sub_field (FLD_size
, 0, 1, &field
);
1785 if (!extract_field_2 (&field
, inst
->value
, 0))
1787 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_S_S
;
1791 /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
1793 decode_fcvt (aarch64_inst
*inst
)
1795 enum aarch64_opnd_qualifier qualifier
;
1797 const aarch64_field field
= {15, 2};
1800 value
= extract_field_2 (&field
, inst
->value
, 0);
1803 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
1804 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
1805 case 3: qualifier
= AARCH64_OPND_QLF_S_H
; break;
1808 inst
->operands
[0].qualifier
= qualifier
;
1813 /* Do miscellaneous decodings that are not common enough to be driven by
1817 do_misc_decoding (aarch64_inst
*inst
)
1820 switch (inst
->opcode
->op
)
1823 return decode_fcvt (inst
);
1829 return decode_asimd_fcvt (inst
);
1832 return decode_asisd_fcvtxn (inst
);
1836 value
= extract_field (FLD_SVE_Pn
, inst
->value
, 0);
1837 return (value
== extract_field (FLD_SVE_Pm
, inst
->value
, 0)
1838 && value
== extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
1841 return (extract_field (FLD_SVE_Zd
, inst
->value
, 0)
1842 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
1845 /* Index must be zero. */
1846 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1847 return value
== 1 || value
== 2 || value
== 4 || value
== 8;
1850 return (extract_field (FLD_SVE_Zn
, inst
->value
, 0)
1851 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
1854 /* Index must be nonzero. */
1855 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1856 return value
!= 1 && value
!= 2 && value
!= 4 && value
!= 8;
1859 return (extract_field (FLD_SVE_Pd
, inst
->value
, 0)
1860 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
1862 case OP_MOVZS_P_P_P
:
1864 return (extract_field (FLD_SVE_Pn
, inst
->value
, 0)
1865 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
1867 case OP_NOTS_P_P_P_Z
:
1868 case OP_NOT_P_P_P_Z
:
1869 return (extract_field (FLD_SVE_Pm
, inst
->value
, 0)
1870 == extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
1877 /* Opcodes that have fields shared by multiple operands are usually flagged
1878 with flags. In this function, we detect such flags, decode the related
1879 field(s) and store the information in one of the related operands. The
1880 'one' operand is not any operand but one of the operands that can
1881 accommadate all the information that has been decoded. */
1884 do_special_decoding (aarch64_inst
*inst
)
1888 /* Condition for truly conditional executed instructions, e.g. b.cond. */
1889 if (inst
->opcode
->flags
& F_COND
)
1891 value
= extract_field (FLD_cond2
, inst
->value
, 0);
1892 inst
->cond
= get_cond_from_value (value
);
1895 if (inst
->opcode
->flags
& F_SF
)
1897 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
1898 value
= extract_field (FLD_sf
, inst
->value
, 0);
1899 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1900 if ((inst
->opcode
->flags
& F_N
)
1901 && extract_field (FLD_N
, inst
->value
, 0) != value
)
1905 if (inst
->opcode
->flags
& F_LSE_SZ
)
1907 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
1908 value
= extract_field (FLD_lse_sz
, inst
->value
, 0);
1909 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1911 /* size:Q fields. */
1912 if (inst
->opcode
->flags
& F_SIZEQ
)
1913 return decode_sizeq (inst
);
1915 if (inst
->opcode
->flags
& F_FPTYPE
)
1917 idx
= select_operand_for_fptype_field_coding (inst
->opcode
);
1918 value
= extract_field (FLD_type
, inst
->value
, 0);
1921 case 0: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_S
; break;
1922 case 1: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_D
; break;
1923 case 3: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_H
; break;
1928 if (inst
->opcode
->flags
& F_SSIZE
)
1930 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
1931 of the base opcode. */
1933 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1934 idx
= select_operand_for_scalar_size_field_coding (inst
->opcode
);
1935 value
= extract_field (FLD_size
, inst
->value
, inst
->opcode
->mask
);
1936 mask
= extract_field (FLD_size
, ~inst
->opcode
->mask
, 0);
1937 /* For most related instruciton, the 'size' field is fully available for
1938 operand encoding. */
1940 inst
->operands
[idx
].qualifier
= get_sreg_qualifier_from_value (value
);
1943 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1945 inst
->operands
[idx
].qualifier
1946 = get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1950 if (inst
->opcode
->flags
& F_T
)
1952 /* Num of consecutive '0's on the right side of imm5<3:0>. */
1955 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1956 == AARCH64_OPND_CLASS_SIMD_REG
);
1967 val
= extract_field (FLD_imm5
, inst
->value
, 0);
1968 while ((val
& 0x1) == 0 && ++num
<= 3)
1972 Q
= (unsigned) extract_field (FLD_Q
, inst
->value
, inst
->opcode
->mask
);
1973 inst
->operands
[0].qualifier
=
1974 get_vreg_qualifier_from_value ((num
<< 1) | Q
);
1977 if (inst
->opcode
->flags
& F_GPRSIZE_IN_Q
)
1979 /* Use Rt to encode in the case of e.g.
1980 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1981 idx
= aarch64_operand_index (inst
->opcode
->operands
, AARCH64_OPND_Rt
);
1984 /* Otherwise use the result operand, which has to be a integer
1986 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1987 == AARCH64_OPND_CLASS_INT_REG
);
1990 assert (idx
== 0 || idx
== 1);
1991 value
= extract_field (FLD_Q
, inst
->value
, 0);
1992 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1995 if (inst
->opcode
->flags
& F_LDS_SIZE
)
1997 aarch64_field field
= {0, 0};
1998 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1999 == AARCH64_OPND_CLASS_INT_REG
);
2000 gen_sub_field (FLD_opc
, 0, 1, &field
);
2001 value
= extract_field_2 (&field
, inst
->value
, 0);
2002 inst
->operands
[0].qualifier
2003 = value
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2006 /* Miscellaneous decoding; done as the last step. */
2007 if (inst
->opcode
->flags
& F_MISC
)
2008 return do_misc_decoding (inst
);
2013 /* Converters converting a real opcode instruction to its alias form. */
2015 /* ROR <Wd>, <Ws>, #<shift>
2017 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
2019 convert_extr_to_ror (aarch64_inst
*inst
)
2021 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2023 copy_operand_info (inst
, 2, 3);
2024 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2030 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
2032 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
2034 convert_shll_to_xtl (aarch64_inst
*inst
)
2036 if (inst
->operands
[2].imm
.value
== 0)
2038 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2045 UBFM <Xd>, <Xn>, #<shift>, #63.
2047 LSR <Xd>, <Xn>, #<shift>. */
2049 convert_bfm_to_sr (aarch64_inst
*inst
)
2053 imms
= inst
->operands
[3].imm
.value
;
2054 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2057 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2064 /* Convert MOV to ORR. */
2066 convert_orr_to_mov (aarch64_inst
*inst
)
2068 /* MOV <Vd>.<T>, <Vn>.<T>
2070 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
2071 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2073 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2079 /* When <imms> >= <immr>, the instruction written:
2080 SBFX <Xd>, <Xn>, #<lsb>, #<width>
2082 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
2085 convert_bfm_to_bfx (aarch64_inst
*inst
)
2089 immr
= inst
->operands
[2].imm
.value
;
2090 imms
= inst
->operands
[3].imm
.value
;
2094 inst
->operands
[2].imm
.value
= lsb
;
2095 inst
->operands
[3].imm
.value
= imms
+ 1 - lsb
;
2096 /* The two opcodes have different qualifiers for
2097 the immediate operands; reset to help the checking. */
2098 reset_operand_qualifier (inst
, 2);
2099 reset_operand_qualifier (inst
, 3);
2106 /* When <imms> < <immr>, the instruction written:
2107 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
2109 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
2112 convert_bfm_to_bfi (aarch64_inst
*inst
)
2114 int64_t immr
, imms
, val
;
2116 immr
= inst
->operands
[2].imm
.value
;
2117 imms
= inst
->operands
[3].imm
.value
;
2118 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2121 inst
->operands
[2].imm
.value
= (val
- immr
) & (val
- 1);
2122 inst
->operands
[3].imm
.value
= imms
+ 1;
2123 /* The two opcodes have different qualifiers for
2124 the immediate operands; reset to help the checking. */
2125 reset_operand_qualifier (inst
, 2);
2126 reset_operand_qualifier (inst
, 3);
2133 /* The instruction written:
2134 BFC <Xd>, #<lsb>, #<width>
2136 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
2139 convert_bfm_to_bfc (aarch64_inst
*inst
)
2141 int64_t immr
, imms
, val
;
2143 /* Should have been assured by the base opcode value. */
2144 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2146 immr
= inst
->operands
[2].imm
.value
;
2147 imms
= inst
->operands
[3].imm
.value
;
2148 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2151 /* Drop XZR from the second operand. */
2152 copy_operand_info (inst
, 1, 2);
2153 copy_operand_info (inst
, 2, 3);
2154 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2156 /* Recalculate the immediates. */
2157 inst
->operands
[1].imm
.value
= (val
- immr
) & (val
- 1);
2158 inst
->operands
[2].imm
.value
= imms
+ 1;
2160 /* The two opcodes have different qualifiers for the operands; reset to
2161 help the checking. */
2162 reset_operand_qualifier (inst
, 1);
2163 reset_operand_qualifier (inst
, 2);
2164 reset_operand_qualifier (inst
, 3);
2172 /* The instruction written:
2173 LSL <Xd>, <Xn>, #<shift>
2175 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
2178 convert_ubfm_to_lsl (aarch64_inst
*inst
)
2180 int64_t immr
= inst
->operands
[2].imm
.value
;
2181 int64_t imms
= inst
->operands
[3].imm
.value
;
2183 = inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2185 if ((immr
== 0 && imms
== val
) || immr
== imms
+ 1)
2187 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2188 inst
->operands
[2].imm
.value
= val
- imms
;
2195 /* CINC <Wd>, <Wn>, <cond>
2197 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
2198 where <cond> is not AL or NV. */
2201 convert_from_csel (aarch64_inst
*inst
)
2203 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
2204 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2206 copy_operand_info (inst
, 2, 3);
2207 inst
->operands
[2].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2208 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2214 /* CSET <Wd>, <cond>
2216 CSINC <Wd>, WZR, WZR, invert(<cond>)
2217 where <cond> is not AL or NV. */
2220 convert_csinc_to_cset (aarch64_inst
*inst
)
2222 if (inst
->operands
[1].reg
.regno
== 0x1f
2223 && inst
->operands
[2].reg
.regno
== 0x1f
2224 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2226 copy_operand_info (inst
, 1, 3);
2227 inst
->operands
[1].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2228 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2229 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2237 MOVZ <Wd>, #<imm16>, LSL #<shift>.
2239 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2240 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2241 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2242 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2243 machine-instruction mnemonic must be used. */
2246 convert_movewide_to_mov (aarch64_inst
*inst
)
2248 uint64_t value
= inst
->operands
[1].imm
.value
;
2249 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
2250 if (value
== 0 && inst
->operands
[1].shifter
.amount
!= 0)
2252 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2253 inst
->operands
[1].shifter
.kind
= AARCH64_MOD_NONE
;
2254 value
<<= inst
->operands
[1].shifter
.amount
;
2255 /* As an alias convertor, it has to be clear that the INST->OPCODE
2256 is the opcode of the real instruction. */
2257 if (inst
->opcode
->op
== OP_MOVN
)
2259 int is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2261 /* A MOVN has an immediate that could be encoded by MOVZ. */
2262 if (aarch64_wide_constant_p (value
, is32
, NULL
) == TRUE
)
2265 inst
->operands
[1].imm
.value
= value
;
2266 inst
->operands
[1].shifter
.amount
= 0;
2272 ORR <Wd>, WZR, #<imm>.
2274 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2275 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2276 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2277 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2278 machine-instruction mnemonic must be used. */
2281 convert_movebitmask_to_mov (aarch64_inst
*inst
)
2286 /* Should have been assured by the base opcode value. */
2287 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2288 copy_operand_info (inst
, 1, 2);
2289 is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2290 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2291 value
= inst
->operands
[1].imm
.value
;
2292 /* ORR has an immediate that could be generated by a MOVZ or MOVN
2294 if (inst
->operands
[0].reg
.regno
!= 0x1f
2295 && (aarch64_wide_constant_p (value
, is32
, NULL
) == TRUE
2296 || aarch64_wide_constant_p (~value
, is32
, NULL
) == TRUE
))
2299 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2303 /* Some alias opcodes are disassembled by being converted from their real-form.
2304 N.B. INST->OPCODE is the real opcode rather than the alias. */
2307 convert_to_alias (aarch64_inst
*inst
, const aarch64_opcode
*alias
)
2313 return convert_bfm_to_sr (inst
);
2315 return convert_ubfm_to_lsl (inst
);
2319 return convert_from_csel (inst
);
2322 return convert_csinc_to_cset (inst
);
2326 return convert_bfm_to_bfx (inst
);
2330 return convert_bfm_to_bfi (inst
);
2332 return convert_bfm_to_bfc (inst
);
2334 return convert_orr_to_mov (inst
);
2335 case OP_MOV_IMM_WIDE
:
2336 case OP_MOV_IMM_WIDEN
:
2337 return convert_movewide_to_mov (inst
);
2338 case OP_MOV_IMM_LOG
:
2339 return convert_movebitmask_to_mov (inst
);
2341 return convert_extr_to_ror (inst
);
2346 return convert_shll_to_xtl (inst
);
2352 static int aarch64_opcode_decode (const aarch64_opcode
*, const aarch64_insn
,
2353 aarch64_inst
*, int);
2355 /* Given the instruction information in *INST, check if the instruction has
2356 any alias form that can be used to represent *INST. If the answer is yes,
2357 update *INST to be in the form of the determined alias. */
2359 /* In the opcode description table, the following flags are used in opcode
2360 entries to help establish the relations between the real and alias opcodes:
2362 F_ALIAS: opcode is an alias
2363 F_HAS_ALIAS: opcode has alias(es)
2366 F_P3: Disassembly preference priority 1-3 (the larger the
2367 higher). If nothing is specified, it is the priority
2368 0 by default, i.e. the lowest priority.
2370 Although the relation between the machine and the alias instructions are not
2371 explicitly described, it can be easily determined from the base opcode
2372 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
2373 description entries:
2375 The mask of an alias opcode must be equal to or a super-set (i.e. more
2376 constrained) of that of the aliased opcode; so is the base opcode value.
2378 if (opcode_has_alias (real) && alias_opcode_p (opcode)
2379 && (opcode->mask & real->mask) == real->mask
2380 && (real->mask & opcode->opcode) == (real->mask & real->opcode))
2381 then OPCODE is an alias of, and only of, the REAL instruction
2383 The alias relationship is forced flat-structured to keep related algorithm
2384 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
2386 During the disassembling, the decoding decision tree (in
2387 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
2388 if the decoding of such a machine instruction succeeds (and -Mno-aliases is
2389 not specified), the disassembler will check whether there is any alias
2390 instruction exists for this real instruction. If there is, the disassembler
2391 will try to disassemble the 32-bit binary again using the alias's rule, or
2392 try to convert the IR to the form of the alias. In the case of the multiple
2393 aliases, the aliases are tried one by one from the highest priority
2394 (currently the flag F_P3) to the lowest priority (no priority flag), and the
2395 first succeeds first adopted.
2397 You may ask why there is a need for the conversion of IR from one form to
2398 another in handling certain aliases. This is because on one hand it avoids
2399 adding more operand code to handle unusual encoding/decoding; on other
2400 hand, during the disassembling, the conversion is an effective approach to
2401 check the condition of an alias (as an alias may be adopted only if certain
2402 conditions are met).
2404 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
2405 aarch64_opcode_table and generated aarch64_find_alias_opcode and
2406 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
2409 determine_disassembling_preference (struct aarch64_inst
*inst
)
2411 const aarch64_opcode
*opcode
;
2412 const aarch64_opcode
*alias
;
2414 opcode
= inst
->opcode
;
2416 /* This opcode does not have an alias, so use itself. */
2417 if (opcode_has_alias (opcode
) == FALSE
)
2420 alias
= aarch64_find_alias_opcode (opcode
);
2423 #ifdef DEBUG_AARCH64
2426 const aarch64_opcode
*tmp
= alias
;
2427 printf ("#### LIST orderd: ");
2430 printf ("%s, ", tmp
->name
);
2431 tmp
= aarch64_find_next_alias_opcode (tmp
);
2435 #endif /* DEBUG_AARCH64 */
2437 for (; alias
; alias
= aarch64_find_next_alias_opcode (alias
))
2439 DEBUG_TRACE ("try %s", alias
->name
);
2440 assert (alias_opcode_p (alias
) || opcode_has_alias (opcode
));
2442 /* An alias can be a pseudo opcode which will never be used in the
2443 disassembly, e.g. BIC logical immediate is such a pseudo opcode
2445 if (pseudo_opcode_p (alias
))
2447 DEBUG_TRACE ("skip pseudo %s", alias
->name
);
2451 if ((inst
->value
& alias
->mask
) != alias
->opcode
)
2453 DEBUG_TRACE ("skip %s as base opcode not match", alias
->name
);
2456 /* No need to do any complicated transformation on operands, if the alias
2457 opcode does not have any operand. */
2458 if (aarch64_num_of_operands (alias
) == 0 && alias
->opcode
== inst
->value
)
2460 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias
->name
);
2461 aarch64_replace_opcode (inst
, alias
);
2464 if (alias
->flags
& F_CONV
)
2467 memcpy (©
, inst
, sizeof (aarch64_inst
));
2468 /* ALIAS is the preference as long as the instruction can be
2469 successfully converted to the form of ALIAS. */
2470 if (convert_to_alias (©
, alias
) == 1)
2472 aarch64_replace_opcode (©
, alias
);
2473 assert (aarch64_match_operands_constraint (©
, NULL
));
2474 DEBUG_TRACE ("succeed with %s via conversion", alias
->name
);
2475 memcpy (inst
, ©
, sizeof (aarch64_inst
));
2481 /* Directly decode the alias opcode. */
2483 memset (&temp
, '\0', sizeof (aarch64_inst
));
2484 if (aarch64_opcode_decode (alias
, inst
->value
, &temp
, 1) == 1)
2486 DEBUG_TRACE ("succeed with %s via direct decoding", alias
->name
);
2487 memcpy (inst
, &temp
, sizeof (aarch64_inst
));
2494 /* Some instructions (including all SVE ones) use the instruction class
2495 to describe how a qualifiers_list index is represented in the instruction
2496 encoding. If INST is such an instruction, decode the appropriate fields
2497 and fill in the operand qualifiers accordingly. Return true if no
2498 problems are found. */
2501 aarch64_decode_variant_using_iclass (aarch64_inst
*inst
)
2506 switch (inst
->opcode
->iclass
)
2509 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_14
);
2513 i
= extract_field (FLD_SVE_tsz
, inst
->value
, 0);
2516 while ((i
& 1) == 0)
2524 /* Pick the smallest applicable element size. */
2525 if ((inst
->value
& 0x20600) == 0x600)
2527 else if ((inst
->value
& 0x20400) == 0x400)
2529 else if ((inst
->value
& 0x20000) == 0)
2536 /* sve_misc instructions have only a single variant. */
2540 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_16
);
2544 variant
= extract_field (FLD_SVE_M_4
, inst
->value
, 0);
2547 case sve_shift_pred
:
2548 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_8
);
2559 case sve_shift_unpred
:
2560 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_19
);
2564 variant
= extract_field (FLD_size
, inst
->value
, 0);
2570 variant
= extract_field (FLD_size
, inst
->value
, 0);
2574 i
= extract_field (FLD_size
, inst
->value
, 0);
2581 variant
= extract_field (FLD_SVE_sz
, inst
->value
, 0);
2585 /* No mapping between instruction class and qualifiers. */
2589 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2590 inst
->operands
[i
].qualifier
= inst
->opcode
->qualifiers_list
[variant
][i
];
2593 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
2594 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
2597 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
2598 determined and used to disassemble CODE; this is done just before the
2602 aarch64_opcode_decode (const aarch64_opcode
*opcode
, const aarch64_insn code
,
2603 aarch64_inst
*inst
, int noaliases_p
)
2607 DEBUG_TRACE ("enter with %s", opcode
->name
);
2609 assert (opcode
&& inst
);
2611 /* Check the base opcode. */
2612 if ((code
& opcode
->mask
) != (opcode
->opcode
& opcode
->mask
))
2614 DEBUG_TRACE ("base opcode match FAIL");
2619 memset (inst
, '\0', sizeof (aarch64_inst
));
2621 inst
->opcode
= opcode
;
2624 /* Assign operand codes and indexes. */
2625 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2627 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
)
2629 inst
->operands
[i
].type
= opcode
->operands
[i
];
2630 inst
->operands
[i
].idx
= i
;
2633 /* Call the opcode decoder indicated by flags. */
2634 if (opcode_has_special_coder (opcode
) && do_special_decoding (inst
) == 0)
2636 DEBUG_TRACE ("opcode flag-based decoder FAIL");
2640 /* Possibly use the instruction class to determine the correct
2642 if (!aarch64_decode_variant_using_iclass (inst
))
2644 DEBUG_TRACE ("iclass-based decoder FAIL");
2648 /* Call operand decoders. */
2649 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2651 const aarch64_operand
*opnd
;
2652 enum aarch64_opnd type
;
2654 type
= opcode
->operands
[i
];
2655 if (type
== AARCH64_OPND_NIL
)
2657 opnd
= &aarch64_operands
[type
];
2658 if (operand_has_extractor (opnd
)
2659 && (! aarch64_extract_operand (opnd
, &inst
->operands
[i
], code
, inst
)))
2661 DEBUG_TRACE ("operand decoder FAIL at operand %d", i
);
2666 /* If the opcode has a verifier, then check it now. */
2667 if (opcode
->verifier
&& ! opcode
->verifier (opcode
, code
))
2669 DEBUG_TRACE ("operand verifier FAIL");
2673 /* Match the qualifiers. */
2674 if (aarch64_match_operands_constraint (inst
, NULL
) == 1)
2676 /* Arriving here, the CODE has been determined as a valid instruction
2677 of OPCODE and *INST has been filled with information of this OPCODE
2678 instruction. Before the return, check if the instruction has any
2679 alias and should be disassembled in the form of its alias instead.
2680 If the answer is yes, *INST will be updated. */
2682 determine_disassembling_preference (inst
);
2683 DEBUG_TRACE ("SUCCESS");
2688 DEBUG_TRACE ("constraint matching FAIL");
2695 /* This does some user-friendly fix-up to *INST. It is currently focus on
2696 the adjustment of qualifiers to help the printed instruction
2697 recognized/understood more easily. */
2700 user_friendly_fixup (aarch64_inst
*inst
)
2702 switch (inst
->opcode
->iclass
)
2705 /* TBNZ Xn|Wn, #uimm6, label
2706 Test and Branch Not Zero: conditionally jumps to label if bit number
2707 uimm6 in register Xn is not zero. The bit number implies the width of
2708 the register, which may be written and should be disassembled as Wn if
2709 uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
2711 if (inst
->operands
[1].imm
.value
< 32)
2712 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
2718 /* Decode INSN and fill in *INST the instruction information. An alias
2719 opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
2723 aarch64_decode_insn (aarch64_insn insn
, aarch64_inst
*inst
,
2724 bfd_boolean noaliases_p
)
2726 const aarch64_opcode
*opcode
= aarch64_opcode_lookup (insn
);
2728 #ifdef DEBUG_AARCH64
2731 const aarch64_opcode
*tmp
= opcode
;
2733 DEBUG_TRACE ("opcode lookup:");
2736 aarch64_verbose (" %s", tmp
->name
);
2737 tmp
= aarch64_find_next_opcode (tmp
);
2740 #endif /* DEBUG_AARCH64 */
2742 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
2743 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
2744 opcode field and value, apart from the difference that one of them has an
2745 extra field as part of the opcode, but such a field is used for operand
2746 encoding in other opcode(s) ('immh' in the case of the example). */
2747 while (opcode
!= NULL
)
2749 /* But only one opcode can be decoded successfully for, as the
2750 decoding routine will check the constraint carefully. */
2751 if (aarch64_opcode_decode (opcode
, insn
, inst
, noaliases_p
) == 1)
2753 opcode
= aarch64_find_next_opcode (opcode
);
2759 /* Print operands. */
2762 print_operands (bfd_vma pc
, const aarch64_opcode
*opcode
,
2763 const aarch64_opnd_info
*opnds
, struct disassemble_info
*info
)
2765 int i
, pcrel_p
, num_printed
;
2766 for (i
= 0, num_printed
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2769 /* We regard the opcode operand info more, however we also look into
2770 the inst->operands to support the disassembling of the optional
2772 The two operand code should be the same in all cases, apart from
2773 when the operand can be optional. */
2774 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
2775 || opnds
[i
].type
== AARCH64_OPND_NIL
)
2778 /* Generate the operand string in STR. */
2779 aarch64_print_operand (str
, sizeof (str
), pc
, opcode
, opnds
, i
, &pcrel_p
,
2782 /* Print the delimiter (taking account of omitted operand(s)). */
2784 (*info
->fprintf_func
) (info
->stream
, "%s",
2785 num_printed
++ == 0 ? "\t" : ", ");
2787 /* Print the operand. */
2789 (*info
->print_address_func
) (info
->target
, info
);
2791 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
2795 /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */
2798 remove_dot_suffix (char *name
, const aarch64_inst
*inst
)
2803 ptr
= strchr (inst
->opcode
->name
, '.');
2804 assert (ptr
&& inst
->cond
);
2805 len
= ptr
- inst
->opcode
->name
;
2807 strncpy (name
, inst
->opcode
->name
, len
);
2811 /* Print the instruction mnemonic name. */
2814 print_mnemonic_name (const aarch64_inst
*inst
, struct disassemble_info
*info
)
2816 if (inst
->opcode
->flags
& F_COND
)
2818 /* For instructions that are truly conditionally executed, e.g. b.cond,
2819 prepare the full mnemonic name with the corresponding condition
2823 remove_dot_suffix (name
, inst
);
2824 (*info
->fprintf_func
) (info
->stream
, "%s.%s", name
, inst
->cond
->names
[0]);
2827 (*info
->fprintf_func
) (info
->stream
, "%s", inst
->opcode
->name
);
2830 /* Decide whether we need to print a comment after the operands of
2831 instruction INST. */
2834 print_comment (const aarch64_inst
*inst
, struct disassemble_info
*info
)
2836 if (inst
->opcode
->flags
& F_COND
)
2839 unsigned int i
, num_conds
;
2841 remove_dot_suffix (name
, inst
);
2842 num_conds
= ARRAY_SIZE (inst
->cond
->names
);
2843 for (i
= 1; i
< num_conds
&& inst
->cond
->names
[i
]; ++i
)
2844 (*info
->fprintf_func
) (info
->stream
, "%s %s.%s",
2845 i
== 1 ? " //" : ",",
2846 name
, inst
->cond
->names
[i
]);
2850 /* Print the instruction according to *INST. */
2853 print_aarch64_insn (bfd_vma pc
, const aarch64_inst
*inst
,
2854 struct disassemble_info
*info
)
2856 print_mnemonic_name (inst
, info
);
2857 print_operands (pc
, inst
->opcode
, inst
->operands
, info
);
2858 print_comment (inst
, info
);
2861 /* Entry-point of the instruction disassembler and printer. */
2864 print_insn_aarch64_word (bfd_vma pc
,
2866 struct disassemble_info
*info
)
2868 static const char *err_msg
[6] =
2871 [-ERR_UND
] = "undefined",
2872 [-ERR_UNP
] = "unpredictable",
2879 info
->insn_info_valid
= 1;
2880 info
->branch_delay_insns
= 0;
2881 info
->data_size
= 0;
2885 if (info
->flags
& INSN_HAS_RELOC
)
2886 /* If the instruction has a reloc associated with it, then
2887 the offset field in the instruction will actually be the
2888 addend for the reloc. (If we are using REL type relocs).
2889 In such cases, we can ignore the pc when computing
2890 addresses, since the addend is not currently pc-relative. */
2893 ret
= aarch64_decode_insn (word
, &inst
, no_aliases
);
2895 if (((word
>> 21) & 0x3ff) == 1)
2897 /* RESERVED for ALES. */
2898 assert (ret
!= ERR_OK
);
2907 /* Handle undefined instructions. */
2908 info
->insn_type
= dis_noninsn
;
2909 (*info
->fprintf_func
) (info
->stream
,".inst\t0x%08x ; %s",
2910 word
, err_msg
[-ret
]);
2913 user_friendly_fixup (&inst
);
2914 print_aarch64_insn (pc
, &inst
, info
);
2921 /* Disallow mapping symbols ($x, $d etc) from
2922 being displayed in symbol relative addresses. */
2925 aarch64_symbol_is_valid (asymbol
* sym
,
2926 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
2933 name
= bfd_asymbol_name (sym
);
2937 || (name
[1] != 'x' && name
[1] != 'd')
2938 || (name
[2] != '\0' && name
[2] != '.'));
2941 /* Print data bytes on INFO->STREAM. */
2944 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
2946 struct disassemble_info
*info
)
2948 switch (info
->bytes_per_chunk
)
2951 info
->fprintf_func (info
->stream
, ".byte\t0x%02x", word
);
2954 info
->fprintf_func (info
->stream
, ".short\t0x%04x", word
);
2957 info
->fprintf_func (info
->stream
, ".word\t0x%08x", word
);
2964 /* Try to infer the code or data type from a symbol.
2965 Returns nonzero if *MAP_TYPE was set. */
2968 get_sym_code_type (struct disassemble_info
*info
, int n
,
2969 enum map_type
*map_type
)
2971 elf_symbol_type
*es
;
2975 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
2976 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
2978 /* If the symbol has function type then use that. */
2979 if (type
== STT_FUNC
)
2981 *map_type
= MAP_INSN
;
2985 /* Check for mapping symbols. */
2986 name
= bfd_asymbol_name(info
->symtab
[n
]);
2988 && (name
[1] == 'x' || name
[1] == 'd')
2989 && (name
[2] == '\0' || name
[2] == '.'))
2991 *map_type
= (name
[1] == 'x' ? MAP_INSN
: MAP_DATA
);
2998 /* Entry-point of the AArch64 disassembler. */
3001 print_insn_aarch64 (bfd_vma pc
,
3002 struct disassemble_info
*info
)
3004 bfd_byte buffer
[INSNLEN
];
3006 void (*printer
) (bfd_vma
, uint32_t, struct disassemble_info
*);
3007 bfd_boolean found
= FALSE
;
3008 unsigned int size
= 4;
3011 if (info
->disassembler_options
)
3013 set_default_aarch64_dis_options (info
);
3015 parse_aarch64_dis_options (info
->disassembler_options
);
3017 /* To avoid repeated parsing of these options, we remove them here. */
3018 info
->disassembler_options
= NULL
;
3021 /* Aarch64 instructions are always little-endian */
3022 info
->endian_code
= BFD_ENDIAN_LITTLE
;
3024 /* First check the full symtab for a mapping symbol, even if there
3025 are no usable non-mapping symbols for this address. */
3026 if (info
->symtab_size
!= 0
3027 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
3029 enum map_type type
= MAP_INSN
;
3034 if (pc
<= last_mapping_addr
)
3035 last_mapping_sym
= -1;
3037 /* Start scanning at the start of the function, or wherever
3038 we finished last time. */
3039 n
= info
->symtab_pos
+ 1;
3040 if (n
< last_mapping_sym
)
3041 n
= last_mapping_sym
;
3043 /* Scan up to the location being disassembled. */
3044 for (; n
< info
->symtab_size
; n
++)
3046 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3049 if ((info
->section
== NULL
3050 || info
->section
== info
->symtab
[n
]->section
)
3051 && get_sym_code_type (info
, n
, &type
))
3060 n
= info
->symtab_pos
;
3061 if (n
< last_mapping_sym
)
3062 n
= last_mapping_sym
;
3064 /* No mapping symbol found at this address. Look backwards
3065 for a preceeding one. */
3068 if (get_sym_code_type (info
, n
, &type
))
3077 last_mapping_sym
= last_sym
;
3080 /* Look a little bit ahead to see if we should print out
3081 less than four bytes of data. If there's a symbol,
3082 mapping or otherwise, after two bytes then don't
3084 if (last_type
== MAP_DATA
)
3086 size
= 4 - (pc
& 3);
3087 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
3089 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3092 if (addr
- pc
< size
)
3097 /* If the next symbol is after three bytes, we need to
3098 print only part of the data, so that we can use either
3101 size
= (pc
& 1) ? 1 : 2;
3105 if (last_type
== MAP_DATA
)
3107 /* size was set above. */
3108 info
->bytes_per_chunk
= size
;
3109 info
->display_endian
= info
->endian
;
3110 printer
= print_insn_data
;
3114 info
->bytes_per_chunk
= size
= INSNLEN
;
3115 info
->display_endian
= info
->endian_code
;
3116 printer
= print_insn_aarch64_word
;
3119 status
= (*info
->read_memory_func
) (pc
, buffer
, size
, info
);
3122 (*info
->memory_error_func
) (status
, pc
, info
);
3126 data
= bfd_get_bits (buffer
, size
* 8,
3127 info
->display_endian
== BFD_ENDIAN_BIG
);
3129 (*printer
) (pc
, data
, info
);
3135 print_aarch64_disassembler_options (FILE *stream
)
3137 fprintf (stream
, _("\n\
3138 The following AARCH64 specific disassembler options are supported for use\n\
3139 with the -M switch (multiple options should be separated by commas):\n"));
3141 fprintf (stream
, _("\n\
3142 no-aliases Don't print instruction aliases.\n"));
3144 fprintf (stream
, _("\n\
3145 aliases Do print instruction aliases.\n"));
3147 #ifdef DEBUG_AARCH64
3148 fprintf (stream
, _("\n\
3149 debug_dump Temp switch for debug trace.\n"));
3150 #endif /* DEBUG_AARCH64 */
3152 fprintf (stream
, _("\n"));