1 /* aarch64-dis.c -- AArch64 disassembler.
2 Copyright (C) 2009-2020 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
22 #include "bfd_stdint.h"
23 #include "disassemble.h"
24 #include "libiberty.h"
26 #include "aarch64-dis.h"
31 /* Cached mapping symbol state. */
38 static enum map_type last_type
;
39 static int last_mapping_sym
= -1;
40 static bfd_vma last_stop_offset
= 0;
41 static bfd_vma last_mapping_addr
= 0;
44 static int no_aliases
= 0; /* If set disassemble as most general inst. */
45 \fstatic int no_notes
= 1; /* If set do not print disassemble notes in the
46 output as comments. */
48 /* Currently active instruction sequence. */
49 static aarch64_instr_sequence insn_sequence
;
52 set_default_aarch64_dis_options (struct disassemble_info
*info ATTRIBUTE_UNUSED
)
57 parse_aarch64_dis_option (const char *option
, unsigned int len ATTRIBUTE_UNUSED
)
59 /* Try to match options that are simple flags */
60 if (CONST_STRNEQ (option
, "no-aliases"))
66 if (CONST_STRNEQ (option
, "aliases"))
72 if (CONST_STRNEQ (option
, "no-notes"))
78 if (CONST_STRNEQ (option
, "notes"))
85 if (CONST_STRNEQ (option
, "debug_dump"))
90 #endif /* DEBUG_AARCH64 */
93 opcodes_error_handler (_("unrecognised disassembler option: %s"), option
);
97 parse_aarch64_dis_options (const char *options
)
99 const char *option_end
;
104 while (*options
!= '\0')
106 /* Skip empty options. */
113 /* We know that *options is neither NUL or a comma. */
114 option_end
= options
+ 1;
115 while (*option_end
!= ',' && *option_end
!= '\0')
118 parse_aarch64_dis_option (options
, option_end
- options
);
120 /* Go on to the next one. If option_end points to a comma, it
121 will be skipped above. */
122 options
= option_end
;
126 /* Functions doing the instruction disassembling. */
128 /* The unnamed arguments consist of the number of fields and information about
129 these fields where the VALUE will be extracted from CODE and returned.
130 MASK can be zero or the base mask of the opcode.
132 N.B. the fields are required to be in such an order than the most signficant
133 field for VALUE comes the first, e.g. the <index> in
134 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
135 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
136 the order of H, L, M. */
139 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...)
142 const aarch64_field
*field
;
143 enum aarch64_field_kind kind
;
147 num
= va_arg (va
, uint32_t);
149 aarch64_insn value
= 0x0;
152 kind
= va_arg (va
, enum aarch64_field_kind
);
153 field
= &fields
[kind
];
154 value
<<= field
->width
;
155 value
|= extract_field (kind
, code
, mask
);
160 /* Extract the value of all fields in SELF->fields from instruction CODE.
161 The least significant bit comes from the final field. */
164 extract_all_fields (const aarch64_operand
*self
, aarch64_insn code
)
168 enum aarch64_field_kind kind
;
171 for (i
= 0; i
< ARRAY_SIZE (self
->fields
) && self
->fields
[i
] != FLD_NIL
; ++i
)
173 kind
= self
->fields
[i
];
174 value
<<= fields
[kind
].width
;
175 value
|= extract_field (kind
, code
, 0);
180 /* Sign-extend bit I of VALUE. */
181 static inline uint64_t
182 sign_extend (aarch64_insn value
, unsigned i
)
188 sign
= (uint64_t) 1 << i
;
189 return ((ret
& (sign
+ sign
- 1)) ^ sign
) - sign
;
192 /* N.B. the following inline helpfer functions create a dependency on the
193 order of operand qualifier enumerators. */
195 /* Given VALUE, return qualifier for a general purpose register. */
196 static inline enum aarch64_opnd_qualifier
197 get_greg_qualifier_from_value (aarch64_insn value
)
199 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_W
+ value
;
201 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
205 /* Given VALUE, return qualifier for a vector register. This does not support
206 decoding instructions that accept the 2H vector type. */
208 static inline enum aarch64_opnd_qualifier
209 get_vreg_qualifier_from_value (aarch64_insn value
)
211 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_V_8B
+ value
;
213 /* Instructions using vector type 2H should not call this function. Skip over
215 if (qualifier
>= AARCH64_OPND_QLF_V_2H
)
219 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
223 /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
224 static inline enum aarch64_opnd_qualifier
225 get_sreg_qualifier_from_value (aarch64_insn value
)
227 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_S_B
+ value
;
230 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
234 /* Given the instruction in *INST which is probably half way through the
235 decoding and our caller wants to know the expected qualifier for operand
236 I. Return such a qualifier if we can establish it; otherwise return
237 AARCH64_OPND_QLF_NIL. */
239 static aarch64_opnd_qualifier_t
240 get_expected_qualifier (const aarch64_inst
*inst
, int i
)
242 aarch64_opnd_qualifier_seq_t qualifiers
;
243 /* Should not be called if the qualifier is known. */
244 assert (inst
->operands
[i
].qualifier
== AARCH64_OPND_QLF_NIL
);
245 if (aarch64_find_best_match (inst
, inst
->opcode
->qualifiers_list
,
247 return qualifiers
[i
];
249 return AARCH64_OPND_QLF_NIL
;
252 /* Operand extractors. */
255 aarch64_ext_none (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
256 aarch64_opnd_info
*info ATTRIBUTE_UNUSED
,
257 const aarch64_insn code ATTRIBUTE_UNUSED
,
258 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
259 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
265 aarch64_ext_regno (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
266 const aarch64_insn code
,
267 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
268 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
270 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
275 aarch64_ext_regno_pair (const aarch64_operand
*self ATTRIBUTE_UNUSED
, aarch64_opnd_info
*info
,
276 const aarch64_insn code ATTRIBUTE_UNUSED
,
277 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
278 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
280 assert (info
->idx
== 1
282 info
->reg
.regno
= inst
->operands
[info
->idx
- 1].reg
.regno
+ 1;
286 /* e.g. IC <ic_op>{, <Xt>}. */
288 aarch64_ext_regrt_sysins (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
289 const aarch64_insn code
,
290 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
291 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
293 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
294 assert (info
->idx
== 1
295 && (aarch64_get_operand_class (inst
->operands
[0].type
)
296 == AARCH64_OPND_CLASS_SYSTEM
));
297 /* This will make the constraint checking happy and more importantly will
298 help the disassembler determine whether this operand is optional or
300 info
->present
= aarch64_sys_ins_reg_has_xt (inst
->operands
[0].sysins_op
);
305 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
307 aarch64_ext_reglane (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
308 const aarch64_insn code
,
309 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
310 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
313 info
->reglane
.regno
= extract_field (self
->fields
[0], code
,
316 /* Index and/or type. */
317 if (inst
->opcode
->iclass
== asisdone
318 || inst
->opcode
->iclass
== asimdins
)
320 if (info
->type
== AARCH64_OPND_En
321 && inst
->opcode
->operands
[0] == AARCH64_OPND_Ed
)
324 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
325 assert (info
->idx
== 1); /* Vn */
326 aarch64_insn value
= extract_field (FLD_imm4
, code
, 0);
327 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
328 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
329 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
330 info
->reglane
.index
= value
>> shift
;
334 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
342 aarch64_insn value
= extract_field (FLD_imm5
, code
, 0);
343 while (++pos
<= 3 && (value
& 0x1) == 0)
347 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
348 info
->reglane
.index
= (unsigned) (value
>> 1);
351 else if (inst
->opcode
->iclass
== dotproduct
)
353 /* Need information in other operand(s) to help decoding. */
354 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
355 switch (info
->qualifier
)
357 case AARCH64_OPND_QLF_S_4B
:
358 case AARCH64_OPND_QLF_S_2H
:
360 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
361 info
->reglane
.regno
&= 0x1f;
367 else if (inst
->opcode
->iclass
== cryptosm3
)
369 /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>]. */
370 info
->reglane
.index
= extract_field (FLD_SM3_imm2
, code
, 0);
374 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
375 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
377 /* Need information in other operand(s) to help decoding. */
378 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
379 switch (info
->qualifier
)
381 case AARCH64_OPND_QLF_S_H
:
382 if (info
->type
== AARCH64_OPND_Em16
)
385 info
->reglane
.index
= extract_fields (code
, 0, 3, FLD_H
, FLD_L
,
387 info
->reglane
.regno
&= 0xf;
392 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
395 case AARCH64_OPND_QLF_S_S
:
397 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
399 case AARCH64_OPND_QLF_S_D
:
401 info
->reglane
.index
= extract_field (FLD_H
, code
, 0);
407 if (inst
->opcode
->op
== OP_FCMLA_ELEM
408 && info
->qualifier
!= AARCH64_OPND_QLF_S_H
)
410 /* Complex operand takes two elements. */
411 if (info
->reglane
.index
& 1)
413 info
->reglane
.index
/= 2;
421 aarch64_ext_reglist (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
422 const aarch64_insn code
,
423 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
424 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
427 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
429 info
->reglist
.num_regs
= extract_field (FLD_len
, code
, 0) + 1;
433 /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
435 aarch64_ext_ldst_reglist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
436 aarch64_opnd_info
*info
, const aarch64_insn code
,
437 const aarch64_inst
*inst
,
438 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
441 /* Number of elements in each structure to be loaded/stored. */
442 unsigned expected_num
= get_opcode_dependent_value (inst
->opcode
);
446 unsigned is_reserved
;
448 unsigned num_elements
;
464 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
466 value
= extract_field (FLD_opcode
, code
, 0);
467 /* PR 21595: Check for a bogus value. */
468 if (value
>= ARRAY_SIZE (data
))
470 if (expected_num
!= data
[value
].num_elements
|| data
[value
].is_reserved
)
472 info
->reglist
.num_regs
= data
[value
].num_regs
;
477 /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
478 lanes instructions. */
480 aarch64_ext_ldst_reglist_r (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
481 aarch64_opnd_info
*info
, const aarch64_insn code
,
482 const aarch64_inst
*inst
,
483 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
488 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
490 value
= extract_field (FLD_S
, code
, 0);
492 /* Number of registers is equal to the number of elements in
493 each structure to be loaded/stored. */
494 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
495 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
497 /* Except when it is LD1R. */
498 if (info
->reglist
.num_regs
== 1 && value
== (aarch64_insn
) 1)
499 info
->reglist
.num_regs
= 2;
504 /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
505 load/store single element instructions. */
507 aarch64_ext_ldst_elemlist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
508 aarch64_opnd_info
*info
, const aarch64_insn code
,
509 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
510 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
512 aarch64_field field
= {0, 0};
513 aarch64_insn QSsize
; /* fields Q:S:size. */
514 aarch64_insn opcodeh2
; /* opcode<2:1> */
517 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
519 /* Decode the index, opcode<2:1> and size. */
520 gen_sub_field (FLD_asisdlso_opcode
, 1, 2, &field
);
521 opcodeh2
= extract_field_2 (&field
, code
, 0);
522 QSsize
= extract_fields (code
, 0, 3, FLD_Q
, FLD_S
, FLD_vldst_size
);
526 info
->qualifier
= AARCH64_OPND_QLF_S_B
;
527 /* Index encoded in "Q:S:size". */
528 info
->reglist
.index
= QSsize
;
534 info
->qualifier
= AARCH64_OPND_QLF_S_H
;
535 /* Index encoded in "Q:S:size<1>". */
536 info
->reglist
.index
= QSsize
>> 1;
539 if ((QSsize
>> 1) & 0x1)
542 if ((QSsize
& 0x1) == 0)
544 info
->qualifier
= AARCH64_OPND_QLF_S_S
;
545 /* Index encoded in "Q:S". */
546 info
->reglist
.index
= QSsize
>> 2;
550 if (extract_field (FLD_S
, code
, 0))
553 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
554 /* Index encoded in "Q". */
555 info
->reglist
.index
= QSsize
>> 3;
562 info
->reglist
.has_index
= 1;
563 info
->reglist
.num_regs
= 0;
564 /* Number of registers is equal to the number of elements in
565 each structure to be loaded/stored. */
566 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
567 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
572 /* Decode fields immh:immb and/or Q for e.g.
573 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
574 or SSHR <V><d>, <V><n>, #<shift>. */
577 aarch64_ext_advsimd_imm_shift (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
578 aarch64_opnd_info
*info
, const aarch64_insn code
,
579 const aarch64_inst
*inst
,
580 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
583 aarch64_insn Q
, imm
, immh
;
584 enum aarch64_insn_class iclass
= inst
->opcode
->iclass
;
586 immh
= extract_field (FLD_immh
, code
, 0);
589 imm
= extract_fields (code
, 0, 2, FLD_immh
, FLD_immb
);
591 /* Get highest set bit in immh. */
592 while (--pos
>= 0 && (immh
& 0x8) == 0)
595 assert ((iclass
== asimdshf
|| iclass
== asisdshf
)
596 && (info
->type
== AARCH64_OPND_IMM_VLSR
597 || info
->type
== AARCH64_OPND_IMM_VLSL
));
599 if (iclass
== asimdshf
)
601 Q
= extract_field (FLD_Q
, code
, 0);
603 0000 x SEE AdvSIMD modified immediate
613 get_vreg_qualifier_from_value ((pos
<< 1) | (int) Q
);
616 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
618 if (info
->type
== AARCH64_OPND_IMM_VLSR
)
620 0000 SEE AdvSIMD modified immediate
621 0001 (16-UInt(immh:immb))
622 001x (32-UInt(immh:immb))
623 01xx (64-UInt(immh:immb))
624 1xxx (128-UInt(immh:immb)) */
625 info
->imm
.value
= (16 << pos
) - imm
;
629 0000 SEE AdvSIMD modified immediate
630 0001 (UInt(immh:immb)-8)
631 001x (UInt(immh:immb)-16)
632 01xx (UInt(immh:immb)-32)
633 1xxx (UInt(immh:immb)-64) */
634 info
->imm
.value
= imm
- (8 << pos
);
639 /* Decode shift immediate for e.g. sshr (imm). */
641 aarch64_ext_shll_imm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
642 aarch64_opnd_info
*info
, const aarch64_insn code
,
643 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
644 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
648 val
= extract_field (FLD_size
, code
, 0);
651 case 0: imm
= 8; break;
652 case 1: imm
= 16; break;
653 case 2: imm
= 32; break;
654 default: return FALSE
;
656 info
->imm
.value
= imm
;
660 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
661 value in the field(s) will be extracted as unsigned immediate value. */
663 aarch64_ext_imm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
664 const aarch64_insn code
,
665 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
666 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
670 imm
= extract_all_fields (self
, code
);
672 if (operand_need_sign_extension (self
))
673 imm
= sign_extend (imm
, get_operand_fields_width (self
) - 1);
675 if (operand_need_shift_by_two (self
))
677 else if (operand_need_shift_by_four (self
))
680 if (info
->type
== AARCH64_OPND_ADDR_ADRP
)
683 info
->imm
.value
= imm
;
687 /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
689 aarch64_ext_imm_half (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
690 const aarch64_insn code
,
691 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
692 aarch64_operand_error
*errors
)
694 aarch64_ext_imm (self
, info
, code
, inst
, errors
);
695 info
->shifter
.kind
= AARCH64_MOD_LSL
;
696 info
->shifter
.amount
= extract_field (FLD_hw
, code
, 0) << 4;
700 /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
701 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
703 aarch64_ext_advsimd_imm_modified (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
704 aarch64_opnd_info
*info
,
705 const aarch64_insn code
,
706 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
707 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
710 enum aarch64_opnd_qualifier opnd0_qualifier
= inst
->operands
[0].qualifier
;
711 aarch64_field field
= {0, 0};
713 assert (info
->idx
== 1);
715 if (info
->type
== AARCH64_OPND_SIMD_FPIMM
)
718 /* a:b:c:d:e:f:g:h */
719 imm
= extract_fields (code
, 0, 2, FLD_abc
, FLD_defgh
);
720 if (!info
->imm
.is_fp
&& aarch64_get_qualifier_esize (opnd0_qualifier
) == 8)
722 /* Either MOVI <Dd>, #<imm>
723 or MOVI <Vd>.2D, #<imm>.
724 <imm> is a 64-bit immediate
725 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
726 encoded in "a:b:c:d:e:f:g:h". */
728 unsigned abcdefgh
= imm
;
729 for (imm
= 0ull, i
= 0; i
< 8; i
++)
730 if (((abcdefgh
>> i
) & 0x1) != 0)
731 imm
|= 0xffull
<< (8 * i
);
733 info
->imm
.value
= imm
;
736 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
737 switch (info
->qualifier
)
739 case AARCH64_OPND_QLF_NIL
:
741 info
->shifter
.kind
= AARCH64_MOD_NONE
;
743 case AARCH64_OPND_QLF_LSL
:
745 info
->shifter
.kind
= AARCH64_MOD_LSL
;
746 switch (aarch64_get_qualifier_esize (opnd0_qualifier
))
748 case 4: gen_sub_field (FLD_cmode
, 1, 2, &field
); break; /* per word */
749 case 2: gen_sub_field (FLD_cmode
, 1, 1, &field
); break; /* per half */
750 case 1: gen_sub_field (FLD_cmode
, 1, 0, &field
); break; /* per byte */
751 default: assert (0); return FALSE
;
753 /* 00: 0; 01: 8; 10:16; 11:24. */
754 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) << 3;
756 case AARCH64_OPND_QLF_MSL
:
758 info
->shifter
.kind
= AARCH64_MOD_MSL
;
759 gen_sub_field (FLD_cmode
, 0, 1, &field
); /* per word */
760 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) ? 16 : 8;
770 /* Decode an 8-bit floating-point immediate. */
772 aarch64_ext_fpimm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
773 const aarch64_insn code
,
774 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
775 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
777 info
->imm
.value
= extract_all_fields (self
, code
);
782 /* Decode a 1-bit rotate immediate (#90 or #270). */
784 aarch64_ext_imm_rotate1 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
785 const aarch64_insn code
,
786 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
787 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
789 uint64_t rot
= extract_field (self
->fields
[0], code
, 0);
791 info
->imm
.value
= rot
* 180 + 90;
795 /* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */
797 aarch64_ext_imm_rotate2 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
798 const aarch64_insn code
,
799 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
800 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
802 uint64_t rot
= extract_field (self
->fields
[0], code
, 0);
804 info
->imm
.value
= rot
* 90;
808 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
810 aarch64_ext_fbits (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
811 aarch64_opnd_info
*info
, const aarch64_insn code
,
812 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
813 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
815 info
->imm
.value
= 64- extract_field (FLD_scale
, code
, 0);
819 /* Decode arithmetic immediate for e.g.
820 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
822 aarch64_ext_aimm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
823 aarch64_opnd_info
*info
, const aarch64_insn code
,
824 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
825 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
829 info
->shifter
.kind
= AARCH64_MOD_LSL
;
831 value
= extract_field (FLD_shift
, code
, 0);
834 info
->shifter
.amount
= value
? 12 : 0;
835 /* imm12 (unsigned) */
836 info
->imm
.value
= extract_field (FLD_imm12
, code
, 0);
841 /* Return true if VALUE is a valid logical immediate encoding, storing the
842 decoded value in *RESULT if so. ESIZE is the number of bytes in the
843 decoded immediate. */
845 decode_limm (uint32_t esize
, aarch64_insn value
, int64_t *result
)
851 /* value is N:immr:imms. */
853 R
= (value
>> 6) & 0x3f;
854 N
= (value
>> 12) & 0x1;
856 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
857 (in other words, right rotated by R), then replicated. */
861 mask
= 0xffffffffffffffffull
;
867 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size
= 32; break;
868 case 0x20 ... 0x2f: /* 10xxxx */ simd_size
= 16; S
&= 0xf; break;
869 case 0x30 ... 0x37: /* 110xxx */ simd_size
= 8; S
&= 0x7; break;
870 case 0x38 ... 0x3b: /* 1110xx */ simd_size
= 4; S
&= 0x3; break;
871 case 0x3c ... 0x3d: /* 11110x */ simd_size
= 2; S
&= 0x1; break;
872 default: return FALSE
;
874 mask
= (1ull << simd_size
) - 1;
875 /* Top bits are IGNORED. */
879 if (simd_size
> esize
* 8)
882 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
883 if (S
== simd_size
- 1)
885 /* S+1 consecutive bits to 1. */
886 /* NOTE: S can't be 63 due to detection above. */
887 imm
= (1ull << (S
+ 1)) - 1;
888 /* Rotate to the left by simd_size - R. */
890 imm
= ((imm
<< (simd_size
- R
)) & mask
) | (imm
>> R
);
891 /* Replicate the value according to SIMD size. */
894 case 2: imm
= (imm
<< 2) | imm
;
896 case 4: imm
= (imm
<< 4) | imm
;
898 case 8: imm
= (imm
<< 8) | imm
;
900 case 16: imm
= (imm
<< 16) | imm
;
902 case 32: imm
= (imm
<< 32) | imm
;
905 default: assert (0); return 0;
908 *result
= imm
& ~((uint64_t) -1 << (esize
* 4) << (esize
* 4));
913 /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
915 aarch64_ext_limm (const aarch64_operand
*self
,
916 aarch64_opnd_info
*info
, const aarch64_insn code
,
917 const aarch64_inst
*inst
,
918 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
923 value
= extract_fields (code
, 0, 3, self
->fields
[0], self
->fields
[1],
925 esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
926 return decode_limm (esize
, value
, &info
->imm
.value
);
929 /* Decode a logical immediate for the BIC alias of AND (etc.). */
931 aarch64_ext_inv_limm (const aarch64_operand
*self
,
932 aarch64_opnd_info
*info
, const aarch64_insn code
,
933 const aarch64_inst
*inst
,
934 aarch64_operand_error
*errors
)
936 if (!aarch64_ext_limm (self
, info
, code
, inst
, errors
))
938 info
->imm
.value
= ~info
->imm
.value
;
942 /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
943 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
945 aarch64_ext_ft (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
946 aarch64_opnd_info
*info
,
947 const aarch64_insn code
, const aarch64_inst
*inst
,
948 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
953 info
->reg
.regno
= extract_field (FLD_Rt
, code
, 0);
956 value
= extract_field (FLD_ldst_size
, code
, 0);
957 if (inst
->opcode
->iclass
== ldstpair_indexed
958 || inst
->opcode
->iclass
== ldstnapair_offs
959 || inst
->opcode
->iclass
== ldstpair_off
960 || inst
->opcode
->iclass
== loadlit
)
962 enum aarch64_opnd_qualifier qualifier
;
965 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
966 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
967 case 2: qualifier
= AARCH64_OPND_QLF_S_Q
; break;
968 default: return FALSE
;
970 info
->qualifier
= qualifier
;
975 value
= extract_fields (code
, 0, 2, FLD_opc1
, FLD_ldst_size
);
978 info
->qualifier
= get_sreg_qualifier_from_value (value
);
984 /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
986 aarch64_ext_addr_simple (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
987 aarch64_opnd_info
*info
,
989 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
990 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
993 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
997 /* Decode the address operand for e.g.
998 stlur <Xt>, [<Xn|SP>{, <amount>}]. */
1000 aarch64_ext_addr_offset (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1001 aarch64_opnd_info
*info
,
1002 aarch64_insn code
, const aarch64_inst
*inst
,
1003 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1005 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1008 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1011 aarch64_insn imm
= extract_fields (code
, 0, 1, self
->fields
[1]);
1012 info
->addr
.offset
.imm
= sign_extend (imm
, 8);
1013 if (extract_field (self
->fields
[2], code
, 0) == 1) {
1014 info
->addr
.writeback
= 1;
1015 info
->addr
.preind
= 1;
1020 /* Decode the address operand for e.g.
1021 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1023 aarch64_ext_addr_regoff (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1024 aarch64_opnd_info
*info
,
1025 aarch64_insn code
, const aarch64_inst
*inst
,
1026 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1028 aarch64_insn S
, value
;
1031 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
1033 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
1035 value
= extract_field (FLD_option
, code
, 0);
1036 info
->shifter
.kind
=
1037 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
1038 /* Fix-up the shifter kind; although the table-driven approach is
1039 efficient, it is slightly inflexible, thus needing this fix-up. */
1040 if (info
->shifter
.kind
== AARCH64_MOD_UXTX
)
1041 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1043 S
= extract_field (FLD_S
, code
, 0);
1046 info
->shifter
.amount
= 0;
1047 info
->shifter
.amount_present
= 0;
1052 /* Need information in other operand(s) to help achieve the decoding
1054 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1055 /* Get the size of the data element that is accessed, which may be
1056 different from that of the source register size, e.g. in strb/ldrb. */
1057 size
= aarch64_get_qualifier_esize (info
->qualifier
);
1058 info
->shifter
.amount
= get_logsz (size
);
1059 info
->shifter
.amount_present
= 1;
1065 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
1067 aarch64_ext_addr_simm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1068 aarch64_insn code
, const aarch64_inst
*inst
,
1069 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1072 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1075 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
1076 /* simm (imm9 or imm7) */
1077 imm
= extract_field (self
->fields
[0], code
, 0);
1078 info
->addr
.offset
.imm
= sign_extend (imm
, fields
[self
->fields
[0]].width
- 1);
1079 if (self
->fields
[0] == FLD_imm7
1080 || info
->qualifier
== AARCH64_OPND_QLF_imm_tag
)
1081 /* scaled immediate in ld/st pair instructions. */
1082 info
->addr
.offset
.imm
*= aarch64_get_qualifier_esize (info
->qualifier
);
1084 if (inst
->opcode
->iclass
== ldst_unscaled
1085 || inst
->opcode
->iclass
== ldstnapair_offs
1086 || inst
->opcode
->iclass
== ldstpair_off
1087 || inst
->opcode
->iclass
== ldst_unpriv
)
1088 info
->addr
.writeback
= 0;
1091 /* pre/post- index */
1092 info
->addr
.writeback
= 1;
1093 if (extract_field (self
->fields
[1], code
, 0) == 1)
1094 info
->addr
.preind
= 1;
1096 info
->addr
.postind
= 1;
1102 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
1104 aarch64_ext_addr_uimm12 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1106 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1107 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1110 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1111 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
1113 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1115 info
->addr
.offset
.imm
= extract_field (self
->fields
[1], code
, 0) << shift
;
1119 /* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
1121 aarch64_ext_addr_simm10 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1123 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1124 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1128 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
1130 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1132 imm
= extract_fields (code
, 0, 2, self
->fields
[1], self
->fields
[2]);
1133 info
->addr
.offset
.imm
= sign_extend (imm
, 9) << 3;
1134 if (extract_field (self
->fields
[3], code
, 0) == 1) {
1135 info
->addr
.writeback
= 1;
1136 info
->addr
.preind
= 1;
1141 /* Decode the address operand for e.g.
1142 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
1144 aarch64_ext_simd_addr_post (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1145 aarch64_opnd_info
*info
,
1146 aarch64_insn code
, const aarch64_inst
*inst
,
1147 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1149 /* The opcode dependent area stores the number of elements in
1150 each structure to be loaded/stored. */
1151 int is_ld1r
= get_opcode_dependent_value (inst
->opcode
) == 1;
1154 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
1155 /* Rm | #<amount> */
1156 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
1157 if (info
->addr
.offset
.regno
== 31)
1159 if (inst
->opcode
->operands
[0] == AARCH64_OPND_LVt_AL
)
1160 /* Special handling of loading single structure to all lane. */
1161 info
->addr
.offset
.imm
= (is_ld1r
? 1
1162 : inst
->operands
[0].reglist
.num_regs
)
1163 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1165 info
->addr
.offset
.imm
= inst
->operands
[0].reglist
.num_regs
1166 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
)
1167 * aarch64_get_qualifier_nelem (inst
->operands
[0].qualifier
);
1170 info
->addr
.offset
.is_reg
= 1;
1171 info
->addr
.writeback
= 1;
1176 /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
1178 aarch64_ext_cond (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1179 aarch64_opnd_info
*info
,
1180 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1181 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1185 value
= extract_field (FLD_cond
, code
, 0);
1186 info
->cond
= get_cond_from_value (value
);
1190 /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
1192 aarch64_ext_sysreg (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1193 aarch64_opnd_info
*info
,
1195 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1196 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1198 /* op0:op1:CRn:CRm:op2 */
1199 info
->sysreg
.value
= extract_fields (code
, 0, 5, FLD_op0
, FLD_op1
, FLD_CRn
,
1201 info
->sysreg
.flags
= 0;
1203 /* If a system instruction, check which restrictions should be on the register
1204 value during decoding, these will be enforced then. */
1205 if (inst
->opcode
->iclass
== ic_system
)
1207 /* Check to see if it's read-only, else check if it's write only.
1208 if it's both or unspecified don't care. */
1209 if ((inst
->opcode
->flags
& (F_SYS_READ
| F_SYS_WRITE
)) == F_SYS_READ
)
1210 info
->sysreg
.flags
= F_REG_READ
;
1211 else if ((inst
->opcode
->flags
& (F_SYS_READ
| F_SYS_WRITE
))
1213 info
->sysreg
.flags
= F_REG_WRITE
;
1219 /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
1221 aarch64_ext_pstatefield (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1222 aarch64_opnd_info
*info
, aarch64_insn code
,
1223 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1224 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1228 info
->pstatefield
= extract_fields (code
, 0, 2, FLD_op1
, FLD_op2
);
1229 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
1230 if (aarch64_pstatefields
[i
].value
== (aarch64_insn
)info
->pstatefield
)
1232 /* Reserved value in <pstatefield>. */
1236 /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
1238 aarch64_ext_sysins_op (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1239 aarch64_opnd_info
*info
,
1241 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1242 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1246 const aarch64_sys_ins_reg
*sysins_ops
;
1247 /* op0:op1:CRn:CRm:op2 */
1248 value
= extract_fields (code
, 0, 5,
1249 FLD_op0
, FLD_op1
, FLD_CRn
,
1254 case AARCH64_OPND_SYSREG_AT
: sysins_ops
= aarch64_sys_regs_at
; break;
1255 case AARCH64_OPND_SYSREG_DC
: sysins_ops
= aarch64_sys_regs_dc
; break;
1256 case AARCH64_OPND_SYSREG_IC
: sysins_ops
= aarch64_sys_regs_ic
; break;
1257 case AARCH64_OPND_SYSREG_TLBI
: sysins_ops
= aarch64_sys_regs_tlbi
; break;
1258 case AARCH64_OPND_SYSREG_SR
:
1259 sysins_ops
= aarch64_sys_regs_sr
;
1260 /* Let's remove op2 for rctx. Refer to comments in the definition of
1261 aarch64_sys_regs_sr[]. */
1262 value
= value
& ~(0x7);
1264 default: assert (0); return FALSE
;
1267 for (i
= 0; sysins_ops
[i
].name
!= NULL
; ++i
)
1268 if (sysins_ops
[i
].value
== value
)
1270 info
->sysins_op
= sysins_ops
+ i
;
1271 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1272 info
->sysins_op
->name
,
1273 (unsigned)info
->sysins_op
->value
,
1274 aarch64_sys_ins_reg_has_xt (info
->sysins_op
), i
);
1281 /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
1284 aarch64_ext_barrier (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1285 aarch64_opnd_info
*info
,
1287 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1288 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1291 info
->barrier
= aarch64_barrier_options
+ extract_field (FLD_CRm
, code
, 0);
1295 /* Decode the prefetch operation option operand for e.g.
1296 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
1299 aarch64_ext_prfop (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1300 aarch64_opnd_info
*info
,
1301 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1302 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1305 info
->prfop
= aarch64_prfops
+ extract_field (FLD_Rt
, code
, 0);
1309 /* Decode the hint number for an alias taking an operand. Set info->hint_option
1310 to the matching name/value pair in aarch64_hint_options. */
1313 aarch64_ext_hint (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1314 aarch64_opnd_info
*info
,
1316 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1317 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1320 unsigned hint_number
;
1323 hint_number
= extract_fields (code
, 0, 2, FLD_CRm
, FLD_op2
);
1325 for (i
= 0; aarch64_hint_options
[i
].name
!= NULL
; i
++)
1327 if (hint_number
== HINT_VAL (aarch64_hint_options
[i
].value
))
1329 info
->hint_option
= &(aarch64_hint_options
[i
]);
1337 /* Decode the extended register operand for e.g.
1338 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1340 aarch64_ext_reg_extended (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1341 aarch64_opnd_info
*info
,
1343 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1344 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1349 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1351 value
= extract_field (FLD_option
, code
, 0);
1352 info
->shifter
.kind
=
1353 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
1355 info
->shifter
.amount
= extract_field (FLD_imm3
, code
, 0);
1357 /* This makes the constraint checking happy. */
1358 info
->shifter
.operator_present
= 1;
1360 /* Assume inst->operands[0].qualifier has been resolved. */
1361 assert (inst
->operands
[0].qualifier
!= AARCH64_OPND_QLF_NIL
);
1362 info
->qualifier
= AARCH64_OPND_QLF_W
;
1363 if (inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_X
1364 && (info
->shifter
.kind
== AARCH64_MOD_UXTX
1365 || info
->shifter
.kind
== AARCH64_MOD_SXTX
))
1366 info
->qualifier
= AARCH64_OPND_QLF_X
;
1371 /* Decode the shifted register operand for e.g.
1372 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
1374 aarch64_ext_reg_shifted (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1375 aarch64_opnd_info
*info
,
1377 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1378 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1383 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1385 value
= extract_field (FLD_shift
, code
, 0);
1386 info
->shifter
.kind
=
1387 aarch64_get_operand_modifier_from_value (value
, FALSE
/* extend_p */);
1388 if (info
->shifter
.kind
== AARCH64_MOD_ROR
1389 && inst
->opcode
->iclass
!= log_shift
)
1390 /* ROR is not available for the shifted register operand in arithmetic
1394 info
->shifter
.amount
= extract_field (FLD_imm6
, code
, 0);
1396 /* This makes the constraint checking happy. */
1397 info
->shifter
.operator_present
= 1;
1402 /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
1403 where <offset> is given by the OFFSET parameter and where <factor> is
1404 1 plus SELF's operand-dependent value. fields[0] specifies the field
1405 that holds <base>. */
1407 aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand
*self
,
1408 aarch64_opnd_info
*info
, aarch64_insn code
,
1411 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1412 info
->addr
.offset
.imm
= offset
* (1 + get_operand_specific_data (self
));
1413 info
->addr
.offset
.is_reg
= FALSE
;
1414 info
->addr
.writeback
= FALSE
;
1415 info
->addr
.preind
= TRUE
;
1417 info
->shifter
.kind
= AARCH64_MOD_MUL_VL
;
1418 info
->shifter
.amount
= 1;
1419 info
->shifter
.operator_present
= (info
->addr
.offset
.imm
!= 0);
1420 info
->shifter
.amount_present
= FALSE
;
1424 /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
1425 where <simm4> is a 4-bit signed value and where <factor> is 1 plus
1426 SELF's operand-dependent value. fields[0] specifies the field that
1427 holds <base>. <simm4> is encoded in the SVE_imm4 field. */
1429 aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand
*self
,
1430 aarch64_opnd_info
*info
, aarch64_insn code
,
1431 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1432 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1436 offset
= extract_field (FLD_SVE_imm4
, code
, 0);
1437 offset
= ((offset
+ 8) & 15) - 8;
1438 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1441 /* Decode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
1442 where <simm6> is a 6-bit signed value and where <factor> is 1 plus
1443 SELF's operand-dependent value. fields[0] specifies the field that
1444 holds <base>. <simm6> is encoded in the SVE_imm6 field. */
1446 aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand
*self
,
1447 aarch64_opnd_info
*info
, aarch64_insn code
,
1448 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1449 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1453 offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1454 offset
= (((offset
+ 32) & 63) - 32);
1455 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1458 /* Decode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
1459 where <simm9> is a 9-bit signed value and where <factor> is 1 plus
1460 SELF's operand-dependent value. fields[0] specifies the field that
1461 holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
1462 and imm3 fields, with imm3 being the less-significant part. */
1464 aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand
*self
,
1465 aarch64_opnd_info
*info
,
1467 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1468 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1472 offset
= extract_fields (code
, 0, 2, FLD_SVE_imm6
, FLD_imm3
);
1473 offset
= (((offset
+ 256) & 511) - 256);
1474 return aarch64_ext_sve_addr_reg_mul_vl (self
, info
, code
, offset
);
1477 /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
1478 is given by the OFFSET parameter and where <shift> is SELF's operand-
1479 dependent value. fields[0] specifies the base register field <base>. */
1481 aarch64_ext_sve_addr_reg_imm (const aarch64_operand
*self
,
1482 aarch64_opnd_info
*info
, aarch64_insn code
,
1485 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1486 info
->addr
.offset
.imm
= offset
* (1 << get_operand_specific_data (self
));
1487 info
->addr
.offset
.is_reg
= FALSE
;
1488 info
->addr
.writeback
= FALSE
;
1489 info
->addr
.preind
= TRUE
;
1490 info
->shifter
.operator_present
= FALSE
;
1491 info
->shifter
.amount_present
= FALSE
;
1495 /* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
1496 is a 4-bit signed number and where <shift> is SELF's operand-dependent
1497 value. fields[0] specifies the base register field. */
1499 aarch64_ext_sve_addr_ri_s4 (const aarch64_operand
*self
,
1500 aarch64_opnd_info
*info
, aarch64_insn code
,
1501 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1502 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1504 int offset
= sign_extend (extract_field (FLD_SVE_imm4
, code
, 0), 3);
1505 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1508 /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
1509 is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
1510 value. fields[0] specifies the base register field. */
1512 aarch64_ext_sve_addr_ri_u6 (const aarch64_operand
*self
,
1513 aarch64_opnd_info
*info
, aarch64_insn code
,
1514 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1515 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1517 int offset
= extract_field (FLD_SVE_imm6
, code
, 0);
1518 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1521 /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
1522 is SELF's operand-dependent value. fields[0] specifies the base
1523 register field and fields[1] specifies the offset register field. */
1525 aarch64_ext_sve_addr_rr_lsl (const aarch64_operand
*self
,
1526 aarch64_opnd_info
*info
, aarch64_insn code
,
1527 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1528 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1532 index_regno
= extract_field (self
->fields
[1], code
, 0);
1533 if (index_regno
== 31 && (self
->flags
& OPD_F_NO_ZR
) != 0)
1536 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1537 info
->addr
.offset
.regno
= index_regno
;
1538 info
->addr
.offset
.is_reg
= TRUE
;
1539 info
->addr
.writeback
= FALSE
;
1540 info
->addr
.preind
= TRUE
;
1541 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1542 info
->shifter
.amount
= get_operand_specific_data (self
);
1543 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1544 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1548 /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
1549 <shift> is SELF's operand-dependent value. fields[0] specifies the
1550 base register field, fields[1] specifies the offset register field and
1551 fields[2] is a single-bit field that selects SXTW over UXTW. */
1553 aarch64_ext_sve_addr_rz_xtw (const aarch64_operand
*self
,
1554 aarch64_opnd_info
*info
, aarch64_insn code
,
1555 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1556 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1558 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1559 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1560 info
->addr
.offset
.is_reg
= TRUE
;
1561 info
->addr
.writeback
= FALSE
;
1562 info
->addr
.preind
= TRUE
;
1563 if (extract_field (self
->fields
[2], code
, 0))
1564 info
->shifter
.kind
= AARCH64_MOD_SXTW
;
1566 info
->shifter
.kind
= AARCH64_MOD_UXTW
;
1567 info
->shifter
.amount
= get_operand_specific_data (self
);
1568 info
->shifter
.operator_present
= TRUE
;
1569 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1573 /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
1574 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
1575 fields[0] specifies the base register field. */
1577 aarch64_ext_sve_addr_zi_u5 (const aarch64_operand
*self
,
1578 aarch64_opnd_info
*info
, aarch64_insn code
,
1579 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1580 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1582 int offset
= extract_field (FLD_imm5
, code
, 0);
1583 return aarch64_ext_sve_addr_reg_imm (self
, info
, code
, offset
);
1586 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
1587 where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
1588 number. fields[0] specifies the base register field and fields[1]
1589 specifies the offset register field. */
1591 aarch64_ext_sve_addr_zz (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
1592 aarch64_insn code
, enum aarch64_modifier_kind kind
)
1594 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
1595 info
->addr
.offset
.regno
= extract_field (self
->fields
[1], code
, 0);
1596 info
->addr
.offset
.is_reg
= TRUE
;
1597 info
->addr
.writeback
= FALSE
;
1598 info
->addr
.preind
= TRUE
;
1599 info
->shifter
.kind
= kind
;
1600 info
->shifter
.amount
= extract_field (FLD_SVE_msz
, code
, 0);
1601 info
->shifter
.operator_present
= (kind
!= AARCH64_MOD_LSL
1602 || info
->shifter
.amount
!= 0);
1603 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1607 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
1608 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1609 field and fields[1] specifies the offset register field. */
1611 aarch64_ext_sve_addr_zz_lsl (const aarch64_operand
*self
,
1612 aarch64_opnd_info
*info
, aarch64_insn code
,
1613 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1614 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1616 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_LSL
);
1619 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
1620 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1621 field and fields[1] specifies the offset register field. */
1623 aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand
*self
,
1624 aarch64_opnd_info
*info
, aarch64_insn code
,
1625 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1626 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1628 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_SXTW
);
1631 /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
1632 <msz> is a 2-bit unsigned number. fields[0] specifies the base register
1633 field and fields[1] specifies the offset register field. */
1635 aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand
*self
,
1636 aarch64_opnd_info
*info
, aarch64_insn code
,
1637 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1638 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1640 return aarch64_ext_sve_addr_zz (self
, info
, code
, AARCH64_MOD_UXTW
);
1643 /* Finish decoding an SVE arithmetic immediate, given that INFO already
1644 has the raw field value and that the low 8 bits decode to VALUE. */
1646 decode_sve_aimm (aarch64_opnd_info
*info
, int64_t value
)
1648 info
->shifter
.kind
= AARCH64_MOD_LSL
;
1649 info
->shifter
.amount
= 0;
1650 if (info
->imm
.value
& 0x100)
1653 /* Decode 0x100 as #0, LSL #8. */
1654 info
->shifter
.amount
= 8;
1658 info
->shifter
.operator_present
= (info
->shifter
.amount
!= 0);
1659 info
->shifter
.amount_present
= (info
->shifter
.amount
!= 0);
1660 info
->imm
.value
= value
;
1664 /* Decode an SVE ADD/SUB immediate. */
1666 aarch64_ext_sve_aimm (const aarch64_operand
*self
,
1667 aarch64_opnd_info
*info
, const aarch64_insn code
,
1668 const aarch64_inst
*inst
,
1669 aarch64_operand_error
*errors
)
1671 return (aarch64_ext_imm (self
, info
, code
, inst
, errors
)
1672 && decode_sve_aimm (info
, (uint8_t) info
->imm
.value
));
1675 /* Decode an SVE CPY/DUP immediate. */
1677 aarch64_ext_sve_asimm (const aarch64_operand
*self
,
1678 aarch64_opnd_info
*info
, const aarch64_insn code
,
1679 const aarch64_inst
*inst
,
1680 aarch64_operand_error
*errors
)
1682 return (aarch64_ext_imm (self
, info
, code
, inst
, errors
)
1683 && decode_sve_aimm (info
, (int8_t) info
->imm
.value
));
1686 /* Decode a single-bit immediate that selects between #0.5 and #1.0.
1687 The fields array specifies which field to use. */
1689 aarch64_ext_sve_float_half_one (const aarch64_operand
*self
,
1690 aarch64_opnd_info
*info
, aarch64_insn code
,
1691 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1692 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1694 if (extract_field (self
->fields
[0], code
, 0))
1695 info
->imm
.value
= 0x3f800000;
1697 info
->imm
.value
= 0x3f000000;
1698 info
->imm
.is_fp
= TRUE
;
1702 /* Decode a single-bit immediate that selects between #0.5 and #2.0.
1703 The fields array specifies which field to use. */
1705 aarch64_ext_sve_float_half_two (const aarch64_operand
*self
,
1706 aarch64_opnd_info
*info
, aarch64_insn code
,
1707 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1708 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1710 if (extract_field (self
->fields
[0], code
, 0))
1711 info
->imm
.value
= 0x40000000;
1713 info
->imm
.value
= 0x3f000000;
1714 info
->imm
.is_fp
= TRUE
;
1718 /* Decode a single-bit immediate that selects between #0.0 and #1.0.
1719 The fields array specifies which field to use. */
1721 aarch64_ext_sve_float_zero_one (const aarch64_operand
*self
,
1722 aarch64_opnd_info
*info
, aarch64_insn code
,
1723 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1724 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1726 if (extract_field (self
->fields
[0], code
, 0))
1727 info
->imm
.value
= 0x3f800000;
1729 info
->imm
.value
= 0x0;
1730 info
->imm
.is_fp
= TRUE
;
1734 /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
1735 array specifies which field to use for Zn. MM is encoded in the
1736 concatenation of imm5 and SVE_tszh, with imm5 being the less
1737 significant part. */
1739 aarch64_ext_sve_index (const aarch64_operand
*self
,
1740 aarch64_opnd_info
*info
, aarch64_insn code
,
1741 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1742 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1746 info
->reglane
.regno
= extract_field (self
->fields
[0], code
, 0);
1747 val
= extract_fields (code
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
1748 if ((val
& 31) == 0)
1750 while ((val
& 1) == 0)
1752 info
->reglane
.index
= val
/ 2;
1756 /* Decode a logical immediate for the MOV alias of SVE DUPM. */
1758 aarch64_ext_sve_limm_mov (const aarch64_operand
*self
,
1759 aarch64_opnd_info
*info
, const aarch64_insn code
,
1760 const aarch64_inst
*inst
,
1761 aarch64_operand_error
*errors
)
1763 int esize
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
1764 return (aarch64_ext_limm (self
, info
, code
, inst
, errors
)
1765 && aarch64_sve_dupm_mov_immediate_p (info
->imm
.value
, esize
));
1768 /* Decode Zn[MM], where Zn occupies the least-significant part of the field
1769 and where MM occupies the most-significant part. The operand-dependent
1770 value specifies the number of bits in Zn. */
1772 aarch64_ext_sve_quad_index (const aarch64_operand
*self
,
1773 aarch64_opnd_info
*info
, aarch64_insn code
,
1774 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1775 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1777 unsigned int reg_bits
= get_operand_specific_data (self
);
1778 unsigned int val
= extract_all_fields (self
, code
);
1779 info
->reglane
.regno
= val
& ((1 << reg_bits
) - 1);
1780 info
->reglane
.index
= val
>> reg_bits
;
1784 /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
1785 to use for Zn. The opcode-dependent value specifies the number
1786 of registers in the list. */
1788 aarch64_ext_sve_reglist (const aarch64_operand
*self
,
1789 aarch64_opnd_info
*info
, aarch64_insn code
,
1790 const aarch64_inst
*inst ATTRIBUTE_UNUSED
,
1791 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
1793 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
1794 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
1798 /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
1799 fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
1802 aarch64_ext_sve_scale (const aarch64_operand
*self
,
1803 aarch64_opnd_info
*info
, aarch64_insn code
,
1804 const aarch64_inst
*inst
, aarch64_operand_error
*errors
)
1808 if (!aarch64_ext_imm (self
, info
, code
, inst
, errors
))
1810 val
= extract_field (FLD_SVE_imm4
, code
, 0);
1811 info
->shifter
.kind
= AARCH64_MOD_MUL
;
1812 info
->shifter
.amount
= val
+ 1;
1813 info
->shifter
.operator_present
= (val
!= 0);
1814 info
->shifter
.amount_present
= (val
!= 0);
1818 /* Return the top set bit in VALUE, which is expected to be relatively
1821 get_top_bit (uint64_t value
)
1823 while ((value
& -value
) != value
)
1824 value
-= value
& -value
;
1828 /* Decode an SVE shift-left immediate. */
1830 aarch64_ext_sve_shlimm (const aarch64_operand
*self
,
1831 aarch64_opnd_info
*info
, const aarch64_insn code
,
1832 const aarch64_inst
*inst
, aarch64_operand_error
*errors
)
1834 if (!aarch64_ext_imm (self
, info
, code
, inst
, errors
)
1835 || info
->imm
.value
== 0)
1838 info
->imm
.value
-= get_top_bit (info
->imm
.value
);
1842 /* Decode an SVE shift-right immediate. */
1844 aarch64_ext_sve_shrimm (const aarch64_operand
*self
,
1845 aarch64_opnd_info
*info
, const aarch64_insn code
,
1846 const aarch64_inst
*inst
, aarch64_operand_error
*errors
)
1848 if (!aarch64_ext_imm (self
, info
, code
, inst
, errors
)
1849 || info
->imm
.value
== 0)
1852 info
->imm
.value
= get_top_bit (info
->imm
.value
) * 2 - info
->imm
.value
;
1856 /* Bitfields that are commonly used to encode certain operands' information
1857 may be partially used as part of the base opcode in some instructions.
1858 For example, the bit 1 of the field 'size' in
1859 FCVTXN <Vb><d>, <Va><n>
1860 is actually part of the base opcode, while only size<0> is available
1861 for encoding the register type. Another example is the AdvSIMD
1862 instruction ORR (register), in which the field 'size' is also used for
1863 the base opcode, leaving only the field 'Q' available to encode the
1864 vector register arrangement specifier '8B' or '16B'.
1866 This function tries to deduce the qualifier from the value of partially
1867 constrained field(s). Given the VALUE of such a field or fields, the
1868 qualifiers CANDIDATES and the MASK (indicating which bits are valid for
1869 operand encoding), the function returns the matching qualifier or
1870 AARCH64_OPND_QLF_NIL if nothing matches.
1872 N.B. CANDIDATES is a group of possible qualifiers that are valid for
1873 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
1874 may end with AARCH64_OPND_QLF_NIL. */
1876 static enum aarch64_opnd_qualifier
1877 get_qualifier_from_partial_encoding (aarch64_insn value
,
1878 const enum aarch64_opnd_qualifier
* \
1883 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value
, (int)mask
);
1884 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1886 aarch64_insn standard_value
;
1887 if (candidates
[i
] == AARCH64_OPND_QLF_NIL
)
1889 standard_value
= aarch64_get_qualifier_standard_value (candidates
[i
]);
1890 if ((standard_value
& mask
) == (value
& mask
))
1891 return candidates
[i
];
1893 return AARCH64_OPND_QLF_NIL
;
1896 /* Given a list of qualifier sequences, return all possible valid qualifiers
1897 for operand IDX in QUALIFIERS.
1898 Assume QUALIFIERS is an array whose length is large enough. */
1901 get_operand_possible_qualifiers (int idx
,
1902 const aarch64_opnd_qualifier_seq_t
*list
,
1903 enum aarch64_opnd_qualifier
*qualifiers
)
1906 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1907 if ((qualifiers
[i
] = list
[i
][idx
]) == AARCH64_OPND_QLF_NIL
)
1911 /* Decode the size Q field for e.g. SHADD.
1912 We tag one operand with the qualifer according to the code;
1913 whether the qualifier is valid for this opcode or not, it is the
1914 duty of the semantic checking. */
1917 decode_sizeq (aarch64_inst
*inst
)
1920 enum aarch64_opnd_qualifier qualifier
;
1922 aarch64_insn value
, mask
;
1923 enum aarch64_field_kind fld_sz
;
1924 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1926 if (inst
->opcode
->iclass
== asisdlse
1927 || inst
->opcode
->iclass
== asisdlsep
1928 || inst
->opcode
->iclass
== asisdlso
1929 || inst
->opcode
->iclass
== asisdlsop
)
1930 fld_sz
= FLD_vldst_size
;
1935 value
= extract_fields (code
, inst
->opcode
->mask
, 2, fld_sz
, FLD_Q
);
1936 /* Obtain the info that which bits of fields Q and size are actually
1937 available for operand encoding. Opcodes like FMAXNM and FMLA have
1938 size[1] unavailable. */
1939 mask
= extract_fields (~inst
->opcode
->mask
, 0, 2, fld_sz
, FLD_Q
);
1941 /* The index of the operand we are going to tag a qualifier and the qualifer
1942 itself are reasoned from the value of the size and Q fields and the
1943 possible valid qualifier lists. */
1944 idx
= aarch64_select_operand_for_sizeq_field_coding (inst
->opcode
);
1945 DEBUG_TRACE ("key idx: %d", idx
);
1947 /* For most related instruciton, size:Q are fully available for operand
1951 inst
->operands
[idx
].qualifier
= get_vreg_qualifier_from_value (value
);
1955 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1957 #ifdef DEBUG_AARCH64
1961 for (i
= 0; candidates
[i
] != AARCH64_OPND_QLF_NIL
1962 && i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1963 DEBUG_TRACE ("qualifier %d: %s", i
,
1964 aarch64_get_qualifier_name(candidates
[i
]));
1965 DEBUG_TRACE ("%d, %d", (int)value
, (int)mask
);
1967 #endif /* DEBUG_AARCH64 */
1969 qualifier
= get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1971 if (qualifier
== AARCH64_OPND_QLF_NIL
)
1974 inst
->operands
[idx
].qualifier
= qualifier
;
1978 /* Decode size[0]:Q, i.e. bit 22 and bit 30, for
1979 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1982 decode_asimd_fcvt (aarch64_inst
*inst
)
1984 aarch64_field field
= {0, 0};
1986 enum aarch64_opnd_qualifier qualifier
;
1988 gen_sub_field (FLD_size
, 0, 1, &field
);
1989 value
= extract_field_2 (&field
, inst
->value
, 0);
1990 qualifier
= value
== 0 ? AARCH64_OPND_QLF_V_4S
1991 : AARCH64_OPND_QLF_V_2D
;
1992 switch (inst
->opcode
->op
)
1996 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1997 inst
->operands
[1].qualifier
= qualifier
;
2001 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
2002 inst
->operands
[0].qualifier
= qualifier
;
2012 /* Decode size[0], i.e. bit 22, for
2013 e.g. FCVTXN <Vb><d>, <Va><n>. */
2016 decode_asisd_fcvtxn (aarch64_inst
*inst
)
2018 aarch64_field field
= {0, 0};
2019 gen_sub_field (FLD_size
, 0, 1, &field
);
2020 if (!extract_field_2 (&field
, inst
->value
, 0))
2022 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_S_S
;
2026 /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
2028 decode_fcvt (aarch64_inst
*inst
)
2030 enum aarch64_opnd_qualifier qualifier
;
2032 const aarch64_field field
= {15, 2};
2035 value
= extract_field_2 (&field
, inst
->value
, 0);
2038 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
2039 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
2040 case 3: qualifier
= AARCH64_OPND_QLF_S_H
; break;
2043 inst
->operands
[0].qualifier
= qualifier
;
2048 /* Do miscellaneous decodings that are not common enough to be driven by
2052 do_misc_decoding (aarch64_inst
*inst
)
2055 switch (inst
->opcode
->op
)
2058 return decode_fcvt (inst
);
2064 return decode_asimd_fcvt (inst
);
2067 return decode_asisd_fcvtxn (inst
);
2071 value
= extract_field (FLD_SVE_Pn
, inst
->value
, 0);
2072 return (value
== extract_field (FLD_SVE_Pm
, inst
->value
, 0)
2073 && value
== extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
2076 return (extract_field (FLD_SVE_Zd
, inst
->value
, 0)
2077 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
2080 /* Index must be zero. */
2081 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
2082 return value
> 0 && value
<= 16 && value
== (value
& -value
);
2085 return (extract_field (FLD_SVE_Zn
, inst
->value
, 0)
2086 == extract_field (FLD_SVE_Zm_16
, inst
->value
, 0));
2089 /* Index must be nonzero. */
2090 value
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
2091 return value
> 0 && value
!= (value
& -value
);
2094 return (extract_field (FLD_SVE_Pd
, inst
->value
, 0)
2095 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
2097 case OP_MOVZS_P_P_P
:
2099 return (extract_field (FLD_SVE_Pn
, inst
->value
, 0)
2100 == extract_field (FLD_SVE_Pm
, inst
->value
, 0));
2102 case OP_NOTS_P_P_P_Z
:
2103 case OP_NOT_P_P_P_Z
:
2104 return (extract_field (FLD_SVE_Pm
, inst
->value
, 0)
2105 == extract_field (FLD_SVE_Pg4_10
, inst
->value
, 0));
2112 /* Opcodes that have fields shared by multiple operands are usually flagged
2113 with flags. In this function, we detect such flags, decode the related
2114 field(s) and store the information in one of the related operands. The
2115 'one' operand is not any operand but one of the operands that can
2116 accommadate all the information that has been decoded. */
2119 do_special_decoding (aarch64_inst
*inst
)
2123 /* Condition for truly conditional executed instructions, e.g. b.cond. */
2124 if (inst
->opcode
->flags
& F_COND
)
2126 value
= extract_field (FLD_cond2
, inst
->value
, 0);
2127 inst
->cond
= get_cond_from_value (value
);
2130 if (inst
->opcode
->flags
& F_SF
)
2132 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
2133 value
= extract_field (FLD_sf
, inst
->value
, 0);
2134 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
2135 if ((inst
->opcode
->flags
& F_N
)
2136 && extract_field (FLD_N
, inst
->value
, 0) != value
)
2140 if (inst
->opcode
->flags
& F_LSE_SZ
)
2142 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
2143 value
= extract_field (FLD_lse_sz
, inst
->value
, 0);
2144 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
2146 /* size:Q fields. */
2147 if (inst
->opcode
->flags
& F_SIZEQ
)
2148 return decode_sizeq (inst
);
2150 if (inst
->opcode
->flags
& F_FPTYPE
)
2152 idx
= select_operand_for_fptype_field_coding (inst
->opcode
);
2153 value
= extract_field (FLD_type
, inst
->value
, 0);
2156 case 0: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_S
; break;
2157 case 1: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_D
; break;
2158 case 3: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_H
; break;
2163 if (inst
->opcode
->flags
& F_SSIZE
)
2165 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
2166 of the base opcode. */
2168 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
2169 idx
= select_operand_for_scalar_size_field_coding (inst
->opcode
);
2170 value
= extract_field (FLD_size
, inst
->value
, inst
->opcode
->mask
);
2171 mask
= extract_field (FLD_size
, ~inst
->opcode
->mask
, 0);
2172 /* For most related instruciton, the 'size' field is fully available for
2173 operand encoding. */
2175 inst
->operands
[idx
].qualifier
= get_sreg_qualifier_from_value (value
);
2178 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
2180 inst
->operands
[idx
].qualifier
2181 = get_qualifier_from_partial_encoding (value
, candidates
, mask
);
2185 if (inst
->opcode
->flags
& F_T
)
2187 /* Num of consecutive '0's on the right side of imm5<3:0>. */
2190 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2191 == AARCH64_OPND_CLASS_SIMD_REG
);
2202 val
= extract_field (FLD_imm5
, inst
->value
, 0);
2203 while ((val
& 0x1) == 0 && ++num
<= 3)
2207 Q
= (unsigned) extract_field (FLD_Q
, inst
->value
, inst
->opcode
->mask
);
2208 inst
->operands
[0].qualifier
=
2209 get_vreg_qualifier_from_value ((num
<< 1) | Q
);
2212 if (inst
->opcode
->flags
& F_GPRSIZE_IN_Q
)
2214 /* Use Rt to encode in the case of e.g.
2215 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
2216 idx
= aarch64_operand_index (inst
->opcode
->operands
, AARCH64_OPND_Rt
);
2219 /* Otherwise use the result operand, which has to be a integer
2221 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2222 == AARCH64_OPND_CLASS_INT_REG
);
2225 assert (idx
== 0 || idx
== 1);
2226 value
= extract_field (FLD_Q
, inst
->value
, 0);
2227 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
2230 if (inst
->opcode
->flags
& F_LDS_SIZE
)
2232 aarch64_field field
= {0, 0};
2233 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
2234 == AARCH64_OPND_CLASS_INT_REG
);
2235 gen_sub_field (FLD_opc
, 0, 1, &field
);
2236 value
= extract_field_2 (&field
, inst
->value
, 0);
2237 inst
->operands
[0].qualifier
2238 = value
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
2241 /* Miscellaneous decoding; done as the last step. */
2242 if (inst
->opcode
->flags
& F_MISC
)
2243 return do_misc_decoding (inst
);
2248 /* Converters converting a real opcode instruction to its alias form. */
2250 /* ROR <Wd>, <Ws>, #<shift>
2252 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
2254 convert_extr_to_ror (aarch64_inst
*inst
)
2256 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2258 copy_operand_info (inst
, 2, 3);
2259 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2265 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
2267 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
2269 convert_shll_to_xtl (aarch64_inst
*inst
)
2271 if (inst
->operands
[2].imm
.value
== 0)
2273 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2280 UBFM <Xd>, <Xn>, #<shift>, #63.
2282 LSR <Xd>, <Xn>, #<shift>. */
2284 convert_bfm_to_sr (aarch64_inst
*inst
)
2288 imms
= inst
->operands
[3].imm
.value
;
2289 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2292 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2299 /* Convert MOV to ORR. */
2301 convert_orr_to_mov (aarch64_inst
*inst
)
2303 /* MOV <Vd>.<T>, <Vn>.<T>
2305 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
2306 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
2308 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2314 /* When <imms> >= <immr>, the instruction written:
2315 SBFX <Xd>, <Xn>, #<lsb>, #<width>
2317 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
2320 convert_bfm_to_bfx (aarch64_inst
*inst
)
2324 immr
= inst
->operands
[2].imm
.value
;
2325 imms
= inst
->operands
[3].imm
.value
;
2329 inst
->operands
[2].imm
.value
= lsb
;
2330 inst
->operands
[3].imm
.value
= imms
+ 1 - lsb
;
2331 /* The two opcodes have different qualifiers for
2332 the immediate operands; reset to help the checking. */
2333 reset_operand_qualifier (inst
, 2);
2334 reset_operand_qualifier (inst
, 3);
2341 /* When <imms> < <immr>, the instruction written:
2342 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
2344 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
2347 convert_bfm_to_bfi (aarch64_inst
*inst
)
2349 int64_t immr
, imms
, val
;
2351 immr
= inst
->operands
[2].imm
.value
;
2352 imms
= inst
->operands
[3].imm
.value
;
2353 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2356 inst
->operands
[2].imm
.value
= (val
- immr
) & (val
- 1);
2357 inst
->operands
[3].imm
.value
= imms
+ 1;
2358 /* The two opcodes have different qualifiers for
2359 the immediate operands; reset to help the checking. */
2360 reset_operand_qualifier (inst
, 2);
2361 reset_operand_qualifier (inst
, 3);
2368 /* The instruction written:
2369 BFC <Xd>, #<lsb>, #<width>
2371 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
2374 convert_bfm_to_bfc (aarch64_inst
*inst
)
2376 int64_t immr
, imms
, val
;
2378 /* Should have been assured by the base opcode value. */
2379 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2381 immr
= inst
->operands
[2].imm
.value
;
2382 imms
= inst
->operands
[3].imm
.value
;
2383 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
2386 /* Drop XZR from the second operand. */
2387 copy_operand_info (inst
, 1, 2);
2388 copy_operand_info (inst
, 2, 3);
2389 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2391 /* Recalculate the immediates. */
2392 inst
->operands
[1].imm
.value
= (val
- immr
) & (val
- 1);
2393 inst
->operands
[2].imm
.value
= imms
+ 1;
2395 /* The two opcodes have different qualifiers for the operands; reset to
2396 help the checking. */
2397 reset_operand_qualifier (inst
, 1);
2398 reset_operand_qualifier (inst
, 2);
2399 reset_operand_qualifier (inst
, 3);
2407 /* The instruction written:
2408 LSL <Xd>, <Xn>, #<shift>
2410 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
2413 convert_ubfm_to_lsl (aarch64_inst
*inst
)
2415 int64_t immr
= inst
->operands
[2].imm
.value
;
2416 int64_t imms
= inst
->operands
[3].imm
.value
;
2418 = inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
2420 if ((immr
== 0 && imms
== val
) || immr
== imms
+ 1)
2422 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2423 inst
->operands
[2].imm
.value
= val
- imms
;
2430 /* CINC <Wd>, <Wn>, <cond>
2432 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
2433 where <cond> is not AL or NV. */
2436 convert_from_csel (aarch64_inst
*inst
)
2438 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
2439 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2441 copy_operand_info (inst
, 2, 3);
2442 inst
->operands
[2].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2443 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2449 /* CSET <Wd>, <cond>
2451 CSINC <Wd>, WZR, WZR, invert(<cond>)
2452 where <cond> is not AL or NV. */
2455 convert_csinc_to_cset (aarch64_inst
*inst
)
2457 if (inst
->operands
[1].reg
.regno
== 0x1f
2458 && inst
->operands
[2].reg
.regno
== 0x1f
2459 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
2461 copy_operand_info (inst
, 1, 3);
2462 inst
->operands
[1].cond
= get_inverted_cond (inst
->operands
[3].cond
);
2463 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
2464 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2472 MOVZ <Wd>, #<imm16>, LSL #<shift>.
2474 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2475 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2476 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2477 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2478 machine-instruction mnemonic must be used. */
2481 convert_movewide_to_mov (aarch64_inst
*inst
)
2483 uint64_t value
= inst
->operands
[1].imm
.value
;
2484 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
2485 if (value
== 0 && inst
->operands
[1].shifter
.amount
!= 0)
2487 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2488 inst
->operands
[1].shifter
.kind
= AARCH64_MOD_NONE
;
2489 value
<<= inst
->operands
[1].shifter
.amount
;
2490 /* As an alias convertor, it has to be clear that the INST->OPCODE
2491 is the opcode of the real instruction. */
2492 if (inst
->opcode
->op
== OP_MOVN
)
2494 int is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2496 /* A MOVN has an immediate that could be encoded by MOVZ. */
2497 if (aarch64_wide_constant_p (value
, is32
, NULL
))
2500 inst
->operands
[1].imm
.value
= value
;
2501 inst
->operands
[1].shifter
.amount
= 0;
2507 ORR <Wd>, WZR, #<imm>.
2509 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
2510 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
2511 or where a MOVN has an immediate that could be encoded by MOVZ, or where
2512 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
2513 machine-instruction mnemonic must be used. */
2516 convert_movebitmask_to_mov (aarch64_inst
*inst
)
2521 /* Should have been assured by the base opcode value. */
2522 assert (inst
->operands
[1].reg
.regno
== 0x1f);
2523 copy_operand_info (inst
, 1, 2);
2524 is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
2525 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
2526 value
= inst
->operands
[1].imm
.value
;
2527 /* ORR has an immediate that could be generated by a MOVZ or MOVN
2529 if (inst
->operands
[0].reg
.regno
!= 0x1f
2530 && (aarch64_wide_constant_p (value
, is32
, NULL
)
2531 || aarch64_wide_constant_p (~value
, is32
, NULL
)))
2534 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
2538 /* Some alias opcodes are disassembled by being converted from their real-form.
2539 N.B. INST->OPCODE is the real opcode rather than the alias. */
2542 convert_to_alias (aarch64_inst
*inst
, const aarch64_opcode
*alias
)
2548 return convert_bfm_to_sr (inst
);
2550 return convert_ubfm_to_lsl (inst
);
2554 return convert_from_csel (inst
);
2557 return convert_csinc_to_cset (inst
);
2561 return convert_bfm_to_bfx (inst
);
2565 return convert_bfm_to_bfi (inst
);
2567 return convert_bfm_to_bfc (inst
);
2569 return convert_orr_to_mov (inst
);
2570 case OP_MOV_IMM_WIDE
:
2571 case OP_MOV_IMM_WIDEN
:
2572 return convert_movewide_to_mov (inst
);
2573 case OP_MOV_IMM_LOG
:
2574 return convert_movebitmask_to_mov (inst
);
2576 return convert_extr_to_ror (inst
);
2581 return convert_shll_to_xtl (inst
);
2588 aarch64_opcode_decode (const aarch64_opcode
*, const aarch64_insn
,
2589 aarch64_inst
*, int, aarch64_operand_error
*errors
);
2591 /* Given the instruction information in *INST, check if the instruction has
2592 any alias form that can be used to represent *INST. If the answer is yes,
2593 update *INST to be in the form of the determined alias. */
2595 /* In the opcode description table, the following flags are used in opcode
2596 entries to help establish the relations between the real and alias opcodes:
2598 F_ALIAS: opcode is an alias
2599 F_HAS_ALIAS: opcode has alias(es)
2602 F_P3: Disassembly preference priority 1-3 (the larger the
2603 higher). If nothing is specified, it is the priority
2604 0 by default, i.e. the lowest priority.
2606 Although the relation between the machine and the alias instructions are not
2607 explicitly described, it can be easily determined from the base opcode
2608 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
2609 description entries:
2611 The mask of an alias opcode must be equal to or a super-set (i.e. more
2612 constrained) of that of the aliased opcode; so is the base opcode value.
2614 if (opcode_has_alias (real) && alias_opcode_p (opcode)
2615 && (opcode->mask & real->mask) == real->mask
2616 && (real->mask & opcode->opcode) == (real->mask & real->opcode))
2617 then OPCODE is an alias of, and only of, the REAL instruction
2619 The alias relationship is forced flat-structured to keep related algorithm
2620 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
2622 During the disassembling, the decoding decision tree (in
2623 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
2624 if the decoding of such a machine instruction succeeds (and -Mno-aliases is
2625 not specified), the disassembler will check whether there is any alias
2626 instruction exists for this real instruction. If there is, the disassembler
2627 will try to disassemble the 32-bit binary again using the alias's rule, or
2628 try to convert the IR to the form of the alias. In the case of the multiple
2629 aliases, the aliases are tried one by one from the highest priority
2630 (currently the flag F_P3) to the lowest priority (no priority flag), and the
2631 first succeeds first adopted.
2633 You may ask why there is a need for the conversion of IR from one form to
2634 another in handling certain aliases. This is because on one hand it avoids
2635 adding more operand code to handle unusual encoding/decoding; on other
2636 hand, during the disassembling, the conversion is an effective approach to
2637 check the condition of an alias (as an alias may be adopted only if certain
2638 conditions are met).
2640 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
2641 aarch64_opcode_table and generated aarch64_find_alias_opcode and
2642 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
2645 determine_disassembling_preference (struct aarch64_inst
*inst
,
2646 aarch64_operand_error
*errors
)
2648 const aarch64_opcode
*opcode
;
2649 const aarch64_opcode
*alias
;
2651 opcode
= inst
->opcode
;
2653 /* This opcode does not have an alias, so use itself. */
2654 if (!opcode_has_alias (opcode
))
2657 alias
= aarch64_find_alias_opcode (opcode
);
2660 #ifdef DEBUG_AARCH64
2663 const aarch64_opcode
*tmp
= alias
;
2664 printf ("#### LIST orderd: ");
2667 printf ("%s, ", tmp
->name
);
2668 tmp
= aarch64_find_next_alias_opcode (tmp
);
2672 #endif /* DEBUG_AARCH64 */
2674 for (; alias
; alias
= aarch64_find_next_alias_opcode (alias
))
2676 DEBUG_TRACE ("try %s", alias
->name
);
2677 assert (alias_opcode_p (alias
) || opcode_has_alias (opcode
));
2679 /* An alias can be a pseudo opcode which will never be used in the
2680 disassembly, e.g. BIC logical immediate is such a pseudo opcode
2682 if (pseudo_opcode_p (alias
))
2684 DEBUG_TRACE ("skip pseudo %s", alias
->name
);
2688 if ((inst
->value
& alias
->mask
) != alias
->opcode
)
2690 DEBUG_TRACE ("skip %s as base opcode not match", alias
->name
);
2693 /* No need to do any complicated transformation on operands, if the alias
2694 opcode does not have any operand. */
2695 if (aarch64_num_of_operands (alias
) == 0 && alias
->opcode
== inst
->value
)
2697 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias
->name
);
2698 aarch64_replace_opcode (inst
, alias
);
2701 if (alias
->flags
& F_CONV
)
2704 memcpy (©
, inst
, sizeof (aarch64_inst
));
2705 /* ALIAS is the preference as long as the instruction can be
2706 successfully converted to the form of ALIAS. */
2707 if (convert_to_alias (©
, alias
) == 1)
2709 aarch64_replace_opcode (©
, alias
);
2710 assert (aarch64_match_operands_constraint (©
, NULL
));
2711 DEBUG_TRACE ("succeed with %s via conversion", alias
->name
);
2712 memcpy (inst
, ©
, sizeof (aarch64_inst
));
2718 /* Directly decode the alias opcode. */
2720 memset (&temp
, '\0', sizeof (aarch64_inst
));
2721 if (aarch64_opcode_decode (alias
, inst
->value
, &temp
, 1, errors
) == 1)
2723 DEBUG_TRACE ("succeed with %s via direct decoding", alias
->name
);
2724 memcpy (inst
, &temp
, sizeof (aarch64_inst
));
2731 /* Some instructions (including all SVE ones) use the instruction class
2732 to describe how a qualifiers_list index is represented in the instruction
2733 encoding. If INST is such an instruction, decode the appropriate fields
2734 and fill in the operand qualifiers accordingly. Return true if no
2735 problems are found. */
2738 aarch64_decode_variant_using_iclass (aarch64_inst
*inst
)
2743 switch (inst
->opcode
->iclass
)
2746 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_14
);
2750 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_imm5
);
2753 while ((i
& 1) == 0)
2761 /* Pick the smallest applicable element size. */
2762 if ((inst
->value
& 0x20600) == 0x600)
2764 else if ((inst
->value
& 0x20400) == 0x400)
2766 else if ((inst
->value
& 0x20000) == 0)
2773 /* sve_misc instructions have only a single variant. */
2777 variant
= extract_fields (inst
->value
, 0, 2, FLD_size
, FLD_SVE_M_16
);
2781 variant
= extract_field (FLD_SVE_M_4
, inst
->value
, 0);
2784 case sve_shift_pred
:
2785 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_8
);
2796 case sve_shift_unpred
:
2797 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_19
);
2801 variant
= extract_field (FLD_size
, inst
->value
, 0);
2807 variant
= extract_field (FLD_size
, inst
->value
, 0);
2811 i
= extract_field (FLD_size
, inst
->value
, 0);
2819 variant
= extract_field (FLD_SVE_sz
, inst
->value
, 0);
2823 variant
= extract_field (FLD_SVE_sz2
, inst
->value
, 0);
2827 i
= extract_field (FLD_SVE_size
, inst
->value
, 0);
2834 /* Ignore low bit of this field since that is set in the opcode for
2835 instructions of this iclass. */
2836 i
= (extract_field (FLD_size
, inst
->value
, 0) & 2);
2840 case sve_shift_tsz_bhsd
:
2841 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_tszh
, FLD_SVE_tszl_19
);
2851 case sve_size_tsz_bhs
:
2852 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_sz
, FLD_SVE_tszl_19
);
2864 case sve_shift_tsz_hsd
:
2865 i
= extract_fields (inst
->value
, 0, 2, FLD_SVE_sz
, FLD_SVE_tszl_19
);
2876 /* No mapping between instruction class and qualifiers. */
2880 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2881 inst
->operands
[i
].qualifier
= inst
->opcode
->qualifiers_list
[variant
][i
];
2884 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
2885 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
2888 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
2889 determined and used to disassemble CODE; this is done just before the
2893 aarch64_opcode_decode (const aarch64_opcode
*opcode
, const aarch64_insn code
,
2894 aarch64_inst
*inst
, int noaliases_p
,
2895 aarch64_operand_error
*errors
)
2899 DEBUG_TRACE ("enter with %s", opcode
->name
);
2901 assert (opcode
&& inst
);
2904 memset (inst
, '\0', sizeof (aarch64_inst
));
2906 /* Check the base opcode. */
2907 if ((code
& opcode
->mask
) != (opcode
->opcode
& opcode
->mask
))
2909 DEBUG_TRACE ("base opcode match FAIL");
2913 inst
->opcode
= opcode
;
2916 /* Assign operand codes and indexes. */
2917 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2919 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
)
2921 inst
->operands
[i
].type
= opcode
->operands
[i
];
2922 inst
->operands
[i
].idx
= i
;
2925 /* Call the opcode decoder indicated by flags. */
2926 if (opcode_has_special_coder (opcode
) && do_special_decoding (inst
) == 0)
2928 DEBUG_TRACE ("opcode flag-based decoder FAIL");
2932 /* Possibly use the instruction class to determine the correct
2934 if (!aarch64_decode_variant_using_iclass (inst
))
2936 DEBUG_TRACE ("iclass-based decoder FAIL");
2940 /* Call operand decoders. */
2941 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2943 const aarch64_operand
*opnd
;
2944 enum aarch64_opnd type
;
2946 type
= opcode
->operands
[i
];
2947 if (type
== AARCH64_OPND_NIL
)
2949 opnd
= &aarch64_operands
[type
];
2950 if (operand_has_extractor (opnd
)
2951 && (! aarch64_extract_operand (opnd
, &inst
->operands
[i
], code
, inst
,
2954 DEBUG_TRACE ("operand decoder FAIL at operand %d", i
);
2959 /* If the opcode has a verifier, then check it now. */
2960 if (opcode
->verifier
2961 && opcode
->verifier (inst
, code
, 0, FALSE
, errors
, NULL
) != ERR_OK
)
2963 DEBUG_TRACE ("operand verifier FAIL");
2967 /* Match the qualifiers. */
2968 if (aarch64_match_operands_constraint (inst
, NULL
) == 1)
2970 /* Arriving here, the CODE has been determined as a valid instruction
2971 of OPCODE and *INST has been filled with information of this OPCODE
2972 instruction. Before the return, check if the instruction has any
2973 alias and should be disassembled in the form of its alias instead.
2974 If the answer is yes, *INST will be updated. */
2976 determine_disassembling_preference (inst
, errors
);
2977 DEBUG_TRACE ("SUCCESS");
2982 DEBUG_TRACE ("constraint matching FAIL");
2989 /* This does some user-friendly fix-up to *INST. It is currently focus on
2990 the adjustment of qualifiers to help the printed instruction
2991 recognized/understood more easily. */
2994 user_friendly_fixup (aarch64_inst
*inst
)
2996 switch (inst
->opcode
->iclass
)
2999 /* TBNZ Xn|Wn, #uimm6, label
3000 Test and Branch Not Zero: conditionally jumps to label if bit number
3001 uimm6 in register Xn is not zero. The bit number implies the width of
3002 the register, which may be written and should be disassembled as Wn if
3003 uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
3005 if (inst
->operands
[1].imm
.value
< 32)
3006 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
3012 /* Decode INSN and fill in *INST the instruction information. An alias
3013 opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
3017 aarch64_decode_insn (aarch64_insn insn
, aarch64_inst
*inst
,
3018 bfd_boolean noaliases_p
,
3019 aarch64_operand_error
*errors
)
3021 const aarch64_opcode
*opcode
= aarch64_opcode_lookup (insn
);
3023 #ifdef DEBUG_AARCH64
3026 const aarch64_opcode
*tmp
= opcode
;
3028 DEBUG_TRACE ("opcode lookup:");
3031 aarch64_verbose (" %s", tmp
->name
);
3032 tmp
= aarch64_find_next_opcode (tmp
);
3035 #endif /* DEBUG_AARCH64 */
3037 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
3038 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
3039 opcode field and value, apart from the difference that one of them has an
3040 extra field as part of the opcode, but such a field is used for operand
3041 encoding in other opcode(s) ('immh' in the case of the example). */
3042 while (opcode
!= NULL
)
3044 /* But only one opcode can be decoded successfully for, as the
3045 decoding routine will check the constraint carefully. */
3046 if (aarch64_opcode_decode (opcode
, insn
, inst
, noaliases_p
, errors
) == 1)
3048 opcode
= aarch64_find_next_opcode (opcode
);
3054 /* Print operands. */
3057 print_operands (bfd_vma pc
, const aarch64_opcode
*opcode
,
3058 const aarch64_opnd_info
*opnds
, struct disassemble_info
*info
,
3059 bfd_boolean
*has_notes
)
3062 int i
, pcrel_p
, num_printed
;
3063 for (i
= 0, num_printed
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
3066 /* We regard the opcode operand info more, however we also look into
3067 the inst->operands to support the disassembling of the optional
3069 The two operand code should be the same in all cases, apart from
3070 when the operand can be optional. */
3071 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
3072 || opnds
[i
].type
== AARCH64_OPND_NIL
)
3075 /* Generate the operand string in STR. */
3076 aarch64_print_operand (str
, sizeof (str
), pc
, opcode
, opnds
, i
, &pcrel_p
,
3077 &info
->target
, ¬es
);
3079 /* Print the delimiter (taking account of omitted operand(s)). */
3081 (*info
->fprintf_func
) (info
->stream
, "%s",
3082 num_printed
++ == 0 ? "\t" : ", ");
3084 /* Print the operand. */
3086 (*info
->print_address_func
) (info
->target
, info
);
3088 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
3091 if (notes
&& !no_notes
)
3094 (*info
->fprintf_func
) (info
->stream
, " // note: %s", notes
);
3098 /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */
3101 remove_dot_suffix (char *name
, const aarch64_inst
*inst
)
3106 ptr
= strchr (inst
->opcode
->name
, '.');
3107 assert (ptr
&& inst
->cond
);
3108 len
= ptr
- inst
->opcode
->name
;
3110 strncpy (name
, inst
->opcode
->name
, len
);
3114 /* Print the instruction mnemonic name. */
3117 print_mnemonic_name (const aarch64_inst
*inst
, struct disassemble_info
*info
)
3119 if (inst
->opcode
->flags
& F_COND
)
3121 /* For instructions that are truly conditionally executed, e.g. b.cond,
3122 prepare the full mnemonic name with the corresponding condition
3126 remove_dot_suffix (name
, inst
);
3127 (*info
->fprintf_func
) (info
->stream
, "%s.%s", name
, inst
->cond
->names
[0]);
3130 (*info
->fprintf_func
) (info
->stream
, "%s", inst
->opcode
->name
);
3133 /* Decide whether we need to print a comment after the operands of
3134 instruction INST. */
3137 print_comment (const aarch64_inst
*inst
, struct disassemble_info
*info
)
3139 if (inst
->opcode
->flags
& F_COND
)
3142 unsigned int i
, num_conds
;
3144 remove_dot_suffix (name
, inst
);
3145 num_conds
= ARRAY_SIZE (inst
->cond
->names
);
3146 for (i
= 1; i
< num_conds
&& inst
->cond
->names
[i
]; ++i
)
3147 (*info
->fprintf_func
) (info
->stream
, "%s %s.%s",
3148 i
== 1 ? " //" : ",",
3149 name
, inst
->cond
->names
[i
]);
3153 /* Build notes from verifiers into a string for printing. */
3156 print_verifier_notes (aarch64_operand_error
*detail
,
3157 struct disassemble_info
*info
)
3162 /* The output of the verifier cannot be a fatal error, otherwise the assembly
3163 would not have succeeded. We can safely ignore these. */
3164 assert (detail
->non_fatal
);
3165 assert (detail
->error
);
3167 /* If there are multiple verifier messages, concat them up to 1k. */
3168 (*info
->fprintf_func
) (info
->stream
, " // note: %s", detail
->error
);
3169 if (detail
->index
>= 0)
3170 (*info
->fprintf_func
) (info
->stream
, " at operand %d", detail
->index
+ 1);
3173 /* Print the instruction according to *INST. */
3176 print_aarch64_insn (bfd_vma pc
, const aarch64_inst
*inst
,
3177 const aarch64_insn code
,
3178 struct disassemble_info
*info
,
3179 aarch64_operand_error
*mismatch_details
)
3181 bfd_boolean has_notes
= FALSE
;
3183 print_mnemonic_name (inst
, info
);
3184 print_operands (pc
, inst
->opcode
, inst
->operands
, info
, &has_notes
);
3185 print_comment (inst
, info
);
3187 /* We've already printed a note, not enough space to print more so exit.
3188 Usually notes shouldn't overlap so it shouldn't happen that we have a note
3189 from a register and instruction at the same time. */
3193 /* Always run constraint verifiers, this is needed because constraints need to
3194 maintain a global state regardless of whether the instruction has the flag
3196 enum err_type result
= verify_constraints (inst
, code
, pc
, FALSE
,
3197 mismatch_details
, &insn_sequence
);
3205 print_verifier_notes (mismatch_details
, info
);
3212 /* Entry-point of the instruction disassembler and printer. */
3215 print_insn_aarch64_word (bfd_vma pc
,
3217 struct disassemble_info
*info
,
3218 aarch64_operand_error
*errors
)
3220 static const char *err_msg
[ERR_NR_ENTRIES
+1] =
3223 [ERR_UND
] = "undefined",
3224 [ERR_UNP
] = "unpredictable",
3231 info
->insn_info_valid
= 1;
3232 info
->branch_delay_insns
= 0;
3233 info
->data_size
= 0;
3237 if (info
->flags
& INSN_HAS_RELOC
)
3238 /* If the instruction has a reloc associated with it, then
3239 the offset field in the instruction will actually be the
3240 addend for the reloc. (If we are using REL type relocs).
3241 In such cases, we can ignore the pc when computing
3242 addresses, since the addend is not currently pc-relative. */
3245 ret
= aarch64_decode_insn (word
, &inst
, no_aliases
, errors
);
3247 if (((word
>> 21) & 0x3ff) == 1)
3249 /* RESERVED for ALES. */
3250 assert (ret
!= ERR_OK
);
3259 /* Handle undefined instructions. */
3260 info
->insn_type
= dis_noninsn
;
3261 (*info
->fprintf_func
) (info
->stream
,".inst\t0x%08x ; %s",
3262 word
, err_msg
[ret
]);
3265 user_friendly_fixup (&inst
);
3266 print_aarch64_insn (pc
, &inst
, word
, info
, errors
);
3273 /* Disallow mapping symbols ($x, $d etc) from
3274 being displayed in symbol relative addresses. */
3277 aarch64_symbol_is_valid (asymbol
* sym
,
3278 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
3285 name
= bfd_asymbol_name (sym
);
3289 || (name
[1] != 'x' && name
[1] != 'd')
3290 || (name
[2] != '\0' && name
[2] != '.'));
3293 /* Print data bytes on INFO->STREAM. */
3296 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
3298 struct disassemble_info
*info
,
3299 aarch64_operand_error
*errors ATTRIBUTE_UNUSED
)
3301 switch (info
->bytes_per_chunk
)
3304 info
->fprintf_func (info
->stream
, ".byte\t0x%02x", word
);
3307 info
->fprintf_func (info
->stream
, ".short\t0x%04x", word
);
3310 info
->fprintf_func (info
->stream
, ".word\t0x%08x", word
);
3317 /* Try to infer the code or data type from a symbol.
3318 Returns nonzero if *MAP_TYPE was set. */
3321 get_sym_code_type (struct disassemble_info
*info
, int n
,
3322 enum map_type
*map_type
)
3324 elf_symbol_type
*es
;
3328 /* If the symbol is in a different section, ignore it. */
3329 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
3332 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
3333 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
3335 /* If the symbol has function type then use that. */
3336 if (type
== STT_FUNC
)
3338 *map_type
= MAP_INSN
;
3342 /* Check for mapping symbols. */
3343 name
= bfd_asymbol_name(info
->symtab
[n
]);
3345 && (name
[1] == 'x' || name
[1] == 'd')
3346 && (name
[2] == '\0' || name
[2] == '.'))
3348 *map_type
= (name
[1] == 'x' ? MAP_INSN
: MAP_DATA
);
3355 /* Entry-point of the AArch64 disassembler. */
3358 print_insn_aarch64 (bfd_vma pc
,
3359 struct disassemble_info
*info
)
3361 bfd_byte buffer
[INSNLEN
];
3363 void (*printer
) (bfd_vma
, uint32_t, struct disassemble_info
*,
3364 aarch64_operand_error
*);
3365 bfd_boolean found
= FALSE
;
3366 unsigned int size
= 4;
3368 aarch64_operand_error errors
;
3370 if (info
->disassembler_options
)
3372 set_default_aarch64_dis_options (info
);
3374 parse_aarch64_dis_options (info
->disassembler_options
);
3376 /* To avoid repeated parsing of these options, we remove them here. */
3377 info
->disassembler_options
= NULL
;
3380 /* Aarch64 instructions are always little-endian */
3381 info
->endian_code
= BFD_ENDIAN_LITTLE
;
3383 /* Default to DATA. A text section is required by the ABI to contain an
3384 INSN mapping symbol at the start. A data section has no such
3385 requirement, hence if no mapping symbol is found the section must
3386 contain only data. This however isn't very useful if the user has
3387 fully stripped the binaries. If this is the case use the section
3388 attributes to determine the default. If we have no section default to
3389 INSN as well, as we may be disassembling some raw bytes on a baremetal
3390 HEX file or similar. */
3391 enum map_type type
= MAP_DATA
;
3392 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
3395 /* First check the full symtab for a mapping symbol, even if there
3396 are no usable non-mapping symbols for this address. */
3397 if (info
->symtab_size
!= 0
3398 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
3401 bfd_vma addr
, section_vma
= 0;
3402 bfd_boolean can_use_search_opt_p
;
3405 if (pc
<= last_mapping_addr
)
3406 last_mapping_sym
= -1;
3408 /* Start scanning at the start of the function, or wherever
3409 we finished last time. */
3410 n
= info
->symtab_pos
+ 1;
3412 /* If the last stop offset is different from the current one it means we
3413 are disassembling a different glob of bytes. As such the optimization
3414 would not be safe and we should start over. */
3415 can_use_search_opt_p
= last_mapping_sym
>= 0
3416 && info
->stop_offset
== last_stop_offset
;
3418 if (n
>= last_mapping_sym
&& can_use_search_opt_p
)
3419 n
= last_mapping_sym
;
3421 /* Look down while we haven't passed the location being disassembled.
3422 The reason for this is that there's no defined order between a symbol
3423 and an mapping symbol that may be at the same address. We may have to
3424 look at least one position ahead. */
3425 for (; n
< info
->symtab_size
; n
++)
3427 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3430 if (get_sym_code_type (info
, n
, &type
))
3439 n
= info
->symtab_pos
;
3440 if (n
>= last_mapping_sym
&& can_use_search_opt_p
)
3441 n
= last_mapping_sym
;
3443 /* No mapping symbol found at this address. Look backwards
3444 for a preceeding one, but don't go pass the section start
3445 otherwise a data section with no mapping symbol can pick up
3446 a text mapping symbol of a preceeding section. The documentation
3447 says section can be NULL, in which case we will seek up all the
3450 section_vma
= info
->section
->vma
;
3454 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3455 if (addr
< section_vma
)
3458 if (get_sym_code_type (info
, n
, &type
))
3467 last_mapping_sym
= last_sym
;
3469 last_stop_offset
= info
->stop_offset
;
3471 /* Look a little bit ahead to see if we should print out
3472 less than four bytes of data. If there's a symbol,
3473 mapping or otherwise, after two bytes then don't
3475 if (last_type
== MAP_DATA
)
3477 size
= 4 - (pc
& 3);
3478 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
3480 addr
= bfd_asymbol_value (info
->symtab
[n
]);
3483 if (addr
- pc
< size
)
3488 /* If the next symbol is after three bytes, we need to
3489 print only part of the data, so that we can use either
3492 size
= (pc
& 1) ? 1 : 2;
3498 /* PR 10263: Disassemble data if requested to do so by the user. */
3499 if (last_type
== MAP_DATA
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
3501 /* size was set above. */
3502 info
->bytes_per_chunk
= size
;
3503 info
->display_endian
= info
->endian
;
3504 printer
= print_insn_data
;
3508 info
->bytes_per_chunk
= size
= INSNLEN
;
3509 info
->display_endian
= info
->endian_code
;
3510 printer
= print_insn_aarch64_word
;
3513 status
= (*info
->read_memory_func
) (pc
, buffer
, size
, info
);
3516 (*info
->memory_error_func
) (status
, pc
, info
);
3520 data
= bfd_get_bits (buffer
, size
* 8,
3521 info
->display_endian
== BFD_ENDIAN_BIG
);
3523 (*printer
) (pc
, data
, info
, &errors
);
3529 print_aarch64_disassembler_options (FILE *stream
)
3531 fprintf (stream
, _("\n\
3532 The following AARCH64 specific disassembler options are supported for use\n\
3533 with the -M switch (multiple options should be separated by commas):\n"));
3535 fprintf (stream
, _("\n\
3536 no-aliases Don't print instruction aliases.\n"));
3538 fprintf (stream
, _("\n\
3539 aliases Do print instruction aliases.\n"));
3541 fprintf (stream
, _("\n\
3542 no-notes Don't print instruction notes.\n"));
3544 fprintf (stream
, _("\n\
3545 notes Do print instruction notes.\n"));
3547 #ifdef DEBUG_AARCH64
3548 fprintf (stream
, _("\n\
3549 debug_dump Temp switch for debug trace.\n"));
3550 #endif /* DEBUG_AARCH64 */
3552 fprintf (stream
, _("\n"));