1 /* aarch64-dis.c -- AArch64 disassembler.
2 Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
22 #include "bfd_stdint.h"
24 #include "libiberty.h"
26 #include "aarch64-dis.h"
28 #if !defined(EMBEDDED_ENV)
29 #define SYMTAB_AVAILABLE 1
31 #include "elf/aarch64.h"
41 /* Cached mapping symbol state. */
48 static enum map_type last_type
;
49 static int last_mapping_sym
= -1;
50 static bfd_vma last_mapping_addr
= 0;
53 static int no_aliases
= 0; /* If set disassemble as most general inst. */
57 set_default_aarch64_dis_options (struct disassemble_info
*info ATTRIBUTE_UNUSED
)
62 parse_aarch64_dis_option (const char *option
, unsigned int len ATTRIBUTE_UNUSED
)
64 /* Try to match options that are simple flags */
65 if (CONST_STRNEQ (option
, "no-aliases"))
71 if (CONST_STRNEQ (option
, "aliases"))
78 if (CONST_STRNEQ (option
, "debug_dump"))
83 #endif /* DEBUG_AARCH64 */
86 fprintf (stderr
, _("Unrecognised disassembler option: %s\n"), option
);
90 parse_aarch64_dis_options (const char *options
)
92 const char *option_end
;
97 while (*options
!= '\0')
99 /* Skip empty options. */
106 /* We know that *options is neither NUL or a comma. */
107 option_end
= options
+ 1;
108 while (*option_end
!= ',' && *option_end
!= '\0')
111 parse_aarch64_dis_option (options
, option_end
- options
);
113 /* Go on to the next one. If option_end points to a comma, it
114 will be skipped above. */
115 options
= option_end
;
119 /* Functions doing the instruction disassembling. */
121 /* The unnamed arguments consist of the number of fields and information about
122 these fields where the VALUE will be extracted from CODE and returned.
123 MASK can be zero or the base mask of the opcode.
125 N.B. the fields are required to be in such an order than the most signficant
126 field for VALUE comes the first, e.g. the <index> in
127 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
128 is encoded in H:L:M in some cases, the the fields H:L:M should be passed in
129 the order of H, L, M. */
131 static inline aarch64_insn
132 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...)
135 const aarch64_field
*field
;
136 enum aarch64_field_kind kind
;
140 num
= va_arg (va
, uint32_t);
142 aarch64_insn value
= 0x0;
145 kind
= va_arg (va
, enum aarch64_field_kind
);
146 field
= &fields
[kind
];
147 value
<<= field
->width
;
148 value
|= extract_field (kind
, code
, mask
);
153 /* Sign-extend bit I of VALUE. */
154 static inline int32_t
155 sign_extend (aarch64_insn value
, unsigned i
)
157 uint32_t ret
= value
;
160 if ((value
>> i
) & 0x1)
162 uint32_t val
= (uint32_t)(-1) << i
;
165 return (int32_t) ret
;
168 /* N.B. the following inline helpfer functions create a dependency on the
169 order of operand qualifier enumerators. */
171 /* Given VALUE, return qualifier for a general purpose register. */
172 static inline enum aarch64_opnd_qualifier
173 get_greg_qualifier_from_value (aarch64_insn value
)
175 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_W
+ value
;
177 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
181 /* Given VALUE, return qualifier for a vector register. */
182 static inline enum aarch64_opnd_qualifier
183 get_vreg_qualifier_from_value (aarch64_insn value
)
185 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_V_8B
+ value
;
188 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
192 /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
193 static inline enum aarch64_opnd_qualifier
194 get_sreg_qualifier_from_value (aarch64_insn value
)
196 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_S_B
+ value
;
199 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
203 /* Given the instruction in *INST which is probably half way through the
204 decoding and our caller wants to know the expected qualifier for operand
205 I. Return such a qualifier if we can establish it; otherwise return
206 AARCH64_OPND_QLF_NIL. */
208 static aarch64_opnd_qualifier_t
209 get_expected_qualifier (const aarch64_inst
*inst
, int i
)
211 aarch64_opnd_qualifier_seq_t qualifiers
;
212 /* Should not be called if the qualifier is known. */
213 assert (inst
->operands
[i
].qualifier
== AARCH64_OPND_QLF_NIL
);
214 if (aarch64_find_best_match (inst
, inst
->opcode
->qualifiers_list
,
216 return qualifiers
[i
];
218 return AARCH64_OPND_QLF_NIL
;
221 /* Operand extractors. */
224 aarch64_ext_regno (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
225 const aarch64_insn code
,
226 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
228 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
232 /* e.g. IC <ic_op>{, <Xt>}. */
234 aarch64_ext_regrt_sysins (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
235 const aarch64_insn code
,
236 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
238 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
239 assert (info
->idx
== 1
240 && (aarch64_get_operand_class (inst
->operands
[0].type
)
241 == AARCH64_OPND_CLASS_SYSTEM
));
242 /* This will make the constraint checking happy and more importantly will
243 help the disassembler determine whether this operand is optional or
245 info
->present
= inst
->operands
[0].sysins_op
->has_xt
;
250 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
252 aarch64_ext_reglane (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
253 const aarch64_insn code
,
254 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
257 info
->reglane
.regno
= extract_field (self
->fields
[0], code
,
260 /* Index and/or type. */
261 if (inst
->opcode
->iclass
== asisdone
262 || inst
->opcode
->iclass
== asimdins
)
264 if (info
->type
== AARCH64_OPND_En
265 && inst
->opcode
->operands
[0] == AARCH64_OPND_Ed
)
268 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
269 assert (info
->idx
== 1); /* Vn */
270 aarch64_insn value
= extract_field (FLD_imm4
, code
, 0);
271 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
272 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
273 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
274 info
->reglane
.index
= value
>> shift
;
278 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
286 aarch64_insn value
= extract_field (FLD_imm5
, code
, 0);
287 while (++pos
<= 3 && (value
& 0x1) == 0)
291 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
292 info
->reglane
.index
= (unsigned) (value
>> 1);
297 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
298 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
300 /* Need information in other operand(s) to help decoding. */
301 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
302 switch (info
->qualifier
)
304 case AARCH64_OPND_QLF_S_H
:
306 info
->reglane
.index
= extract_fields (code
, 0, 3, FLD_H
, FLD_L
,
308 info
->reglane
.regno
&= 0xf;
310 case AARCH64_OPND_QLF_S_S
:
312 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
314 case AARCH64_OPND_QLF_S_D
:
316 info
->reglane
.index
= extract_field (FLD_H
, code
, 0);
327 aarch64_ext_reglist (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
328 const aarch64_insn code
,
329 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
332 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
334 info
->reglist
.num_regs
= extract_field (FLD_len
, code
, 0) + 1;
338 /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
340 aarch64_ext_ldst_reglist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
341 aarch64_opnd_info
*info
, const aarch64_insn code
,
342 const aarch64_inst
*inst
)
345 /* Number of elements in each structure to be loaded/stored. */
346 unsigned expected_num
= get_opcode_dependent_value (inst
->opcode
);
350 unsigned is_reserved
;
352 unsigned num_elements
;
368 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
370 value
= extract_field (FLD_opcode
, code
, 0);
371 if (expected_num
!= data
[value
].num_elements
|| data
[value
].is_reserved
)
373 info
->reglist
.num_regs
= data
[value
].num_regs
;
378 /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
379 lanes instructions. */
381 aarch64_ext_ldst_reglist_r (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
382 aarch64_opnd_info
*info
, const aarch64_insn code
,
383 const aarch64_inst
*inst
)
388 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
390 value
= extract_field (FLD_S
, code
, 0);
392 /* Number of registers is equal to the number of elements in
393 each structure to be loaded/stored. */
394 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
395 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
397 /* Except when it is LD1R. */
398 if (info
->reglist
.num_regs
== 1 && value
== (aarch64_insn
) 1)
399 info
->reglist
.num_regs
= 2;
404 /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
405 load/store single element instructions. */
407 aarch64_ext_ldst_elemlist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
408 aarch64_opnd_info
*info
, const aarch64_insn code
,
409 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
411 aarch64_field field
= {0, 0};
412 aarch64_insn QSsize
; /* fields Q:S:size. */
413 aarch64_insn opcodeh2
; /* opcode<2:1> */
416 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
418 /* Decode the index, opcode<2:1> and size. */
419 gen_sub_field (FLD_asisdlso_opcode
, 1, 2, &field
);
420 opcodeh2
= extract_field_2 (&field
, code
, 0);
421 QSsize
= extract_fields (code
, 0, 3, FLD_Q
, FLD_S
, FLD_vldst_size
);
425 info
->qualifier
= AARCH64_OPND_QLF_S_B
;
426 /* Index encoded in "Q:S:size". */
427 info
->reglist
.index
= QSsize
;
430 info
->qualifier
= AARCH64_OPND_QLF_S_H
;
431 /* Index encoded in "Q:S:size<1>". */
432 info
->reglist
.index
= QSsize
>> 1;
435 if ((QSsize
& 0x1) == 0)
437 info
->qualifier
= AARCH64_OPND_QLF_S_S
;
438 /* Index encoded in "Q:S". */
439 info
->reglist
.index
= QSsize
>> 2;
443 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
444 /* Index encoded in "Q". */
445 info
->reglist
.index
= QSsize
>> 3;
446 if (extract_field (FLD_S
, code
, 0))
455 info
->reglist
.has_index
= 1;
456 info
->reglist
.num_regs
= 0;
457 /* Number of registers is equal to the number of elements in
458 each structure to be loaded/stored. */
459 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
460 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
465 /* Decode fields immh:immb and/or Q for e.g.
466 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
467 or SSHR <V><d>, <V><n>, #<shift>. */
470 aarch64_ext_advsimd_imm_shift (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
471 aarch64_opnd_info
*info
, const aarch64_insn code
,
472 const aarch64_inst
*inst
)
475 aarch64_insn Q
, imm
, immh
;
476 enum aarch64_insn_class iclass
= inst
->opcode
->iclass
;
478 immh
= extract_field (FLD_immh
, code
, 0);
481 imm
= extract_fields (code
, 0, 2, FLD_immh
, FLD_immb
);
483 /* Get highest set bit in immh. */
484 while (--pos
>= 0 && (immh
& 0x8) == 0)
487 assert ((iclass
== asimdshf
|| iclass
== asisdshf
)
488 && (info
->type
== AARCH64_OPND_IMM_VLSR
489 || info
->type
== AARCH64_OPND_IMM_VLSL
));
491 if (iclass
== asimdshf
)
493 Q
= extract_field (FLD_Q
, code
, 0);
495 0000 x SEE AdvSIMD modified immediate
505 get_vreg_qualifier_from_value ((pos
<< 1) | (int) Q
);
508 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
510 if (info
->type
== AARCH64_OPND_IMM_VLSR
)
512 0000 SEE AdvSIMD modified immediate
513 0001 (16-UInt(immh:immb))
514 001x (32-UInt(immh:immb))
515 01xx (64-UInt(immh:immb))
516 1xxx (128-UInt(immh:immb)) */
517 info
->imm
.value
= (16 << pos
) - imm
;
521 0000 SEE AdvSIMD modified immediate
522 0001 (UInt(immh:immb)-8)
523 001x (UInt(immh:immb)-16)
524 01xx (UInt(immh:immb)-32)
525 1xxx (UInt(immh:immb)-64) */
526 info
->imm
.value
= imm
- (8 << pos
);
531 /* Decode shift immediate for e.g. sshr (imm). */
533 aarch64_ext_shll_imm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
534 aarch64_opnd_info
*info
, const aarch64_insn code
,
535 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
539 val
= extract_field (FLD_size
, code
, 0);
542 case 0: imm
= 8; break;
543 case 1: imm
= 16; break;
544 case 2: imm
= 32; break;
547 info
->imm
.value
= imm
;
551 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
552 value in the field(s) will be extracted as unsigned immediate value. */
554 aarch64_ext_imm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
555 const aarch64_insn code
,
556 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
559 /* Maximum of two fields to extract. */
560 assert (self
->fields
[2] == FLD_NIL
);
562 if (self
->fields
[1] == FLD_NIL
)
563 imm
= extract_field (self
->fields
[0], code
, 0);
565 /* e.g. TBZ b5:b40. */
566 imm
= extract_fields (code
, 0, 2, self
->fields
[0], self
->fields
[1]);
568 if (info
->type
== AARCH64_OPND_FPIMM
)
571 if (operand_need_sign_extension (self
))
572 imm
= sign_extend (imm
, get_operand_fields_width (self
) - 1);
574 if (operand_need_shift_by_two (self
))
577 if (info
->type
== AARCH64_OPND_ADDR_ADRP
)
580 info
->imm
.value
= imm
;
584 /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
586 aarch64_ext_imm_half (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
587 const aarch64_insn code
,
588 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
590 aarch64_ext_imm (self
, info
, code
, inst
);
591 info
->shifter
.kind
= AARCH64_MOD_LSL
;
592 info
->shifter
.amount
= extract_field (FLD_hw
, code
, 0) << 4;
596 /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
597 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
599 aarch64_ext_advsimd_imm_modified (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
600 aarch64_opnd_info
*info
,
601 const aarch64_insn code
,
602 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
605 enum aarch64_opnd_qualifier opnd0_qualifier
= inst
->operands
[0].qualifier
;
606 aarch64_field field
= {0, 0};
608 assert (info
->idx
== 1);
610 if (info
->type
== AARCH64_OPND_SIMD_FPIMM
)
613 /* a:b:c:d:e:f:g:h */
614 imm
= extract_fields (code
, 0, 2, FLD_abc
, FLD_defgh
);
615 if (!info
->imm
.is_fp
&& aarch64_get_qualifier_esize (opnd0_qualifier
) == 8)
617 /* Either MOVI <Dd>, #<imm>
618 or MOVI <Vd>.2D, #<imm>.
619 <imm> is a 64-bit immediate
620 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
621 encoded in "a:b:c:d:e:f:g:h". */
623 unsigned abcdefgh
= imm
;
624 for (imm
= 0ull, i
= 0; i
< 8; i
++)
625 if (((abcdefgh
>> i
) & 0x1) != 0)
626 imm
|= 0xffull
<< (8 * i
);
628 info
->imm
.value
= imm
;
631 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
632 switch (info
->qualifier
)
634 case AARCH64_OPND_QLF_NIL
:
636 info
->shifter
.kind
= AARCH64_MOD_NONE
;
638 case AARCH64_OPND_QLF_LSL
:
640 info
->shifter
.kind
= AARCH64_MOD_LSL
;
641 switch (aarch64_get_qualifier_esize (opnd0_qualifier
))
643 case 4: gen_sub_field (FLD_cmode
, 1, 2, &field
); break; /* per word */
644 case 2: gen_sub_field (FLD_cmode
, 1, 1, &field
); break; /* per half */
645 default: assert (0); return 0;
647 /* 00: 0; 01: 8; 10:16; 11:24. */
648 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) << 3;
650 case AARCH64_OPND_QLF_MSL
:
652 info
->shifter
.kind
= AARCH64_MOD_MSL
;
653 gen_sub_field (FLD_cmode
, 0, 1, &field
); /* per word */
654 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) ? 16 : 8;
664 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
666 aarch64_ext_fbits (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
667 aarch64_opnd_info
*info
, const aarch64_insn code
,
668 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
670 info
->imm
.value
= 64- extract_field (FLD_scale
, code
, 0);
674 /* Decode arithmetic immediate for e.g.
675 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
677 aarch64_ext_aimm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
678 aarch64_opnd_info
*info
, const aarch64_insn code
,
679 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
683 info
->shifter
.kind
= AARCH64_MOD_LSL
;
685 value
= extract_field (FLD_shift
, code
, 0);
688 info
->shifter
.amount
= value
? 12 : 0;
689 /* imm12 (unsigned) */
690 info
->imm
.value
= extract_field (FLD_imm12
, code
, 0);
695 /* Decode logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
698 aarch64_ext_limm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
699 aarch64_opnd_info
*info
, const aarch64_insn code
,
700 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
708 value
= extract_fields (code
, 0, 3, FLD_N
, FLD_immr
, FLD_imms
);
709 assert (inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
710 || inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_X
);
711 sf
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
) != 4;
713 /* value is N:immr:imms. */
715 R
= (value
>> 6) & 0x3f;
716 N
= (value
>> 12) & 0x1;
718 if (sf
== 0 && N
== 1)
721 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
722 (in other words, right rotated by R), then replicated. */
726 mask
= 0xffffffffffffffffull
;
732 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size
= 32; break;
733 case 0x20 ... 0x2f: /* 10xxxx */ simd_size
= 16; S
&= 0xf; break;
734 case 0x30 ... 0x37: /* 110xxx */ simd_size
= 8; S
&= 0x7; break;
735 case 0x38 ... 0x3b: /* 1110xx */ simd_size
= 4; S
&= 0x3; break;
736 case 0x3c ... 0x3d: /* 11110x */ simd_size
= 2; S
&= 0x1; break;
739 mask
= (1ull << simd_size
) - 1;
740 /* Top bits are IGNORED. */
743 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
744 if (S
== simd_size
- 1)
746 /* S+1 consecutive bits to 1. */
747 /* NOTE: S can't be 63 due to detection above. */
748 imm
= (1ull << (S
+ 1)) - 1;
749 /* Rotate to the left by simd_size - R. */
751 imm
= ((imm
<< (simd_size
- R
)) & mask
) | (imm
>> R
);
752 /* Replicate the value according to SIMD size. */
755 case 2: imm
= (imm
<< 2) | imm
;
756 case 4: imm
= (imm
<< 4) | imm
;
757 case 8: imm
= (imm
<< 8) | imm
;
758 case 16: imm
= (imm
<< 16) | imm
;
759 case 32: imm
= (imm
<< 32) | imm
;
761 default: assert (0); return 0;
764 info
->imm
.value
= sf
? imm
: imm
& 0xffffffff;
769 /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
770 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
772 aarch64_ext_ft (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
773 aarch64_opnd_info
*info
,
774 const aarch64_insn code
, const aarch64_inst
*inst
)
779 info
->reg
.regno
= extract_field (FLD_Rt
, code
, 0);
782 value
= extract_field (FLD_ldst_size
, code
, 0);
783 if (inst
->opcode
->iclass
== ldstpair_indexed
784 || inst
->opcode
->iclass
== ldstnapair_offs
785 || inst
->opcode
->iclass
== ldstpair_off
786 || inst
->opcode
->iclass
== loadlit
)
788 enum aarch64_opnd_qualifier qualifier
;
791 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
792 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
793 case 2: qualifier
= AARCH64_OPND_QLF_S_Q
; break;
796 info
->qualifier
= qualifier
;
801 value
= extract_fields (code
, 0, 2, FLD_opc1
, FLD_ldst_size
);
804 info
->qualifier
= get_sreg_qualifier_from_value (value
);
810 /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
812 aarch64_ext_addr_simple (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
813 aarch64_opnd_info
*info
,
815 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
818 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
822 /* Decode the address operand for e.g.
823 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
825 aarch64_ext_addr_regoff (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
826 aarch64_opnd_info
*info
,
827 aarch64_insn code
, const aarch64_inst
*inst
)
829 aarch64_insn S
, value
;
832 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
834 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
836 value
= extract_field (FLD_option
, code
, 0);
838 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
839 /* Fix-up the shifter kind; although the table-driven approach is
840 efficient, it is slightly inflexible, thus needing this fix-up. */
841 if (info
->shifter
.kind
== AARCH64_MOD_UXTX
)
842 info
->shifter
.kind
= AARCH64_MOD_LSL
;
844 S
= extract_field (FLD_S
, code
, 0);
847 info
->shifter
.amount
= 0;
848 info
->shifter
.amount_present
= 0;
853 /* Need information in other operand(s) to help achieve the decoding
855 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
856 /* Get the size of the data element that is accessed, which may be
857 different from that of the source register size, e.g. in strb/ldrb. */
858 size
= aarch64_get_qualifier_esize (info
->qualifier
);
859 info
->shifter
.amount
= get_logsz (size
);
860 info
->shifter
.amount_present
= 1;
866 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
868 aarch64_ext_addr_simm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
869 aarch64_insn code
, const aarch64_inst
*inst
)
872 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
875 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
876 /* simm (imm9 or imm7) */
877 imm
= extract_field (self
->fields
[0], code
, 0);
878 info
->addr
.offset
.imm
= sign_extend (imm
, fields
[self
->fields
[0]].width
- 1);
879 if (self
->fields
[0] == FLD_imm7
)
880 /* scaled immediate in ld/st pair instructions. */
881 info
->addr
.offset
.imm
*= aarch64_get_qualifier_esize (info
->qualifier
);
883 if (inst
->opcode
->iclass
== ldst_unscaled
884 || inst
->opcode
->iclass
== ldstnapair_offs
885 || inst
->opcode
->iclass
== ldstpair_off
886 || inst
->opcode
->iclass
== ldst_unpriv
)
887 info
->addr
.writeback
= 0;
890 /* pre/post- index */
891 info
->addr
.writeback
= 1;
892 if (extract_field (self
->fields
[1], code
, 0) == 1)
893 info
->addr
.preind
= 1;
895 info
->addr
.postind
= 1;
901 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
903 aarch64_ext_addr_uimm12 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
905 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
908 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
909 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
911 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
913 info
->addr
.offset
.imm
= extract_field (self
->fields
[1], code
, 0) << shift
;
917 /* Decode the address operand for e.g.
918 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
920 aarch64_ext_simd_addr_post (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
921 aarch64_opnd_info
*info
,
922 aarch64_insn code
, const aarch64_inst
*inst
)
924 /* The opcode dependent area stores the number of elements in
925 each structure to be loaded/stored. */
926 int is_ld1r
= get_opcode_dependent_value (inst
->opcode
) == 1;
929 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
931 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
932 if (info
->addr
.offset
.regno
== 31)
934 if (inst
->opcode
->operands
[0] == AARCH64_OPND_LVt_AL
)
935 /* Special handling of loading single structure to all lane. */
936 info
->addr
.offset
.imm
= (is_ld1r
? 1
937 : inst
->operands
[0].reglist
.num_regs
)
938 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
940 info
->addr
.offset
.imm
= inst
->operands
[0].reglist
.num_regs
941 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
)
942 * aarch64_get_qualifier_nelem (inst
->operands
[0].qualifier
);
945 info
->addr
.offset
.is_reg
= 1;
946 info
->addr
.writeback
= 1;
951 /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
953 aarch64_ext_cond (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
954 aarch64_opnd_info
*info
,
955 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
959 value
= extract_field (FLD_cond
, code
, 0);
960 info
->cond
= get_cond_from_value (value
);
964 /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
966 aarch64_ext_sysreg (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
967 aarch64_opnd_info
*info
,
969 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
971 /* op0:op1:CRn:CRm:op2 */
972 info
->sysreg
= extract_fields (code
, 0, 5, FLD_op0
, FLD_op1
, FLD_CRn
,
977 /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
979 aarch64_ext_pstatefield (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
980 aarch64_opnd_info
*info
, aarch64_insn code
,
981 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
985 info
->pstatefield
= extract_fields (code
, 0, 2, FLD_op1
, FLD_op2
);
986 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
987 if (aarch64_pstatefields
[i
].value
== (aarch64_insn
)info
->pstatefield
)
989 /* Reserved value in <pstatefield>. */
993 /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
995 aarch64_ext_sysins_op (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
996 aarch64_opnd_info
*info
,
998 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1002 const aarch64_sys_ins_reg
*sysins_ops
;
1003 /* op0:op1:CRn:CRm:op2 */
1004 value
= extract_fields (code
, 0, 5,
1005 FLD_op0
, FLD_op1
, FLD_CRn
,
1010 case AARCH64_OPND_SYSREG_AT
: sysins_ops
= aarch64_sys_regs_at
; break;
1011 case AARCH64_OPND_SYSREG_DC
: sysins_ops
= aarch64_sys_regs_dc
; break;
1012 case AARCH64_OPND_SYSREG_IC
: sysins_ops
= aarch64_sys_regs_ic
; break;
1013 case AARCH64_OPND_SYSREG_TLBI
: sysins_ops
= aarch64_sys_regs_tlbi
; break;
1014 default: assert (0); return 0;
1017 for (i
= 0; sysins_ops
[i
].template != NULL
; ++i
)
1018 if (sysins_ops
[i
].value
== value
)
1020 info
->sysins_op
= sysins_ops
+ i
;
1021 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1022 info
->sysins_op
->template,
1023 (unsigned)info
->sysins_op
->value
,
1024 info
->sysins_op
->has_xt
, i
);
1031 /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
1034 aarch64_ext_barrier (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1035 aarch64_opnd_info
*info
,
1037 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1040 info
->barrier
= aarch64_barrier_options
+ extract_field (FLD_CRm
, code
, 0);
1044 /* Decode the prefetch operation option operand for e.g.
1045 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
1048 aarch64_ext_prfop (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1049 aarch64_opnd_info
*info
,
1050 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1053 info
->prfop
= aarch64_prfops
+ extract_field (FLD_Rt
, code
, 0);
1057 /* Decode the extended register operand for e.g.
1058 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1060 aarch64_ext_reg_extended (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1061 aarch64_opnd_info
*info
,
1063 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1068 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1070 value
= extract_field (FLD_option
, code
, 0);
1071 info
->shifter
.kind
=
1072 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
1074 info
->shifter
.amount
= extract_field (FLD_imm3
, code
, 0);
1076 /* This makes the constraint checking happy. */
1077 info
->shifter
.operator_present
= 1;
1079 /* Assume inst->operands[0].qualifier has been resolved. */
1080 assert (inst
->operands
[0].qualifier
!= AARCH64_OPND_QLF_NIL
);
1081 info
->qualifier
= AARCH64_OPND_QLF_W
;
1082 if (inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_X
1083 && (info
->shifter
.kind
== AARCH64_MOD_UXTX
1084 || info
->shifter
.kind
== AARCH64_MOD_SXTX
))
1085 info
->qualifier
= AARCH64_OPND_QLF_X
;
1090 /* Decode the shifted register operand for e.g.
1091 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
1093 aarch64_ext_reg_shifted (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1094 aarch64_opnd_info
*info
,
1096 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1101 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1103 value
= extract_field (FLD_shift
, code
, 0);
1104 info
->shifter
.kind
=
1105 aarch64_get_operand_modifier_from_value (value
, FALSE
/* extend_p */);
1106 if (info
->shifter
.kind
== AARCH64_MOD_ROR
1107 && inst
->opcode
->iclass
!= log_shift
)
1108 /* ROR is not available for the shifted register operand in arithmetic
1112 info
->shifter
.amount
= extract_field (FLD_imm6
, code
, 0);
1114 /* This makes the constraint checking happy. */
1115 info
->shifter
.operator_present
= 1;
1120 /* Bitfields that are commonly used to encode certain operands' information
1121 may be partially used as part of the base opcode in some instructions.
1122 For example, the bit 1 of the field 'size' in
1123 FCVTXN <Vb><d>, <Va><n>
1124 is actually part of the base opcode, while only size<0> is available
1125 for encoding the register type. Another example is the AdvSIMD
1126 instruction ORR (register), in which the field 'size' is also used for
1127 the base opcode, leaving only the field 'Q' available to encode the
1128 vector register arrangement specifier '8B' or '16B'.
1130 This function tries to deduce the qualifier from the value of partially
1131 constrained field(s). Given the VALUE of such a field or fields, the
1132 qualifiers CANDIDATES and the MASK (indicating which bits are valid for
1133 operand encoding), the function returns the matching qualifier or
1134 AARCH64_OPND_QLF_NIL if nothing matches.
1136 N.B. CANDIDATES is a group of possible qualifiers that are valid for
1137 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
1138 may end with AARCH64_OPND_QLF_NIL. */
1140 static enum aarch64_opnd_qualifier
1141 get_qualifier_from_partial_encoding (aarch64_insn value
,
1142 const enum aarch64_opnd_qualifier
* \
1147 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value
, (int)mask
);
1148 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1150 aarch64_insn standard_value
;
1151 if (candidates
[i
] == AARCH64_OPND_QLF_NIL
)
1153 standard_value
= aarch64_get_qualifier_standard_value (candidates
[i
]);
1154 if ((standard_value
& mask
) == (value
& mask
))
1155 return candidates
[i
];
1157 return AARCH64_OPND_QLF_NIL
;
1160 /* Given a list of qualifier sequences, return all possible valid qualifiers
1161 for operand IDX in QUALIFIERS.
1162 Assume QUALIFIERS is an array whose length is large enough. */
1165 get_operand_possible_qualifiers (int idx
,
1166 const aarch64_opnd_qualifier_seq_t
*list
,
1167 enum aarch64_opnd_qualifier
*qualifiers
)
1170 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1171 if ((qualifiers
[i
] = list
[i
][idx
]) == AARCH64_OPND_QLF_NIL
)
1175 /* Decode the size Q field for e.g. SHADD.
1176 We tag one operand with the qualifer according to the code;
1177 whether the qualifier is valid for this opcode or not, it is the
1178 duty of the semantic checking. */
1181 decode_sizeq (aarch64_inst
*inst
)
1184 enum aarch64_opnd_qualifier qualifier
;
1186 aarch64_insn value
, mask
;
1187 enum aarch64_field_kind fld_sz
;
1188 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1190 if (inst
->opcode
->iclass
== asisdlse
1191 || inst
->opcode
->iclass
== asisdlsep
1192 || inst
->opcode
->iclass
== asisdlso
1193 || inst
->opcode
->iclass
== asisdlsop
)
1194 fld_sz
= FLD_vldst_size
;
1199 value
= extract_fields (code
, inst
->opcode
->mask
, 2, fld_sz
, FLD_Q
);
1200 /* Obtain the info that which bits of fields Q and size are actually
1201 available for operand encoding. Opcodes like FMAXNM and FMLA have
1202 size[1] unavailable. */
1203 mask
= extract_fields (~inst
->opcode
->mask
, 0, 2, fld_sz
, FLD_Q
);
1205 /* The index of the operand we are going to tag a qualifier and the qualifer
1206 itself are reasoned from the value of the size and Q fields and the
1207 possible valid qualifier lists. */
1208 idx
= aarch64_select_operand_for_sizeq_field_coding (inst
->opcode
);
1209 DEBUG_TRACE ("key idx: %d", idx
);
1211 /* For most related instruciton, size:Q are fully available for operand
1215 inst
->operands
[idx
].qualifier
= get_vreg_qualifier_from_value (value
);
1219 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1221 #ifdef DEBUG_AARCH64
1225 for (i
= 0; candidates
[i
] != AARCH64_OPND_QLF_NIL
1226 && i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1227 DEBUG_TRACE ("qualifier %d: %s", i
,
1228 aarch64_get_qualifier_name(candidates
[i
]));
1229 DEBUG_TRACE ("%d, %d", (int)value
, (int)mask
);
1231 #endif /* DEBUG_AARCH64 */
1233 qualifier
= get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1235 if (qualifier
== AARCH64_OPND_QLF_NIL
)
1238 inst
->operands
[idx
].qualifier
= qualifier
;
1242 /* Decode size[0]:Q, i.e. bit 22 and bit 30, for
1243 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1246 decode_asimd_fcvt (aarch64_inst
*inst
)
1248 aarch64_field field
= {0, 0};
1250 enum aarch64_opnd_qualifier qualifier
;
1252 gen_sub_field (FLD_size
, 0, 1, &field
);
1253 value
= extract_field_2 (&field
, inst
->value
, 0);
1254 qualifier
= value
== 0 ? AARCH64_OPND_QLF_V_4S
1255 : AARCH64_OPND_QLF_V_2D
;
1256 switch (inst
->opcode
->op
)
1260 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1261 inst
->operands
[1].qualifier
= qualifier
;
1265 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
1266 inst
->operands
[0].qualifier
= qualifier
;
1276 /* Decode size[0], i.e. bit 22, for
1277 e.g. FCVTXN <Vb><d>, <Va><n>. */
1280 decode_asisd_fcvtxn (aarch64_inst
*inst
)
1282 aarch64_field field
= {0, 0};
1283 gen_sub_field (FLD_size
, 0, 1, &field
);
1284 if (!extract_field_2 (&field
, inst
->value
, 0))
1286 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_S_S
;
1290 /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
1292 decode_fcvt (aarch64_inst
*inst
)
1294 enum aarch64_opnd_qualifier qualifier
;
1296 const aarch64_field field
= {15, 2};
1299 value
= extract_field_2 (&field
, inst
->value
, 0);
1302 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
1303 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
1304 case 3: qualifier
= AARCH64_OPND_QLF_S_H
; break;
1307 inst
->operands
[0].qualifier
= qualifier
;
1312 /* Do miscellaneous decodings that are not common enough to be driven by
1316 do_misc_decoding (aarch64_inst
*inst
)
1318 switch (inst
->opcode
->op
)
1321 return decode_fcvt (inst
);
1326 return decode_asimd_fcvt (inst
);
1328 return decode_asisd_fcvtxn (inst
);
1334 /* Opcodes that have fields shared by multiple operands are usually flagged
1335 with flags. In this function, we detect such flags, decode the related
1336 field(s) and store the information in one of the related operands. The
1337 'one' operand is not any operand but one of the operands that can
1338 accommadate all the information that has been decoded. */
1341 do_special_decoding (aarch64_inst
*inst
)
1345 /* Condition for truly conditional executed instructions, e.g. b.cond. */
1346 if (inst
->opcode
->flags
& F_COND
)
1348 value
= extract_field (FLD_cond2
, inst
->value
, 0);
1349 inst
->cond
= get_cond_from_value (value
);
1352 if (inst
->opcode
->flags
& F_SF
)
1354 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
1355 value
= extract_field (FLD_sf
, inst
->value
, 0);
1356 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1357 if ((inst
->opcode
->flags
& F_N
)
1358 && extract_field (FLD_N
, inst
->value
, 0) != value
)
1361 /* size:Q fields. */
1362 if (inst
->opcode
->flags
& F_SIZEQ
)
1363 return decode_sizeq (inst
);
1365 if (inst
->opcode
->flags
& F_FPTYPE
)
1367 idx
= select_operand_for_fptype_field_coding (inst
->opcode
);
1368 value
= extract_field (FLD_type
, inst
->value
, 0);
1371 case 0: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_S
; break;
1372 case 1: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_D
; break;
1373 case 3: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_H
; break;
1378 if (inst
->opcode
->flags
& F_SSIZE
)
1380 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
1381 of the base opcode. */
1383 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1384 idx
= select_operand_for_scalar_size_field_coding (inst
->opcode
);
1385 value
= extract_field (FLD_size
, inst
->value
, inst
->opcode
->mask
);
1386 mask
= extract_field (FLD_size
, ~inst
->opcode
->mask
, 0);
1387 /* For most related instruciton, the 'size' field is fully available for
1388 operand encoding. */
1390 inst
->operands
[idx
].qualifier
= get_sreg_qualifier_from_value (value
);
1393 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1395 inst
->operands
[idx
].qualifier
1396 = get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1400 if (inst
->opcode
->flags
& F_T
)
1402 /* Num of consecutive '0's on the right side of imm5<3:0>. */
1405 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1406 == AARCH64_OPND_CLASS_SIMD_REG
);
1417 val
= extract_field (FLD_imm5
, inst
->value
, 0);
1418 while ((val
& 0x1) == 0 && ++num
<= 3)
1422 Q
= (unsigned) extract_field (FLD_Q
, inst
->value
, inst
->opcode
->mask
);
1423 inst
->operands
[0].qualifier
=
1424 get_vreg_qualifier_from_value ((num
<< 1) | Q
);
1427 if (inst
->opcode
->flags
& F_GPRSIZE_IN_Q
)
1429 /* Use Rt to encode in the case of e.g.
1430 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1431 idx
= aarch64_operand_index (inst
->opcode
->operands
, AARCH64_OPND_Rt
);
1434 /* Otherwise use the result operand, which has to be a integer
1436 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1437 == AARCH64_OPND_CLASS_INT_REG
);
1440 assert (idx
== 0 || idx
== 1);
1441 value
= extract_field (FLD_Q
, inst
->value
, 0);
1442 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1445 if (inst
->opcode
->flags
& F_LDS_SIZE
)
1447 aarch64_field field
= {0, 0};
1448 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1449 == AARCH64_OPND_CLASS_INT_REG
);
1450 gen_sub_field (FLD_opc
, 0, 1, &field
);
1451 value
= extract_field_2 (&field
, inst
->value
, 0);
1452 inst
->operands
[0].qualifier
1453 = value
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
1456 /* Miscellaneous decoding; done as the last step. */
1457 if (inst
->opcode
->flags
& F_MISC
)
1458 return do_misc_decoding (inst
);
1463 /* Converters converting a real opcode instruction to its alias form. */
1465 /* ROR <Wd>, <Ws>, #<shift>
1467 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
1469 convert_extr_to_ror (aarch64_inst
*inst
)
1471 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
1473 copy_operand_info (inst
, 2, 3);
1474 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1481 UBFM <Xd>, <Xn>, #<shift>, #63.
1483 LSR <Xd>, <Xn>, #<shift>. */
1485 convert_bfm_to_sr (aarch64_inst
*inst
)
1489 imms
= inst
->operands
[3].imm
.value
;
1490 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
1493 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1500 /* Convert MOV to ORR. */
1502 convert_orr_to_mov (aarch64_inst
*inst
)
1504 /* MOV <Vd>.<T>, <Vn>.<T>
1506 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
1507 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
1509 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
1515 /* When <imms> >= <immr>, the instruction written:
1516 SBFX <Xd>, <Xn>, #<lsb>, #<width>
1518 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
1521 convert_bfm_to_bfx (aarch64_inst
*inst
)
1525 immr
= inst
->operands
[2].imm
.value
;
1526 imms
= inst
->operands
[3].imm
.value
;
1530 inst
->operands
[2].imm
.value
= lsb
;
1531 inst
->operands
[3].imm
.value
= imms
+ 1 - lsb
;
1532 /* The two opcodes have different qualifiers for
1533 the immediate operands; reset to help the checking. */
1534 reset_operand_qualifier (inst
, 2);
1535 reset_operand_qualifier (inst
, 3);
1542 /* When <imms> < <immr>, the instruction written:
1543 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
1545 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
1548 convert_bfm_to_bfi (aarch64_inst
*inst
)
1550 int64_t immr
, imms
, val
;
1552 immr
= inst
->operands
[2].imm
.value
;
1553 imms
= inst
->operands
[3].imm
.value
;
1554 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
1557 inst
->operands
[2].imm
.value
= (val
- immr
) & (val
- 1);
1558 inst
->operands
[3].imm
.value
= imms
+ 1;
1559 /* The two opcodes have different qualifiers for
1560 the immediate operands; reset to help the checking. */
1561 reset_operand_qualifier (inst
, 2);
1562 reset_operand_qualifier (inst
, 3);
1569 /* The instruction written:
1570 LSL <Xd>, <Xn>, #<shift>
1572 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
1575 convert_ubfm_to_lsl (aarch64_inst
*inst
)
1577 int64_t immr
= inst
->operands
[2].imm
.value
;
1578 int64_t imms
= inst
->operands
[3].imm
.value
;
1580 = inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
1582 if ((immr
== 0 && imms
== val
) || immr
== imms
+ 1)
1584 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1585 inst
->operands
[2].imm
.value
= val
- imms
;
1592 /* CINC <Wd>, <Wn>, <cond>
1594 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>). */
1597 convert_from_csel (aarch64_inst
*inst
)
1599 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
1601 copy_operand_info (inst
, 2, 3);
1602 inst
->operands
[2].cond
= get_inverted_cond (inst
->operands
[3].cond
);
1603 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1609 /* CSET <Wd>, <cond>
1611 CSINC <Wd>, WZR, WZR, invert(<cond>). */
1614 convert_csinc_to_cset (aarch64_inst
*inst
)
1616 if (inst
->operands
[1].reg
.regno
== 0x1f
1617 && inst
->operands
[2].reg
.regno
== 0x1f)
1619 copy_operand_info (inst
, 1, 3);
1620 inst
->operands
[1].cond
= get_inverted_cond (inst
->operands
[3].cond
);
1621 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1622 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
1630 MOVZ <Wd>, #<imm16>, LSL #<shift>.
1632 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
1633 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
1634 or where a MOVN has an immediate that could be encoded by MOVZ, or where
1635 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
1636 machine-instruction mnemonic must be used. */
1639 convert_movewide_to_mov (aarch64_inst
*inst
)
1641 uint64_t value
= inst
->operands
[1].imm
.value
;
1642 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
1643 if (value
== 0 && inst
->operands
[1].shifter
.amount
!= 0)
1645 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
1646 inst
->operands
[1].shifter
.kind
= AARCH64_MOD_NONE
;
1647 value
<<= inst
->operands
[1].shifter
.amount
;
1648 /* As an alias convertor, it has to be clear that the INST->OPCODE
1649 is the opcode of the real instruction. */
1650 if (inst
->opcode
->op
== OP_MOVN
)
1652 int is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
1654 /* A MOVN has an immediate that could be encoded by MOVZ. */
1655 if (aarch64_wide_constant_p (value
, is32
, NULL
) == TRUE
)
1658 inst
->operands
[1].imm
.value
= value
;
1659 inst
->operands
[1].shifter
.amount
= 0;
1665 ORR <Wd>, WZR, #<imm>.
1667 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
1668 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
1669 or where a MOVN has an immediate that could be encoded by MOVZ, or where
1670 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
1671 machine-instruction mnemonic must be used. */
1674 convert_movebitmask_to_mov (aarch64_inst
*inst
)
1679 /* Should have been assured by the base opcode value. */
1680 assert (inst
->operands
[1].reg
.regno
== 0x1f);
1681 copy_operand_info (inst
, 1, 2);
1682 is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
1683 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
1684 value
= inst
->operands
[1].imm
.value
;
1685 /* ORR has an immediate that could be generated by a MOVZ or MOVN
1687 if (inst
->operands
[0].reg
.regno
!= 0x1f
1688 && (aarch64_wide_constant_p (value
, is32
, NULL
) == TRUE
1689 || aarch64_wide_constant_p (~value
, is32
, NULL
) == TRUE
))
1692 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
1696 /* Some alias opcodes are disassembled by being converted from their real-form.
1697 N.B. INST->OPCODE is the real opcode rather than the alias. */
1700 convert_to_alias (aarch64_inst
*inst
, const aarch64_opcode
*alias
)
1706 return convert_bfm_to_sr (inst
);
1708 return convert_ubfm_to_lsl (inst
);
1712 return convert_from_csel (inst
);
1715 return convert_csinc_to_cset (inst
);
1719 return convert_bfm_to_bfx (inst
);
1723 return convert_bfm_to_bfi (inst
);
1725 return convert_orr_to_mov (inst
);
1726 case OP_MOV_IMM_WIDE
:
1727 case OP_MOV_IMM_WIDEN
:
1728 return convert_movewide_to_mov (inst
);
1729 case OP_MOV_IMM_LOG
:
1730 return convert_movebitmask_to_mov (inst
);
1732 return convert_extr_to_ror (inst
);
1738 static int aarch64_opcode_decode (const aarch64_opcode
*, const aarch64_insn
,
1739 aarch64_inst
*, int);
1741 /* Given the instruction information in *INST, check if the instruction has
1742 any alias form that can be used to represent *INST. If the answer is yes,
1743 update *INST to be in the form of the determined alias. */
1745 /* In the opcode description table, the following flags are used in opcode
1746 entries to help establish the relations between the real and alias opcodes:
1748 F_ALIAS: opcode is an alias
1749 F_HAS_ALIAS: opcode has alias(es)
1752 F_P3: Disassembly preference priority 1-3 (the larger the
1753 higher). If nothing is specified, it is the priority
1754 0 by default, i.e. the lowest priority.
1756 Although the relation between the machine and the alias instructions are not
1757 explicitly described, it can be easily determined from the base opcode
1758 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
1759 description entries:
1761 The mask of an alias opcode must be equal to or a super-set (i.e. more
1762 constrained) of that of the aliased opcode; so is the base opcode value.
1764 if (opcode_has_alias (real) && alias_opcode_p (opcode)
1765 && (opcode->mask & real->mask) == real->mask
1766 && (real->mask & opcode->opcode) == (real->mask & real->opcode))
1767 then OPCODE is an alias of, and only of, the REAL instruction
1769 The alias relationship is forced flat-structured to keep related algorithm
1770 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
1772 During the disassembling, the decoding decision tree (in
1773 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
1774 if the decoding of such a machine instruction succeeds (and -Mno-aliases is
1775 not specified), the disassembler will check whether there is any alias
1776 instruction exists for this real instruction. If there is, the disassembler
1777 will try to disassemble the 32-bit binary again using the alias's rule, or
1778 try to convert the IR to the form of the alias. In the case of the multiple
1779 aliases, the aliases are tried one by one from the highest priority
1780 (currently the flag F_P3) to the lowest priority (no priority flag), and the
1781 first succeeds first adopted.
1783 You may ask why there is a need for the conversion of IR from one form to
1784 another in handling certain aliases. This is because on one hand it avoids
1785 adding more operand code to handle unusual encoding/decoding; on other
1786 hand, during the disassembling, the conversion is an effective approach to
1787 check the condition of an alias (as an alias may be adopted only if certain
1788 conditions are met).
1790 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
1791 aarch64_opcode_table and generated aarch64_find_alias_opcode and
1792 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
1795 determine_disassembling_preference (struct aarch64_inst
*inst
)
1797 const aarch64_opcode
*opcode
;
1798 const aarch64_opcode
*alias
;
1800 opcode
= inst
->opcode
;
1802 /* This opcode does not have an alias, so use itself. */
1803 if (opcode_has_alias (opcode
) == FALSE
)
1806 alias
= aarch64_find_alias_opcode (opcode
);
1809 #ifdef DEBUG_AARCH64
1812 const aarch64_opcode
*tmp
= alias
;
1813 printf ("#### LIST orderd: ");
1816 printf ("%s, ", tmp
->name
);
1817 tmp
= aarch64_find_next_alias_opcode (tmp
);
1821 #endif /* DEBUG_AARCH64 */
1823 for (; alias
; alias
= aarch64_find_next_alias_opcode (alias
))
1825 DEBUG_TRACE ("try %s", alias
->name
);
1826 assert (alias_opcode_p (alias
));
1828 /* An alias can be a pseudo opcode which will never be used in the
1829 disassembly, e.g. BIC logical immediate is such a pseudo opcode
1831 if (pseudo_opcode_p (alias
))
1833 DEBUG_TRACE ("skip pseudo %s", alias
->name
);
1837 if ((inst
->value
& alias
->mask
) != alias
->opcode
)
1839 DEBUG_TRACE ("skip %s as base opcode not match", alias
->name
);
1842 /* No need to do any complicated transformation on operands, if the alias
1843 opcode does not have any operand. */
1844 if (aarch64_num_of_operands (alias
) == 0 && alias
->opcode
== inst
->value
)
1846 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias
->name
);
1847 aarch64_replace_opcode (inst
, alias
);
1850 if (alias
->flags
& F_CONV
)
1853 memcpy (©
, inst
, sizeof (aarch64_inst
));
1854 /* ALIAS is the preference as long as the instruction can be
1855 successfully converted to the form of ALIAS. */
1856 if (convert_to_alias (©
, alias
) == 1)
1858 aarch64_replace_opcode (©
, alias
);
1859 assert (aarch64_match_operands_constraint (©
, NULL
));
1860 DEBUG_TRACE ("succeed with %s via conversion", alias
->name
);
1861 memcpy (inst
, ©
, sizeof (aarch64_inst
));
1867 /* Directly decode the alias opcode. */
1869 memset (&temp
, '\0', sizeof (aarch64_inst
));
1870 if (aarch64_opcode_decode (alias
, inst
->value
, &temp
, 1) == 1)
1872 DEBUG_TRACE ("succeed with %s via direct decoding", alias
->name
);
1873 memcpy (inst
, &temp
, sizeof (aarch64_inst
));
1880 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
1881 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
1884 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
1885 determined and used to disassemble CODE; this is done just before the
1889 aarch64_opcode_decode (const aarch64_opcode
*opcode
, const aarch64_insn code
,
1890 aarch64_inst
*inst
, int noaliases_p
)
1894 DEBUG_TRACE ("enter with %s", opcode
->name
);
1896 assert (opcode
&& inst
);
1898 /* Check the base opcode. */
1899 if ((code
& opcode
->mask
) != (opcode
->opcode
& opcode
->mask
))
1901 DEBUG_TRACE ("base opcode match FAIL");
1906 memset (inst
, '\0', sizeof (aarch64_inst
));
1908 inst
->opcode
= opcode
;
1911 /* Assign operand codes and indexes. */
1912 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
1914 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
)
1916 inst
->operands
[i
].type
= opcode
->operands
[i
];
1917 inst
->operands
[i
].idx
= i
;
1920 /* Call the opcode decoder indicated by flags. */
1921 if (opcode_has_special_coder (opcode
) && do_special_decoding (inst
) == 0)
1923 DEBUG_TRACE ("opcode flag-based decoder FAIL");
1927 /* Call operand decoders. */
1928 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
1930 const aarch64_operand
*opnd
;
1931 enum aarch64_opnd type
;
1932 type
= opcode
->operands
[i
];
1933 if (type
== AARCH64_OPND_NIL
)
1935 opnd
= &aarch64_operands
[type
];
1936 if (operand_has_extractor (opnd
)
1937 && (! aarch64_extract_operand (opnd
, &inst
->operands
[i
], code
, inst
)))
1939 DEBUG_TRACE ("operand decoder FAIL at operand %d", i
);
1944 /* Match the qualifiers. */
1945 if (aarch64_match_operands_constraint (inst
, NULL
) == 1)
1947 /* Arriving here, the CODE has been determined as a valid instruction
1948 of OPCODE and *INST has been filled with information of this OPCODE
1949 instruction. Before the return, check if the instruction has any
1950 alias and should be disassembled in the form of its alias instead.
1951 If the answer is yes, *INST will be updated. */
1953 determine_disassembling_preference (inst
);
1954 DEBUG_TRACE ("SUCCESS");
1959 DEBUG_TRACE ("constraint matching FAIL");
1966 /* This does some user-friendly fix-up to *INST. It is currently focus on
1967 the adjustment of qualifiers to help the printed instruction
1968 recognized/understood more easily. */
1971 user_friendly_fixup (aarch64_inst
*inst
)
1973 switch (inst
->opcode
->iclass
)
1976 /* TBNZ Xn|Wn, #uimm6, label
1977 Test and Branch Not Zero: conditionally jumps to label if bit number
1978 uimm6 in register Xn is not zero. The bit number implies the width of
1979 the register, which may be written and should be disassembled as Wn if
1980 uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
1982 if (inst
->operands
[1].imm
.value
< 32)
1983 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
1989 /* Decode INSN and fill in *INST the instruction information. */
1992 disas_aarch64_insn (uint64_t pc ATTRIBUTE_UNUSED
, uint32_t insn
,
1995 const aarch64_opcode
*opcode
= aarch64_opcode_lookup (insn
);
1997 #ifdef DEBUG_AARCH64
2000 const aarch64_opcode
*tmp
= opcode
;
2002 DEBUG_TRACE ("opcode lookup:");
2005 aarch64_verbose (" %s", tmp
->name
);
2006 tmp
= aarch64_find_next_opcode (tmp
);
2009 #endif /* DEBUG_AARCH64 */
2011 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
2012 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
2013 opcode field and value, apart from the difference that one of them has an
2014 extra field as part of the opcode, but such a field is used for operand
2015 encoding in other opcode(s) ('immh' in the case of the example). */
2016 while (opcode
!= NULL
)
2018 /* But only one opcode can be decoded successfully for, as the
2019 decoding routine will check the constraint carefully. */
2020 if (aarch64_opcode_decode (opcode
, insn
, inst
, no_aliases
) == 1)
2022 opcode
= aarch64_find_next_opcode (opcode
);
2028 /* Print operands. */
2031 print_operands (bfd_vma pc
, const aarch64_opcode
*opcode
,
2032 const aarch64_opnd_info
*opnds
, struct disassemble_info
*info
)
2034 int i
, pcrel_p
, num_printed
;
2035 for (i
= 0, num_printed
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2037 const size_t size
= 128;
2039 /* We regard the opcode operand info more, however we also look into
2040 the inst->operands to support the disassembling of the optional
2042 The two operand code should be the same in all cases, apart from
2043 when the operand can be optional. */
2044 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
2045 || opnds
[i
].type
== AARCH64_OPND_NIL
)
2048 /* Generate the operand string in STR. */
2049 aarch64_print_operand (str
, size
, pc
, opcode
, opnds
, i
, &pcrel_p
,
2052 /* Print the delimiter (taking account of omitted operand(s)). */
2054 (*info
->fprintf_func
) (info
->stream
, "%s",
2055 num_printed
++ == 0 ? "\t" : ", ");
2057 /* Print the operand. */
2059 (*info
->print_address_func
) (info
->target
, info
);
2061 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
2065 /* Print the instruction mnemonic name. */
2068 print_mnemonic_name (const aarch64_inst
*inst
, struct disassemble_info
*info
)
2070 if (inst
->opcode
->flags
& F_COND
)
2072 /* For instructions that are truly conditionally executed, e.g. b.cond,
2073 prepare the full mnemonic name with the corresponding condition
2078 ptr
= strchr (inst
->opcode
->name
, '.');
2079 assert (ptr
&& inst
->cond
);
2080 len
= ptr
- inst
->opcode
->name
;
2082 strncpy (name
, inst
->opcode
->name
, len
);
2084 (*info
->fprintf_func
) (info
->stream
, "%s.%s", name
, inst
->cond
->names
[0]);
2087 (*info
->fprintf_func
) (info
->stream
, "%s", inst
->opcode
->name
);
2090 /* Print the instruction according to *INST. */
2093 print_aarch64_insn (bfd_vma pc
, const aarch64_inst
*inst
,
2094 struct disassemble_info
*info
)
2096 print_mnemonic_name (inst
, info
);
2097 print_operands (pc
, inst
->opcode
, inst
->operands
, info
);
2100 /* Entry-point of the instruction disassembler and printer. */
2103 print_insn_aarch64_word (bfd_vma pc
,
2105 struct disassemble_info
*info
)
2107 static const char *err_msg
[6] =
2110 [-ERR_UND
] = "undefined",
2111 [-ERR_UNP
] = "unpredictable",
2118 info
->insn_info_valid
= 1;
2119 info
->branch_delay_insns
= 0;
2120 info
->data_size
= 0;
2124 if (info
->flags
& INSN_HAS_RELOC
)
2125 /* If the instruction has a reloc associated with it, then
2126 the offset field in the instruction will actually be the
2127 addend for the reloc. (If we are using REL type relocs).
2128 In such cases, we can ignore the pc when computing
2129 addresses, since the addend is not currently pc-relative. */
2132 ret
= disas_aarch64_insn (pc
, word
, &inst
);
2134 if (((word
>> 21) & 0x3ff) == 1)
2136 /* RESERVED for ALES. */
2137 assert (ret
!= ERR_OK
);
2146 /* Handle undefined instructions. */
2147 info
->insn_type
= dis_noninsn
;
2148 (*info
->fprintf_func
) (info
->stream
,".inst\t0x%08x ; %s",
2149 word
, err_msg
[-ret
]);
2152 user_friendly_fixup (&inst
);
2153 print_aarch64_insn (pc
, &inst
, info
);
2160 /* Disallow mapping symbols ($x, $d etc) from
2161 being displayed in symbol relative addresses. */
2164 aarch64_symbol_is_valid (asymbol
* sym
,
2165 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
2172 name
= bfd_asymbol_name (sym
);
2176 || (name
[1] != 'x' && name
[1] != 'd')
2177 || (name
[2] != '\0' && name
[2] != '.'));
2180 /* Print data bytes on INFO->STREAM. */
2183 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
2185 struct disassemble_info
*info
)
2187 switch (info
->bytes_per_chunk
)
2190 info
->fprintf_func (info
->stream
, ".byte\t0x%02x", word
);
2193 info
->fprintf_func (info
->stream
, ".short\t0x%04x", word
);
2196 info
->fprintf_func (info
->stream
, ".word\t0x%08x", word
);
2203 /* Try to infer the code or data type from a symbol.
2204 Returns nonzero if *MAP_TYPE was set. */
2207 get_sym_code_type (struct disassemble_info
*info
, int n
,
2208 enum map_type
*map_type
)
2210 elf_symbol_type
*es
;
2214 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
2215 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
2217 /* If the symbol has function type then use that. */
2218 if (type
== STT_FUNC
)
2220 *map_type
= MAP_INSN
;
2224 /* Check for mapping symbols. */
2225 name
= bfd_asymbol_name(info
->symtab
[n
]);
2227 && (name
[1] == 'x' || name
[1] == 'd')
2228 && (name
[2] == '\0' || name
[2] == '.'))
2230 *map_type
= (name
[1] == 'x' ? MAP_INSN
: MAP_DATA
);
2237 /* Entry-point of the AArch64 disassembler. */
2240 print_insn_aarch64 (bfd_vma pc
,
2241 struct disassemble_info
*info
)
2243 bfd_byte buffer
[INSNLEN
];
2245 void (*printer
) (bfd_vma
, uint32_t, struct disassemble_info
*);
2246 bfd_boolean found
= FALSE
;
2247 unsigned int size
= 4;
2250 if (info
->disassembler_options
)
2252 set_default_aarch64_dis_options (info
);
2254 parse_aarch64_dis_options (info
->disassembler_options
);
2256 /* To avoid repeated parsing of these options, we remove them here. */
2257 info
->disassembler_options
= NULL
;
2260 /* Aarch64 instructions are always little-endian */
2261 info
->endian_code
= BFD_ENDIAN_LITTLE
;
2263 /* First check the full symtab for a mapping symbol, even if there
2264 are no usable non-mapping symbols for this address. */
2265 if (info
->symtab_size
!= 0
2266 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
2268 enum map_type type
= MAP_INSN
;
2273 if (pc
<= last_mapping_addr
)
2274 last_mapping_sym
= -1;
2276 /* Start scanning at the start of the function, or wherever
2277 we finished last time. */
2278 n
= info
->symtab_pos
+ 1;
2279 if (n
< last_mapping_sym
)
2280 n
= last_mapping_sym
;
2282 /* Scan up to the location being disassembled. */
2283 for (; n
< info
->symtab_size
; n
++)
2285 addr
= bfd_asymbol_value (info
->symtab
[n
]);
2288 if ((info
->section
== NULL
2289 || info
->section
== info
->symtab
[n
]->section
)
2290 && get_sym_code_type (info
, n
, &type
))
2299 n
= info
->symtab_pos
;
2300 if (n
< last_mapping_sym
)
2301 n
= last_mapping_sym
;
2303 /* No mapping symbol found at this address. Look backwards
2304 for a preceeding one. */
2307 if (get_sym_code_type (info
, n
, &type
))
2316 last_mapping_sym
= last_sym
;
2319 /* Look a little bit ahead to see if we should print out
2320 less than four bytes of data. If there's a symbol,
2321 mapping or otherwise, after two bytes then don't
2323 if (last_type
== MAP_DATA
)
2325 size
= 4 - (pc
& 3);
2326 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
2328 addr
= bfd_asymbol_value (info
->symtab
[n
]);
2331 if (addr
- pc
< size
)
2336 /* If the next symbol is after three bytes, we need to
2337 print only part of the data, so that we can use either
2340 size
= (pc
& 1) ? 1 : 2;
2344 if (last_type
== MAP_DATA
)
2346 /* size was set above. */
2347 info
->bytes_per_chunk
= size
;
2348 info
->display_endian
= info
->endian
;
2349 printer
= print_insn_data
;
2353 info
->bytes_per_chunk
= size
= INSNLEN
;
2354 info
->display_endian
= info
->endian_code
;
2355 printer
= print_insn_aarch64_word
;
2358 status
= (*info
->read_memory_func
) (pc
, buffer
, size
, info
);
2361 (*info
->memory_error_func
) (status
, pc
, info
);
2365 data
= bfd_get_bits (buffer
, size
* 8,
2366 info
->display_endian
== BFD_ENDIAN_BIG
);
2368 (*printer
) (pc
, data
, info
);
2374 print_aarch64_disassembler_options (FILE *stream
)
2376 fprintf (stream
, _("\n\
2377 The following AARCH64 specific disassembler options are supported for use\n\
2378 with the -M switch (multiple options should be separated by commas):\n"));
2380 fprintf (stream
, _("\n\
2381 no-aliases Don't print instruction aliases.\n"));
2383 fprintf (stream
, _("\n\
2384 aliases Do print instruction aliases.\n"));
2386 #ifdef DEBUG_AARCH64
2387 fprintf (stream
, _("\n\
2388 debug_dump Temp switch for debug trace.\n"));
2389 #endif /* DEBUG_AARCH64 */
2391 fprintf (stream
, _("\n"));