1 /* aarch64-dis.c -- AArch64 disassembler.
2 Copyright (C) 2009-2015 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
22 #include "bfd_stdint.h"
24 #include "libiberty.h"
26 #include "aarch64-dis.h"
36 /* Cached mapping symbol state. */
43 static enum map_type last_type
;
44 static int last_mapping_sym
= -1;
45 static bfd_vma last_mapping_addr
= 0;
48 static int no_aliases
= 0; /* If set disassemble as most general inst. */
52 set_default_aarch64_dis_options (struct disassemble_info
*info ATTRIBUTE_UNUSED
)
57 parse_aarch64_dis_option (const char *option
, unsigned int len ATTRIBUTE_UNUSED
)
59 /* Try to match options that are simple flags */
60 if (CONST_STRNEQ (option
, "no-aliases"))
66 if (CONST_STRNEQ (option
, "aliases"))
73 if (CONST_STRNEQ (option
, "debug_dump"))
78 #endif /* DEBUG_AARCH64 */
81 fprintf (stderr
, _("Unrecognised disassembler option: %s\n"), option
);
85 parse_aarch64_dis_options (const char *options
)
87 const char *option_end
;
92 while (*options
!= '\0')
94 /* Skip empty options. */
101 /* We know that *options is neither NUL or a comma. */
102 option_end
= options
+ 1;
103 while (*option_end
!= ',' && *option_end
!= '\0')
106 parse_aarch64_dis_option (options
, option_end
- options
);
108 /* Go on to the next one. If option_end points to a comma, it
109 will be skipped above. */
110 options
= option_end
;
114 /* Functions doing the instruction disassembling. */
116 /* The unnamed arguments consist of the number of fields and information about
117 these fields where the VALUE will be extracted from CODE and returned.
118 MASK can be zero or the base mask of the opcode.
120 N.B. the fields are required to be in such an order than the most signficant
121 field for VALUE comes the first, e.g. the <index> in
122 SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
123 is encoded in H:L:M in some cases, the fields H:L:M should be passed in
124 the order of H, L, M. */
126 static inline aarch64_insn
127 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...)
130 const aarch64_field
*field
;
131 enum aarch64_field_kind kind
;
135 num
= va_arg (va
, uint32_t);
137 aarch64_insn value
= 0x0;
140 kind
= va_arg (va
, enum aarch64_field_kind
);
141 field
= &fields
[kind
];
142 value
<<= field
->width
;
143 value
|= extract_field (kind
, code
, mask
);
148 /* Sign-extend bit I of VALUE. */
149 static inline int32_t
150 sign_extend (aarch64_insn value
, unsigned i
)
152 uint32_t ret
= value
;
155 if ((value
>> i
) & 0x1)
157 uint32_t val
= (uint32_t)(-1) << i
;
160 return (int32_t) ret
;
163 /* N.B. the following inline helpfer functions create a dependency on the
164 order of operand qualifier enumerators. */
166 /* Given VALUE, return qualifier for a general purpose register. */
167 static inline enum aarch64_opnd_qualifier
168 get_greg_qualifier_from_value (aarch64_insn value
)
170 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_W
+ value
;
172 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
176 /* Given VALUE, return qualifier for a vector register. */
177 static inline enum aarch64_opnd_qualifier
178 get_vreg_qualifier_from_value (aarch64_insn value
)
180 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_V_8B
+ value
;
183 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
187 /* Given VALUE, return qualifier for an FP or AdvSIMD scalar register. */
188 static inline enum aarch64_opnd_qualifier
189 get_sreg_qualifier_from_value (aarch64_insn value
)
191 enum aarch64_opnd_qualifier qualifier
= AARCH64_OPND_QLF_S_B
+ value
;
194 && aarch64_get_qualifier_standard_value (qualifier
) == value
);
198 /* Given the instruction in *INST which is probably half way through the
199 decoding and our caller wants to know the expected qualifier for operand
200 I. Return such a qualifier if we can establish it; otherwise return
201 AARCH64_OPND_QLF_NIL. */
203 static aarch64_opnd_qualifier_t
204 get_expected_qualifier (const aarch64_inst
*inst
, int i
)
206 aarch64_opnd_qualifier_seq_t qualifiers
;
207 /* Should not be called if the qualifier is known. */
208 assert (inst
->operands
[i
].qualifier
== AARCH64_OPND_QLF_NIL
);
209 if (aarch64_find_best_match (inst
, inst
->opcode
->qualifiers_list
,
211 return qualifiers
[i
];
213 return AARCH64_OPND_QLF_NIL
;
216 /* Operand extractors. */
219 aarch64_ext_regno (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
220 const aarch64_insn code
,
221 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
223 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
228 aarch64_ext_regno_pair (const aarch64_operand
*self ATTRIBUTE_UNUSED
, aarch64_opnd_info
*info
,
229 const aarch64_insn code ATTRIBUTE_UNUSED
,
230 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
232 assert (info
->idx
== 1
234 info
->reg
.regno
= inst
->operands
[info
->idx
- 1].reg
.regno
+ 1;
238 /* e.g. IC <ic_op>{, <Xt>}. */
240 aarch64_ext_regrt_sysins (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
241 const aarch64_insn code
,
242 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
244 info
->reg
.regno
= extract_field (self
->fields
[0], code
, 0);
245 assert (info
->idx
== 1
246 && (aarch64_get_operand_class (inst
->operands
[0].type
)
247 == AARCH64_OPND_CLASS_SYSTEM
));
248 /* This will make the constraint checking happy and more importantly will
249 help the disassembler determine whether this operand is optional or
251 info
->present
= inst
->operands
[0].sysins_op
->has_xt
;
256 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
258 aarch64_ext_reglane (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
259 const aarch64_insn code
,
260 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
263 info
->reglane
.regno
= extract_field (self
->fields
[0], code
,
266 /* Index and/or type. */
267 if (inst
->opcode
->iclass
== asisdone
268 || inst
->opcode
->iclass
== asimdins
)
270 if (info
->type
== AARCH64_OPND_En
271 && inst
->opcode
->operands
[0] == AARCH64_OPND_Ed
)
274 /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]. */
275 assert (info
->idx
== 1); /* Vn */
276 aarch64_insn value
= extract_field (FLD_imm4
, code
, 0);
277 /* Depend on AARCH64_OPND_Ed to determine the qualifier. */
278 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
279 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
280 info
->reglane
.index
= value
>> shift
;
284 /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
292 aarch64_insn value
= extract_field (FLD_imm5
, code
, 0);
293 while (++pos
<= 3 && (value
& 0x1) == 0)
297 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
298 info
->reglane
.index
= (unsigned) (value
>> 1);
303 /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
304 or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
306 /* Need information in other operand(s) to help decoding. */
307 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
308 switch (info
->qualifier
)
310 case AARCH64_OPND_QLF_S_H
:
312 info
->reglane
.index
= extract_fields (code
, 0, 3, FLD_H
, FLD_L
,
314 info
->reglane
.regno
&= 0xf;
316 case AARCH64_OPND_QLF_S_S
:
318 info
->reglane
.index
= extract_fields (code
, 0, 2, FLD_H
, FLD_L
);
320 case AARCH64_OPND_QLF_S_D
:
322 info
->reglane
.index
= extract_field (FLD_H
, code
, 0);
333 aarch64_ext_reglist (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
334 const aarch64_insn code
,
335 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
338 info
->reglist
.first_regno
= extract_field (self
->fields
[0], code
, 0);
340 info
->reglist
.num_regs
= extract_field (FLD_len
, code
, 0) + 1;
344 /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
346 aarch64_ext_ldst_reglist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
347 aarch64_opnd_info
*info
, const aarch64_insn code
,
348 const aarch64_inst
*inst
)
351 /* Number of elements in each structure to be loaded/stored. */
352 unsigned expected_num
= get_opcode_dependent_value (inst
->opcode
);
356 unsigned is_reserved
;
358 unsigned num_elements
;
374 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
376 value
= extract_field (FLD_opcode
, code
, 0);
377 if (expected_num
!= data
[value
].num_elements
|| data
[value
].is_reserved
)
379 info
->reglist
.num_regs
= data
[value
].num_regs
;
384 /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
385 lanes instructions. */
387 aarch64_ext_ldst_reglist_r (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
388 aarch64_opnd_info
*info
, const aarch64_insn code
,
389 const aarch64_inst
*inst
)
394 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
396 value
= extract_field (FLD_S
, code
, 0);
398 /* Number of registers is equal to the number of elements in
399 each structure to be loaded/stored. */
400 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
401 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
403 /* Except when it is LD1R. */
404 if (info
->reglist
.num_regs
== 1 && value
== (aarch64_insn
) 1)
405 info
->reglist
.num_regs
= 2;
410 /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
411 load/store single element instructions. */
413 aarch64_ext_ldst_elemlist (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
414 aarch64_opnd_info
*info
, const aarch64_insn code
,
415 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
417 aarch64_field field
= {0, 0};
418 aarch64_insn QSsize
; /* fields Q:S:size. */
419 aarch64_insn opcodeh2
; /* opcode<2:1> */
422 info
->reglist
.first_regno
= extract_field (FLD_Rt
, code
, 0);
424 /* Decode the index, opcode<2:1> and size. */
425 gen_sub_field (FLD_asisdlso_opcode
, 1, 2, &field
);
426 opcodeh2
= extract_field_2 (&field
, code
, 0);
427 QSsize
= extract_fields (code
, 0, 3, FLD_Q
, FLD_S
, FLD_vldst_size
);
431 info
->qualifier
= AARCH64_OPND_QLF_S_B
;
432 /* Index encoded in "Q:S:size". */
433 info
->reglist
.index
= QSsize
;
439 info
->qualifier
= AARCH64_OPND_QLF_S_H
;
440 /* Index encoded in "Q:S:size<1>". */
441 info
->reglist
.index
= QSsize
>> 1;
444 if ((QSsize
>> 1) & 0x1)
447 if ((QSsize
& 0x1) == 0)
449 info
->qualifier
= AARCH64_OPND_QLF_S_S
;
450 /* Index encoded in "Q:S". */
451 info
->reglist
.index
= QSsize
>> 2;
455 if (extract_field (FLD_S
, code
, 0))
458 info
->qualifier
= AARCH64_OPND_QLF_S_D
;
459 /* Index encoded in "Q". */
460 info
->reglist
.index
= QSsize
>> 3;
467 info
->reglist
.has_index
= 1;
468 info
->reglist
.num_regs
= 0;
469 /* Number of registers is equal to the number of elements in
470 each structure to be loaded/stored. */
471 info
->reglist
.num_regs
= get_opcode_dependent_value (inst
->opcode
);
472 assert (info
->reglist
.num_regs
>= 1 && info
->reglist
.num_regs
<= 4);
477 /* Decode fields immh:immb and/or Q for e.g.
478 SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
479 or SSHR <V><d>, <V><n>, #<shift>. */
482 aarch64_ext_advsimd_imm_shift (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
483 aarch64_opnd_info
*info
, const aarch64_insn code
,
484 const aarch64_inst
*inst
)
487 aarch64_insn Q
, imm
, immh
;
488 enum aarch64_insn_class iclass
= inst
->opcode
->iclass
;
490 immh
= extract_field (FLD_immh
, code
, 0);
493 imm
= extract_fields (code
, 0, 2, FLD_immh
, FLD_immb
);
495 /* Get highest set bit in immh. */
496 while (--pos
>= 0 && (immh
& 0x8) == 0)
499 assert ((iclass
== asimdshf
|| iclass
== asisdshf
)
500 && (info
->type
== AARCH64_OPND_IMM_VLSR
501 || info
->type
== AARCH64_OPND_IMM_VLSL
));
503 if (iclass
== asimdshf
)
505 Q
= extract_field (FLD_Q
, code
, 0);
507 0000 x SEE AdvSIMD modified immediate
517 get_vreg_qualifier_from_value ((pos
<< 1) | (int) Q
);
520 info
->qualifier
= get_sreg_qualifier_from_value (pos
);
522 if (info
->type
== AARCH64_OPND_IMM_VLSR
)
524 0000 SEE AdvSIMD modified immediate
525 0001 (16-UInt(immh:immb))
526 001x (32-UInt(immh:immb))
527 01xx (64-UInt(immh:immb))
528 1xxx (128-UInt(immh:immb)) */
529 info
->imm
.value
= (16 << pos
) - imm
;
533 0000 SEE AdvSIMD modified immediate
534 0001 (UInt(immh:immb)-8)
535 001x (UInt(immh:immb)-16)
536 01xx (UInt(immh:immb)-32)
537 1xxx (UInt(immh:immb)-64) */
538 info
->imm
.value
= imm
- (8 << pos
);
543 /* Decode shift immediate for e.g. sshr (imm). */
545 aarch64_ext_shll_imm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
546 aarch64_opnd_info
*info
, const aarch64_insn code
,
547 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
551 val
= extract_field (FLD_size
, code
, 0);
554 case 0: imm
= 8; break;
555 case 1: imm
= 16; break;
556 case 2: imm
= 32; break;
559 info
->imm
.value
= imm
;
563 /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
564 value in the field(s) will be extracted as unsigned immediate value. */
566 aarch64_ext_imm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
567 const aarch64_insn code
,
568 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
571 /* Maximum of two fields to extract. */
572 assert (self
->fields
[2] == FLD_NIL
);
574 if (self
->fields
[1] == FLD_NIL
)
575 imm
= extract_field (self
->fields
[0], code
, 0);
577 /* e.g. TBZ b5:b40. */
578 imm
= extract_fields (code
, 0, 2, self
->fields
[0], self
->fields
[1]);
580 if (info
->type
== AARCH64_OPND_FPIMM
)
583 if (operand_need_sign_extension (self
))
584 imm
= sign_extend (imm
, get_operand_fields_width (self
) - 1);
586 if (operand_need_shift_by_two (self
))
589 if (info
->type
== AARCH64_OPND_ADDR_ADRP
)
592 info
->imm
.value
= imm
;
596 /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
598 aarch64_ext_imm_half (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
599 const aarch64_insn code
,
600 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
602 aarch64_ext_imm (self
, info
, code
, inst
);
603 info
->shifter
.kind
= AARCH64_MOD_LSL
;
604 info
->shifter
.amount
= extract_field (FLD_hw
, code
, 0) << 4;
608 /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
609 MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
611 aarch64_ext_advsimd_imm_modified (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
612 aarch64_opnd_info
*info
,
613 const aarch64_insn code
,
614 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
617 enum aarch64_opnd_qualifier opnd0_qualifier
= inst
->operands
[0].qualifier
;
618 aarch64_field field
= {0, 0};
620 assert (info
->idx
== 1);
622 if (info
->type
== AARCH64_OPND_SIMD_FPIMM
)
625 /* a:b:c:d:e:f:g:h */
626 imm
= extract_fields (code
, 0, 2, FLD_abc
, FLD_defgh
);
627 if (!info
->imm
.is_fp
&& aarch64_get_qualifier_esize (opnd0_qualifier
) == 8)
629 /* Either MOVI <Dd>, #<imm>
630 or MOVI <Vd>.2D, #<imm>.
631 <imm> is a 64-bit immediate
632 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
633 encoded in "a:b:c:d:e:f:g:h". */
635 unsigned abcdefgh
= imm
;
636 for (imm
= 0ull, i
= 0; i
< 8; i
++)
637 if (((abcdefgh
>> i
) & 0x1) != 0)
638 imm
|= 0xffull
<< (8 * i
);
640 info
->imm
.value
= imm
;
643 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
644 switch (info
->qualifier
)
646 case AARCH64_OPND_QLF_NIL
:
648 info
->shifter
.kind
= AARCH64_MOD_NONE
;
650 case AARCH64_OPND_QLF_LSL
:
652 info
->shifter
.kind
= AARCH64_MOD_LSL
;
653 switch (aarch64_get_qualifier_esize (opnd0_qualifier
))
655 case 4: gen_sub_field (FLD_cmode
, 1, 2, &field
); break; /* per word */
656 case 2: gen_sub_field (FLD_cmode
, 1, 1, &field
); break; /* per half */
657 case 1: gen_sub_field (FLD_cmode
, 1, 0, &field
); break; /* per byte */
658 default: assert (0); return 0;
660 /* 00: 0; 01: 8; 10:16; 11:24. */
661 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) << 3;
663 case AARCH64_OPND_QLF_MSL
:
665 info
->shifter
.kind
= AARCH64_MOD_MSL
;
666 gen_sub_field (FLD_cmode
, 0, 1, &field
); /* per word */
667 info
->shifter
.amount
= extract_field_2 (&field
, code
, 0) ? 16 : 8;
677 /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
679 aarch64_ext_fbits (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
680 aarch64_opnd_info
*info
, const aarch64_insn code
,
681 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
683 info
->imm
.value
= 64- extract_field (FLD_scale
, code
, 0);
687 /* Decode arithmetic immediate for e.g.
688 SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
690 aarch64_ext_aimm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
691 aarch64_opnd_info
*info
, const aarch64_insn code
,
692 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
696 info
->shifter
.kind
= AARCH64_MOD_LSL
;
698 value
= extract_field (FLD_shift
, code
, 0);
701 info
->shifter
.amount
= value
? 12 : 0;
702 /* imm12 (unsigned) */
703 info
->imm
.value
= extract_field (FLD_imm12
, code
, 0);
708 /* Decode logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
711 aarch64_ext_limm (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
712 aarch64_opnd_info
*info
, const aarch64_insn code
,
713 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
721 value
= extract_fields (code
, 0, 3, FLD_N
, FLD_immr
, FLD_imms
);
722 assert (inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
723 || inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_X
);
724 sf
= aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
) != 4;
726 /* value is N:immr:imms. */
728 R
= (value
>> 6) & 0x3f;
729 N
= (value
>> 12) & 0x1;
731 if (sf
== 0 && N
== 1)
734 /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
735 (in other words, right rotated by R), then replicated. */
739 mask
= 0xffffffffffffffffull
;
745 case 0x00 ... 0x1f: /* 0xxxxx */ simd_size
= 32; break;
746 case 0x20 ... 0x2f: /* 10xxxx */ simd_size
= 16; S
&= 0xf; break;
747 case 0x30 ... 0x37: /* 110xxx */ simd_size
= 8; S
&= 0x7; break;
748 case 0x38 ... 0x3b: /* 1110xx */ simd_size
= 4; S
&= 0x3; break;
749 case 0x3c ... 0x3d: /* 11110x */ simd_size
= 2; S
&= 0x1; break;
752 mask
= (1ull << simd_size
) - 1;
753 /* Top bits are IGNORED. */
756 /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
757 if (S
== simd_size
- 1)
759 /* S+1 consecutive bits to 1. */
760 /* NOTE: S can't be 63 due to detection above. */
761 imm
= (1ull << (S
+ 1)) - 1;
762 /* Rotate to the left by simd_size - R. */
764 imm
= ((imm
<< (simd_size
- R
)) & mask
) | (imm
>> R
);
765 /* Replicate the value according to SIMD size. */
768 case 2: imm
= (imm
<< 2) | imm
;
769 case 4: imm
= (imm
<< 4) | imm
;
770 case 8: imm
= (imm
<< 8) | imm
;
771 case 16: imm
= (imm
<< 16) | imm
;
772 case 32: imm
= (imm
<< 32) | imm
;
774 default: assert (0); return 0;
777 info
->imm
.value
= sf
? imm
: imm
& 0xffffffff;
782 /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
783 or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
785 aarch64_ext_ft (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
786 aarch64_opnd_info
*info
,
787 const aarch64_insn code
, const aarch64_inst
*inst
)
792 info
->reg
.regno
= extract_field (FLD_Rt
, code
, 0);
795 value
= extract_field (FLD_ldst_size
, code
, 0);
796 if (inst
->opcode
->iclass
== ldstpair_indexed
797 || inst
->opcode
->iclass
== ldstnapair_offs
798 || inst
->opcode
->iclass
== ldstpair_off
799 || inst
->opcode
->iclass
== loadlit
)
801 enum aarch64_opnd_qualifier qualifier
;
804 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
805 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
806 case 2: qualifier
= AARCH64_OPND_QLF_S_Q
; break;
809 info
->qualifier
= qualifier
;
814 value
= extract_fields (code
, 0, 2, FLD_opc1
, FLD_ldst_size
);
817 info
->qualifier
= get_sreg_qualifier_from_value (value
);
823 /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
825 aarch64_ext_addr_simple (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
826 aarch64_opnd_info
*info
,
828 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
831 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
835 /* Decode the address operand for e.g.
836 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
838 aarch64_ext_addr_regoff (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
839 aarch64_opnd_info
*info
,
840 aarch64_insn code
, const aarch64_inst
*inst
)
842 aarch64_insn S
, value
;
845 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
847 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
849 value
= extract_field (FLD_option
, code
, 0);
851 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
852 /* Fix-up the shifter kind; although the table-driven approach is
853 efficient, it is slightly inflexible, thus needing this fix-up. */
854 if (info
->shifter
.kind
== AARCH64_MOD_UXTX
)
855 info
->shifter
.kind
= AARCH64_MOD_LSL
;
857 S
= extract_field (FLD_S
, code
, 0);
860 info
->shifter
.amount
= 0;
861 info
->shifter
.amount_present
= 0;
866 /* Need information in other operand(s) to help achieve the decoding
868 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
869 /* Get the size of the data element that is accessed, which may be
870 different from that of the source register size, e.g. in strb/ldrb. */
871 size
= aarch64_get_qualifier_esize (info
->qualifier
);
872 info
->shifter
.amount
= get_logsz (size
);
873 info
->shifter
.amount_present
= 1;
879 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
881 aarch64_ext_addr_simm (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
882 aarch64_insn code
, const aarch64_inst
*inst
)
885 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
888 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
889 /* simm (imm9 or imm7) */
890 imm
= extract_field (self
->fields
[0], code
, 0);
891 info
->addr
.offset
.imm
= sign_extend (imm
, fields
[self
->fields
[0]].width
- 1);
892 if (self
->fields
[0] == FLD_imm7
)
893 /* scaled immediate in ld/st pair instructions. */
894 info
->addr
.offset
.imm
*= aarch64_get_qualifier_esize (info
->qualifier
);
896 if (inst
->opcode
->iclass
== ldst_unscaled
897 || inst
->opcode
->iclass
== ldstnapair_offs
898 || inst
->opcode
->iclass
== ldstpair_off
899 || inst
->opcode
->iclass
== ldst_unpriv
)
900 info
->addr
.writeback
= 0;
903 /* pre/post- index */
904 info
->addr
.writeback
= 1;
905 if (extract_field (self
->fields
[1], code
, 0) == 1)
906 info
->addr
.preind
= 1;
908 info
->addr
.postind
= 1;
914 /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
916 aarch64_ext_addr_uimm12 (const aarch64_operand
*self
, aarch64_opnd_info
*info
,
918 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
921 info
->qualifier
= get_expected_qualifier (inst
, info
->idx
);
922 shift
= get_logsz (aarch64_get_qualifier_esize (info
->qualifier
));
924 info
->addr
.base_regno
= extract_field (self
->fields
[0], code
, 0);
926 info
->addr
.offset
.imm
= extract_field (self
->fields
[1], code
, 0) << shift
;
930 /* Decode the address operand for e.g.
931 LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
933 aarch64_ext_simd_addr_post (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
934 aarch64_opnd_info
*info
,
935 aarch64_insn code
, const aarch64_inst
*inst
)
937 /* The opcode dependent area stores the number of elements in
938 each structure to be loaded/stored. */
939 int is_ld1r
= get_opcode_dependent_value (inst
->opcode
) == 1;
942 info
->addr
.base_regno
= extract_field (FLD_Rn
, code
, 0);
944 info
->addr
.offset
.regno
= extract_field (FLD_Rm
, code
, 0);
945 if (info
->addr
.offset
.regno
== 31)
947 if (inst
->opcode
->operands
[0] == AARCH64_OPND_LVt_AL
)
948 /* Special handling of loading single structure to all lane. */
949 info
->addr
.offset
.imm
= (is_ld1r
? 1
950 : inst
->operands
[0].reglist
.num_regs
)
951 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
);
953 info
->addr
.offset
.imm
= inst
->operands
[0].reglist
.num_regs
954 * aarch64_get_qualifier_esize (inst
->operands
[0].qualifier
)
955 * aarch64_get_qualifier_nelem (inst
->operands
[0].qualifier
);
958 info
->addr
.offset
.is_reg
= 1;
959 info
->addr
.writeback
= 1;
964 /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
966 aarch64_ext_cond (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
967 aarch64_opnd_info
*info
,
968 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
972 value
= extract_field (FLD_cond
, code
, 0);
973 info
->cond
= get_cond_from_value (value
);
977 /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
979 aarch64_ext_sysreg (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
980 aarch64_opnd_info
*info
,
982 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
984 /* op0:op1:CRn:CRm:op2 */
985 info
->sysreg
= extract_fields (code
, 0, 5, FLD_op0
, FLD_op1
, FLD_CRn
,
990 /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
992 aarch64_ext_pstatefield (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
993 aarch64_opnd_info
*info
, aarch64_insn code
,
994 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
998 info
->pstatefield
= extract_fields (code
, 0, 2, FLD_op1
, FLD_op2
);
999 for (i
= 0; aarch64_pstatefields
[i
].name
!= NULL
; ++i
)
1000 if (aarch64_pstatefields
[i
].value
== (aarch64_insn
)info
->pstatefield
)
1002 /* Reserved value in <pstatefield>. */
1006 /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
1008 aarch64_ext_sysins_op (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1009 aarch64_opnd_info
*info
,
1011 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1015 const aarch64_sys_ins_reg
*sysins_ops
;
1016 /* op0:op1:CRn:CRm:op2 */
1017 value
= extract_fields (code
, 0, 5,
1018 FLD_op0
, FLD_op1
, FLD_CRn
,
1023 case AARCH64_OPND_SYSREG_AT
: sysins_ops
= aarch64_sys_regs_at
; break;
1024 case AARCH64_OPND_SYSREG_DC
: sysins_ops
= aarch64_sys_regs_dc
; break;
1025 case AARCH64_OPND_SYSREG_IC
: sysins_ops
= aarch64_sys_regs_ic
; break;
1026 case AARCH64_OPND_SYSREG_TLBI
: sysins_ops
= aarch64_sys_regs_tlbi
; break;
1027 default: assert (0); return 0;
1030 for (i
= 0; sysins_ops
[i
].name
!= NULL
; ++i
)
1031 if (sysins_ops
[i
].value
== value
)
1033 info
->sysins_op
= sysins_ops
+ i
;
1034 DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
1035 info
->sysins_op
->name
,
1036 (unsigned)info
->sysins_op
->value
,
1037 info
->sysins_op
->has_xt
, i
);
1044 /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
1047 aarch64_ext_barrier (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1048 aarch64_opnd_info
*info
,
1050 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1053 info
->barrier
= aarch64_barrier_options
+ extract_field (FLD_CRm
, code
, 0);
1057 /* Decode the prefetch operation option operand for e.g.
1058 PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
1061 aarch64_ext_prfop (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1062 aarch64_opnd_info
*info
,
1063 aarch64_insn code
, const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1066 info
->prfop
= aarch64_prfops
+ extract_field (FLD_Rt
, code
, 0);
1070 /* Decode the extended register operand for e.g.
1071 STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1073 aarch64_ext_reg_extended (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1074 aarch64_opnd_info
*info
,
1076 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1081 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1083 value
= extract_field (FLD_option
, code
, 0);
1084 info
->shifter
.kind
=
1085 aarch64_get_operand_modifier_from_value (value
, TRUE
/* extend_p */);
1087 info
->shifter
.amount
= extract_field (FLD_imm3
, code
, 0);
1089 /* This makes the constraint checking happy. */
1090 info
->shifter
.operator_present
= 1;
1092 /* Assume inst->operands[0].qualifier has been resolved. */
1093 assert (inst
->operands
[0].qualifier
!= AARCH64_OPND_QLF_NIL
);
1094 info
->qualifier
= AARCH64_OPND_QLF_W
;
1095 if (inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_X
1096 && (info
->shifter
.kind
== AARCH64_MOD_UXTX
1097 || info
->shifter
.kind
== AARCH64_MOD_SXTX
))
1098 info
->qualifier
= AARCH64_OPND_QLF_X
;
1103 /* Decode the shifted register operand for e.g.
1104 SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
1106 aarch64_ext_reg_shifted (const aarch64_operand
*self ATTRIBUTE_UNUSED
,
1107 aarch64_opnd_info
*info
,
1109 const aarch64_inst
*inst ATTRIBUTE_UNUSED
)
1114 info
->reg
.regno
= extract_field (FLD_Rm
, code
, 0);
1116 value
= extract_field (FLD_shift
, code
, 0);
1117 info
->shifter
.kind
=
1118 aarch64_get_operand_modifier_from_value (value
, FALSE
/* extend_p */);
1119 if (info
->shifter
.kind
== AARCH64_MOD_ROR
1120 && inst
->opcode
->iclass
!= log_shift
)
1121 /* ROR is not available for the shifted register operand in arithmetic
1125 info
->shifter
.amount
= extract_field (FLD_imm6
, code
, 0);
1127 /* This makes the constraint checking happy. */
1128 info
->shifter
.operator_present
= 1;
1133 /* Bitfields that are commonly used to encode certain operands' information
1134 may be partially used as part of the base opcode in some instructions.
1135 For example, the bit 1 of the field 'size' in
1136 FCVTXN <Vb><d>, <Va><n>
1137 is actually part of the base opcode, while only size<0> is available
1138 for encoding the register type. Another example is the AdvSIMD
1139 instruction ORR (register), in which the field 'size' is also used for
1140 the base opcode, leaving only the field 'Q' available to encode the
1141 vector register arrangement specifier '8B' or '16B'.
1143 This function tries to deduce the qualifier from the value of partially
1144 constrained field(s). Given the VALUE of such a field or fields, the
1145 qualifiers CANDIDATES and the MASK (indicating which bits are valid for
1146 operand encoding), the function returns the matching qualifier or
1147 AARCH64_OPND_QLF_NIL if nothing matches.
1149 N.B. CANDIDATES is a group of possible qualifiers that are valid for
1150 one operand; it has a maximum of AARCH64_MAX_QLF_SEQ_NUM qualifiers and
1151 may end with AARCH64_OPND_QLF_NIL. */
1153 static enum aarch64_opnd_qualifier
1154 get_qualifier_from_partial_encoding (aarch64_insn value
,
1155 const enum aarch64_opnd_qualifier
* \
1160 DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value
, (int)mask
);
1161 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1163 aarch64_insn standard_value
;
1164 if (candidates
[i
] == AARCH64_OPND_QLF_NIL
)
1166 standard_value
= aarch64_get_qualifier_standard_value (candidates
[i
]);
1167 if ((standard_value
& mask
) == (value
& mask
))
1168 return candidates
[i
];
1170 return AARCH64_OPND_QLF_NIL
;
1173 /* Given a list of qualifier sequences, return all possible valid qualifiers
1174 for operand IDX in QUALIFIERS.
1175 Assume QUALIFIERS is an array whose length is large enough. */
1178 get_operand_possible_qualifiers (int idx
,
1179 const aarch64_opnd_qualifier_seq_t
*list
,
1180 enum aarch64_opnd_qualifier
*qualifiers
)
1183 for (i
= 0; i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1184 if ((qualifiers
[i
] = list
[i
][idx
]) == AARCH64_OPND_QLF_NIL
)
1188 /* Decode the size Q field for e.g. SHADD.
1189 We tag one operand with the qualifer according to the code;
1190 whether the qualifier is valid for this opcode or not, it is the
1191 duty of the semantic checking. */
1194 decode_sizeq (aarch64_inst
*inst
)
1197 enum aarch64_opnd_qualifier qualifier
;
1199 aarch64_insn value
, mask
;
1200 enum aarch64_field_kind fld_sz
;
1201 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1203 if (inst
->opcode
->iclass
== asisdlse
1204 || inst
->opcode
->iclass
== asisdlsep
1205 || inst
->opcode
->iclass
== asisdlso
1206 || inst
->opcode
->iclass
== asisdlsop
)
1207 fld_sz
= FLD_vldst_size
;
1212 value
= extract_fields (code
, inst
->opcode
->mask
, 2, fld_sz
, FLD_Q
);
1213 /* Obtain the info that which bits of fields Q and size are actually
1214 available for operand encoding. Opcodes like FMAXNM and FMLA have
1215 size[1] unavailable. */
1216 mask
= extract_fields (~inst
->opcode
->mask
, 0, 2, fld_sz
, FLD_Q
);
1218 /* The index of the operand we are going to tag a qualifier and the qualifer
1219 itself are reasoned from the value of the size and Q fields and the
1220 possible valid qualifier lists. */
1221 idx
= aarch64_select_operand_for_sizeq_field_coding (inst
->opcode
);
1222 DEBUG_TRACE ("key idx: %d", idx
);
1224 /* For most related instruciton, size:Q are fully available for operand
1228 inst
->operands
[idx
].qualifier
= get_vreg_qualifier_from_value (value
);
1232 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1234 #ifdef DEBUG_AARCH64
1238 for (i
= 0; candidates
[i
] != AARCH64_OPND_QLF_NIL
1239 && i
< AARCH64_MAX_QLF_SEQ_NUM
; ++i
)
1240 DEBUG_TRACE ("qualifier %d: %s", i
,
1241 aarch64_get_qualifier_name(candidates
[i
]));
1242 DEBUG_TRACE ("%d, %d", (int)value
, (int)mask
);
1244 #endif /* DEBUG_AARCH64 */
1246 qualifier
= get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1248 if (qualifier
== AARCH64_OPND_QLF_NIL
)
1251 inst
->operands
[idx
].qualifier
= qualifier
;
1255 /* Decode size[0]:Q, i.e. bit 22 and bit 30, for
1256 e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1259 decode_asimd_fcvt (aarch64_inst
*inst
)
1261 aarch64_field field
= {0, 0};
1263 enum aarch64_opnd_qualifier qualifier
;
1265 gen_sub_field (FLD_size
, 0, 1, &field
);
1266 value
= extract_field_2 (&field
, inst
->value
, 0);
1267 qualifier
= value
== 0 ? AARCH64_OPND_QLF_V_4S
1268 : AARCH64_OPND_QLF_V_2D
;
1269 switch (inst
->opcode
->op
)
1273 /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
1274 inst
->operands
[1].qualifier
= qualifier
;
1278 /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
1279 inst
->operands
[0].qualifier
= qualifier
;
1289 /* Decode size[0], i.e. bit 22, for
1290 e.g. FCVTXN <Vb><d>, <Va><n>. */
1293 decode_asisd_fcvtxn (aarch64_inst
*inst
)
1295 aarch64_field field
= {0, 0};
1296 gen_sub_field (FLD_size
, 0, 1, &field
);
1297 if (!extract_field_2 (&field
, inst
->value
, 0))
1299 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_S_S
;
1303 /* Decode the 'opc' field for e.g. FCVT <Dd>, <Sn>. */
1305 decode_fcvt (aarch64_inst
*inst
)
1307 enum aarch64_opnd_qualifier qualifier
;
1309 const aarch64_field field
= {15, 2};
1312 value
= extract_field_2 (&field
, inst
->value
, 0);
1315 case 0: qualifier
= AARCH64_OPND_QLF_S_S
; break;
1316 case 1: qualifier
= AARCH64_OPND_QLF_S_D
; break;
1317 case 3: qualifier
= AARCH64_OPND_QLF_S_H
; break;
1320 inst
->operands
[0].qualifier
= qualifier
;
1325 /* Do miscellaneous decodings that are not common enough to be driven by
1329 do_misc_decoding (aarch64_inst
*inst
)
1331 switch (inst
->opcode
->op
)
1334 return decode_fcvt (inst
);
1339 return decode_asimd_fcvt (inst
);
1341 return decode_asisd_fcvtxn (inst
);
1347 /* Opcodes that have fields shared by multiple operands are usually flagged
1348 with flags. In this function, we detect such flags, decode the related
1349 field(s) and store the information in one of the related operands. The
1350 'one' operand is not any operand but one of the operands that can
1351 accommadate all the information that has been decoded. */
1354 do_special_decoding (aarch64_inst
*inst
)
1358 /* Condition for truly conditional executed instructions, e.g. b.cond. */
1359 if (inst
->opcode
->flags
& F_COND
)
1361 value
= extract_field (FLD_cond2
, inst
->value
, 0);
1362 inst
->cond
= get_cond_from_value (value
);
1365 if (inst
->opcode
->flags
& F_SF
)
1367 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
1368 value
= extract_field (FLD_sf
, inst
->value
, 0);
1369 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1370 if ((inst
->opcode
->flags
& F_N
)
1371 && extract_field (FLD_N
, inst
->value
, 0) != value
)
1375 if (inst
->opcode
->flags
& F_LSE_SZ
)
1377 idx
= select_operand_for_sf_field_coding (inst
->opcode
);
1378 value
= extract_field (FLD_lse_sz
, inst
->value
, 0);
1379 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1381 /* size:Q fields. */
1382 if (inst
->opcode
->flags
& F_SIZEQ
)
1383 return decode_sizeq (inst
);
1385 if (inst
->opcode
->flags
& F_FPTYPE
)
1387 idx
= select_operand_for_fptype_field_coding (inst
->opcode
);
1388 value
= extract_field (FLD_type
, inst
->value
, 0);
1391 case 0: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_S
; break;
1392 case 1: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_D
; break;
1393 case 3: inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_S_H
; break;
1398 if (inst
->opcode
->flags
& F_SSIZE
)
1400 /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
1401 of the base opcode. */
1403 enum aarch64_opnd_qualifier candidates
[AARCH64_MAX_QLF_SEQ_NUM
];
1404 idx
= select_operand_for_scalar_size_field_coding (inst
->opcode
);
1405 value
= extract_field (FLD_size
, inst
->value
, inst
->opcode
->mask
);
1406 mask
= extract_field (FLD_size
, ~inst
->opcode
->mask
, 0);
1407 /* For most related instruciton, the 'size' field is fully available for
1408 operand encoding. */
1410 inst
->operands
[idx
].qualifier
= get_sreg_qualifier_from_value (value
);
1413 get_operand_possible_qualifiers (idx
, inst
->opcode
->qualifiers_list
,
1415 inst
->operands
[idx
].qualifier
1416 = get_qualifier_from_partial_encoding (value
, candidates
, mask
);
1420 if (inst
->opcode
->flags
& F_T
)
1422 /* Num of consecutive '0's on the right side of imm5<3:0>. */
1425 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1426 == AARCH64_OPND_CLASS_SIMD_REG
);
1437 val
= extract_field (FLD_imm5
, inst
->value
, 0);
1438 while ((val
& 0x1) == 0 && ++num
<= 3)
1442 Q
= (unsigned) extract_field (FLD_Q
, inst
->value
, inst
->opcode
->mask
);
1443 inst
->operands
[0].qualifier
=
1444 get_vreg_qualifier_from_value ((num
<< 1) | Q
);
1447 if (inst
->opcode
->flags
& F_GPRSIZE_IN_Q
)
1449 /* Use Rt to encode in the case of e.g.
1450 STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1451 idx
= aarch64_operand_index (inst
->opcode
->operands
, AARCH64_OPND_Rt
);
1454 /* Otherwise use the result operand, which has to be a integer
1456 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1457 == AARCH64_OPND_CLASS_INT_REG
);
1460 assert (idx
== 0 || idx
== 1);
1461 value
= extract_field (FLD_Q
, inst
->value
, 0);
1462 inst
->operands
[idx
].qualifier
= get_greg_qualifier_from_value (value
);
1465 if (inst
->opcode
->flags
& F_LDS_SIZE
)
1467 aarch64_field field
= {0, 0};
1468 assert (aarch64_get_operand_class (inst
->opcode
->operands
[0])
1469 == AARCH64_OPND_CLASS_INT_REG
);
1470 gen_sub_field (FLD_opc
, 0, 1, &field
);
1471 value
= extract_field_2 (&field
, inst
->value
, 0);
1472 inst
->operands
[0].qualifier
1473 = value
? AARCH64_OPND_QLF_W
: AARCH64_OPND_QLF_X
;
1476 /* Miscellaneous decoding; done as the last step. */
1477 if (inst
->opcode
->flags
& F_MISC
)
1478 return do_misc_decoding (inst
);
1483 /* Converters converting a real opcode instruction to its alias form. */
1485 /* ROR <Wd>, <Ws>, #<shift>
1487 EXTR <Wd>, <Ws>, <Ws>, #<shift>. */
1489 convert_extr_to_ror (aarch64_inst
*inst
)
1491 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
1493 copy_operand_info (inst
, 2, 3);
1494 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1500 /* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
1502 USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0. */
1504 convert_shll_to_xtl (aarch64_inst
*inst
)
1506 if (inst
->operands
[2].imm
.value
== 0)
1508 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
1515 UBFM <Xd>, <Xn>, #<shift>, #63.
1517 LSR <Xd>, <Xn>, #<shift>. */
1519 convert_bfm_to_sr (aarch64_inst
*inst
)
1523 imms
= inst
->operands
[3].imm
.value
;
1524 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
1527 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1534 /* Convert MOV to ORR. */
1536 convert_orr_to_mov (aarch64_inst
*inst
)
1538 /* MOV <Vd>.<T>, <Vn>.<T>
1540 ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>. */
1541 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
)
1543 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
1549 /* When <imms> >= <immr>, the instruction written:
1550 SBFX <Xd>, <Xn>, #<lsb>, #<width>
1552 SBFM <Xd>, <Xn>, #<lsb>, #(<lsb>+<width>-1). */
1555 convert_bfm_to_bfx (aarch64_inst
*inst
)
1559 immr
= inst
->operands
[2].imm
.value
;
1560 imms
= inst
->operands
[3].imm
.value
;
1564 inst
->operands
[2].imm
.value
= lsb
;
1565 inst
->operands
[3].imm
.value
= imms
+ 1 - lsb
;
1566 /* The two opcodes have different qualifiers for
1567 the immediate operands; reset to help the checking. */
1568 reset_operand_qualifier (inst
, 2);
1569 reset_operand_qualifier (inst
, 3);
1576 /* When <imms> < <immr>, the instruction written:
1577 SBFIZ <Xd>, <Xn>, #<lsb>, #<width>
1579 SBFM <Xd>, <Xn>, #((64-<lsb>)&0x3f), #(<width>-1). */
1582 convert_bfm_to_bfi (aarch64_inst
*inst
)
1584 int64_t immr
, imms
, val
;
1586 immr
= inst
->operands
[2].imm
.value
;
1587 imms
= inst
->operands
[3].imm
.value
;
1588 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
1591 inst
->operands
[2].imm
.value
= (val
- immr
) & (val
- 1);
1592 inst
->operands
[3].imm
.value
= imms
+ 1;
1593 /* The two opcodes have different qualifiers for
1594 the immediate operands; reset to help the checking. */
1595 reset_operand_qualifier (inst
, 2);
1596 reset_operand_qualifier (inst
, 3);
1603 /* The instruction written:
1604 BFC <Xd>, #<lsb>, #<width>
1606 BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */
1609 convert_bfm_to_bfc (aarch64_inst
*inst
)
1611 int64_t immr
, imms
, val
;
1613 /* Should have been assured by the base opcode value. */
1614 assert (inst
->operands
[1].reg
.regno
== 0x1f);
1616 immr
= inst
->operands
[2].imm
.value
;
1617 imms
= inst
->operands
[3].imm
.value
;
1618 val
= inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 32 : 64;
1621 /* Drop XZR from the second operand. */
1622 copy_operand_info (inst
, 1, 2);
1623 copy_operand_info (inst
, 2, 3);
1624 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1626 /* Recalculate the immediates. */
1627 inst
->operands
[1].imm
.value
= (val
- immr
) & (val
- 1);
1628 inst
->operands
[2].imm
.value
= imms
+ 1;
1630 /* The two opcodes have different qualifiers for the operands; reset to
1631 help the checking. */
1632 reset_operand_qualifier (inst
, 1);
1633 reset_operand_qualifier (inst
, 2);
1634 reset_operand_qualifier (inst
, 3);
1642 /* The instruction written:
1643 LSL <Xd>, <Xn>, #<shift>
1645 UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */
1648 convert_ubfm_to_lsl (aarch64_inst
*inst
)
1650 int64_t immr
= inst
->operands
[2].imm
.value
;
1651 int64_t imms
= inst
->operands
[3].imm
.value
;
1653 = inst
->operands
[2].qualifier
== AARCH64_OPND_QLF_imm_0_31
? 31 : 63;
1655 if ((immr
== 0 && imms
== val
) || immr
== imms
+ 1)
1657 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1658 inst
->operands
[2].imm
.value
= val
- imms
;
1665 /* CINC <Wd>, <Wn>, <cond>
1667 CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
1668 where <cond> is not AL or NV. */
1671 convert_from_csel (aarch64_inst
*inst
)
1673 if (inst
->operands
[1].reg
.regno
== inst
->operands
[2].reg
.regno
1674 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
1676 copy_operand_info (inst
, 2, 3);
1677 inst
->operands
[2].cond
= get_inverted_cond (inst
->operands
[3].cond
);
1678 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1684 /* CSET <Wd>, <cond>
1686 CSINC <Wd>, WZR, WZR, invert(<cond>)
1687 where <cond> is not AL or NV. */
1690 convert_csinc_to_cset (aarch64_inst
*inst
)
1692 if (inst
->operands
[1].reg
.regno
== 0x1f
1693 && inst
->operands
[2].reg
.regno
== 0x1f
1694 && (inst
->operands
[3].cond
->value
& 0xe) != 0xe)
1696 copy_operand_info (inst
, 1, 3);
1697 inst
->operands
[1].cond
= get_inverted_cond (inst
->operands
[3].cond
);
1698 inst
->operands
[3].type
= AARCH64_OPND_NIL
;
1699 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
1707 MOVZ <Wd>, #<imm16>, LSL #<shift>.
1709 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
1710 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
1711 or where a MOVN has an immediate that could be encoded by MOVZ, or where
1712 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
1713 machine-instruction mnemonic must be used. */
1716 convert_movewide_to_mov (aarch64_inst
*inst
)
1718 uint64_t value
= inst
->operands
[1].imm
.value
;
1719 /* MOVZ/MOVN #0 have a shift amount other than LSL #0. */
1720 if (value
== 0 && inst
->operands
[1].shifter
.amount
!= 0)
1722 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
1723 inst
->operands
[1].shifter
.kind
= AARCH64_MOD_NONE
;
1724 value
<<= inst
->operands
[1].shifter
.amount
;
1725 /* As an alias convertor, it has to be clear that the INST->OPCODE
1726 is the opcode of the real instruction. */
1727 if (inst
->opcode
->op
== OP_MOVN
)
1729 int is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
1731 /* A MOVN has an immediate that could be encoded by MOVZ. */
1732 if (aarch64_wide_constant_p (value
, is32
, NULL
) == TRUE
)
1735 inst
->operands
[1].imm
.value
= value
;
1736 inst
->operands
[1].shifter
.amount
= 0;
1742 ORR <Wd>, WZR, #<imm>.
1744 A disassembler may output ORR, MOVZ and MOVN as a MOV mnemonic, except when
1745 ORR has an immediate that could be generated by a MOVZ or MOVN instruction,
1746 or where a MOVN has an immediate that could be encoded by MOVZ, or where
1747 MOVZ/MOVN #0 have a shift amount other than LSL #0, in which case the
1748 machine-instruction mnemonic must be used. */
1751 convert_movebitmask_to_mov (aarch64_inst
*inst
)
1756 /* Should have been assured by the base opcode value. */
1757 assert (inst
->operands
[1].reg
.regno
== 0x1f);
1758 copy_operand_info (inst
, 1, 2);
1759 is32
= inst
->operands
[0].qualifier
== AARCH64_OPND_QLF_W
;
1760 inst
->operands
[1].type
= AARCH64_OPND_IMM_MOV
;
1761 value
= inst
->operands
[1].imm
.value
;
1762 /* ORR has an immediate that could be generated by a MOVZ or MOVN
1764 if (inst
->operands
[0].reg
.regno
!= 0x1f
1765 && (aarch64_wide_constant_p (value
, is32
, NULL
) == TRUE
1766 || aarch64_wide_constant_p (~value
, is32
, NULL
) == TRUE
))
1769 inst
->operands
[2].type
= AARCH64_OPND_NIL
;
1773 /* Some alias opcodes are disassembled by being converted from their real-form.
1774 N.B. INST->OPCODE is the real opcode rather than the alias. */
1777 convert_to_alias (aarch64_inst
*inst
, const aarch64_opcode
*alias
)
1783 return convert_bfm_to_sr (inst
);
1785 return convert_ubfm_to_lsl (inst
);
1789 return convert_from_csel (inst
);
1792 return convert_csinc_to_cset (inst
);
1796 return convert_bfm_to_bfx (inst
);
1800 return convert_bfm_to_bfi (inst
);
1802 return convert_bfm_to_bfc (inst
);
1804 return convert_orr_to_mov (inst
);
1805 case OP_MOV_IMM_WIDE
:
1806 case OP_MOV_IMM_WIDEN
:
1807 return convert_movewide_to_mov (inst
);
1808 case OP_MOV_IMM_LOG
:
1809 return convert_movebitmask_to_mov (inst
);
1811 return convert_extr_to_ror (inst
);
1816 return convert_shll_to_xtl (inst
);
1822 static int aarch64_opcode_decode (const aarch64_opcode
*, const aarch64_insn
,
1823 aarch64_inst
*, int);
1825 /* Given the instruction information in *INST, check if the instruction has
1826 any alias form that can be used to represent *INST. If the answer is yes,
1827 update *INST to be in the form of the determined alias. */
1829 /* In the opcode description table, the following flags are used in opcode
1830 entries to help establish the relations between the real and alias opcodes:
1832 F_ALIAS: opcode is an alias
1833 F_HAS_ALIAS: opcode has alias(es)
1836 F_P3: Disassembly preference priority 1-3 (the larger the
1837 higher). If nothing is specified, it is the priority
1838 0 by default, i.e. the lowest priority.
1840 Although the relation between the machine and the alias instructions are not
1841 explicitly described, it can be easily determined from the base opcode
1842 values, masks and the flags F_ALIAS and F_HAS_ALIAS in their opcode
1843 description entries:
1845 The mask of an alias opcode must be equal to or a super-set (i.e. more
1846 constrained) of that of the aliased opcode; so is the base opcode value.
1848 if (opcode_has_alias (real) && alias_opcode_p (opcode)
1849 && (opcode->mask & real->mask) == real->mask
1850 && (real->mask & opcode->opcode) == (real->mask & real->opcode))
1851 then OPCODE is an alias of, and only of, the REAL instruction
1853 The alias relationship is forced flat-structured to keep related algorithm
1854 simple; an opcode entry cannot be flagged with both F_ALIAS and F_HAS_ALIAS.
1856 During the disassembling, the decoding decision tree (in
1857 opcodes/aarch64-dis-2.c) always returns an machine instruction opcode entry;
1858 if the decoding of such a machine instruction succeeds (and -Mno-aliases is
1859 not specified), the disassembler will check whether there is any alias
1860 instruction exists for this real instruction. If there is, the disassembler
1861 will try to disassemble the 32-bit binary again using the alias's rule, or
1862 try to convert the IR to the form of the alias. In the case of the multiple
1863 aliases, the aliases are tried one by one from the highest priority
1864 (currently the flag F_P3) to the lowest priority (no priority flag), and the
1865 first succeeds first adopted.
1867 You may ask why there is a need for the conversion of IR from one form to
1868 another in handling certain aliases. This is because on one hand it avoids
1869 adding more operand code to handle unusual encoding/decoding; on other
1870 hand, during the disassembling, the conversion is an effective approach to
1871 check the condition of an alias (as an alias may be adopted only if certain
1872 conditions are met).
1874 In order to speed up the alias opcode lookup, aarch64-gen has preprocessed
1875 aarch64_opcode_table and generated aarch64_find_alias_opcode and
1876 aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
1879 determine_disassembling_preference (struct aarch64_inst
*inst
)
1881 const aarch64_opcode
*opcode
;
1882 const aarch64_opcode
*alias
;
1884 opcode
= inst
->opcode
;
1886 /* This opcode does not have an alias, so use itself. */
1887 if (opcode_has_alias (opcode
) == FALSE
)
1890 alias
= aarch64_find_alias_opcode (opcode
);
1893 #ifdef DEBUG_AARCH64
1896 const aarch64_opcode
*tmp
= alias
;
1897 printf ("#### LIST orderd: ");
1900 printf ("%s, ", tmp
->name
);
1901 tmp
= aarch64_find_next_alias_opcode (tmp
);
1905 #endif /* DEBUG_AARCH64 */
1907 for (; alias
; alias
= aarch64_find_next_alias_opcode (alias
))
1909 DEBUG_TRACE ("try %s", alias
->name
);
1910 assert (alias_opcode_p (alias
) || opcode_has_alias (opcode
));
1912 /* An alias can be a pseudo opcode which will never be used in the
1913 disassembly, e.g. BIC logical immediate is such a pseudo opcode
1915 if (pseudo_opcode_p (alias
))
1917 DEBUG_TRACE ("skip pseudo %s", alias
->name
);
1921 if ((inst
->value
& alias
->mask
) != alias
->opcode
)
1923 DEBUG_TRACE ("skip %s as base opcode not match", alias
->name
);
1926 /* No need to do any complicated transformation on operands, if the alias
1927 opcode does not have any operand. */
1928 if (aarch64_num_of_operands (alias
) == 0 && alias
->opcode
== inst
->value
)
1930 DEBUG_TRACE ("succeed with 0-operand opcode %s", alias
->name
);
1931 aarch64_replace_opcode (inst
, alias
);
1934 if (alias
->flags
& F_CONV
)
1937 memcpy (©
, inst
, sizeof (aarch64_inst
));
1938 /* ALIAS is the preference as long as the instruction can be
1939 successfully converted to the form of ALIAS. */
1940 if (convert_to_alias (©
, alias
) == 1)
1942 aarch64_replace_opcode (©
, alias
);
1943 assert (aarch64_match_operands_constraint (©
, NULL
));
1944 DEBUG_TRACE ("succeed with %s via conversion", alias
->name
);
1945 memcpy (inst
, ©
, sizeof (aarch64_inst
));
1951 /* Directly decode the alias opcode. */
1953 memset (&temp
, '\0', sizeof (aarch64_inst
));
1954 if (aarch64_opcode_decode (alias
, inst
->value
, &temp
, 1) == 1)
1956 DEBUG_TRACE ("succeed with %s via direct decoding", alias
->name
);
1957 memcpy (inst
, &temp
, sizeof (aarch64_inst
));
1964 /* Decode the CODE according to OPCODE; fill INST. Return 0 if the decoding
1965 fails, which meanes that CODE is not an instruction of OPCODE; otherwise
1968 If OPCODE has alias(es) and NOALIASES_P is 0, an alias opcode may be
1969 determined and used to disassemble CODE; this is done just before the
1973 aarch64_opcode_decode (const aarch64_opcode
*opcode
, const aarch64_insn code
,
1974 aarch64_inst
*inst
, int noaliases_p
)
1978 DEBUG_TRACE ("enter with %s", opcode
->name
);
1980 assert (opcode
&& inst
);
1982 /* Check the base opcode. */
1983 if ((code
& opcode
->mask
) != (opcode
->opcode
& opcode
->mask
))
1985 DEBUG_TRACE ("base opcode match FAIL");
1990 memset (inst
, '\0', sizeof (aarch64_inst
));
1992 inst
->opcode
= opcode
;
1995 /* Assign operand codes and indexes. */
1996 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
1998 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
)
2000 inst
->operands
[i
].type
= opcode
->operands
[i
];
2001 inst
->operands
[i
].idx
= i
;
2004 /* Call the opcode decoder indicated by flags. */
2005 if (opcode_has_special_coder (opcode
) && do_special_decoding (inst
) == 0)
2007 DEBUG_TRACE ("opcode flag-based decoder FAIL");
2011 /* Call operand decoders. */
2012 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2014 const aarch64_operand
*opnd
;
2015 enum aarch64_opnd type
;
2016 type
= opcode
->operands
[i
];
2017 if (type
== AARCH64_OPND_NIL
)
2019 opnd
= &aarch64_operands
[type
];
2020 if (operand_has_extractor (opnd
)
2021 && (! aarch64_extract_operand (opnd
, &inst
->operands
[i
], code
, inst
)))
2023 DEBUG_TRACE ("operand decoder FAIL at operand %d", i
);
2028 /* Match the qualifiers. */
2029 if (aarch64_match_operands_constraint (inst
, NULL
) == 1)
2031 /* Arriving here, the CODE has been determined as a valid instruction
2032 of OPCODE and *INST has been filled with information of this OPCODE
2033 instruction. Before the return, check if the instruction has any
2034 alias and should be disassembled in the form of its alias instead.
2035 If the answer is yes, *INST will be updated. */
2037 determine_disassembling_preference (inst
);
2038 DEBUG_TRACE ("SUCCESS");
2043 DEBUG_TRACE ("constraint matching FAIL");
2050 /* This does some user-friendly fix-up to *INST. It is currently focus on
2051 the adjustment of qualifiers to help the printed instruction
2052 recognized/understood more easily. */
2055 user_friendly_fixup (aarch64_inst
*inst
)
2057 switch (inst
->opcode
->iclass
)
2060 /* TBNZ Xn|Wn, #uimm6, label
2061 Test and Branch Not Zero: conditionally jumps to label if bit number
2062 uimm6 in register Xn is not zero. The bit number implies the width of
2063 the register, which may be written and should be disassembled as Wn if
2064 uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
2066 if (inst
->operands
[1].imm
.value
< 32)
2067 inst
->operands
[0].qualifier
= AARCH64_OPND_QLF_W
;
2073 /* Decode INSN and fill in *INST the instruction information. An alias
2074 opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
2078 aarch64_decode_insn (aarch64_insn insn
, aarch64_inst
*inst
,
2079 bfd_boolean noaliases_p
)
2081 const aarch64_opcode
*opcode
= aarch64_opcode_lookup (insn
);
2083 #ifdef DEBUG_AARCH64
2086 const aarch64_opcode
*tmp
= opcode
;
2088 DEBUG_TRACE ("opcode lookup:");
2091 aarch64_verbose (" %s", tmp
->name
);
2092 tmp
= aarch64_find_next_opcode (tmp
);
2095 #endif /* DEBUG_AARCH64 */
2097 /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
2098 distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
2099 opcode field and value, apart from the difference that one of them has an
2100 extra field as part of the opcode, but such a field is used for operand
2101 encoding in other opcode(s) ('immh' in the case of the example). */
2102 while (opcode
!= NULL
)
2104 /* But only one opcode can be decoded successfully for, as the
2105 decoding routine will check the constraint carefully. */
2106 if (aarch64_opcode_decode (opcode
, insn
, inst
, noaliases_p
) == 1)
2108 opcode
= aarch64_find_next_opcode (opcode
);
2114 /* Print operands. */
2117 print_operands (bfd_vma pc
, const aarch64_opcode
*opcode
,
2118 const aarch64_opnd_info
*opnds
, struct disassemble_info
*info
)
2120 int i
, pcrel_p
, num_printed
;
2121 for (i
= 0, num_printed
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
2123 const size_t size
= 128;
2125 /* We regard the opcode operand info more, however we also look into
2126 the inst->operands to support the disassembling of the optional
2128 The two operand code should be the same in all cases, apart from
2129 when the operand can be optional. */
2130 if (opcode
->operands
[i
] == AARCH64_OPND_NIL
2131 || opnds
[i
].type
== AARCH64_OPND_NIL
)
2134 /* Generate the operand string in STR. */
2135 aarch64_print_operand (str
, size
, pc
, opcode
, opnds
, i
, &pcrel_p
,
2138 /* Print the delimiter (taking account of omitted operand(s)). */
2140 (*info
->fprintf_func
) (info
->stream
, "%s",
2141 num_printed
++ == 0 ? "\t" : ", ");
2143 /* Print the operand. */
2145 (*info
->print_address_func
) (info
->target
, info
);
2147 (*info
->fprintf_func
) (info
->stream
, "%s", str
);
2151 /* Print the instruction mnemonic name. */
2154 print_mnemonic_name (const aarch64_inst
*inst
, struct disassemble_info
*info
)
2156 if (inst
->opcode
->flags
& F_COND
)
2158 /* For instructions that are truly conditionally executed, e.g. b.cond,
2159 prepare the full mnemonic name with the corresponding condition
2164 ptr
= strchr (inst
->opcode
->name
, '.');
2165 assert (ptr
&& inst
->cond
);
2166 len
= ptr
- inst
->opcode
->name
;
2168 strncpy (name
, inst
->opcode
->name
, len
);
2170 (*info
->fprintf_func
) (info
->stream
, "%s.%s", name
, inst
->cond
->names
[0]);
2173 (*info
->fprintf_func
) (info
->stream
, "%s", inst
->opcode
->name
);
2176 /* Print the instruction according to *INST. */
2179 print_aarch64_insn (bfd_vma pc
, const aarch64_inst
*inst
,
2180 struct disassemble_info
*info
)
2182 print_mnemonic_name (inst
, info
);
2183 print_operands (pc
, inst
->opcode
, inst
->operands
, info
);
2186 /* Entry-point of the instruction disassembler and printer. */
2189 print_insn_aarch64_word (bfd_vma pc
,
2191 struct disassemble_info
*info
)
2193 static const char *err_msg
[6] =
2196 [-ERR_UND
] = "undefined",
2197 [-ERR_UNP
] = "unpredictable",
2204 info
->insn_info_valid
= 1;
2205 info
->branch_delay_insns
= 0;
2206 info
->data_size
= 0;
2210 if (info
->flags
& INSN_HAS_RELOC
)
2211 /* If the instruction has a reloc associated with it, then
2212 the offset field in the instruction will actually be the
2213 addend for the reloc. (If we are using REL type relocs).
2214 In such cases, we can ignore the pc when computing
2215 addresses, since the addend is not currently pc-relative. */
2218 ret
= aarch64_decode_insn (word
, &inst
, no_aliases
);
2220 if (((word
>> 21) & 0x3ff) == 1)
2222 /* RESERVED for ALES. */
2223 assert (ret
!= ERR_OK
);
2232 /* Handle undefined instructions. */
2233 info
->insn_type
= dis_noninsn
;
2234 (*info
->fprintf_func
) (info
->stream
,".inst\t0x%08x ; %s",
2235 word
, err_msg
[-ret
]);
2238 user_friendly_fixup (&inst
);
2239 print_aarch64_insn (pc
, &inst
, info
);
2246 /* Disallow mapping symbols ($x, $d etc) from
2247 being displayed in symbol relative addresses. */
2250 aarch64_symbol_is_valid (asymbol
* sym
,
2251 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
2258 name
= bfd_asymbol_name (sym
);
2262 || (name
[1] != 'x' && name
[1] != 'd')
2263 || (name
[2] != '\0' && name
[2] != '.'));
2266 /* Print data bytes on INFO->STREAM. */
2269 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
2271 struct disassemble_info
*info
)
2273 switch (info
->bytes_per_chunk
)
2276 info
->fprintf_func (info
->stream
, ".byte\t0x%02x", word
);
2279 info
->fprintf_func (info
->stream
, ".short\t0x%04x", word
);
2282 info
->fprintf_func (info
->stream
, ".word\t0x%08x", word
);
2289 /* Try to infer the code or data type from a symbol.
2290 Returns nonzero if *MAP_TYPE was set. */
2293 get_sym_code_type (struct disassemble_info
*info
, int n
,
2294 enum map_type
*map_type
)
2296 elf_symbol_type
*es
;
2300 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
2301 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
2303 /* If the symbol has function type then use that. */
2304 if (type
== STT_FUNC
)
2306 *map_type
= MAP_INSN
;
2310 /* Check for mapping symbols. */
2311 name
= bfd_asymbol_name(info
->symtab
[n
]);
2313 && (name
[1] == 'x' || name
[1] == 'd')
2314 && (name
[2] == '\0' || name
[2] == '.'))
2316 *map_type
= (name
[1] == 'x' ? MAP_INSN
: MAP_DATA
);
2323 /* Entry-point of the AArch64 disassembler. */
2326 print_insn_aarch64 (bfd_vma pc
,
2327 struct disassemble_info
*info
)
2329 bfd_byte buffer
[INSNLEN
];
2331 void (*printer
) (bfd_vma
, uint32_t, struct disassemble_info
*);
2332 bfd_boolean found
= FALSE
;
2333 unsigned int size
= 4;
2336 if (info
->disassembler_options
)
2338 set_default_aarch64_dis_options (info
);
2340 parse_aarch64_dis_options (info
->disassembler_options
);
2342 /* To avoid repeated parsing of these options, we remove them here. */
2343 info
->disassembler_options
= NULL
;
2346 /* Aarch64 instructions are always little-endian */
2347 info
->endian_code
= BFD_ENDIAN_LITTLE
;
2349 /* First check the full symtab for a mapping symbol, even if there
2350 are no usable non-mapping symbols for this address. */
2351 if (info
->symtab_size
!= 0
2352 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
2354 enum map_type type
= MAP_INSN
;
2359 if (pc
<= last_mapping_addr
)
2360 last_mapping_sym
= -1;
2362 /* Start scanning at the start of the function, or wherever
2363 we finished last time. */
2364 n
= info
->symtab_pos
+ 1;
2365 if (n
< last_mapping_sym
)
2366 n
= last_mapping_sym
;
2368 /* Scan up to the location being disassembled. */
2369 for (; n
< info
->symtab_size
; n
++)
2371 addr
= bfd_asymbol_value (info
->symtab
[n
]);
2374 if ((info
->section
== NULL
2375 || info
->section
== info
->symtab
[n
]->section
)
2376 && get_sym_code_type (info
, n
, &type
))
2385 n
= info
->symtab_pos
;
2386 if (n
< last_mapping_sym
)
2387 n
= last_mapping_sym
;
2389 /* No mapping symbol found at this address. Look backwards
2390 for a preceeding one. */
2393 if (get_sym_code_type (info
, n
, &type
))
2402 last_mapping_sym
= last_sym
;
2405 /* Look a little bit ahead to see if we should print out
2406 less than four bytes of data. If there's a symbol,
2407 mapping or otherwise, after two bytes then don't
2409 if (last_type
== MAP_DATA
)
2411 size
= 4 - (pc
& 3);
2412 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
2414 addr
= bfd_asymbol_value (info
->symtab
[n
]);
2417 if (addr
- pc
< size
)
2422 /* If the next symbol is after three bytes, we need to
2423 print only part of the data, so that we can use either
2426 size
= (pc
& 1) ? 1 : 2;
2430 if (last_type
== MAP_DATA
)
2432 /* size was set above. */
2433 info
->bytes_per_chunk
= size
;
2434 info
->display_endian
= info
->endian
;
2435 printer
= print_insn_data
;
2439 info
->bytes_per_chunk
= size
= INSNLEN
;
2440 info
->display_endian
= info
->endian_code
;
2441 printer
= print_insn_aarch64_word
;
2444 status
= (*info
->read_memory_func
) (pc
, buffer
, size
, info
);
2447 (*info
->memory_error_func
) (status
, pc
, info
);
2451 data
= bfd_get_bits (buffer
, size
* 8,
2452 info
->display_endian
== BFD_ENDIAN_BIG
);
2454 (*printer
) (pc
, data
, info
);
2460 print_aarch64_disassembler_options (FILE *stream
)
2462 fprintf (stream
, _("\n\
2463 The following AARCH64 specific disassembler options are supported for use\n\
2464 with the -M switch (multiple options should be separated by commas):\n"));
2466 fprintf (stream
, _("\n\
2467 no-aliases Don't print instruction aliases.\n"));
2469 fprintf (stream
, _("\n\
2470 aliases Do print instruction aliases.\n"));
2472 #ifdef DEBUG_AARCH64
2473 fprintf (stream
, _("\n\
2474 debug_dump Temp switch for debug trace.\n"));
2475 #endif /* DEBUG_AARCH64 */
2477 fprintf (stream
, _("\n"));