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[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c
1 /* aarch64-opc.c -- AArch64 opcode support.
2 Copyright (C) 2009-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21 #include "sysdep.h"
22 #include <assert.h>
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include <stdint.h>
26 #include <stdarg.h>
27 #include <inttypes.h>
28
29 #include "opintl.h"
30 #include "libiberty.h"
31
32 #include "aarch64-opc.h"
33
34 #ifdef DEBUG_AARCH64
35 int debug_dump = FALSE;
36 #endif /* DEBUG_AARCH64 */
37
38 /* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40 const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77 };
78
79 /* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81 const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100 };
101
102 /* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105 static inline bfd_boolean
106 vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107 {
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111 }
112
113 static inline bfd_boolean
114 fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115 {
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119 }
120
121 enum data_pattern
122 {
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128 };
129
130 static const char significant_operand_index [] =
131 {
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137 };
138
139 /* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144 static enum data_pattern
145 get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146 {
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185 }
186
187 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189 /* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195 int
196 aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197 {
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200 }
201 \f
202 const aarch64_field fields[] =
203 {
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
243 { 15, 6 }, /* imm6_2: in rmif instructions. */
244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
245 { 0, 4 }, /* imm4_2: in rmif instructions. */
246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
254 { 0, 26 }, /* imm26: in unconditional branch instructions. */
255 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
256 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
257 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
258 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
259 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
260 { 22, 1 }, /* N: in logical (immediate) instructions. */
261 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
262 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
263 { 31, 1 }, /* sf: in integer data processing instructions. */
264 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
265 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
266 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
267 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
268 { 31, 1 }, /* b5: in the test bit and branch instructions. */
269 { 19, 5 }, /* b40: in the test bit and branch instructions. */
270 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
271 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
272 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
273 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
274 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
275 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
276 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
277 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
278 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
279 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
280 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
281 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
282 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
283 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
284 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
285 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
286 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
288 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
290 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
291 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
293 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
294 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
295 { 5, 1 }, /* SVE_i1: single-bit immediate. */
296 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
297 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
298 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
299 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
300 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
301 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
302 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
303 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
304 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
305 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
306 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
307 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
308 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
309 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
310 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
311 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
312 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
313 { 16, 4 }, /* SVE_tsz: triangular size select. */
314 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
315 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
316 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
317 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
318 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
319 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
320 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
321 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
322 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
323 };
324
325 enum aarch64_operand_class
326 aarch64_get_operand_class (enum aarch64_opnd type)
327 {
328 return aarch64_operands[type].op_class;
329 }
330
331 const char *
332 aarch64_get_operand_name (enum aarch64_opnd type)
333 {
334 return aarch64_operands[type].name;
335 }
336
337 /* Get operand description string.
338 This is usually for the diagnosis purpose. */
339 const char *
340 aarch64_get_operand_desc (enum aarch64_opnd type)
341 {
342 return aarch64_operands[type].desc;
343 }
344
345 /* Table of all conditional affixes. */
346 const aarch64_cond aarch64_conds[16] =
347 {
348 {{"eq", "none"}, 0x0},
349 {{"ne", "any"}, 0x1},
350 {{"cs", "hs", "nlast"}, 0x2},
351 {{"cc", "lo", "ul", "last"}, 0x3},
352 {{"mi", "first"}, 0x4},
353 {{"pl", "nfrst"}, 0x5},
354 {{"vs"}, 0x6},
355 {{"vc"}, 0x7},
356 {{"hi", "pmore"}, 0x8},
357 {{"ls", "plast"}, 0x9},
358 {{"ge", "tcont"}, 0xa},
359 {{"lt", "tstop"}, 0xb},
360 {{"gt"}, 0xc},
361 {{"le"}, 0xd},
362 {{"al"}, 0xe},
363 {{"nv"}, 0xf},
364 };
365
366 const aarch64_cond *
367 get_cond_from_value (aarch64_insn value)
368 {
369 assert (value < 16);
370 return &aarch64_conds[(unsigned int) value];
371 }
372
373 const aarch64_cond *
374 get_inverted_cond (const aarch64_cond *cond)
375 {
376 return &aarch64_conds[cond->value ^ 0x1];
377 }
378
379 /* Table describing the operand extension/shifting operators; indexed by
380 enum aarch64_modifier_kind.
381
382 The value column provides the most common values for encoding modifiers,
383 which enables table-driven encoding/decoding for the modifiers. */
384 const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
385 {
386 {"none", 0x0},
387 {"msl", 0x0},
388 {"ror", 0x3},
389 {"asr", 0x2},
390 {"lsr", 0x1},
391 {"lsl", 0x0},
392 {"uxtb", 0x0},
393 {"uxth", 0x1},
394 {"uxtw", 0x2},
395 {"uxtx", 0x3},
396 {"sxtb", 0x4},
397 {"sxth", 0x5},
398 {"sxtw", 0x6},
399 {"sxtx", 0x7},
400 {"mul", 0x0},
401 {"mul vl", 0x0},
402 {NULL, 0},
403 };
404
405 enum aarch64_modifier_kind
406 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
407 {
408 return desc - aarch64_operand_modifiers;
409 }
410
411 aarch64_insn
412 aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
413 {
414 return aarch64_operand_modifiers[kind].value;
415 }
416
417 enum aarch64_modifier_kind
418 aarch64_get_operand_modifier_from_value (aarch64_insn value,
419 bfd_boolean extend_p)
420 {
421 if (extend_p == TRUE)
422 return AARCH64_MOD_UXTB + value;
423 else
424 return AARCH64_MOD_LSL - value;
425 }
426
427 bfd_boolean
428 aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
429 {
430 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
431 ? TRUE : FALSE;
432 }
433
434 static inline bfd_boolean
435 aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
436 {
437 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
438 ? TRUE : FALSE;
439 }
440
441 const struct aarch64_name_value_pair aarch64_barrier_options[16] =
442 {
443 { "#0x00", 0x0 },
444 { "oshld", 0x1 },
445 { "oshst", 0x2 },
446 { "osh", 0x3 },
447 { "#0x04", 0x4 },
448 { "nshld", 0x5 },
449 { "nshst", 0x6 },
450 { "nsh", 0x7 },
451 { "#0x08", 0x8 },
452 { "ishld", 0x9 },
453 { "ishst", 0xa },
454 { "ish", 0xb },
455 { "#0x0c", 0xc },
456 { "ld", 0xd },
457 { "st", 0xe },
458 { "sy", 0xf },
459 };
460
461 /* Table describing the operands supported by the aliases of the HINT
462 instruction.
463
464 The name column is the operand that is accepted for the alias. The value
465 column is the hint number of the alias. The list of operands is terminated
466 by NULL in the name column. */
467
468 const struct aarch64_name_value_pair aarch64_hint_options[] =
469 {
470 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
471 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
472 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
473 { "c", HINT_OPD_C }, /* BTI C. */
474 { "j", HINT_OPD_J }, /* BTI J. */
475 { "jc", HINT_OPD_JC }, /* BTI JC. */
476 { NULL, HINT_OPD_NULL },
477 };
478
479 /* op -> op: load = 0 instruction = 1 store = 2
480 l -> level: 1-3
481 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
482 #define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
483 const struct aarch64_name_value_pair aarch64_prfops[32] =
484 {
485 { "pldl1keep", B(0, 1, 0) },
486 { "pldl1strm", B(0, 1, 1) },
487 { "pldl2keep", B(0, 2, 0) },
488 { "pldl2strm", B(0, 2, 1) },
489 { "pldl3keep", B(0, 3, 0) },
490 { "pldl3strm", B(0, 3, 1) },
491 { NULL, 0x06 },
492 { NULL, 0x07 },
493 { "plil1keep", B(1, 1, 0) },
494 { "plil1strm", B(1, 1, 1) },
495 { "plil2keep", B(1, 2, 0) },
496 { "plil2strm", B(1, 2, 1) },
497 { "plil3keep", B(1, 3, 0) },
498 { "plil3strm", B(1, 3, 1) },
499 { NULL, 0x0e },
500 { NULL, 0x0f },
501 { "pstl1keep", B(2, 1, 0) },
502 { "pstl1strm", B(2, 1, 1) },
503 { "pstl2keep", B(2, 2, 0) },
504 { "pstl2strm", B(2, 2, 1) },
505 { "pstl3keep", B(2, 3, 0) },
506 { "pstl3strm", B(2, 3, 1) },
507 { NULL, 0x16 },
508 { NULL, 0x17 },
509 { NULL, 0x18 },
510 { NULL, 0x19 },
511 { NULL, 0x1a },
512 { NULL, 0x1b },
513 { NULL, 0x1c },
514 { NULL, 0x1d },
515 { NULL, 0x1e },
516 { NULL, 0x1f },
517 };
518 #undef B
519 \f
520 /* Utilities on value constraint. */
521
522 static inline int
523 value_in_range_p (int64_t value, int low, int high)
524 {
525 return (value >= low && value <= high) ? 1 : 0;
526 }
527
528 /* Return true if VALUE is a multiple of ALIGN. */
529 static inline int
530 value_aligned_p (int64_t value, int align)
531 {
532 return (value % align) == 0;
533 }
534
535 /* A signed value fits in a field. */
536 static inline int
537 value_fit_signed_field_p (int64_t value, unsigned width)
538 {
539 assert (width < 32);
540 if (width < sizeof (value) * 8)
541 {
542 int64_t lim = (int64_t)1 << (width - 1);
543 if (value >= -lim && value < lim)
544 return 1;
545 }
546 return 0;
547 }
548
549 /* An unsigned value fits in a field. */
550 static inline int
551 value_fit_unsigned_field_p (int64_t value, unsigned width)
552 {
553 assert (width < 32);
554 if (width < sizeof (value) * 8)
555 {
556 int64_t lim = (int64_t)1 << width;
557 if (value >= 0 && value < lim)
558 return 1;
559 }
560 return 0;
561 }
562
563 /* Return 1 if OPERAND is SP or WSP. */
564 int
565 aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
566 {
567 return ((aarch64_get_operand_class (operand->type)
568 == AARCH64_OPND_CLASS_INT_REG)
569 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
570 && operand->reg.regno == 31);
571 }
572
573 /* Return 1 if OPERAND is XZR or WZP. */
574 int
575 aarch64_zero_register_p (const aarch64_opnd_info *operand)
576 {
577 return ((aarch64_get_operand_class (operand->type)
578 == AARCH64_OPND_CLASS_INT_REG)
579 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
580 && operand->reg.regno == 31);
581 }
582
583 /* Return true if the operand *OPERAND that has the operand code
584 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
585 qualified by the qualifier TARGET. */
586
587 static inline int
588 operand_also_qualified_p (const struct aarch64_opnd_info *operand,
589 aarch64_opnd_qualifier_t target)
590 {
591 switch (operand->qualifier)
592 {
593 case AARCH64_OPND_QLF_W:
594 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
595 return 1;
596 break;
597 case AARCH64_OPND_QLF_X:
598 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
599 return 1;
600 break;
601 case AARCH64_OPND_QLF_WSP:
602 if (target == AARCH64_OPND_QLF_W
603 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
604 return 1;
605 break;
606 case AARCH64_OPND_QLF_SP:
607 if (target == AARCH64_OPND_QLF_X
608 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
609 return 1;
610 break;
611 default:
612 break;
613 }
614
615 return 0;
616 }
617
618 /* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
619 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
620
621 Return NIL if more than one expected qualifiers are found. */
622
623 aarch64_opnd_qualifier_t
624 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
625 int idx,
626 const aarch64_opnd_qualifier_t known_qlf,
627 int known_idx)
628 {
629 int i, saved_i;
630
631 /* Special case.
632
633 When the known qualifier is NIL, we have to assume that there is only
634 one qualifier sequence in the *QSEQ_LIST and return the corresponding
635 qualifier directly. One scenario is that for instruction
636 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
637 which has only one possible valid qualifier sequence
638 NIL, S_D
639 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
640 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
641
642 Because the qualifier NIL has dual roles in the qualifier sequence:
643 it can mean no qualifier for the operand, or the qualifer sequence is
644 not in use (when all qualifiers in the sequence are NILs), we have to
645 handle this special case here. */
646 if (known_qlf == AARCH64_OPND_NIL)
647 {
648 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
649 return qseq_list[0][idx];
650 }
651
652 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
653 {
654 if (qseq_list[i][known_idx] == known_qlf)
655 {
656 if (saved_i != -1)
657 /* More than one sequences are found to have KNOWN_QLF at
658 KNOWN_IDX. */
659 return AARCH64_OPND_NIL;
660 saved_i = i;
661 }
662 }
663
664 return qseq_list[saved_i][idx];
665 }
666
667 enum operand_qualifier_kind
668 {
669 OQK_NIL,
670 OQK_OPD_VARIANT,
671 OQK_VALUE_IN_RANGE,
672 OQK_MISC,
673 };
674
675 /* Operand qualifier description. */
676 struct operand_qualifier_data
677 {
678 /* The usage of the three data fields depends on the qualifier kind. */
679 int data0;
680 int data1;
681 int data2;
682 /* Description. */
683 const char *desc;
684 /* Kind. */
685 enum operand_qualifier_kind kind;
686 };
687
688 /* Indexed by the operand qualifier enumerators. */
689 struct operand_qualifier_data aarch64_opnd_qualifiers[] =
690 {
691 {0, 0, 0, "NIL", OQK_NIL},
692
693 /* Operand variant qualifiers.
694 First 3 fields:
695 element size, number of elements and common value for encoding. */
696
697 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
698 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
699 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
700 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
701
702 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
703 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
704 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
705 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
706 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
707 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
708
709 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
710 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
711 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
712 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
713 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
714 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
715 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
716 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
717 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
718 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
719 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
720
721 {0, 0, 0, "z", OQK_OPD_VARIANT},
722 {0, 0, 0, "m", OQK_OPD_VARIANT},
723
724 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
725 {16, 0, 0, "tag", OQK_OPD_VARIANT},
726
727 /* Qualifiers constraining the value range.
728 First 3 fields:
729 Lower bound, higher bound, unused. */
730
731 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
732 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
733 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
734 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
735 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
736 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
737 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
738
739 /* Qualifiers for miscellaneous purpose.
740 First 3 fields:
741 unused, unused and unused. */
742
743 {0, 0, 0, "lsl", 0},
744 {0, 0, 0, "msl", 0},
745
746 {0, 0, 0, "retrieving", 0},
747 };
748
749 static inline bfd_boolean
750 operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
751 {
752 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
753 ? TRUE : FALSE;
754 }
755
756 static inline bfd_boolean
757 qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
758 {
759 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
760 ? TRUE : FALSE;
761 }
762
763 const char*
764 aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
765 {
766 return aarch64_opnd_qualifiers[qualifier].desc;
767 }
768
769 /* Given an operand qualifier, return the expected data element size
770 of a qualified operand. */
771 unsigned char
772 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
773 {
774 assert (operand_variant_qualifier_p (qualifier) == TRUE);
775 return aarch64_opnd_qualifiers[qualifier].data0;
776 }
777
778 unsigned char
779 aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
780 {
781 assert (operand_variant_qualifier_p (qualifier) == TRUE);
782 return aarch64_opnd_qualifiers[qualifier].data1;
783 }
784
785 aarch64_insn
786 aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
787 {
788 assert (operand_variant_qualifier_p (qualifier) == TRUE);
789 return aarch64_opnd_qualifiers[qualifier].data2;
790 }
791
792 static int
793 get_lower_bound (aarch64_opnd_qualifier_t qualifier)
794 {
795 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
796 return aarch64_opnd_qualifiers[qualifier].data0;
797 }
798
799 static int
800 get_upper_bound (aarch64_opnd_qualifier_t qualifier)
801 {
802 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
803 return aarch64_opnd_qualifiers[qualifier].data1;
804 }
805
806 #ifdef DEBUG_AARCH64
807 void
808 aarch64_verbose (const char *str, ...)
809 {
810 va_list ap;
811 va_start (ap, str);
812 printf ("#### ");
813 vprintf (str, ap);
814 printf ("\n");
815 va_end (ap);
816 }
817
818 static inline void
819 dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
820 {
821 int i;
822 printf ("#### \t");
823 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
824 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
825 printf ("\n");
826 }
827
828 static void
829 dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
830 const aarch64_opnd_qualifier_t *qualifier)
831 {
832 int i;
833 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
834
835 aarch64_verbose ("dump_match_qualifiers:");
836 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
837 curr[i] = opnd[i].qualifier;
838 dump_qualifier_sequence (curr);
839 aarch64_verbose ("against");
840 dump_qualifier_sequence (qualifier);
841 }
842 #endif /* DEBUG_AARCH64 */
843
844 /* This function checks if the given instruction INSN is a destructive
845 instruction based on the usage of the registers. It does not recognize
846 unary destructive instructions. */
847 bfd_boolean
848 aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
849 {
850 int i = 0;
851 const enum aarch64_opnd *opnds = opcode->operands;
852
853 if (opnds[0] == AARCH64_OPND_NIL)
854 return FALSE;
855
856 while (opnds[++i] != AARCH64_OPND_NIL)
857 if (opnds[i] == opnds[0])
858 return TRUE;
859
860 return FALSE;
861 }
862
863 /* TODO improve this, we can have an extra field at the runtime to
864 store the number of operands rather than calculating it every time. */
865
866 int
867 aarch64_num_of_operands (const aarch64_opcode *opcode)
868 {
869 int i = 0;
870 const enum aarch64_opnd *opnds = opcode->operands;
871 while (opnds[i++] != AARCH64_OPND_NIL)
872 ;
873 --i;
874 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
875 return i;
876 }
877
878 /* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
879 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
880
881 N.B. on the entry, it is very likely that only some operands in *INST
882 have had their qualifiers been established.
883
884 If STOP_AT is not -1, the function will only try to match
885 the qualifier sequence for operands before and including the operand
886 of index STOP_AT; and on success *RET will only be filled with the first
887 (STOP_AT+1) qualifiers.
888
889 A couple examples of the matching algorithm:
890
891 X,W,NIL should match
892 X,W,NIL
893
894 NIL,NIL should match
895 X ,NIL
896
897 Apart from serving the main encoding routine, this can also be called
898 during or after the operand decoding. */
899
900 int
901 aarch64_find_best_match (const aarch64_inst *inst,
902 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
903 int stop_at, aarch64_opnd_qualifier_t *ret)
904 {
905 int found = 0;
906 int i, num_opnds;
907 const aarch64_opnd_qualifier_t *qualifiers;
908
909 num_opnds = aarch64_num_of_operands (inst->opcode);
910 if (num_opnds == 0)
911 {
912 DEBUG_TRACE ("SUCCEED: no operand");
913 return 1;
914 }
915
916 if (stop_at < 0 || stop_at >= num_opnds)
917 stop_at = num_opnds - 1;
918
919 /* For each pattern. */
920 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
921 {
922 int j;
923 qualifiers = *qualifiers_list;
924
925 /* Start as positive. */
926 found = 1;
927
928 DEBUG_TRACE ("%d", i);
929 #ifdef DEBUG_AARCH64
930 if (debug_dump)
931 dump_match_qualifiers (inst->operands, qualifiers);
932 #endif
933
934 /* Most opcodes has much fewer patterns in the list.
935 First NIL qualifier indicates the end in the list. */
936 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
937 {
938 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
939 if (i)
940 found = 0;
941 break;
942 }
943
944 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
945 {
946 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
947 {
948 /* Either the operand does not have qualifier, or the qualifier
949 for the operand needs to be deduced from the qualifier
950 sequence.
951 In the latter case, any constraint checking related with
952 the obtained qualifier should be done later in
953 operand_general_constraint_met_p. */
954 continue;
955 }
956 else if (*qualifiers != inst->operands[j].qualifier)
957 {
958 /* Unless the target qualifier can also qualify the operand
959 (which has already had a non-nil qualifier), non-equal
960 qualifiers are generally un-matched. */
961 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
962 continue;
963 else
964 {
965 found = 0;
966 break;
967 }
968 }
969 else
970 continue; /* Equal qualifiers are certainly matched. */
971 }
972
973 /* Qualifiers established. */
974 if (found == 1)
975 break;
976 }
977
978 if (found == 1)
979 {
980 /* Fill the result in *RET. */
981 int j;
982 qualifiers = *qualifiers_list;
983
984 DEBUG_TRACE ("complete qualifiers using list %d", i);
985 #ifdef DEBUG_AARCH64
986 if (debug_dump)
987 dump_qualifier_sequence (qualifiers);
988 #endif
989
990 for (j = 0; j <= stop_at; ++j, ++qualifiers)
991 ret[j] = *qualifiers;
992 for (; j < AARCH64_MAX_OPND_NUM; ++j)
993 ret[j] = AARCH64_OPND_QLF_NIL;
994
995 DEBUG_TRACE ("SUCCESS");
996 return 1;
997 }
998
999 DEBUG_TRACE ("FAIL");
1000 return 0;
1001 }
1002
1003 /* Operand qualifier matching and resolving.
1004
1005 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1006 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1007
1008 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1009 succeeds. */
1010
1011 static int
1012 match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1013 {
1014 int i, nops;
1015 aarch64_opnd_qualifier_seq_t qualifiers;
1016
1017 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1018 qualifiers))
1019 {
1020 DEBUG_TRACE ("matching FAIL");
1021 return 0;
1022 }
1023
1024 if (inst->opcode->flags & F_STRICT)
1025 {
1026 /* Require an exact qualifier match, even for NIL qualifiers. */
1027 nops = aarch64_num_of_operands (inst->opcode);
1028 for (i = 0; i < nops; ++i)
1029 if (inst->operands[i].qualifier != qualifiers[i])
1030 return FALSE;
1031 }
1032
1033 /* Update the qualifiers. */
1034 if (update_p == TRUE)
1035 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1036 {
1037 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1038 break;
1039 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1040 "update %s with %s for operand %d",
1041 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1042 aarch64_get_qualifier_name (qualifiers[i]), i);
1043 inst->operands[i].qualifier = qualifiers[i];
1044 }
1045
1046 DEBUG_TRACE ("matching SUCCESS");
1047 return 1;
1048 }
1049
1050 /* Return TRUE if VALUE is a wide constant that can be moved into a general
1051 register by MOVZ.
1052
1053 IS32 indicates whether value is a 32-bit immediate or not.
1054 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1055 amount will be returned in *SHIFT_AMOUNT. */
1056
1057 bfd_boolean
1058 aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1059 {
1060 int amount;
1061
1062 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1063
1064 if (is32)
1065 {
1066 /* Allow all zeros or all ones in top 32-bits, so that
1067 32-bit constant expressions like ~0x80000000 are
1068 permitted. */
1069 uint64_t ext = value;
1070 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1071 /* Immediate out of range. */
1072 return FALSE;
1073 value &= (int64_t) 0xffffffff;
1074 }
1075
1076 /* first, try movz then movn */
1077 amount = -1;
1078 if ((value & ((int64_t) 0xffff << 0)) == value)
1079 amount = 0;
1080 else if ((value & ((int64_t) 0xffff << 16)) == value)
1081 amount = 16;
1082 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1083 amount = 32;
1084 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1085 amount = 48;
1086
1087 if (amount == -1)
1088 {
1089 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1090 return FALSE;
1091 }
1092
1093 if (shift_amount != NULL)
1094 *shift_amount = amount;
1095
1096 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1097
1098 return TRUE;
1099 }
1100
1101 /* Build the accepted values for immediate logical SIMD instructions.
1102
1103 The standard encodings of the immediate value are:
1104 N imms immr SIMD size R S
1105 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1106 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1107 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1108 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1109 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1110 0 11110s 00000r 2 UInt(r) UInt(s)
1111 where all-ones value of S is reserved.
1112
1113 Let's call E the SIMD size.
1114
1115 The immediate value is: S+1 bits '1' rotated to the right by R.
1116
1117 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1118 (remember S != E - 1). */
1119
1120 #define TOTAL_IMM_NB 5334
1121
1122 typedef struct
1123 {
1124 uint64_t imm;
1125 aarch64_insn encoding;
1126 } simd_imm_encoding;
1127
1128 static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1129
1130 static int
1131 simd_imm_encoding_cmp(const void *i1, const void *i2)
1132 {
1133 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1134 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1135
1136 if (imm1->imm < imm2->imm)
1137 return -1;
1138 if (imm1->imm > imm2->imm)
1139 return +1;
1140 return 0;
1141 }
1142
1143 /* immediate bitfield standard encoding
1144 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1145 1 ssssss rrrrrr 64 rrrrrr ssssss
1146 0 0sssss 0rrrrr 32 rrrrr sssss
1147 0 10ssss 00rrrr 16 rrrr ssss
1148 0 110sss 000rrr 8 rrr sss
1149 0 1110ss 0000rr 4 rr ss
1150 0 11110s 00000r 2 r s */
1151 static inline int
1152 encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1153 {
1154 return (is64 << 12) | (r << 6) | s;
1155 }
1156
1157 static void
1158 build_immediate_table (void)
1159 {
1160 uint32_t log_e, e, s, r, s_mask;
1161 uint64_t mask, imm;
1162 int nb_imms;
1163 int is64;
1164
1165 nb_imms = 0;
1166 for (log_e = 1; log_e <= 6; log_e++)
1167 {
1168 /* Get element size. */
1169 e = 1u << log_e;
1170 if (log_e == 6)
1171 {
1172 is64 = 1;
1173 mask = 0xffffffffffffffffull;
1174 s_mask = 0;
1175 }
1176 else
1177 {
1178 is64 = 0;
1179 mask = (1ull << e) - 1;
1180 /* log_e s_mask
1181 1 ((1 << 4) - 1) << 2 = 111100
1182 2 ((1 << 3) - 1) << 3 = 111000
1183 3 ((1 << 2) - 1) << 4 = 110000
1184 4 ((1 << 1) - 1) << 5 = 100000
1185 5 ((1 << 0) - 1) << 6 = 000000 */
1186 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1187 }
1188 for (s = 0; s < e - 1; s++)
1189 for (r = 0; r < e; r++)
1190 {
1191 /* s+1 consecutive bits to 1 (s < 63) */
1192 imm = (1ull << (s + 1)) - 1;
1193 /* rotate right by r */
1194 if (r != 0)
1195 imm = (imm >> r) | ((imm << (e - r)) & mask);
1196 /* replicate the constant depending on SIMD size */
1197 switch (log_e)
1198 {
1199 case 1: imm = (imm << 2) | imm;
1200 /* Fall through. */
1201 case 2: imm = (imm << 4) | imm;
1202 /* Fall through. */
1203 case 3: imm = (imm << 8) | imm;
1204 /* Fall through. */
1205 case 4: imm = (imm << 16) | imm;
1206 /* Fall through. */
1207 case 5: imm = (imm << 32) | imm;
1208 /* Fall through. */
1209 case 6: break;
1210 default: abort ();
1211 }
1212 simd_immediates[nb_imms].imm = imm;
1213 simd_immediates[nb_imms].encoding =
1214 encode_immediate_bitfield(is64, s | s_mask, r);
1215 nb_imms++;
1216 }
1217 }
1218 assert (nb_imms == TOTAL_IMM_NB);
1219 qsort(simd_immediates, nb_imms,
1220 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1221 }
1222
1223 /* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1224 be accepted by logical (immediate) instructions
1225 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1226
1227 ESIZE is the number of bytes in the decoded immediate value.
1228 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1229 VALUE will be returned in *ENCODING. */
1230
1231 bfd_boolean
1232 aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
1233 {
1234 simd_imm_encoding imm_enc;
1235 const simd_imm_encoding *imm_encoding;
1236 static bfd_boolean initialized = FALSE;
1237 uint64_t upper;
1238 int i;
1239
1240 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1241 value, esize);
1242
1243 if (!initialized)
1244 {
1245 build_immediate_table ();
1246 initialized = TRUE;
1247 }
1248
1249 /* Allow all zeros or all ones in top bits, so that
1250 constant expressions like ~1 are permitted. */
1251 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1252 if ((value & ~upper) != value && (value | upper) != value)
1253 return FALSE;
1254
1255 /* Replicate to a full 64-bit value. */
1256 value &= ~upper;
1257 for (i = esize * 8; i < 64; i *= 2)
1258 value |= (value << i);
1259
1260 imm_enc.imm = value;
1261 imm_encoding = (const simd_imm_encoding *)
1262 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1263 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1264 if (imm_encoding == NULL)
1265 {
1266 DEBUG_TRACE ("exit with FALSE");
1267 return FALSE;
1268 }
1269 if (encoding != NULL)
1270 *encoding = imm_encoding->encoding;
1271 DEBUG_TRACE ("exit with TRUE");
1272 return TRUE;
1273 }
1274
1275 /* If 64-bit immediate IMM is in the format of
1276 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1277 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1278 of value "abcdefgh". Otherwise return -1. */
1279 int
1280 aarch64_shrink_expanded_imm8 (uint64_t imm)
1281 {
1282 int i, ret;
1283 uint32_t byte;
1284
1285 ret = 0;
1286 for (i = 0; i < 8; i++)
1287 {
1288 byte = (imm >> (8 * i)) & 0xff;
1289 if (byte == 0xff)
1290 ret |= 1 << i;
1291 else if (byte != 0x00)
1292 return -1;
1293 }
1294 return ret;
1295 }
1296
1297 /* Utility inline functions for operand_general_constraint_met_p. */
1298
1299 static inline void
1300 set_error (aarch64_operand_error *mismatch_detail,
1301 enum aarch64_operand_error_kind kind, int idx,
1302 const char* error)
1303 {
1304 if (mismatch_detail == NULL)
1305 return;
1306 mismatch_detail->kind = kind;
1307 mismatch_detail->index = idx;
1308 mismatch_detail->error = error;
1309 }
1310
1311 static inline void
1312 set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1313 const char* error)
1314 {
1315 if (mismatch_detail == NULL)
1316 return;
1317 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1318 }
1319
1320 static inline void
1321 set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1322 int idx, int lower_bound, int upper_bound,
1323 const char* error)
1324 {
1325 if (mismatch_detail == NULL)
1326 return;
1327 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1328 mismatch_detail->data[0] = lower_bound;
1329 mismatch_detail->data[1] = upper_bound;
1330 }
1331
1332 static inline void
1333 set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1334 int idx, int lower_bound, int upper_bound)
1335 {
1336 if (mismatch_detail == NULL)
1337 return;
1338 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1339 _("immediate value"));
1340 }
1341
1342 static inline void
1343 set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1344 int idx, int lower_bound, int upper_bound)
1345 {
1346 if (mismatch_detail == NULL)
1347 return;
1348 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1349 _("immediate offset"));
1350 }
1351
1352 static inline void
1353 set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1354 int idx, int lower_bound, int upper_bound)
1355 {
1356 if (mismatch_detail == NULL)
1357 return;
1358 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1359 _("register number"));
1360 }
1361
1362 static inline void
1363 set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1364 int idx, int lower_bound, int upper_bound)
1365 {
1366 if (mismatch_detail == NULL)
1367 return;
1368 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1369 _("register element index"));
1370 }
1371
1372 static inline void
1373 set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1374 int idx, int lower_bound, int upper_bound)
1375 {
1376 if (mismatch_detail == NULL)
1377 return;
1378 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1379 _("shift amount"));
1380 }
1381
1382 /* Report that the MUL modifier in operand IDX should be in the range
1383 [LOWER_BOUND, UPPER_BOUND]. */
1384 static inline void
1385 set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1386 int idx, int lower_bound, int upper_bound)
1387 {
1388 if (mismatch_detail == NULL)
1389 return;
1390 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1391 _("multiplier"));
1392 }
1393
1394 static inline void
1395 set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1396 int alignment)
1397 {
1398 if (mismatch_detail == NULL)
1399 return;
1400 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1401 mismatch_detail->data[0] = alignment;
1402 }
1403
1404 static inline void
1405 set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1406 int expected_num)
1407 {
1408 if (mismatch_detail == NULL)
1409 return;
1410 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1411 mismatch_detail->data[0] = expected_num;
1412 }
1413
1414 static inline void
1415 set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1416 const char* error)
1417 {
1418 if (mismatch_detail == NULL)
1419 return;
1420 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1421 }
1422
1423 /* General constraint checking based on operand code.
1424
1425 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1426 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1427
1428 This function has to be called after the qualifiers for all operands
1429 have been resolved.
1430
1431 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1432 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1433 of error message during the disassembling where error message is not
1434 wanted. We avoid the dynamic construction of strings of error messages
1435 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1436 use a combination of error code, static string and some integer data to
1437 represent an error. */
1438
1439 static int
1440 operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1441 enum aarch64_opnd type,
1442 const aarch64_opcode *opcode,
1443 aarch64_operand_error *mismatch_detail)
1444 {
1445 unsigned num, modifiers, shift;
1446 unsigned char size;
1447 int64_t imm, min_value, max_value;
1448 uint64_t uvalue, mask;
1449 const aarch64_opnd_info *opnd = opnds + idx;
1450 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1451
1452 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1453
1454 switch (aarch64_operands[type].op_class)
1455 {
1456 case AARCH64_OPND_CLASS_INT_REG:
1457 /* Check pair reg constraints for cas* instructions. */
1458 if (type == AARCH64_OPND_PAIRREG)
1459 {
1460 assert (idx == 1 || idx == 3);
1461 if (opnds[idx - 1].reg.regno % 2 != 0)
1462 {
1463 set_syntax_error (mismatch_detail, idx - 1,
1464 _("reg pair must start from even reg"));
1465 return 0;
1466 }
1467 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1468 {
1469 set_syntax_error (mismatch_detail, idx,
1470 _("reg pair must be contiguous"));
1471 return 0;
1472 }
1473 break;
1474 }
1475
1476 /* <Xt> may be optional in some IC and TLBI instructions. */
1477 if (type == AARCH64_OPND_Rt_SYS)
1478 {
1479 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1480 == AARCH64_OPND_CLASS_SYSTEM));
1481 if (opnds[1].present
1482 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1483 {
1484 set_other_error (mismatch_detail, idx, _("extraneous register"));
1485 return 0;
1486 }
1487 if (!opnds[1].present
1488 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1489 {
1490 set_other_error (mismatch_detail, idx, _("missing register"));
1491 return 0;
1492 }
1493 }
1494 switch (qualifier)
1495 {
1496 case AARCH64_OPND_QLF_WSP:
1497 case AARCH64_OPND_QLF_SP:
1498 if (!aarch64_stack_pointer_p (opnd))
1499 {
1500 set_other_error (mismatch_detail, idx,
1501 _("stack pointer register expected"));
1502 return 0;
1503 }
1504 break;
1505 default:
1506 break;
1507 }
1508 break;
1509
1510 case AARCH64_OPND_CLASS_SVE_REG:
1511 switch (type)
1512 {
1513 case AARCH64_OPND_SVE_Zm3_INDEX:
1514 case AARCH64_OPND_SVE_Zm3_22_INDEX:
1515 case AARCH64_OPND_SVE_Zm4_INDEX:
1516 size = get_operand_fields_width (get_operand_from_code (type));
1517 shift = get_operand_specific_data (&aarch64_operands[type]);
1518 mask = (1 << shift) - 1;
1519 if (opnd->reg.regno > mask)
1520 {
1521 assert (mask == 7 || mask == 15);
1522 set_other_error (mismatch_detail, idx,
1523 mask == 15
1524 ? _("z0-z15 expected")
1525 : _("z0-z7 expected"));
1526 return 0;
1527 }
1528 mask = (1 << (size - shift)) - 1;
1529 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1530 {
1531 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1532 return 0;
1533 }
1534 break;
1535
1536 case AARCH64_OPND_SVE_Zn_INDEX:
1537 size = aarch64_get_qualifier_esize (opnd->qualifier);
1538 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1539 {
1540 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1541 0, 64 / size - 1);
1542 return 0;
1543 }
1544 break;
1545
1546 case AARCH64_OPND_SVE_ZnxN:
1547 case AARCH64_OPND_SVE_ZtxN:
1548 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1549 {
1550 set_other_error (mismatch_detail, idx,
1551 _("invalid register list"));
1552 return 0;
1553 }
1554 break;
1555
1556 default:
1557 break;
1558 }
1559 break;
1560
1561 case AARCH64_OPND_CLASS_PRED_REG:
1562 if (opnd->reg.regno >= 8
1563 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1564 {
1565 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1566 return 0;
1567 }
1568 break;
1569
1570 case AARCH64_OPND_CLASS_COND:
1571 if (type == AARCH64_OPND_COND1
1572 && (opnds[idx].cond->value & 0xe) == 0xe)
1573 {
1574 /* Not allow AL or NV. */
1575 set_syntax_error (mismatch_detail, idx, NULL);
1576 }
1577 break;
1578
1579 case AARCH64_OPND_CLASS_ADDRESS:
1580 /* Check writeback. */
1581 switch (opcode->iclass)
1582 {
1583 case ldst_pos:
1584 case ldst_unscaled:
1585 case ldstnapair_offs:
1586 case ldstpair_off:
1587 case ldst_unpriv:
1588 if (opnd->addr.writeback == 1)
1589 {
1590 set_syntax_error (mismatch_detail, idx,
1591 _("unexpected address writeback"));
1592 return 0;
1593 }
1594 break;
1595 case ldst_imm10:
1596 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1597 {
1598 set_syntax_error (mismatch_detail, idx,
1599 _("unexpected address writeback"));
1600 return 0;
1601 }
1602 break;
1603 case ldst_imm9:
1604 case ldstpair_indexed:
1605 case ldstgv_indexed:
1606 case asisdlsep:
1607 case asisdlsop:
1608 if (opnd->addr.writeback == 0)
1609 {
1610 set_syntax_error (mismatch_detail, idx,
1611 _("address writeback expected"));
1612 return 0;
1613 }
1614 break;
1615 default:
1616 assert (opnd->addr.writeback == 0);
1617 break;
1618 }
1619 switch (type)
1620 {
1621 case AARCH64_OPND_ADDR_SIMM7:
1622 /* Scaled signed 7 bits immediate offset. */
1623 /* Get the size of the data element that is accessed, which may be
1624 different from that of the source register size,
1625 e.g. in strb/ldrb. */
1626 size = aarch64_get_qualifier_esize (opnd->qualifier);
1627 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1628 {
1629 set_offset_out_of_range_error (mismatch_detail, idx,
1630 -64 * size, 63 * size);
1631 return 0;
1632 }
1633 if (!value_aligned_p (opnd->addr.offset.imm, size))
1634 {
1635 set_unaligned_error (mismatch_detail, idx, size);
1636 return 0;
1637 }
1638 break;
1639 case AARCH64_OPND_ADDR_OFFSET:
1640 case AARCH64_OPND_ADDR_SIMM9:
1641 /* Unscaled signed 9 bits immediate offset. */
1642 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1643 {
1644 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1645 return 0;
1646 }
1647 break;
1648
1649 case AARCH64_OPND_ADDR_SIMM9_2:
1650 /* Unscaled signed 9 bits immediate offset, which has to be negative
1651 or unaligned. */
1652 size = aarch64_get_qualifier_esize (qualifier);
1653 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1654 && !value_aligned_p (opnd->addr.offset.imm, size))
1655 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1656 return 1;
1657 set_other_error (mismatch_detail, idx,
1658 _("negative or unaligned offset expected"));
1659 return 0;
1660
1661 case AARCH64_OPND_ADDR_SIMM10:
1662 /* Scaled signed 10 bits immediate offset. */
1663 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1664 {
1665 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1666 return 0;
1667 }
1668 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1669 {
1670 set_unaligned_error (mismatch_detail, idx, 8);
1671 return 0;
1672 }
1673 break;
1674
1675 case AARCH64_OPND_ADDR_SIMM11:
1676 /* Signed 11 bits immediate offset (multiple of 16). */
1677 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
1678 {
1679 set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
1680 return 0;
1681 }
1682
1683 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1684 {
1685 set_unaligned_error (mismatch_detail, idx, 16);
1686 return 0;
1687 }
1688 break;
1689
1690 case AARCH64_OPND_ADDR_SIMM13:
1691 /* Signed 13 bits immediate offset (multiple of 16). */
1692 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
1693 {
1694 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
1695 return 0;
1696 }
1697
1698 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1699 {
1700 set_unaligned_error (mismatch_detail, idx, 16);
1701 return 0;
1702 }
1703 break;
1704
1705 case AARCH64_OPND_SIMD_ADDR_POST:
1706 /* AdvSIMD load/store multiple structures, post-index. */
1707 assert (idx == 1);
1708 if (opnd->addr.offset.is_reg)
1709 {
1710 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1711 return 1;
1712 else
1713 {
1714 set_other_error (mismatch_detail, idx,
1715 _("invalid register offset"));
1716 return 0;
1717 }
1718 }
1719 else
1720 {
1721 const aarch64_opnd_info *prev = &opnds[idx-1];
1722 unsigned num_bytes; /* total number of bytes transferred. */
1723 /* The opcode dependent area stores the number of elements in
1724 each structure to be loaded/stored. */
1725 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1726 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1727 /* Special handling of loading single structure to all lane. */
1728 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1729 * aarch64_get_qualifier_esize (prev->qualifier);
1730 else
1731 num_bytes = prev->reglist.num_regs
1732 * aarch64_get_qualifier_esize (prev->qualifier)
1733 * aarch64_get_qualifier_nelem (prev->qualifier);
1734 if ((int) num_bytes != opnd->addr.offset.imm)
1735 {
1736 set_other_error (mismatch_detail, idx,
1737 _("invalid post-increment amount"));
1738 return 0;
1739 }
1740 }
1741 break;
1742
1743 case AARCH64_OPND_ADDR_REGOFF:
1744 /* Get the size of the data element that is accessed, which may be
1745 different from that of the source register size,
1746 e.g. in strb/ldrb. */
1747 size = aarch64_get_qualifier_esize (opnd->qualifier);
1748 /* It is either no shift or shift by the binary logarithm of SIZE. */
1749 if (opnd->shifter.amount != 0
1750 && opnd->shifter.amount != (int)get_logsz (size))
1751 {
1752 set_other_error (mismatch_detail, idx,
1753 _("invalid shift amount"));
1754 return 0;
1755 }
1756 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1757 operators. */
1758 switch (opnd->shifter.kind)
1759 {
1760 case AARCH64_MOD_UXTW:
1761 case AARCH64_MOD_LSL:
1762 case AARCH64_MOD_SXTW:
1763 case AARCH64_MOD_SXTX: break;
1764 default:
1765 set_other_error (mismatch_detail, idx,
1766 _("invalid extend/shift operator"));
1767 return 0;
1768 }
1769 break;
1770
1771 case AARCH64_OPND_ADDR_UIMM12:
1772 imm = opnd->addr.offset.imm;
1773 /* Get the size of the data element that is accessed, which may be
1774 different from that of the source register size,
1775 e.g. in strb/ldrb. */
1776 size = aarch64_get_qualifier_esize (qualifier);
1777 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1778 {
1779 set_offset_out_of_range_error (mismatch_detail, idx,
1780 0, 4095 * size);
1781 return 0;
1782 }
1783 if (!value_aligned_p (opnd->addr.offset.imm, size))
1784 {
1785 set_unaligned_error (mismatch_detail, idx, size);
1786 return 0;
1787 }
1788 break;
1789
1790 case AARCH64_OPND_ADDR_PCREL14:
1791 case AARCH64_OPND_ADDR_PCREL19:
1792 case AARCH64_OPND_ADDR_PCREL21:
1793 case AARCH64_OPND_ADDR_PCREL26:
1794 imm = opnd->imm.value;
1795 if (operand_need_shift_by_two (get_operand_from_code (type)))
1796 {
1797 /* The offset value in a PC-relative branch instruction is alway
1798 4-byte aligned and is encoded without the lowest 2 bits. */
1799 if (!value_aligned_p (imm, 4))
1800 {
1801 set_unaligned_error (mismatch_detail, idx, 4);
1802 return 0;
1803 }
1804 /* Right shift by 2 so that we can carry out the following check
1805 canonically. */
1806 imm >>= 2;
1807 }
1808 size = get_operand_fields_width (get_operand_from_code (type));
1809 if (!value_fit_signed_field_p (imm, size))
1810 {
1811 set_other_error (mismatch_detail, idx,
1812 _("immediate out of range"));
1813 return 0;
1814 }
1815 break;
1816
1817 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1818 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1819 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1820 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1821 min_value = -8;
1822 max_value = 7;
1823 sve_imm_offset_vl:
1824 assert (!opnd->addr.offset.is_reg);
1825 assert (opnd->addr.preind);
1826 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1827 min_value *= num;
1828 max_value *= num;
1829 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1830 || (opnd->shifter.operator_present
1831 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1832 {
1833 set_other_error (mismatch_detail, idx,
1834 _("invalid addressing mode"));
1835 return 0;
1836 }
1837 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1838 {
1839 set_offset_out_of_range_error (mismatch_detail, idx,
1840 min_value, max_value);
1841 return 0;
1842 }
1843 if (!value_aligned_p (opnd->addr.offset.imm, num))
1844 {
1845 set_unaligned_error (mismatch_detail, idx, num);
1846 return 0;
1847 }
1848 break;
1849
1850 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1851 min_value = -32;
1852 max_value = 31;
1853 goto sve_imm_offset_vl;
1854
1855 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1856 min_value = -256;
1857 max_value = 255;
1858 goto sve_imm_offset_vl;
1859
1860 case AARCH64_OPND_SVE_ADDR_RI_U6:
1861 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1862 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1863 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1864 min_value = 0;
1865 max_value = 63;
1866 sve_imm_offset:
1867 assert (!opnd->addr.offset.is_reg);
1868 assert (opnd->addr.preind);
1869 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1870 min_value *= num;
1871 max_value *= num;
1872 if (opnd->shifter.operator_present
1873 || opnd->shifter.amount_present)
1874 {
1875 set_other_error (mismatch_detail, idx,
1876 _("invalid addressing mode"));
1877 return 0;
1878 }
1879 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1880 {
1881 set_offset_out_of_range_error (mismatch_detail, idx,
1882 min_value, max_value);
1883 return 0;
1884 }
1885 if (!value_aligned_p (opnd->addr.offset.imm, num))
1886 {
1887 set_unaligned_error (mismatch_detail, idx, num);
1888 return 0;
1889 }
1890 break;
1891
1892 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
1893 min_value = -8;
1894 max_value = 7;
1895 goto sve_imm_offset;
1896
1897 case AARCH64_OPND_SVE_ADDR_R:
1898 case AARCH64_OPND_SVE_ADDR_RR:
1899 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1900 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1901 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1902 case AARCH64_OPND_SVE_ADDR_RX:
1903 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1904 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1905 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1906 case AARCH64_OPND_SVE_ADDR_RZ:
1907 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1908 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1909 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1910 modifiers = 1 << AARCH64_MOD_LSL;
1911 sve_rr_operand:
1912 assert (opnd->addr.offset.is_reg);
1913 assert (opnd->addr.preind);
1914 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1915 && opnd->addr.offset.regno == 31)
1916 {
1917 set_other_error (mismatch_detail, idx,
1918 _("index register xzr is not allowed"));
1919 return 0;
1920 }
1921 if (((1 << opnd->shifter.kind) & modifiers) == 0
1922 || (opnd->shifter.amount
1923 != get_operand_specific_data (&aarch64_operands[type])))
1924 {
1925 set_other_error (mismatch_detail, idx,
1926 _("invalid addressing mode"));
1927 return 0;
1928 }
1929 break;
1930
1931 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1932 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1933 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1934 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1935 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1936 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1937 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1938 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1939 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1940 goto sve_rr_operand;
1941
1942 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1943 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1944 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1945 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1946 min_value = 0;
1947 max_value = 31;
1948 goto sve_imm_offset;
1949
1950 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1951 modifiers = 1 << AARCH64_MOD_LSL;
1952 sve_zz_operand:
1953 assert (opnd->addr.offset.is_reg);
1954 assert (opnd->addr.preind);
1955 if (((1 << opnd->shifter.kind) & modifiers) == 0
1956 || opnd->shifter.amount < 0
1957 || opnd->shifter.amount > 3)
1958 {
1959 set_other_error (mismatch_detail, idx,
1960 _("invalid addressing mode"));
1961 return 0;
1962 }
1963 break;
1964
1965 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1966 modifiers = (1 << AARCH64_MOD_SXTW);
1967 goto sve_zz_operand;
1968
1969 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1970 modifiers = 1 << AARCH64_MOD_UXTW;
1971 goto sve_zz_operand;
1972
1973 default:
1974 break;
1975 }
1976 break;
1977
1978 case AARCH64_OPND_CLASS_SIMD_REGLIST:
1979 if (type == AARCH64_OPND_LEt)
1980 {
1981 /* Get the upper bound for the element index. */
1982 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
1983 if (!value_in_range_p (opnd->reglist.index, 0, num))
1984 {
1985 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
1986 return 0;
1987 }
1988 }
1989 /* The opcode dependent area stores the number of elements in
1990 each structure to be loaded/stored. */
1991 num = get_opcode_dependent_value (opcode);
1992 switch (type)
1993 {
1994 case AARCH64_OPND_LVt:
1995 assert (num >= 1 && num <= 4);
1996 /* Unless LD1/ST1, the number of registers should be equal to that
1997 of the structure elements. */
1998 if (num != 1 && opnd->reglist.num_regs != num)
1999 {
2000 set_reg_list_error (mismatch_detail, idx, num);
2001 return 0;
2002 }
2003 break;
2004 case AARCH64_OPND_LVt_AL:
2005 case AARCH64_OPND_LEt:
2006 assert (num >= 1 && num <= 4);
2007 /* The number of registers should be equal to that of the structure
2008 elements. */
2009 if (opnd->reglist.num_regs != num)
2010 {
2011 set_reg_list_error (mismatch_detail, idx, num);
2012 return 0;
2013 }
2014 break;
2015 default:
2016 break;
2017 }
2018 break;
2019
2020 case AARCH64_OPND_CLASS_IMMEDIATE:
2021 /* Constraint check on immediate operand. */
2022 imm = opnd->imm.value;
2023 /* E.g. imm_0_31 constrains value to be 0..31. */
2024 if (qualifier_value_in_range_constraint_p (qualifier)
2025 && !value_in_range_p (imm, get_lower_bound (qualifier),
2026 get_upper_bound (qualifier)))
2027 {
2028 set_imm_out_of_range_error (mismatch_detail, idx,
2029 get_lower_bound (qualifier),
2030 get_upper_bound (qualifier));
2031 return 0;
2032 }
2033
2034 switch (type)
2035 {
2036 case AARCH64_OPND_AIMM:
2037 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2038 {
2039 set_other_error (mismatch_detail, idx,
2040 _("invalid shift operator"));
2041 return 0;
2042 }
2043 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2044 {
2045 set_other_error (mismatch_detail, idx,
2046 _("shift amount must be 0 or 12"));
2047 return 0;
2048 }
2049 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2050 {
2051 set_other_error (mismatch_detail, idx,
2052 _("immediate out of range"));
2053 return 0;
2054 }
2055 break;
2056
2057 case AARCH64_OPND_HALF:
2058 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2059 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2060 {
2061 set_other_error (mismatch_detail, idx,
2062 _("invalid shift operator"));
2063 return 0;
2064 }
2065 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2066 if (!value_aligned_p (opnd->shifter.amount, 16))
2067 {
2068 set_other_error (mismatch_detail, idx,
2069 _("shift amount must be a multiple of 16"));
2070 return 0;
2071 }
2072 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2073 {
2074 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2075 0, size * 8 - 16);
2076 return 0;
2077 }
2078 if (opnd->imm.value < 0)
2079 {
2080 set_other_error (mismatch_detail, idx,
2081 _("negative immediate value not allowed"));
2082 return 0;
2083 }
2084 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2085 {
2086 set_other_error (mismatch_detail, idx,
2087 _("immediate out of range"));
2088 return 0;
2089 }
2090 break;
2091
2092 case AARCH64_OPND_IMM_MOV:
2093 {
2094 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2095 imm = opnd->imm.value;
2096 assert (idx == 1);
2097 switch (opcode->op)
2098 {
2099 case OP_MOV_IMM_WIDEN:
2100 imm = ~imm;
2101 /* Fall through. */
2102 case OP_MOV_IMM_WIDE:
2103 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
2104 {
2105 set_other_error (mismatch_detail, idx,
2106 _("immediate out of range"));
2107 return 0;
2108 }
2109 break;
2110 case OP_MOV_IMM_LOG:
2111 if (!aarch64_logical_immediate_p (imm, esize, NULL))
2112 {
2113 set_other_error (mismatch_detail, idx,
2114 _("immediate out of range"));
2115 return 0;
2116 }
2117 break;
2118 default:
2119 assert (0);
2120 return 0;
2121 }
2122 }
2123 break;
2124
2125 case AARCH64_OPND_NZCV:
2126 case AARCH64_OPND_CCMP_IMM:
2127 case AARCH64_OPND_EXCEPTION:
2128 case AARCH64_OPND_UIMM4:
2129 case AARCH64_OPND_UIMM4_ADDG:
2130 case AARCH64_OPND_UIMM7:
2131 case AARCH64_OPND_UIMM3_OP1:
2132 case AARCH64_OPND_UIMM3_OP2:
2133 case AARCH64_OPND_SVE_UIMM3:
2134 case AARCH64_OPND_SVE_UIMM7:
2135 case AARCH64_OPND_SVE_UIMM8:
2136 case AARCH64_OPND_SVE_UIMM8_53:
2137 size = get_operand_fields_width (get_operand_from_code (type));
2138 assert (size < 32);
2139 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2140 {
2141 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2142 (1 << size) - 1);
2143 return 0;
2144 }
2145 break;
2146
2147 case AARCH64_OPND_UIMM10:
2148 /* Scaled unsigned 10 bits immediate offset. */
2149 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2150 {
2151 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2152 return 0;
2153 }
2154
2155 if (!value_aligned_p (opnd->imm.value, 16))
2156 {
2157 set_unaligned_error (mismatch_detail, idx, 16);
2158 return 0;
2159 }
2160 break;
2161
2162 case AARCH64_OPND_SIMM5:
2163 case AARCH64_OPND_SVE_SIMM5:
2164 case AARCH64_OPND_SVE_SIMM5B:
2165 case AARCH64_OPND_SVE_SIMM6:
2166 case AARCH64_OPND_SVE_SIMM8:
2167 size = get_operand_fields_width (get_operand_from_code (type));
2168 assert (size < 32);
2169 if (!value_fit_signed_field_p (opnd->imm.value, size))
2170 {
2171 set_imm_out_of_range_error (mismatch_detail, idx,
2172 -(1 << (size - 1)),
2173 (1 << (size - 1)) - 1);
2174 return 0;
2175 }
2176 break;
2177
2178 case AARCH64_OPND_WIDTH:
2179 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
2180 && opnds[0].type == AARCH64_OPND_Rd);
2181 size = get_upper_bound (qualifier);
2182 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2183 /* lsb+width <= reg.size */
2184 {
2185 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2186 size - opnds[idx-1].imm.value);
2187 return 0;
2188 }
2189 break;
2190
2191 case AARCH64_OPND_LIMM:
2192 case AARCH64_OPND_SVE_LIMM:
2193 {
2194 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2195 uint64_t uimm = opnd->imm.value;
2196 if (opcode->op == OP_BIC)
2197 uimm = ~uimm;
2198 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2199 {
2200 set_other_error (mismatch_detail, idx,
2201 _("immediate out of range"));
2202 return 0;
2203 }
2204 }
2205 break;
2206
2207 case AARCH64_OPND_IMM0:
2208 case AARCH64_OPND_FPIMM0:
2209 if (opnd->imm.value != 0)
2210 {
2211 set_other_error (mismatch_detail, idx,
2212 _("immediate zero expected"));
2213 return 0;
2214 }
2215 break;
2216
2217 case AARCH64_OPND_IMM_ROT1:
2218 case AARCH64_OPND_IMM_ROT2:
2219 case AARCH64_OPND_SVE_IMM_ROT2:
2220 if (opnd->imm.value != 0
2221 && opnd->imm.value != 90
2222 && opnd->imm.value != 180
2223 && opnd->imm.value != 270)
2224 {
2225 set_other_error (mismatch_detail, idx,
2226 _("rotate expected to be 0, 90, 180 or 270"));
2227 return 0;
2228 }
2229 break;
2230
2231 case AARCH64_OPND_IMM_ROT3:
2232 case AARCH64_OPND_SVE_IMM_ROT1:
2233 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2234 {
2235 set_other_error (mismatch_detail, idx,
2236 _("rotate expected to be 90 or 270"));
2237 return 0;
2238 }
2239 break;
2240
2241 case AARCH64_OPND_SHLL_IMM:
2242 assert (idx == 2);
2243 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2244 if (opnd->imm.value != size)
2245 {
2246 set_other_error (mismatch_detail, idx,
2247 _("invalid shift amount"));
2248 return 0;
2249 }
2250 break;
2251
2252 case AARCH64_OPND_IMM_VLSL:
2253 size = aarch64_get_qualifier_esize (qualifier);
2254 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2255 {
2256 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2257 size * 8 - 1);
2258 return 0;
2259 }
2260 break;
2261
2262 case AARCH64_OPND_IMM_VLSR:
2263 size = aarch64_get_qualifier_esize (qualifier);
2264 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2265 {
2266 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2267 return 0;
2268 }
2269 break;
2270
2271 case AARCH64_OPND_SIMD_IMM:
2272 case AARCH64_OPND_SIMD_IMM_SFT:
2273 /* Qualifier check. */
2274 switch (qualifier)
2275 {
2276 case AARCH64_OPND_QLF_LSL:
2277 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2278 {
2279 set_other_error (mismatch_detail, idx,
2280 _("invalid shift operator"));
2281 return 0;
2282 }
2283 break;
2284 case AARCH64_OPND_QLF_MSL:
2285 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2286 {
2287 set_other_error (mismatch_detail, idx,
2288 _("invalid shift operator"));
2289 return 0;
2290 }
2291 break;
2292 case AARCH64_OPND_QLF_NIL:
2293 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2294 {
2295 set_other_error (mismatch_detail, idx,
2296 _("shift is not permitted"));
2297 return 0;
2298 }
2299 break;
2300 default:
2301 assert (0);
2302 return 0;
2303 }
2304 /* Is the immediate valid? */
2305 assert (idx == 1);
2306 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2307 {
2308 /* uimm8 or simm8 */
2309 if (!value_in_range_p (opnd->imm.value, -128, 255))
2310 {
2311 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
2312 return 0;
2313 }
2314 }
2315 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2316 {
2317 /* uimm64 is not
2318 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2319 ffffffffgggggggghhhhhhhh'. */
2320 set_other_error (mismatch_detail, idx,
2321 _("invalid value for immediate"));
2322 return 0;
2323 }
2324 /* Is the shift amount valid? */
2325 switch (opnd->shifter.kind)
2326 {
2327 case AARCH64_MOD_LSL:
2328 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2329 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
2330 {
2331 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2332 (size - 1) * 8);
2333 return 0;
2334 }
2335 if (!value_aligned_p (opnd->shifter.amount, 8))
2336 {
2337 set_unaligned_error (mismatch_detail, idx, 8);
2338 return 0;
2339 }
2340 break;
2341 case AARCH64_MOD_MSL:
2342 /* Only 8 and 16 are valid shift amount. */
2343 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2344 {
2345 set_other_error (mismatch_detail, idx,
2346 _("shift amount must be 0 or 16"));
2347 return 0;
2348 }
2349 break;
2350 default:
2351 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2352 {
2353 set_other_error (mismatch_detail, idx,
2354 _("invalid shift operator"));
2355 return 0;
2356 }
2357 break;
2358 }
2359 break;
2360
2361 case AARCH64_OPND_FPIMM:
2362 case AARCH64_OPND_SIMD_FPIMM:
2363 case AARCH64_OPND_SVE_FPIMM8:
2364 if (opnd->imm.is_fp == 0)
2365 {
2366 set_other_error (mismatch_detail, idx,
2367 _("floating-point immediate expected"));
2368 return 0;
2369 }
2370 /* The value is expected to be an 8-bit floating-point constant with
2371 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2372 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2373 instruction). */
2374 if (!value_in_range_p (opnd->imm.value, 0, 255))
2375 {
2376 set_other_error (mismatch_detail, idx,
2377 _("immediate out of range"));
2378 return 0;
2379 }
2380 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2381 {
2382 set_other_error (mismatch_detail, idx,
2383 _("invalid shift operator"));
2384 return 0;
2385 }
2386 break;
2387
2388 case AARCH64_OPND_SVE_AIMM:
2389 min_value = 0;
2390 sve_aimm:
2391 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2392 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2393 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2394 uvalue = opnd->imm.value;
2395 shift = opnd->shifter.amount;
2396 if (size == 1)
2397 {
2398 if (shift != 0)
2399 {
2400 set_other_error (mismatch_detail, idx,
2401 _("no shift amount allowed for"
2402 " 8-bit constants"));
2403 return 0;
2404 }
2405 }
2406 else
2407 {
2408 if (shift != 0 && shift != 8)
2409 {
2410 set_other_error (mismatch_detail, idx,
2411 _("shift amount must be 0 or 8"));
2412 return 0;
2413 }
2414 if (shift == 0 && (uvalue & 0xff) == 0)
2415 {
2416 shift = 8;
2417 uvalue = (int64_t) uvalue / 256;
2418 }
2419 }
2420 mask >>= shift;
2421 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2422 {
2423 set_other_error (mismatch_detail, idx,
2424 _("immediate too big for element size"));
2425 return 0;
2426 }
2427 uvalue = (uvalue - min_value) & mask;
2428 if (uvalue > 0xff)
2429 {
2430 set_other_error (mismatch_detail, idx,
2431 _("invalid arithmetic immediate"));
2432 return 0;
2433 }
2434 break;
2435
2436 case AARCH64_OPND_SVE_ASIMM:
2437 min_value = -128;
2438 goto sve_aimm;
2439
2440 case AARCH64_OPND_SVE_I1_HALF_ONE:
2441 assert (opnd->imm.is_fp);
2442 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2443 {
2444 set_other_error (mismatch_detail, idx,
2445 _("floating-point value must be 0.5 or 1.0"));
2446 return 0;
2447 }
2448 break;
2449
2450 case AARCH64_OPND_SVE_I1_HALF_TWO:
2451 assert (opnd->imm.is_fp);
2452 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2453 {
2454 set_other_error (mismatch_detail, idx,
2455 _("floating-point value must be 0.5 or 2.0"));
2456 return 0;
2457 }
2458 break;
2459
2460 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2461 assert (opnd->imm.is_fp);
2462 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2463 {
2464 set_other_error (mismatch_detail, idx,
2465 _("floating-point value must be 0.0 or 1.0"));
2466 return 0;
2467 }
2468 break;
2469
2470 case AARCH64_OPND_SVE_INV_LIMM:
2471 {
2472 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2473 uint64_t uimm = ~opnd->imm.value;
2474 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2475 {
2476 set_other_error (mismatch_detail, idx,
2477 _("immediate out of range"));
2478 return 0;
2479 }
2480 }
2481 break;
2482
2483 case AARCH64_OPND_SVE_LIMM_MOV:
2484 {
2485 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2486 uint64_t uimm = opnd->imm.value;
2487 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2488 {
2489 set_other_error (mismatch_detail, idx,
2490 _("immediate out of range"));
2491 return 0;
2492 }
2493 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2494 {
2495 set_other_error (mismatch_detail, idx,
2496 _("invalid replicated MOV immediate"));
2497 return 0;
2498 }
2499 }
2500 break;
2501
2502 case AARCH64_OPND_SVE_PATTERN_SCALED:
2503 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2504 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2505 {
2506 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2507 return 0;
2508 }
2509 break;
2510
2511 case AARCH64_OPND_SVE_SHLIMM_PRED:
2512 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
2513 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2514 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2515 {
2516 set_imm_out_of_range_error (mismatch_detail, idx,
2517 0, 8 * size - 1);
2518 return 0;
2519 }
2520 break;
2521
2522 case AARCH64_OPND_SVE_SHRIMM_PRED:
2523 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
2524 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2525 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2526 {
2527 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
2528 return 0;
2529 }
2530 break;
2531
2532 default:
2533 break;
2534 }
2535 break;
2536
2537 case AARCH64_OPND_CLASS_SYSTEM:
2538 switch (type)
2539 {
2540 case AARCH64_OPND_PSTATEFIELD:
2541 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
2542 /* MSR UAO, #uimm4
2543 MSR PAN, #uimm4
2544 MSR SSBS,#uimm4
2545 The immediate must be #0 or #1. */
2546 if ((opnd->pstatefield == 0x03 /* UAO. */
2547 || opnd->pstatefield == 0x04 /* PAN. */
2548 || opnd->pstatefield == 0x19 /* SSBS. */
2549 || opnd->pstatefield == 0x1a) /* DIT. */
2550 && opnds[1].imm.value > 1)
2551 {
2552 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2553 return 0;
2554 }
2555 /* MSR SPSel, #uimm4
2556 Uses uimm4 as a control value to select the stack pointer: if
2557 bit 0 is set it selects the current exception level's stack
2558 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2559 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2560 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2561 {
2562 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2563 return 0;
2564 }
2565 break;
2566 default:
2567 break;
2568 }
2569 break;
2570
2571 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2572 /* Get the upper bound for the element index. */
2573 if (opcode->op == OP_FCMLA_ELEM)
2574 /* FCMLA index range depends on the vector size of other operands
2575 and is halfed because complex numbers take two elements. */
2576 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2577 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2578 else
2579 num = 16;
2580 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
2581 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
2582
2583 /* Index out-of-range. */
2584 if (!value_in_range_p (opnd->reglane.index, 0, num))
2585 {
2586 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2587 return 0;
2588 }
2589 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2590 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2591 number is encoded in "size:M:Rm":
2592 size <Vm>
2593 00 RESERVED
2594 01 0:Rm
2595 10 M:Rm
2596 11 RESERVED */
2597 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
2598 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2599 {
2600 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2601 return 0;
2602 }
2603 break;
2604
2605 case AARCH64_OPND_CLASS_MODIFIED_REG:
2606 assert (idx == 1 || idx == 2);
2607 switch (type)
2608 {
2609 case AARCH64_OPND_Rm_EXT:
2610 if (!aarch64_extend_operator_p (opnd->shifter.kind)
2611 && opnd->shifter.kind != AARCH64_MOD_LSL)
2612 {
2613 set_other_error (mismatch_detail, idx,
2614 _("extend operator expected"));
2615 return 0;
2616 }
2617 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2618 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2619 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2620 case. */
2621 if (!aarch64_stack_pointer_p (opnds + 0)
2622 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2623 {
2624 if (!opnd->shifter.operator_present)
2625 {
2626 set_other_error (mismatch_detail, idx,
2627 _("missing extend operator"));
2628 return 0;
2629 }
2630 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2631 {
2632 set_other_error (mismatch_detail, idx,
2633 _("'LSL' operator not allowed"));
2634 return 0;
2635 }
2636 }
2637 assert (opnd->shifter.operator_present /* Default to LSL. */
2638 || opnd->shifter.kind == AARCH64_MOD_LSL);
2639 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2640 {
2641 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2642 return 0;
2643 }
2644 /* In the 64-bit form, the final register operand is written as Wm
2645 for all but the (possibly omitted) UXTX/LSL and SXTX
2646 operators.
2647 N.B. GAS allows X register to be used with any operator as a
2648 programming convenience. */
2649 if (qualifier == AARCH64_OPND_QLF_X
2650 && opnd->shifter.kind != AARCH64_MOD_LSL
2651 && opnd->shifter.kind != AARCH64_MOD_UXTX
2652 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2653 {
2654 set_other_error (mismatch_detail, idx, _("W register expected"));
2655 return 0;
2656 }
2657 break;
2658
2659 case AARCH64_OPND_Rm_SFT:
2660 /* ROR is not available to the shifted register operand in
2661 arithmetic instructions. */
2662 if (!aarch64_shift_operator_p (opnd->shifter.kind))
2663 {
2664 set_other_error (mismatch_detail, idx,
2665 _("shift operator expected"));
2666 return 0;
2667 }
2668 if (opnd->shifter.kind == AARCH64_MOD_ROR
2669 && opcode->iclass != log_shift)
2670 {
2671 set_other_error (mismatch_detail, idx,
2672 _("'ROR' operator not allowed"));
2673 return 0;
2674 }
2675 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2676 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2677 {
2678 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2679 return 0;
2680 }
2681 break;
2682
2683 default:
2684 break;
2685 }
2686 break;
2687
2688 default:
2689 break;
2690 }
2691
2692 return 1;
2693 }
2694
2695 /* Main entrypoint for the operand constraint checking.
2696
2697 Return 1 if operands of *INST meet the constraint applied by the operand
2698 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2699 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2700 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2701 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2702 error kind when it is notified that an instruction does not pass the check).
2703
2704 Un-determined operand qualifiers may get established during the process. */
2705
2706 int
2707 aarch64_match_operands_constraint (aarch64_inst *inst,
2708 aarch64_operand_error *mismatch_detail)
2709 {
2710 int i;
2711
2712 DEBUG_TRACE ("enter");
2713
2714 /* Check for cases where a source register needs to be the same as the
2715 destination register. Do this before matching qualifiers since if
2716 an instruction has both invalid tying and invalid qualifiers,
2717 the error about qualifiers would suggest several alternative
2718 instructions that also have invalid tying. */
2719 i = inst->opcode->tied_operand;
2720 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2721 {
2722 if (mismatch_detail)
2723 {
2724 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2725 mismatch_detail->index = i;
2726 mismatch_detail->error = NULL;
2727 }
2728 return 0;
2729 }
2730
2731 /* Match operands' qualifier.
2732 *INST has already had qualifier establish for some, if not all, of
2733 its operands; we need to find out whether these established
2734 qualifiers match one of the qualifier sequence in
2735 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2736 with the corresponding qualifier in such a sequence.
2737 Only basic operand constraint checking is done here; the more thorough
2738 constraint checking will carried out by operand_general_constraint_met_p,
2739 which has be to called after this in order to get all of the operands'
2740 qualifiers established. */
2741 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2742 {
2743 DEBUG_TRACE ("FAIL on operand qualifier matching");
2744 if (mismatch_detail)
2745 {
2746 /* Return an error type to indicate that it is the qualifier
2747 matching failure; we don't care about which operand as there
2748 are enough information in the opcode table to reproduce it. */
2749 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2750 mismatch_detail->index = -1;
2751 mismatch_detail->error = NULL;
2752 }
2753 return 0;
2754 }
2755
2756 /* Match operands' constraint. */
2757 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2758 {
2759 enum aarch64_opnd type = inst->opcode->operands[i];
2760 if (type == AARCH64_OPND_NIL)
2761 break;
2762 if (inst->operands[i].skip)
2763 {
2764 DEBUG_TRACE ("skip the incomplete operand %d", i);
2765 continue;
2766 }
2767 if (operand_general_constraint_met_p (inst->operands, i, type,
2768 inst->opcode, mismatch_detail) == 0)
2769 {
2770 DEBUG_TRACE ("FAIL on operand %d", i);
2771 return 0;
2772 }
2773 }
2774
2775 DEBUG_TRACE ("PASS");
2776
2777 return 1;
2778 }
2779
2780 /* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2781 Also updates the TYPE of each INST->OPERANDS with the corresponding
2782 value of OPCODE->OPERANDS.
2783
2784 Note that some operand qualifiers may need to be manually cleared by
2785 the caller before it further calls the aarch64_opcode_encode; by
2786 doing this, it helps the qualifier matching facilities work
2787 properly. */
2788
2789 const aarch64_opcode*
2790 aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2791 {
2792 int i;
2793 const aarch64_opcode *old = inst->opcode;
2794
2795 inst->opcode = opcode;
2796
2797 /* Update the operand types. */
2798 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2799 {
2800 inst->operands[i].type = opcode->operands[i];
2801 if (opcode->operands[i] == AARCH64_OPND_NIL)
2802 break;
2803 }
2804
2805 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2806
2807 return old;
2808 }
2809
2810 int
2811 aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2812 {
2813 int i;
2814 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2815 if (operands[i] == operand)
2816 return i;
2817 else if (operands[i] == AARCH64_OPND_NIL)
2818 break;
2819 return -1;
2820 }
2821 \f
2822 /* R0...R30, followed by FOR31. */
2823 #define BANK(R, FOR31) \
2824 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2825 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2826 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2827 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
2828 /* [0][0] 32-bit integer regs with sp Wn
2829 [0][1] 64-bit integer regs with sp Xn sf=1
2830 [1][0] 32-bit integer regs with #0 Wn
2831 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2832 static const char *int_reg[2][2][32] = {
2833 #define R32(X) "w" #X
2834 #define R64(X) "x" #X
2835 { BANK (R32, "wsp"), BANK (R64, "sp") },
2836 { BANK (R32, "wzr"), BANK (R64, "xzr") }
2837 #undef R64
2838 #undef R32
2839 };
2840
2841 /* Names of the SVE vector registers, first with .S suffixes,
2842 then with .D suffixes. */
2843
2844 static const char *sve_reg[2][32] = {
2845 #define ZS(X) "z" #X ".s"
2846 #define ZD(X) "z" #X ".d"
2847 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2848 #undef ZD
2849 #undef ZS
2850 };
2851 #undef BANK
2852
2853 /* Return the integer register name.
2854 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2855
2856 static inline const char *
2857 get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2858 {
2859 const int has_zr = sp_reg_p ? 0 : 1;
2860 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2861 return int_reg[has_zr][is_64][regno];
2862 }
2863
2864 /* Like get_int_reg_name, but IS_64 is always 1. */
2865
2866 static inline const char *
2867 get_64bit_int_reg_name (int regno, int sp_reg_p)
2868 {
2869 const int has_zr = sp_reg_p ? 0 : 1;
2870 return int_reg[has_zr][1][regno];
2871 }
2872
2873 /* Get the name of the integer offset register in OPND, using the shift type
2874 to decide whether it's a word or doubleword. */
2875
2876 static inline const char *
2877 get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2878 {
2879 switch (opnd->shifter.kind)
2880 {
2881 case AARCH64_MOD_UXTW:
2882 case AARCH64_MOD_SXTW:
2883 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2884
2885 case AARCH64_MOD_LSL:
2886 case AARCH64_MOD_SXTX:
2887 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2888
2889 default:
2890 abort ();
2891 }
2892 }
2893
2894 /* Get the name of the SVE vector offset register in OPND, using the operand
2895 qualifier to decide whether the suffix should be .S or .D. */
2896
2897 static inline const char *
2898 get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2899 {
2900 assert (qualifier == AARCH64_OPND_QLF_S_S
2901 || qualifier == AARCH64_OPND_QLF_S_D);
2902 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2903 }
2904
2905 /* Types for expanding an encoded 8-bit value to a floating-point value. */
2906
2907 typedef union
2908 {
2909 uint64_t i;
2910 double d;
2911 } double_conv_t;
2912
2913 typedef union
2914 {
2915 uint32_t i;
2916 float f;
2917 } single_conv_t;
2918
2919 typedef union
2920 {
2921 uint32_t i;
2922 float f;
2923 } half_conv_t;
2924
2925 /* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2926 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2927 (depending on the type of the instruction). IMM8 will be expanded to a
2928 single-precision floating-point value (SIZE == 4) or a double-precision
2929 floating-point value (SIZE == 8). A half-precision floating-point value
2930 (SIZE == 2) is expanded to a single-precision floating-point value. The
2931 expanded value is returned. */
2932
2933 static uint64_t
2934 expand_fp_imm (int size, uint32_t imm8)
2935 {
2936 uint64_t imm = 0;
2937 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2938
2939 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2940 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2941 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2942 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2943 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
2944 if (size == 8)
2945 {
2946 imm = (imm8_7 << (63-32)) /* imm8<7> */
2947 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2948 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2949 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2950 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2951 imm <<= 32;
2952 }
2953 else if (size == 4 || size == 2)
2954 {
2955 imm = (imm8_7 << 31) /* imm8<7> */
2956 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2957 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2958 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2959 }
2960 else
2961 {
2962 /* An unsupported size. */
2963 assert (0);
2964 }
2965
2966 return imm;
2967 }
2968
2969 /* Produce the string representation of the register list operand *OPND
2970 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2971 the register name that comes before the register number, such as "v". */
2972 static void
2973 print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
2974 const char *prefix)
2975 {
2976 const int num_regs = opnd->reglist.num_regs;
2977 const int first_reg = opnd->reglist.first_regno;
2978 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
2979 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
2980 char tb[8]; /* Temporary buffer. */
2981
2982 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
2983 assert (num_regs >= 1 && num_regs <= 4);
2984
2985 /* Prepare the index if any. */
2986 if (opnd->reglist.has_index)
2987 /* PR 21096: The %100 is to silence a warning about possible truncation. */
2988 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
2989 else
2990 tb[0] = '\0';
2991
2992 /* The hyphenated form is preferred for disassembly if there are
2993 more than two registers in the list, and the register numbers
2994 are monotonically increasing in increments of one. */
2995 if (num_regs > 2 && last_reg > first_reg)
2996 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
2997 prefix, last_reg, qlf_name, tb);
2998 else
2999 {
3000 const int reg0 = first_reg;
3001 const int reg1 = (first_reg + 1) & 0x1f;
3002 const int reg2 = (first_reg + 2) & 0x1f;
3003 const int reg3 = (first_reg + 3) & 0x1f;
3004
3005 switch (num_regs)
3006 {
3007 case 1:
3008 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
3009 break;
3010 case 2:
3011 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
3012 prefix, reg1, qlf_name, tb);
3013 break;
3014 case 3:
3015 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3016 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3017 prefix, reg2, qlf_name, tb);
3018 break;
3019 case 4:
3020 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3021 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3022 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
3023 break;
3024 }
3025 }
3026 }
3027
3028 /* Print the register+immediate address in OPND to BUF, which has SIZE
3029 characters. BASE is the name of the base register. */
3030
3031 static void
3032 print_immediate_offset_address (char *buf, size_t size,
3033 const aarch64_opnd_info *opnd,
3034 const char *base)
3035 {
3036 if (opnd->addr.writeback)
3037 {
3038 if (opnd->addr.preind)
3039 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
3040 else
3041 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
3042 }
3043 else
3044 {
3045 if (opnd->shifter.operator_present)
3046 {
3047 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
3048 snprintf (buf, size, "[%s, #%d, mul vl]",
3049 base, opnd->addr.offset.imm);
3050 }
3051 else if (opnd->addr.offset.imm)
3052 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
3053 else
3054 snprintf (buf, size, "[%s]", base);
3055 }
3056 }
3057
3058 /* Produce the string representation of the register offset address operand
3059 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3060 the names of the base and offset registers. */
3061 static void
3062 print_register_offset_address (char *buf, size_t size,
3063 const aarch64_opnd_info *opnd,
3064 const char *base, const char *offset)
3065 {
3066 char tb[16]; /* Temporary buffer. */
3067 bfd_boolean print_extend_p = TRUE;
3068 bfd_boolean print_amount_p = TRUE;
3069 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3070
3071 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3072 || !opnd->shifter.amount_present))
3073 {
3074 /* Not print the shift/extend amount when the amount is zero and
3075 when it is not the special case of 8-bit load/store instruction. */
3076 print_amount_p = FALSE;
3077 /* Likewise, no need to print the shift operator LSL in such a
3078 situation. */
3079 if (opnd->shifter.kind == AARCH64_MOD_LSL)
3080 print_extend_p = FALSE;
3081 }
3082
3083 /* Prepare for the extend/shift. */
3084 if (print_extend_p)
3085 {
3086 if (print_amount_p)
3087 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
3088 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3089 (opnd->shifter.amount % 100));
3090 else
3091 snprintf (tb, sizeof (tb), ", %s", shift_name);
3092 }
3093 else
3094 tb[0] = '\0';
3095
3096 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
3097 }
3098
3099 /* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3100 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3101 PC, PCREL_P and ADDRESS are used to pass in and return information about
3102 the PC-relative address calculation, where the PC value is passed in
3103 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3104 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3105 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3106
3107 The function serves both the disassembler and the assembler diagnostics
3108 issuer, which is the reason why it lives in this file. */
3109
3110 void
3111 aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3112 const aarch64_opcode *opcode,
3113 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
3114 bfd_vma *address, char** notes)
3115 {
3116 unsigned int i, num_conds;
3117 const char *name = NULL;
3118 const aarch64_opnd_info *opnd = opnds + idx;
3119 enum aarch64_modifier_kind kind;
3120 uint64_t addr, enum_value;
3121
3122 buf[0] = '\0';
3123 if (pcrel_p)
3124 *pcrel_p = 0;
3125
3126 switch (opnd->type)
3127 {
3128 case AARCH64_OPND_Rd:
3129 case AARCH64_OPND_Rn:
3130 case AARCH64_OPND_Rm:
3131 case AARCH64_OPND_Rt:
3132 case AARCH64_OPND_Rt2:
3133 case AARCH64_OPND_Rs:
3134 case AARCH64_OPND_Ra:
3135 case AARCH64_OPND_Rt_SYS:
3136 case AARCH64_OPND_PAIRREG:
3137 case AARCH64_OPND_SVE_Rm:
3138 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
3139 the <ic_op>, therefore we use opnd->present to override the
3140 generic optional-ness information. */
3141 if (opnd->type == AARCH64_OPND_Rt_SYS)
3142 {
3143 if (!opnd->present)
3144 break;
3145 }
3146 /* Omit the operand, e.g. RET. */
3147 else if (optional_operand_p (opcode, idx)
3148 && (opnd->reg.regno
3149 == get_optional_operand_default_value (opcode)))
3150 break;
3151 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3152 || opnd->qualifier == AARCH64_OPND_QLF_X);
3153 snprintf (buf, size, "%s",
3154 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3155 break;
3156
3157 case AARCH64_OPND_Rd_SP:
3158 case AARCH64_OPND_Rn_SP:
3159 case AARCH64_OPND_SVE_Rn_SP:
3160 case AARCH64_OPND_Rm_SP:
3161 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3162 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3163 || opnd->qualifier == AARCH64_OPND_QLF_X
3164 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3165 snprintf (buf, size, "%s",
3166 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3167 break;
3168
3169 case AARCH64_OPND_Rm_EXT:
3170 kind = opnd->shifter.kind;
3171 assert (idx == 1 || idx == 2);
3172 if ((aarch64_stack_pointer_p (opnds)
3173 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3174 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3175 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3176 && kind == AARCH64_MOD_UXTW)
3177 || (opnd->qualifier == AARCH64_OPND_QLF_X
3178 && kind == AARCH64_MOD_UXTX)))
3179 {
3180 /* 'LSL' is the preferred form in this case. */
3181 kind = AARCH64_MOD_LSL;
3182 if (opnd->shifter.amount == 0)
3183 {
3184 /* Shifter omitted. */
3185 snprintf (buf, size, "%s",
3186 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3187 break;
3188 }
3189 }
3190 if (opnd->shifter.amount)
3191 snprintf (buf, size, "%s, %s #%" PRIi64,
3192 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3193 aarch64_operand_modifiers[kind].name,
3194 opnd->shifter.amount);
3195 else
3196 snprintf (buf, size, "%s, %s",
3197 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3198 aarch64_operand_modifiers[kind].name);
3199 break;
3200
3201 case AARCH64_OPND_Rm_SFT:
3202 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3203 || opnd->qualifier == AARCH64_OPND_QLF_X);
3204 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3205 snprintf (buf, size, "%s",
3206 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3207 else
3208 snprintf (buf, size, "%s, %s #%" PRIi64,
3209 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3210 aarch64_operand_modifiers[opnd->shifter.kind].name,
3211 opnd->shifter.amount);
3212 break;
3213
3214 case AARCH64_OPND_Fd:
3215 case AARCH64_OPND_Fn:
3216 case AARCH64_OPND_Fm:
3217 case AARCH64_OPND_Fa:
3218 case AARCH64_OPND_Ft:
3219 case AARCH64_OPND_Ft2:
3220 case AARCH64_OPND_Sd:
3221 case AARCH64_OPND_Sn:
3222 case AARCH64_OPND_Sm:
3223 case AARCH64_OPND_SVE_VZn:
3224 case AARCH64_OPND_SVE_Vd:
3225 case AARCH64_OPND_SVE_Vm:
3226 case AARCH64_OPND_SVE_Vn:
3227 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3228 opnd->reg.regno);
3229 break;
3230
3231 case AARCH64_OPND_Va:
3232 case AARCH64_OPND_Vd:
3233 case AARCH64_OPND_Vn:
3234 case AARCH64_OPND_Vm:
3235 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3236 aarch64_get_qualifier_name (opnd->qualifier));
3237 break;
3238
3239 case AARCH64_OPND_Ed:
3240 case AARCH64_OPND_En:
3241 case AARCH64_OPND_Em:
3242 case AARCH64_OPND_Em16:
3243 case AARCH64_OPND_SM3_IMM2:
3244 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3245 aarch64_get_qualifier_name (opnd->qualifier),
3246 opnd->reglane.index);
3247 break;
3248
3249 case AARCH64_OPND_VdD1:
3250 case AARCH64_OPND_VnD1:
3251 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3252 break;
3253
3254 case AARCH64_OPND_LVn:
3255 case AARCH64_OPND_LVt:
3256 case AARCH64_OPND_LVt_AL:
3257 case AARCH64_OPND_LEt:
3258 print_register_list (buf, size, opnd, "v");
3259 break;
3260
3261 case AARCH64_OPND_SVE_Pd:
3262 case AARCH64_OPND_SVE_Pg3:
3263 case AARCH64_OPND_SVE_Pg4_5:
3264 case AARCH64_OPND_SVE_Pg4_10:
3265 case AARCH64_OPND_SVE_Pg4_16:
3266 case AARCH64_OPND_SVE_Pm:
3267 case AARCH64_OPND_SVE_Pn:
3268 case AARCH64_OPND_SVE_Pt:
3269 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3270 snprintf (buf, size, "p%d", opnd->reg.regno);
3271 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3272 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3273 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3274 aarch64_get_qualifier_name (opnd->qualifier));
3275 else
3276 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3277 aarch64_get_qualifier_name (opnd->qualifier));
3278 break;
3279
3280 case AARCH64_OPND_SVE_Za_5:
3281 case AARCH64_OPND_SVE_Za_16:
3282 case AARCH64_OPND_SVE_Zd:
3283 case AARCH64_OPND_SVE_Zm_5:
3284 case AARCH64_OPND_SVE_Zm_16:
3285 case AARCH64_OPND_SVE_Zn:
3286 case AARCH64_OPND_SVE_Zt:
3287 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3288 snprintf (buf, size, "z%d", opnd->reg.regno);
3289 else
3290 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3291 aarch64_get_qualifier_name (opnd->qualifier));
3292 break;
3293
3294 case AARCH64_OPND_SVE_ZnxN:
3295 case AARCH64_OPND_SVE_ZtxN:
3296 print_register_list (buf, size, opnd, "z");
3297 break;
3298
3299 case AARCH64_OPND_SVE_Zm3_INDEX:
3300 case AARCH64_OPND_SVE_Zm3_22_INDEX:
3301 case AARCH64_OPND_SVE_Zm4_INDEX:
3302 case AARCH64_OPND_SVE_Zn_INDEX:
3303 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3304 aarch64_get_qualifier_name (opnd->qualifier),
3305 opnd->reglane.index);
3306 break;
3307
3308 case AARCH64_OPND_CRn:
3309 case AARCH64_OPND_CRm:
3310 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
3311 break;
3312
3313 case AARCH64_OPND_IDX:
3314 case AARCH64_OPND_MASK:
3315 case AARCH64_OPND_IMM:
3316 case AARCH64_OPND_IMM_2:
3317 case AARCH64_OPND_WIDTH:
3318 case AARCH64_OPND_UIMM3_OP1:
3319 case AARCH64_OPND_UIMM3_OP2:
3320 case AARCH64_OPND_BIT_NUM:
3321 case AARCH64_OPND_IMM_VLSL:
3322 case AARCH64_OPND_IMM_VLSR:
3323 case AARCH64_OPND_SHLL_IMM:
3324 case AARCH64_OPND_IMM0:
3325 case AARCH64_OPND_IMMR:
3326 case AARCH64_OPND_IMMS:
3327 case AARCH64_OPND_FBITS:
3328 case AARCH64_OPND_SIMM5:
3329 case AARCH64_OPND_SVE_SHLIMM_PRED:
3330 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
3331 case AARCH64_OPND_SVE_SHRIMM_PRED:
3332 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3333 case AARCH64_OPND_SVE_SIMM5:
3334 case AARCH64_OPND_SVE_SIMM5B:
3335 case AARCH64_OPND_SVE_SIMM6:
3336 case AARCH64_OPND_SVE_SIMM8:
3337 case AARCH64_OPND_SVE_UIMM3:
3338 case AARCH64_OPND_SVE_UIMM7:
3339 case AARCH64_OPND_SVE_UIMM8:
3340 case AARCH64_OPND_SVE_UIMM8_53:
3341 case AARCH64_OPND_IMM_ROT1:
3342 case AARCH64_OPND_IMM_ROT2:
3343 case AARCH64_OPND_IMM_ROT3:
3344 case AARCH64_OPND_SVE_IMM_ROT1:
3345 case AARCH64_OPND_SVE_IMM_ROT2:
3346 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3347 break;
3348
3349 case AARCH64_OPND_SVE_I1_HALF_ONE:
3350 case AARCH64_OPND_SVE_I1_HALF_TWO:
3351 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3352 {
3353 single_conv_t c;
3354 c.i = opnd->imm.value;
3355 snprintf (buf, size, "#%.1f", c.f);
3356 break;
3357 }
3358
3359 case AARCH64_OPND_SVE_PATTERN:
3360 if (optional_operand_p (opcode, idx)
3361 && opnd->imm.value == get_optional_operand_default_value (opcode))
3362 break;
3363 enum_value = opnd->imm.value;
3364 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3365 if (aarch64_sve_pattern_array[enum_value])
3366 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3367 else
3368 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3369 break;
3370
3371 case AARCH64_OPND_SVE_PATTERN_SCALED:
3372 if (optional_operand_p (opcode, idx)
3373 && !opnd->shifter.operator_present
3374 && opnd->imm.value == get_optional_operand_default_value (opcode))
3375 break;
3376 enum_value = opnd->imm.value;
3377 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3378 if (aarch64_sve_pattern_array[opnd->imm.value])
3379 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3380 else
3381 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3382 if (opnd->shifter.operator_present)
3383 {
3384 size_t len = strlen (buf);
3385 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3386 aarch64_operand_modifiers[opnd->shifter.kind].name,
3387 opnd->shifter.amount);
3388 }
3389 break;
3390
3391 case AARCH64_OPND_SVE_PRFOP:
3392 enum_value = opnd->imm.value;
3393 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3394 if (aarch64_sve_prfop_array[enum_value])
3395 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3396 else
3397 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3398 break;
3399
3400 case AARCH64_OPND_IMM_MOV:
3401 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3402 {
3403 case 4: /* e.g. MOV Wd, #<imm32>. */
3404 {
3405 int imm32 = opnd->imm.value;
3406 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3407 }
3408 break;
3409 case 8: /* e.g. MOV Xd, #<imm64>. */
3410 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3411 opnd->imm.value, opnd->imm.value);
3412 break;
3413 default: assert (0);
3414 }
3415 break;
3416
3417 case AARCH64_OPND_FPIMM0:
3418 snprintf (buf, size, "#0.0");
3419 break;
3420
3421 case AARCH64_OPND_LIMM:
3422 case AARCH64_OPND_AIMM:
3423 case AARCH64_OPND_HALF:
3424 case AARCH64_OPND_SVE_INV_LIMM:
3425 case AARCH64_OPND_SVE_LIMM:
3426 case AARCH64_OPND_SVE_LIMM_MOV:
3427 if (opnd->shifter.amount)
3428 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
3429 opnd->shifter.amount);
3430 else
3431 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3432 break;
3433
3434 case AARCH64_OPND_SIMD_IMM:
3435 case AARCH64_OPND_SIMD_IMM_SFT:
3436 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3437 || opnd->shifter.kind == AARCH64_MOD_NONE)
3438 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3439 else
3440 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
3441 aarch64_operand_modifiers[opnd->shifter.kind].name,
3442 opnd->shifter.amount);
3443 break;
3444
3445 case AARCH64_OPND_SVE_AIMM:
3446 case AARCH64_OPND_SVE_ASIMM:
3447 if (opnd->shifter.amount)
3448 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3449 opnd->shifter.amount);
3450 else
3451 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3452 break;
3453
3454 case AARCH64_OPND_FPIMM:
3455 case AARCH64_OPND_SIMD_FPIMM:
3456 case AARCH64_OPND_SVE_FPIMM8:
3457 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3458 {
3459 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3460 {
3461 half_conv_t c;
3462 c.i = expand_fp_imm (2, opnd->imm.value);
3463 snprintf (buf, size, "#%.18e", c.f);
3464 }
3465 break;
3466 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3467 {
3468 single_conv_t c;
3469 c.i = expand_fp_imm (4, opnd->imm.value);
3470 snprintf (buf, size, "#%.18e", c.f);
3471 }
3472 break;
3473 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3474 {
3475 double_conv_t c;
3476 c.i = expand_fp_imm (8, opnd->imm.value);
3477 snprintf (buf, size, "#%.18e", c.d);
3478 }
3479 break;
3480 default: assert (0);
3481 }
3482 break;
3483
3484 case AARCH64_OPND_CCMP_IMM:
3485 case AARCH64_OPND_NZCV:
3486 case AARCH64_OPND_EXCEPTION:
3487 case AARCH64_OPND_UIMM4:
3488 case AARCH64_OPND_UIMM4_ADDG:
3489 case AARCH64_OPND_UIMM7:
3490 case AARCH64_OPND_UIMM10:
3491 if (optional_operand_p (opcode, idx) == TRUE
3492 && (opnd->imm.value ==
3493 (int64_t) get_optional_operand_default_value (opcode)))
3494 /* Omit the operand, e.g. DCPS1. */
3495 break;
3496 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3497 break;
3498
3499 case AARCH64_OPND_COND:
3500 case AARCH64_OPND_COND1:
3501 snprintf (buf, size, "%s", opnd->cond->names[0]);
3502 num_conds = ARRAY_SIZE (opnd->cond->names);
3503 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3504 {
3505 size_t len = strlen (buf);
3506 if (i == 1)
3507 snprintf (buf + len, size - len, " // %s = %s",
3508 opnd->cond->names[0], opnd->cond->names[i]);
3509 else
3510 snprintf (buf + len, size - len, ", %s",
3511 opnd->cond->names[i]);
3512 }
3513 break;
3514
3515 case AARCH64_OPND_ADDR_ADRP:
3516 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3517 + opnd->imm.value;
3518 if (pcrel_p)
3519 *pcrel_p = 1;
3520 if (address)
3521 *address = addr;
3522 /* This is not necessary during the disassembling, as print_address_func
3523 in the disassemble_info will take care of the printing. But some
3524 other callers may be still interested in getting the string in *STR,
3525 so here we do snprintf regardless. */
3526 snprintf (buf, size, "#0x%" PRIx64, addr);
3527 break;
3528
3529 case AARCH64_OPND_ADDR_PCREL14:
3530 case AARCH64_OPND_ADDR_PCREL19:
3531 case AARCH64_OPND_ADDR_PCREL21:
3532 case AARCH64_OPND_ADDR_PCREL26:
3533 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3534 if (pcrel_p)
3535 *pcrel_p = 1;
3536 if (address)
3537 *address = addr;
3538 /* This is not necessary during the disassembling, as print_address_func
3539 in the disassemble_info will take care of the printing. But some
3540 other callers may be still interested in getting the string in *STR,
3541 so here we do snprintf regardless. */
3542 snprintf (buf, size, "#0x%" PRIx64, addr);
3543 break;
3544
3545 case AARCH64_OPND_ADDR_SIMPLE:
3546 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3547 case AARCH64_OPND_SIMD_ADDR_POST:
3548 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3549 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3550 {
3551 if (opnd->addr.offset.is_reg)
3552 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3553 else
3554 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3555 }
3556 else
3557 snprintf (buf, size, "[%s]", name);
3558 break;
3559
3560 case AARCH64_OPND_ADDR_SIMPLE_2:
3561 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3562 snprintf (buf, size, "[%s]!", name);
3563 break;
3564
3565 case AARCH64_OPND_ADDR_REGOFF:
3566 case AARCH64_OPND_SVE_ADDR_R:
3567 case AARCH64_OPND_SVE_ADDR_RR:
3568 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3569 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3570 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3571 case AARCH64_OPND_SVE_ADDR_RX:
3572 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3573 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3574 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
3575 print_register_offset_address
3576 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3577 get_offset_int_reg_name (opnd));
3578 break;
3579
3580 case AARCH64_OPND_SVE_ADDR_RZ:
3581 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3582 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3583 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3584 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3585 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3586 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3587 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3588 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3589 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3590 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3591 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3592 print_register_offset_address
3593 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3594 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3595 break;
3596
3597 case AARCH64_OPND_ADDR_SIMM7:
3598 case AARCH64_OPND_ADDR_SIMM9:
3599 case AARCH64_OPND_ADDR_SIMM9_2:
3600 case AARCH64_OPND_ADDR_SIMM10:
3601 case AARCH64_OPND_ADDR_SIMM11:
3602 case AARCH64_OPND_ADDR_SIMM13:
3603 case AARCH64_OPND_ADDR_OFFSET:
3604 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
3605 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3606 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3607 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3608 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3609 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3610 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
3611 case AARCH64_OPND_SVE_ADDR_RI_U6:
3612 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3613 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3614 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
3615 print_immediate_offset_address
3616 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
3617 break;
3618
3619 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3620 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3621 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3622 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3623 print_immediate_offset_address
3624 (buf, size, opnd,
3625 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3626 break;
3627
3628 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3629 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3630 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3631 print_register_offset_address
3632 (buf, size, opnd,
3633 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3634 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3635 break;
3636
3637 case AARCH64_OPND_ADDR_UIMM12:
3638 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3639 if (opnd->addr.offset.imm)
3640 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
3641 else
3642 snprintf (buf, size, "[%s]", name);
3643 break;
3644
3645 case AARCH64_OPND_SYSREG:
3646 for (i = 0; aarch64_sys_regs[i].name; ++i)
3647 {
3648 bfd_boolean exact_match
3649 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3650 == opnd->sysreg.flags;
3651
3652 /* Try and find an exact match, But if that fails, return the first
3653 partial match that was found. */
3654 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3655 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3656 && (name == NULL || exact_match))
3657 {
3658 name = aarch64_sys_regs[i].name;
3659 if (exact_match)
3660 {
3661 if (notes)
3662 *notes = NULL;
3663 break;
3664 }
3665
3666 /* If we didn't match exactly, that means the presense of a flag
3667 indicates what we didn't want for this instruction. e.g. If
3668 F_REG_READ is there, that means we were looking for a write
3669 register. See aarch64_ext_sysreg. */
3670 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
3671 *notes = _("reading from a write-only register");
3672 else if (aarch64_sys_regs[i].flags & F_REG_READ)
3673 *notes = _("writing to a read-only register");
3674 }
3675 }
3676
3677 if (name)
3678 snprintf (buf, size, "%s", name);
3679 else
3680 {
3681 /* Implementation defined system register. */
3682 unsigned int value = opnd->sysreg.value;
3683 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3684 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3685 value & 0x7);
3686 }
3687 break;
3688
3689 case AARCH64_OPND_PSTATEFIELD:
3690 for (i = 0; aarch64_pstatefields[i].name; ++i)
3691 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3692 break;
3693 assert (aarch64_pstatefields[i].name);
3694 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3695 break;
3696
3697 case AARCH64_OPND_SYSREG_AT:
3698 case AARCH64_OPND_SYSREG_DC:
3699 case AARCH64_OPND_SYSREG_IC:
3700 case AARCH64_OPND_SYSREG_TLBI:
3701 case AARCH64_OPND_SYSREG_SR:
3702 snprintf (buf, size, "%s", opnd->sysins_op->name);
3703 break;
3704
3705 case AARCH64_OPND_BARRIER:
3706 snprintf (buf, size, "%s", opnd->barrier->name);
3707 break;
3708
3709 case AARCH64_OPND_BARRIER_ISB:
3710 /* Operand can be omitted, e.g. in DCPS1. */
3711 if (! optional_operand_p (opcode, idx)
3712 || (opnd->barrier->value
3713 != get_optional_operand_default_value (opcode)))
3714 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3715 break;
3716
3717 case AARCH64_OPND_PRFOP:
3718 if (opnd->prfop->name != NULL)
3719 snprintf (buf, size, "%s", opnd->prfop->name);
3720 else
3721 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
3722 break;
3723
3724 case AARCH64_OPND_BARRIER_PSB:
3725 case AARCH64_OPND_BTI_TARGET:
3726 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3727 snprintf (buf, size, "%s", opnd->hint_option->name);
3728 break;
3729
3730 default:
3731 assert (0);
3732 }
3733 }
3734 \f
3735 #define CPENC(op0,op1,crn,crm,op2) \
3736 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3737 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3738 #define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3739 /* for 3.9.10 System Instructions */
3740 #define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3741
3742 #define C0 0
3743 #define C1 1
3744 #define C2 2
3745 #define C3 3
3746 #define C4 4
3747 #define C5 5
3748 #define C6 6
3749 #define C7 7
3750 #define C8 8
3751 #define C9 9
3752 #define C10 10
3753 #define C11 11
3754 #define C12 12
3755 #define C13 13
3756 #define C14 14
3757 #define C15 15
3758
3759 /* TODO there is one more issues need to be resolved
3760 1. handle cpu-implementation-defined system registers. */
3761 const aarch64_sys_reg aarch64_sys_regs [] =
3762 {
3763 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
3764 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
3765 { "elr_el1", CPEN_(0,C0,1), 0 },
3766 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
3767 { "sp_el0", CPEN_(0,C1,0), 0 },
3768 { "spsel", CPEN_(0,C2,0), 0 },
3769 { "daif", CPEN_(3,C2,1), 0 },
3770 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
3771 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
3772 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
3773 { "nzcv", CPEN_(3,C2,0), 0 },
3774 { "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
3775 { "fpcr", CPEN_(3,C4,0), 0 },
3776 { "fpsr", CPEN_(3,C4,1), 0 },
3777 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3778 { "dlr_el0", CPEN_(3,C5,1), 0 },
3779 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3780 { "elr_el2", CPEN_(4,C0,1), 0 },
3781 { "sp_el1", CPEN_(4,C1,0), 0 },
3782 { "spsr_irq", CPEN_(4,C3,0), 0 },
3783 { "spsr_abt", CPEN_(4,C3,1), 0 },
3784 { "spsr_und", CPEN_(4,C3,2), 0 },
3785 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3786 { "spsr_el3", CPEN_(6,C0,0), 0 },
3787 { "elr_el3", CPEN_(6,C0,1), 0 },
3788 { "sp_el2", CPEN_(6,C1,0), 0 },
3789 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3790 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
3791 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3792 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3793 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3794 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3795 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3796 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3797 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3798 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3799 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
3800 { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
3801 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3802 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3803 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3804 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3805 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3806 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3807 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3808 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3809 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3810 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3811 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3812 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3813 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3814 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3815 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3816 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3817 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3818 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3819 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3820 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3821 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3822 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3823 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3824 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3825 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3826 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3827 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3828 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3829 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
3830 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
3831 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3832 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3833 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3834 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3835 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
3836 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
3837 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3838 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3839 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3840 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
3841 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
3842 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3843 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3844 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3845 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3846 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3847 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3848 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3849 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
3850 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3851 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3852 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3853 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3854 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
3855 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3856 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3857 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
3858 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
3859 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
3860 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3861 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
3862 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3863 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3864 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3865 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
3866 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
3867 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
3868 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3869 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3870 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3871 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3872 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3873 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3874 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3875 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3876 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3877 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
3878 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3879 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3880 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3881 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3882 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
3883 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
3884 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
3885 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
3886 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3887 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3888 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
3889 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
3890 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
3891 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
3892 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
3893 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
3894 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
3895 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3896 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3897 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3898 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3899 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
3900 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3901 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3902 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
3903 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
3904 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3905 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3906 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3907 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3908 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
3909 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
3910 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3911 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3912 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
3913 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
3914 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3915 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3916 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
3917 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
3918 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3919 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3920 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
3921 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3922 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3923 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
3924 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
3925 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3926 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
3927 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
3928 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3929 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
3930 { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
3931 { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
3932 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
3933 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
3934 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3935 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3936 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
3937 { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
3938 { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
3939 { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
3940 { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
3941 { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
3942 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
3943 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3944 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3945 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
3946 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3947 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
3948 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
3949 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
3950 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
3951 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
3952 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
3953 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
3954 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
3955 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
3956 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
3957 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
3958 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
3959 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
3960 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
3961 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
3962 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
3963 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
3964 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
3965 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
3966 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
3967 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
3968 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
3969 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
3970 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
3971 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
3972 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
3973 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
3974 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
3975 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
3976 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
3977 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
3978 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
3979 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
3980 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
3981 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
3982 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
3983 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
3984 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
3985 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
3986 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
3987 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
3988 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
3989 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
3990 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
3991 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
3992 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
3993 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
3994 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
3995 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
3996 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
3997 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
3998 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
3999 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
4000 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
4001 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
4002 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
4003 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
4004 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
4005 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
4006 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
4007 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
4008 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
4009 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
4010 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
4011 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
4012 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
4013 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
4014 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
4015 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
4016 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
4017 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
4018 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
4019 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
4020 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
4021 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
4022 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
4023 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
4024 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
4025 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
4026 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
4027 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
4028 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
4029 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
4030 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
4031 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
4032 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
4033 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
4034 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
4035 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
4036 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
4037 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
4038 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
4039 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
4040 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
4041 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
4042 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
4043 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
4044 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
4045 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
4046 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
4047 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
4048 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
4049 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
4050 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
4051 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
4052 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
4053 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
4054 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
4055 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
4056 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
4057 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
4058 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
4059 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
4060 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
4061 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
4062 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
4063 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
4064 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
4065 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
4066 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
4067 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
4068 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
4069 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
4070 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
4071 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
4072 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
4073 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
4074 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
4075 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
4076 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
4077 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
4078 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
4079 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4080 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4081 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4082 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4083 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4084 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4085 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4086 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4087 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4088 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4089 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4090 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4091 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4092 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4093 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4094 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4095 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4096 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4097 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4098 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4099 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4100 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4101 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4102 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4103 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4104 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4105 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4106 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4107 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4108 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4109 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4110 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4111 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4112 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4113 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4114 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4115 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4116 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4117 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4118 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4119 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4120 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4121 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4122 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4123 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4124 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4125 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4126 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4127 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4128 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4129 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4130 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4131 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4132 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4133 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4134 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4135 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4136 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4137 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4138 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4139 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4140 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4141 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4142 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4143 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4144 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4145 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4146 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4147 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
4148
4149 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4150 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4151 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4152 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4153 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4154 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4155 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4156 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4157 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4158 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4159 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
4160 { 0, CPENC(0,0,0,0,0), 0 },
4161 };
4162
4163 bfd_boolean
4164 aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4165 {
4166 return (reg->flags & F_DEPRECATED) != 0;
4167 }
4168
4169 bfd_boolean
4170 aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4171 const aarch64_sys_reg *reg)
4172 {
4173 if (!(reg->flags & F_ARCHEXT))
4174 return TRUE;
4175
4176 /* PAN. Values are from aarch64_sys_regs. */
4177 if (reg->value == CPEN_(0,C2,3)
4178 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4179 return FALSE;
4180
4181 /* SCXTNUM_ELx registers. */
4182 if ((reg->value == CPENC (3, 3, C13, C0, 7)
4183 || reg->value == CPENC (3, 0, C13, C0, 7)
4184 || reg->value == CPENC (3, 4, C13, C0, 7)
4185 || reg->value == CPENC (3, 6, C13, C0, 7)
4186 || reg->value == CPENC (3, 5, C13, C0, 7))
4187 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
4188 return FALSE;
4189
4190 /* ID_PFR2_EL1 register. */
4191 if (reg->value == CPENC(3, 0, C0, C3, 4)
4192 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
4193 return FALSE;
4194
4195 /* SSBS. Values are from aarch64_sys_regs. */
4196 if (reg->value == CPEN_(3,C2,6)
4197 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4198 return FALSE;
4199
4200 /* Virtualization host extensions: system registers. */
4201 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4202 || reg->value == CPENC (3, 4, C13, C0, 1)
4203 || reg->value == CPENC (3, 4, C14, C3, 0)
4204 || reg->value == CPENC (3, 4, C14, C3, 1)
4205 || reg->value == CPENC (3, 4, C14, C3, 2))
4206 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4207 return FALSE;
4208
4209 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4210 if ((reg->value == CPEN_ (5, C0, 0)
4211 || reg->value == CPEN_ (5, C0, 1)
4212 || reg->value == CPENC (3, 5, C1, C0, 0)
4213 || reg->value == CPENC (3, 5, C1, C0, 2)
4214 || reg->value == CPENC (3, 5, C2, C0, 0)
4215 || reg->value == CPENC (3, 5, C2, C0, 1)
4216 || reg->value == CPENC (3, 5, C2, C0, 2)
4217 || reg->value == CPENC (3, 5, C5, C1, 0)
4218 || reg->value == CPENC (3, 5, C5, C1, 1)
4219 || reg->value == CPENC (3, 5, C5, C2, 0)
4220 || reg->value == CPENC (3, 5, C6, C0, 0)
4221 || reg->value == CPENC (3, 5, C10, C2, 0)
4222 || reg->value == CPENC (3, 5, C10, C3, 0)
4223 || reg->value == CPENC (3, 5, C12, C0, 0)
4224 || reg->value == CPENC (3, 5, C13, C0, 1)
4225 || reg->value == CPENC (3, 5, C14, C1, 0))
4226 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4227 return FALSE;
4228
4229 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4230 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4231 || reg->value == CPENC (3, 5, C14, C2, 1)
4232 || reg->value == CPENC (3, 5, C14, C2, 2)
4233 || reg->value == CPENC (3, 5, C14, C3, 0)
4234 || reg->value == CPENC (3, 5, C14, C3, 1)
4235 || reg->value == CPENC (3, 5, C14, C3, 2))
4236 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4237 return FALSE;
4238
4239 /* ARMv8.2 features. */
4240
4241 /* ID_AA64MMFR2_EL1. */
4242 if (reg->value == CPENC (3, 0, C0, C7, 2)
4243 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4244 return FALSE;
4245
4246 /* PSTATE.UAO. */
4247 if (reg->value == CPEN_ (0, C2, 4)
4248 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4249 return FALSE;
4250
4251 /* RAS extension. */
4252
4253 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4254 ERXMISC0_EL1 AND ERXMISC1_EL1. */
4255 if ((reg->value == CPENC (3, 0, C5, C3, 0)
4256 || reg->value == CPENC (3, 0, C5, C3, 1)
4257 || reg->value == CPENC (3, 0, C5, C3, 2)
4258 || reg->value == CPENC (3, 0, C5, C3, 3)
4259 || reg->value == CPENC (3, 0, C5, C4, 0)
4260 || reg->value == CPENC (3, 0, C5, C4, 1)
4261 || reg->value == CPENC (3, 0, C5, C4, 2)
4262 || reg->value == CPENC (3, 0, C5, C4, 3)
4263 || reg->value == CPENC (3, 0, C5, C5, 0)
4264 || reg->value == CPENC (3, 0, C5, C5, 1))
4265 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4266 return FALSE;
4267
4268 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4269 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4270 || reg->value == CPENC (3, 0, C12, C1, 1)
4271 || reg->value == CPENC (3, 4, C12, C1, 1))
4272 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4273 return FALSE;
4274
4275 /* Statistical Profiling extension. */
4276 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4277 || reg->value == CPENC (3, 0, C9, C10, 1)
4278 || reg->value == CPENC (3, 0, C9, C10, 3)
4279 || reg->value == CPENC (3, 0, C9, C10, 7)
4280 || reg->value == CPENC (3, 0, C9, C9, 0)
4281 || reg->value == CPENC (3, 0, C9, C9, 2)
4282 || reg->value == CPENC (3, 0, C9, C9, 3)
4283 || reg->value == CPENC (3, 0, C9, C9, 4)
4284 || reg->value == CPENC (3, 0, C9, C9, 5)
4285 || reg->value == CPENC (3, 0, C9, C9, 6)
4286 || reg->value == CPENC (3, 0, C9, C9, 7)
4287 || reg->value == CPENC (3, 4, C9, C9, 0)
4288 || reg->value == CPENC (3, 5, C9, C9, 0))
4289 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4290 return FALSE;
4291
4292 /* ARMv8.3 Pointer authentication keys. */
4293 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4294 || reg->value == CPENC (3, 0, C2, C1, 1)
4295 || reg->value == CPENC (3, 0, C2, C1, 2)
4296 || reg->value == CPENC (3, 0, C2, C1, 3)
4297 || reg->value == CPENC (3, 0, C2, C2, 0)
4298 || reg->value == CPENC (3, 0, C2, C2, 1)
4299 || reg->value == CPENC (3, 0, C2, C2, 2)
4300 || reg->value == CPENC (3, 0, C2, C2, 3)
4301 || reg->value == CPENC (3, 0, C2, C3, 0)
4302 || reg->value == CPENC (3, 0, C2, C3, 1))
4303 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4304 return FALSE;
4305
4306 /* SVE. */
4307 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4308 || reg->value == CPENC (3, 0, C1, C2, 0)
4309 || reg->value == CPENC (3, 4, C1, C2, 0)
4310 || reg->value == CPENC (3, 6, C1, C2, 0)
4311 || reg->value == CPENC (3, 5, C1, C2, 0)
4312 || reg->value == CPENC (3, 0, C0, C0, 7))
4313 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4314 return FALSE;
4315
4316 /* ARMv8.4 features. */
4317
4318 /* PSTATE.DIT. */
4319 if (reg->value == CPEN_ (3, C2, 5)
4320 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4321 return FALSE;
4322
4323 /* Virtualization extensions. */
4324 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4325 || reg->value == CPENC(3, 4, C2, C6, 0)
4326 || reg->value == CPENC(3, 4, C14, C4, 0)
4327 || reg->value == CPENC(3, 4, C14, C4, 2)
4328 || reg->value == CPENC(3, 4, C14, C4, 1)
4329 || reg->value == CPENC(3, 4, C14, C5, 0)
4330 || reg->value == CPENC(3, 4, C14, C5, 2)
4331 || reg->value == CPENC(3, 4, C14, C5, 1)
4332 || reg->value == CPENC(3, 4, C1, C3, 1)
4333 || reg->value == CPENC(3, 4, C2, C2, 0))
4334 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4335 return FALSE;
4336
4337 /* ARMv8.4 TLB instructions. */
4338 if ((reg->value == CPENS (0, C8, C1, 0)
4339 || reg->value == CPENS (0, C8, C1, 1)
4340 || reg->value == CPENS (0, C8, C1, 2)
4341 || reg->value == CPENS (0, C8, C1, 3)
4342 || reg->value == CPENS (0, C8, C1, 5)
4343 || reg->value == CPENS (0, C8, C1, 7)
4344 || reg->value == CPENS (4, C8, C4, 0)
4345 || reg->value == CPENS (4, C8, C4, 4)
4346 || reg->value == CPENS (4, C8, C1, 1)
4347 || reg->value == CPENS (4, C8, C1, 5)
4348 || reg->value == CPENS (4, C8, C1, 6)
4349 || reg->value == CPENS (6, C8, C1, 1)
4350 || reg->value == CPENS (6, C8, C1, 5)
4351 || reg->value == CPENS (4, C8, C1, 0)
4352 || reg->value == CPENS (4, C8, C1, 4)
4353 || reg->value == CPENS (6, C8, C1, 0)
4354 || reg->value == CPENS (0, C8, C6, 1)
4355 || reg->value == CPENS (0, C8, C6, 3)
4356 || reg->value == CPENS (0, C8, C6, 5)
4357 || reg->value == CPENS (0, C8, C6, 7)
4358 || reg->value == CPENS (0, C8, C2, 1)
4359 || reg->value == CPENS (0, C8, C2, 3)
4360 || reg->value == CPENS (0, C8, C2, 5)
4361 || reg->value == CPENS (0, C8, C2, 7)
4362 || reg->value == CPENS (0, C8, C5, 1)
4363 || reg->value == CPENS (0, C8, C5, 3)
4364 || reg->value == CPENS (0, C8, C5, 5)
4365 || reg->value == CPENS (0, C8, C5, 7)
4366 || reg->value == CPENS (4, C8, C0, 2)
4367 || reg->value == CPENS (4, C8, C0, 6)
4368 || reg->value == CPENS (4, C8, C4, 2)
4369 || reg->value == CPENS (4, C8, C4, 6)
4370 || reg->value == CPENS (4, C8, C4, 3)
4371 || reg->value == CPENS (4, C8, C4, 7)
4372 || reg->value == CPENS (4, C8, C6, 1)
4373 || reg->value == CPENS (4, C8, C6, 5)
4374 || reg->value == CPENS (4, C8, C2, 1)
4375 || reg->value == CPENS (4, C8, C2, 5)
4376 || reg->value == CPENS (4, C8, C5, 1)
4377 || reg->value == CPENS (4, C8, C5, 5)
4378 || reg->value == CPENS (6, C8, C6, 1)
4379 || reg->value == CPENS (6, C8, C6, 5)
4380 || reg->value == CPENS (6, C8, C2, 1)
4381 || reg->value == CPENS (6, C8, C2, 5)
4382 || reg->value == CPENS (6, C8, C5, 1)
4383 || reg->value == CPENS (6, C8, C5, 5))
4384 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4385 return FALSE;
4386
4387 /* Random Number Instructions. For now they are available
4388 (and optional) only with ARMv8.5-A. */
4389 if ((reg->value == CPENC (3, 3, C2, C4, 0)
4390 || reg->value == CPENC (3, 3, C2, C4, 1))
4391 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
4392 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
4393 return FALSE;
4394
4395 return TRUE;
4396 }
4397
4398 /* The CPENC below is fairly misleading, the fields
4399 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4400 by ins_pstatefield, which just shifts the value by the width of the fields
4401 in a loop. So if you CPENC them only the first value will be set, the rest
4402 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4403 value of 0b110000000001000000 (0x30040) while what you want is
4404 0b011010 (0x1a). */
4405 const aarch64_sys_reg aarch64_pstatefields [] =
4406 {
4407 { "spsel", 0x05, 0 },
4408 { "daifset", 0x1e, 0 },
4409 { "daifclr", 0x1f, 0 },
4410 { "pan", 0x04, F_ARCHEXT },
4411 { "uao", 0x03, F_ARCHEXT },
4412 { "ssbs", 0x19, F_ARCHEXT },
4413 { "dit", 0x1a, F_ARCHEXT },
4414 { 0, CPENC(0,0,0,0,0), 0 },
4415 };
4416
4417 bfd_boolean
4418 aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4419 const aarch64_sys_reg *reg)
4420 {
4421 if (!(reg->flags & F_ARCHEXT))
4422 return TRUE;
4423
4424 /* PAN. Values are from aarch64_pstatefields. */
4425 if (reg->value == 0x04
4426 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4427 return FALSE;
4428
4429 /* UAO. Values are from aarch64_pstatefields. */
4430 if (reg->value == 0x03
4431 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4432 return FALSE;
4433
4434 /* SSBS. Values are from aarch64_pstatefields. */
4435 if (reg->value == 0x19
4436 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4437 return FALSE;
4438
4439 /* DIT. Values are from aarch64_pstatefields. */
4440 if (reg->value == 0x1a
4441 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4442 return FALSE;
4443
4444 return TRUE;
4445 }
4446
4447 const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4448 {
4449 { "ialluis", CPENS(0,C7,C1,0), 0 },
4450 { "iallu", CPENS(0,C7,C5,0), 0 },
4451 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
4452 { 0, CPENS(0,0,0,0), 0 }
4453 };
4454
4455 const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4456 {
4457 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
4458 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
4459 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
4460 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
4461 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
4462 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
4463 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
4464 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
4465 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
4466 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
4467 { 0, CPENS(0,0,0,0), 0 }
4468 };
4469
4470 const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4471 {
4472 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4473 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4474 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4475 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4476 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4477 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4478 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4479 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4480 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4481 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4482 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4483 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
4484 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4485 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
4486 { 0, CPENS(0,0,0,0), 0 }
4487 };
4488
4489 const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4490 {
4491 { "vmalle1", CPENS(0,C8,C7,0), 0 },
4492 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4493 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4494 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
4495 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
4496 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4497 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4498 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4499 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4500 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4501 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4502 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4503 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4504 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
4505 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4506 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
4507 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4508 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
4509 { "alle2", CPENS(4,C8,C7,0), 0 },
4510 { "alle2is", CPENS(4,C8,C3,0), 0 },
4511 { "alle1", CPENS(4,C8,C7,4), 0 },
4512 { "alle1is", CPENS(4,C8,C3,4), 0 },
4513 { "alle3", CPENS(6,C8,C7,0), 0 },
4514 { "alle3is", CPENS(6,C8,C3,0), 0 },
4515 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4516 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4517 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4518 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4519 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4520 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4521 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4522 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
4523
4524 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4525 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4526 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4527 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4528 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4529 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4530 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4531 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4532 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4533 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4534 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4535 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4536 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4537 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4538 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4539 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4540
4541 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4542 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4543 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4544 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4545 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4546 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4547 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4548 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4549 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4550 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4551 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4552 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4553 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4554 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4555 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4556 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4557 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4558 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4559 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4560 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4561 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4562 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4563 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4564 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4565 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4566 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4567 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4568 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4569 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4570 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4571
4572 { 0, CPENS(0,0,0,0), 0 }
4573 };
4574
4575 const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4576 {
4577 /* RCTX is somewhat unique in a way that it has different values
4578 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4579 Thus op2 is masked out and instead encoded directly in the
4580 aarch64_opcode_table entries for the respective instructions. */
4581 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4582
4583 { 0, CPENS(0,0,0,0), 0 }
4584 };
4585
4586 bfd_boolean
4587 aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4588 {
4589 return (sys_ins_reg->flags & F_HASXT) != 0;
4590 }
4591
4592 extern bfd_boolean
4593 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4594 const aarch64_sys_ins_reg *reg)
4595 {
4596 if (!(reg->flags & F_ARCHEXT))
4597 return TRUE;
4598
4599 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4600 if (reg->value == CPENS (3, C7, C12, 1)
4601 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4602 return FALSE;
4603
4604 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4605 if (reg->value == CPENS (3, C7, C13, 1)
4606 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4607 return FALSE;
4608
4609 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4610 if ((reg->value == CPENS (0, C7, C9, 0)
4611 || reg->value == CPENS (0, C7, C9, 1))
4612 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4613 return FALSE;
4614
4615 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4616 if (reg->value == CPENS (3, C7, C3, 0)
4617 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4618 return FALSE;
4619
4620 return TRUE;
4621 }
4622
4623 #undef C0
4624 #undef C1
4625 #undef C2
4626 #undef C3
4627 #undef C4
4628 #undef C5
4629 #undef C6
4630 #undef C7
4631 #undef C8
4632 #undef C9
4633 #undef C10
4634 #undef C11
4635 #undef C12
4636 #undef C13
4637 #undef C14
4638 #undef C15
4639
4640 #define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4641 #define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4642
4643 static enum err_type
4644 verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4645 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4646 bfd_boolean encoding ATTRIBUTE_UNUSED,
4647 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4648 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4649 {
4650 int t = BITS (insn, 4, 0);
4651 int n = BITS (insn, 9, 5);
4652 int t2 = BITS (insn, 14, 10);
4653
4654 if (BIT (insn, 23))
4655 {
4656 /* Write back enabled. */
4657 if ((t == n || t2 == n) && n != 31)
4658 return ERR_UND;
4659 }
4660
4661 if (BIT (insn, 22))
4662 {
4663 /* Load */
4664 if (t == t2)
4665 return ERR_UND;
4666 }
4667
4668 return ERR_OK;
4669 }
4670
4671 /* Initialize an instruction sequence insn_sequence with the instruction INST.
4672 If INST is NULL the given insn_sequence is cleared and the sequence is left
4673 uninitialized. */
4674
4675 void
4676 init_insn_sequence (const struct aarch64_inst *inst,
4677 aarch64_instr_sequence *insn_sequence)
4678 {
4679 int num_req_entries = 0;
4680 insn_sequence->next_insn = 0;
4681 insn_sequence->num_insns = num_req_entries;
4682 if (insn_sequence->instr)
4683 XDELETE (insn_sequence->instr);
4684 insn_sequence->instr = NULL;
4685
4686 if (inst)
4687 {
4688 insn_sequence->instr = XNEW (aarch64_inst);
4689 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4690 }
4691
4692 /* Handle all the cases here. May need to think of something smarter than
4693 a giant if/else chain if this grows. At that time, a lookup table may be
4694 best. */
4695 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4696 num_req_entries = 1;
4697
4698 if (insn_sequence->current_insns)
4699 XDELETEVEC (insn_sequence->current_insns);
4700 insn_sequence->current_insns = NULL;
4701
4702 if (num_req_entries != 0)
4703 {
4704 size_t size = num_req_entries * sizeof (aarch64_inst);
4705 insn_sequence->current_insns
4706 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4707 memset (insn_sequence->current_insns, 0, size);
4708 }
4709 }
4710
4711
4712 /* This function verifies that the instruction INST adheres to its specified
4713 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4714 returned and MISMATCH_DETAIL contains the reason why verification failed.
4715
4716 The function is called both during assembly and disassembly. If assembling
4717 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4718 and will contain the PC of the current instruction w.r.t to the section.
4719
4720 If ENCODING and PC=0 then you are at a start of a section. The constraints
4721 are verified against the given state insn_sequence which is updated as it
4722 transitions through the verification. */
4723
4724 enum err_type
4725 verify_constraints (const struct aarch64_inst *inst,
4726 const aarch64_insn insn ATTRIBUTE_UNUSED,
4727 bfd_vma pc,
4728 bfd_boolean encoding,
4729 aarch64_operand_error *mismatch_detail,
4730 aarch64_instr_sequence *insn_sequence)
4731 {
4732 assert (inst);
4733 assert (inst->opcode);
4734
4735 const struct aarch64_opcode *opcode = inst->opcode;
4736 if (!opcode->constraints && !insn_sequence->instr)
4737 return ERR_OK;
4738
4739 assert (insn_sequence);
4740
4741 enum err_type res = ERR_OK;
4742
4743 /* This instruction puts a constraint on the insn_sequence. */
4744 if (opcode->flags & F_SCAN)
4745 {
4746 if (insn_sequence->instr)
4747 {
4748 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4749 mismatch_detail->error = _("instruction opens new dependency "
4750 "sequence without ending previous one");
4751 mismatch_detail->index = -1;
4752 mismatch_detail->non_fatal = TRUE;
4753 res = ERR_VFI;
4754 }
4755
4756 init_insn_sequence (inst, insn_sequence);
4757 return res;
4758 }
4759
4760 /* Verify constraints on an existing sequence. */
4761 if (insn_sequence->instr)
4762 {
4763 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4764 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4765 closed a previous one that we should have. */
4766 if (!encoding && pc == 0)
4767 {
4768 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4769 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4770 mismatch_detail->index = -1;
4771 mismatch_detail->non_fatal = TRUE;
4772 res = ERR_VFI;
4773 /* Reset the sequence. */
4774 init_insn_sequence (NULL, insn_sequence);
4775 return res;
4776 }
4777
4778 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4779 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4780 {
4781 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4782 instruction for better error messages. */
4783 if (!opcode->avariant || !(*opcode->avariant & AARCH64_FEATURE_SVE))
4784 {
4785 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4786 mismatch_detail->error = _("SVE instruction expected after "
4787 "`movprfx'");
4788 mismatch_detail->index = -1;
4789 mismatch_detail->non_fatal = TRUE;
4790 res = ERR_VFI;
4791 goto done;
4792 }
4793
4794 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4795 instruction that is allowed to be used with a MOVPRFX. */
4796 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4797 {
4798 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4799 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4800 "expected");
4801 mismatch_detail->index = -1;
4802 mismatch_detail->non_fatal = TRUE;
4803 res = ERR_VFI;
4804 goto done;
4805 }
4806
4807 /* Next check for usage of the predicate register. */
4808 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
4809 aarch64_opnd_info blk_pred, inst_pred;
4810 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4811 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
4812 bfd_boolean predicated = FALSE;
4813 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4814
4815 /* Determine if the movprfx instruction used is predicated or not. */
4816 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4817 {
4818 predicated = TRUE;
4819 blk_pred = insn_sequence->instr->operands[1];
4820 }
4821
4822 unsigned char max_elem_size = 0;
4823 unsigned char current_elem_size;
4824 int num_op_used = 0, last_op_usage = 0;
4825 int i, inst_pred_idx = -1;
4826 int num_ops = aarch64_num_of_operands (opcode);
4827 for (i = 0; i < num_ops; i++)
4828 {
4829 aarch64_opnd_info inst_op = inst->operands[i];
4830 switch (inst_op.type)
4831 {
4832 case AARCH64_OPND_SVE_Zd:
4833 case AARCH64_OPND_SVE_Zm_5:
4834 case AARCH64_OPND_SVE_Zm_16:
4835 case AARCH64_OPND_SVE_Zn:
4836 case AARCH64_OPND_SVE_Zt:
4837 case AARCH64_OPND_SVE_Vm:
4838 case AARCH64_OPND_SVE_Vn:
4839 case AARCH64_OPND_Va:
4840 case AARCH64_OPND_Vn:
4841 case AARCH64_OPND_Vm:
4842 case AARCH64_OPND_Sn:
4843 case AARCH64_OPND_Sm:
4844 case AARCH64_OPND_Rn:
4845 case AARCH64_OPND_Rm:
4846 case AARCH64_OPND_Rn_SP:
4847 case AARCH64_OPND_Rm_SP:
4848 if (inst_op.reg.regno == blk_dest.reg.regno)
4849 {
4850 num_op_used++;
4851 last_op_usage = i;
4852 }
4853 current_elem_size
4854 = aarch64_get_qualifier_esize (inst_op.qualifier);
4855 if (current_elem_size > max_elem_size)
4856 max_elem_size = current_elem_size;
4857 break;
4858 case AARCH64_OPND_SVE_Pd:
4859 case AARCH64_OPND_SVE_Pg3:
4860 case AARCH64_OPND_SVE_Pg4_5:
4861 case AARCH64_OPND_SVE_Pg4_10:
4862 case AARCH64_OPND_SVE_Pg4_16:
4863 case AARCH64_OPND_SVE_Pm:
4864 case AARCH64_OPND_SVE_Pn:
4865 case AARCH64_OPND_SVE_Pt:
4866 inst_pred = inst_op;
4867 inst_pred_idx = i;
4868 break;
4869 default:
4870 break;
4871 }
4872 }
4873
4874 assert (max_elem_size != 0);
4875 aarch64_opnd_info inst_dest = inst->operands[0];
4876 /* Determine the size that should be used to compare against the
4877 movprfx size. */
4878 current_elem_size
4879 = opcode->constraints & C_MAX_ELEM
4880 ? max_elem_size
4881 : aarch64_get_qualifier_esize (inst_dest.qualifier);
4882
4883 /* If movprfx is predicated do some extra checks. */
4884 if (predicated)
4885 {
4886 /* The instruction must be predicated. */
4887 if (inst_pred_idx < 0)
4888 {
4889 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4890 mismatch_detail->error = _("predicated instruction expected "
4891 "after `movprfx'");
4892 mismatch_detail->index = -1;
4893 mismatch_detail->non_fatal = TRUE;
4894 res = ERR_VFI;
4895 goto done;
4896 }
4897
4898 /* The instruction must have a merging predicate. */
4899 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
4900 {
4901 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4902 mismatch_detail->error = _("merging predicate expected due "
4903 "to preceding `movprfx'");
4904 mismatch_detail->index = inst_pred_idx;
4905 mismatch_detail->non_fatal = TRUE;
4906 res = ERR_VFI;
4907 goto done;
4908 }
4909
4910 /* The same register must be used in instruction. */
4911 if (blk_pred.reg.regno != inst_pred.reg.regno)
4912 {
4913 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4914 mismatch_detail->error = _("predicate register differs "
4915 "from that in preceding "
4916 "`movprfx'");
4917 mismatch_detail->index = inst_pred_idx;
4918 mismatch_detail->non_fatal = TRUE;
4919 res = ERR_VFI;
4920 goto done;
4921 }
4922 }
4923
4924 /* Destructive operations by definition must allow one usage of the
4925 same register. */
4926 int allowed_usage
4927 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
4928
4929 /* Operand is not used at all. */
4930 if (num_op_used == 0)
4931 {
4932 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4933 mismatch_detail->error = _("output register of preceding "
4934 "`movprfx' not used in current "
4935 "instruction");
4936 mismatch_detail->index = 0;
4937 mismatch_detail->non_fatal = TRUE;
4938 res = ERR_VFI;
4939 goto done;
4940 }
4941
4942 /* We now know it's used, now determine exactly where it's used. */
4943 if (blk_dest.reg.regno != inst_dest.reg.regno)
4944 {
4945 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4946 mismatch_detail->error = _("output register of preceding "
4947 "`movprfx' expected as output");
4948 mismatch_detail->index = 0;
4949 mismatch_detail->non_fatal = TRUE;
4950 res = ERR_VFI;
4951 goto done;
4952 }
4953
4954 /* Operand used more than allowed for the specific opcode type. */
4955 if (num_op_used > allowed_usage)
4956 {
4957 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4958 mismatch_detail->error = _("output register of preceding "
4959 "`movprfx' used as input");
4960 mismatch_detail->index = last_op_usage;
4961 mismatch_detail->non_fatal = TRUE;
4962 res = ERR_VFI;
4963 goto done;
4964 }
4965
4966 /* Now the only thing left is the qualifiers checks. The register
4967 must have the same maximum element size. */
4968 if (inst_dest.qualifier
4969 && blk_dest.qualifier
4970 && current_elem_size
4971 != aarch64_get_qualifier_esize (blk_dest.qualifier))
4972 {
4973 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4974 mismatch_detail->error = _("register size not compatible with "
4975 "previous `movprfx'");
4976 mismatch_detail->index = 0;
4977 mismatch_detail->non_fatal = TRUE;
4978 res = ERR_VFI;
4979 goto done;
4980 }
4981 }
4982
4983 done:
4984 /* Add the new instruction to the sequence. */
4985 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
4986 inst, sizeof (aarch64_inst));
4987
4988 /* Check if sequence is now full. */
4989 if (insn_sequence->next_insn >= insn_sequence->num_insns)
4990 {
4991 /* Sequence is full, but we don't have anything special to do for now,
4992 so clear and reset it. */
4993 init_insn_sequence (NULL, insn_sequence);
4994 }
4995 }
4996
4997 return res;
4998 }
4999
5000
5001 /* Return true if VALUE cannot be moved into an SVE register using DUP
5002 (with any element size, not just ESIZE) and if using DUPM would
5003 therefore be OK. ESIZE is the number of bytes in the immediate. */
5004
5005 bfd_boolean
5006 aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
5007 {
5008 int64_t svalue = uvalue;
5009 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
5010
5011 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
5012 return FALSE;
5013 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
5014 {
5015 svalue = (int32_t) uvalue;
5016 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
5017 {
5018 svalue = (int16_t) uvalue;
5019 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
5020 return FALSE;
5021 }
5022 }
5023 if ((svalue & 0xff) == 0)
5024 svalue /= 256;
5025 return svalue < -128 || svalue >= 128;
5026 }
5027
5028 /* Include the opcode description table as well as the operand description
5029 table. */
5030 #define VERIFIER(x) verify_##x
5031 #include "aarch64-tbl.h"
GDB Binutils - Deliverables
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