projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[binutils][aarch64] New SVE_ADDR_ZX operand.
[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c
1 /* aarch64-opc.c -- AArch64 opcode support.
2 Copyright (C) 2009-2019 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21 #include "sysdep.h"
22 #include <assert.h>
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include "bfd_stdint.h"
26 #include <stdarg.h>
27 #include <inttypes.h>
28
29 #include "opintl.h"
30 #include "libiberty.h"
31
32 #include "aarch64-opc.h"
33
34 #ifdef DEBUG_AARCH64
35 int debug_dump = FALSE;
36 #endif /* DEBUG_AARCH64 */
37
38 /* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40 const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77 };
78
79 /* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81 const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100 };
101
102 /* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105 static inline bfd_boolean
106 vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107 {
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111 }
112
113 static inline bfd_boolean
114 fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115 {
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119 }
120
121 enum data_pattern
122 {
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128 };
129
130 static const char significant_operand_index [] =
131 {
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137 };
138
139 /* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144 static enum data_pattern
145 get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146 {
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185 }
186
187 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189 /* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195 int
196 aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197 {
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200 }
201 \f
202 const aarch64_field fields[] =
203 {
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
243 { 15, 6 }, /* imm6_2: in rmif instructions. */
244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
245 { 0, 4 }, /* imm4_2: in rmif instructions. */
246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
254 { 0, 26 }, /* imm26: in unconditional branch instructions. */
255 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
256 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
257 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
258 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
259 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
260 { 22, 1 }, /* N: in logical (immediate) instructions. */
261 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
262 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
263 { 31, 1 }, /* sf: in integer data processing instructions. */
264 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
265 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
266 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
267 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
268 { 31, 1 }, /* b5: in the test bit and branch instructions. */
269 { 19, 5 }, /* b40: in the test bit and branch instructions. */
270 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
271 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
272 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
273 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
274 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
275 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
276 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
277 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
278 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
279 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
280 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
281 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
282 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
283 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
284 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
285 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
286 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
288 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
290 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
291 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
293 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
294 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
295 { 5, 1 }, /* SVE_i1: single-bit immediate. */
296 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
297 { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
298 { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
299 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
300 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
301 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
302 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
303 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
304 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
305 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
306 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
307 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
308 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
309 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
310 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
311 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
312 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
313 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
314 { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
315 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
316 { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
317 { 16, 4 }, /* SVE_tsz: triangular size select. */
318 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
319 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
320 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
321 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
322 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
323 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
324 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
325 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
326 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
327 { 22, 1 }, /* sz: 1-bit element size select. */
328 };
329
330 enum aarch64_operand_class
331 aarch64_get_operand_class (enum aarch64_opnd type)
332 {
333 return aarch64_operands[type].op_class;
334 }
335
336 const char *
337 aarch64_get_operand_name (enum aarch64_opnd type)
338 {
339 return aarch64_operands[type].name;
340 }
341
342 /* Get operand description string.
343 This is usually for the diagnosis purpose. */
344 const char *
345 aarch64_get_operand_desc (enum aarch64_opnd type)
346 {
347 return aarch64_operands[type].desc;
348 }
349
350 /* Table of all conditional affixes. */
351 const aarch64_cond aarch64_conds[16] =
352 {
353 {{"eq", "none"}, 0x0},
354 {{"ne", "any"}, 0x1},
355 {{"cs", "hs", "nlast"}, 0x2},
356 {{"cc", "lo", "ul", "last"}, 0x3},
357 {{"mi", "first"}, 0x4},
358 {{"pl", "nfrst"}, 0x5},
359 {{"vs"}, 0x6},
360 {{"vc"}, 0x7},
361 {{"hi", "pmore"}, 0x8},
362 {{"ls", "plast"}, 0x9},
363 {{"ge", "tcont"}, 0xa},
364 {{"lt", "tstop"}, 0xb},
365 {{"gt"}, 0xc},
366 {{"le"}, 0xd},
367 {{"al"}, 0xe},
368 {{"nv"}, 0xf},
369 };
370
371 const aarch64_cond *
372 get_cond_from_value (aarch64_insn value)
373 {
374 assert (value < 16);
375 return &aarch64_conds[(unsigned int) value];
376 }
377
378 const aarch64_cond *
379 get_inverted_cond (const aarch64_cond *cond)
380 {
381 return &aarch64_conds[cond->value ^ 0x1];
382 }
383
384 /* Table describing the operand extension/shifting operators; indexed by
385 enum aarch64_modifier_kind.
386
387 The value column provides the most common values for encoding modifiers,
388 which enables table-driven encoding/decoding for the modifiers. */
389 const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
390 {
391 {"none", 0x0},
392 {"msl", 0x0},
393 {"ror", 0x3},
394 {"asr", 0x2},
395 {"lsr", 0x1},
396 {"lsl", 0x0},
397 {"uxtb", 0x0},
398 {"uxth", 0x1},
399 {"uxtw", 0x2},
400 {"uxtx", 0x3},
401 {"sxtb", 0x4},
402 {"sxth", 0x5},
403 {"sxtw", 0x6},
404 {"sxtx", 0x7},
405 {"mul", 0x0},
406 {"mul vl", 0x0},
407 {NULL, 0},
408 };
409
410 enum aarch64_modifier_kind
411 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
412 {
413 return desc - aarch64_operand_modifiers;
414 }
415
416 aarch64_insn
417 aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
418 {
419 return aarch64_operand_modifiers[kind].value;
420 }
421
422 enum aarch64_modifier_kind
423 aarch64_get_operand_modifier_from_value (aarch64_insn value,
424 bfd_boolean extend_p)
425 {
426 if (extend_p == TRUE)
427 return AARCH64_MOD_UXTB + value;
428 else
429 return AARCH64_MOD_LSL - value;
430 }
431
432 bfd_boolean
433 aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
434 {
435 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
436 ? TRUE : FALSE;
437 }
438
439 static inline bfd_boolean
440 aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
441 {
442 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
443 ? TRUE : FALSE;
444 }
445
446 const struct aarch64_name_value_pair aarch64_barrier_options[16] =
447 {
448 { "#0x00", 0x0 },
449 { "oshld", 0x1 },
450 { "oshst", 0x2 },
451 { "osh", 0x3 },
452 { "#0x04", 0x4 },
453 { "nshld", 0x5 },
454 { "nshst", 0x6 },
455 { "nsh", 0x7 },
456 { "#0x08", 0x8 },
457 { "ishld", 0x9 },
458 { "ishst", 0xa },
459 { "ish", 0xb },
460 { "#0x0c", 0xc },
461 { "ld", 0xd },
462 { "st", 0xe },
463 { "sy", 0xf },
464 };
465
466 /* Table describing the operands supported by the aliases of the HINT
467 instruction.
468
469 The name column is the operand that is accepted for the alias. The value
470 column is the hint number of the alias. The list of operands is terminated
471 by NULL in the name column. */
472
473 const struct aarch64_name_value_pair aarch64_hint_options[] =
474 {
475 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
476 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
477 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
478 { "c", HINT_OPD_C }, /* BTI C. */
479 { "j", HINT_OPD_J }, /* BTI J. */
480 { "jc", HINT_OPD_JC }, /* BTI JC. */
481 { NULL, HINT_OPD_NULL },
482 };
483
484 /* op -> op: load = 0 instruction = 1 store = 2
485 l -> level: 1-3
486 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
487 #define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
488 const struct aarch64_name_value_pair aarch64_prfops[32] =
489 {
490 { "pldl1keep", B(0, 1, 0) },
491 { "pldl1strm", B(0, 1, 1) },
492 { "pldl2keep", B(0, 2, 0) },
493 { "pldl2strm", B(0, 2, 1) },
494 { "pldl3keep", B(0, 3, 0) },
495 { "pldl3strm", B(0, 3, 1) },
496 { NULL, 0x06 },
497 { NULL, 0x07 },
498 { "plil1keep", B(1, 1, 0) },
499 { "plil1strm", B(1, 1, 1) },
500 { "plil2keep", B(1, 2, 0) },
501 { "plil2strm", B(1, 2, 1) },
502 { "plil3keep", B(1, 3, 0) },
503 { "plil3strm", B(1, 3, 1) },
504 { NULL, 0x0e },
505 { NULL, 0x0f },
506 { "pstl1keep", B(2, 1, 0) },
507 { "pstl1strm", B(2, 1, 1) },
508 { "pstl2keep", B(2, 2, 0) },
509 { "pstl2strm", B(2, 2, 1) },
510 { "pstl3keep", B(2, 3, 0) },
511 { "pstl3strm", B(2, 3, 1) },
512 { NULL, 0x16 },
513 { NULL, 0x17 },
514 { NULL, 0x18 },
515 { NULL, 0x19 },
516 { NULL, 0x1a },
517 { NULL, 0x1b },
518 { NULL, 0x1c },
519 { NULL, 0x1d },
520 { NULL, 0x1e },
521 { NULL, 0x1f },
522 };
523 #undef B
524 \f
525 /* Utilities on value constraint. */
526
527 static inline int
528 value_in_range_p (int64_t value, int low, int high)
529 {
530 return (value >= low && value <= high) ? 1 : 0;
531 }
532
533 /* Return true if VALUE is a multiple of ALIGN. */
534 static inline int
535 value_aligned_p (int64_t value, int align)
536 {
537 return (value % align) == 0;
538 }
539
540 /* A signed value fits in a field. */
541 static inline int
542 value_fit_signed_field_p (int64_t value, unsigned width)
543 {
544 assert (width < 32);
545 if (width < sizeof (value) * 8)
546 {
547 int64_t lim = (int64_t)1 << (width - 1);
548 if (value >= -lim && value < lim)
549 return 1;
550 }
551 return 0;
552 }
553
554 /* An unsigned value fits in a field. */
555 static inline int
556 value_fit_unsigned_field_p (int64_t value, unsigned width)
557 {
558 assert (width < 32);
559 if (width < sizeof (value) * 8)
560 {
561 int64_t lim = (int64_t)1 << width;
562 if (value >= 0 && value < lim)
563 return 1;
564 }
565 return 0;
566 }
567
568 /* Return 1 if OPERAND is SP or WSP. */
569 int
570 aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
571 {
572 return ((aarch64_get_operand_class (operand->type)
573 == AARCH64_OPND_CLASS_INT_REG)
574 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
575 && operand->reg.regno == 31);
576 }
577
578 /* Return 1 if OPERAND is XZR or WZP. */
579 int
580 aarch64_zero_register_p (const aarch64_opnd_info *operand)
581 {
582 return ((aarch64_get_operand_class (operand->type)
583 == AARCH64_OPND_CLASS_INT_REG)
584 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
585 && operand->reg.regno == 31);
586 }
587
588 /* Return true if the operand *OPERAND that has the operand code
589 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
590 qualified by the qualifier TARGET. */
591
592 static inline int
593 operand_also_qualified_p (const struct aarch64_opnd_info *operand,
594 aarch64_opnd_qualifier_t target)
595 {
596 switch (operand->qualifier)
597 {
598 case AARCH64_OPND_QLF_W:
599 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
600 return 1;
601 break;
602 case AARCH64_OPND_QLF_X:
603 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
604 return 1;
605 break;
606 case AARCH64_OPND_QLF_WSP:
607 if (target == AARCH64_OPND_QLF_W
608 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
609 return 1;
610 break;
611 case AARCH64_OPND_QLF_SP:
612 if (target == AARCH64_OPND_QLF_X
613 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
614 return 1;
615 break;
616 default:
617 break;
618 }
619
620 return 0;
621 }
622
623 /* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
624 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
625
626 Return NIL if more than one expected qualifiers are found. */
627
628 aarch64_opnd_qualifier_t
629 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
630 int idx,
631 const aarch64_opnd_qualifier_t known_qlf,
632 int known_idx)
633 {
634 int i, saved_i;
635
636 /* Special case.
637
638 When the known qualifier is NIL, we have to assume that there is only
639 one qualifier sequence in the *QSEQ_LIST and return the corresponding
640 qualifier directly. One scenario is that for instruction
641 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
642 which has only one possible valid qualifier sequence
643 NIL, S_D
644 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
645 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
646
647 Because the qualifier NIL has dual roles in the qualifier sequence:
648 it can mean no qualifier for the operand, or the qualifer sequence is
649 not in use (when all qualifiers in the sequence are NILs), we have to
650 handle this special case here. */
651 if (known_qlf == AARCH64_OPND_NIL)
652 {
653 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
654 return qseq_list[0][idx];
655 }
656
657 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
658 {
659 if (qseq_list[i][known_idx] == known_qlf)
660 {
661 if (saved_i != -1)
662 /* More than one sequences are found to have KNOWN_QLF at
663 KNOWN_IDX. */
664 return AARCH64_OPND_NIL;
665 saved_i = i;
666 }
667 }
668
669 return qseq_list[saved_i][idx];
670 }
671
672 enum operand_qualifier_kind
673 {
674 OQK_NIL,
675 OQK_OPD_VARIANT,
676 OQK_VALUE_IN_RANGE,
677 OQK_MISC,
678 };
679
680 /* Operand qualifier description. */
681 struct operand_qualifier_data
682 {
683 /* The usage of the three data fields depends on the qualifier kind. */
684 int data0;
685 int data1;
686 int data2;
687 /* Description. */
688 const char *desc;
689 /* Kind. */
690 enum operand_qualifier_kind kind;
691 };
692
693 /* Indexed by the operand qualifier enumerators. */
694 struct operand_qualifier_data aarch64_opnd_qualifiers[] =
695 {
696 {0, 0, 0, "NIL", OQK_NIL},
697
698 /* Operand variant qualifiers.
699 First 3 fields:
700 element size, number of elements and common value for encoding. */
701
702 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
703 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
704 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
705 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
706
707 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
708 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
709 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
710 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
711 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
712 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
713
714 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
715 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
716 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
717 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
718 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
719 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
720 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
721 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
722 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
723 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
724 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
725
726 {0, 0, 0, "z", OQK_OPD_VARIANT},
727 {0, 0, 0, "m", OQK_OPD_VARIANT},
728
729 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
730 {16, 0, 0, "tag", OQK_OPD_VARIANT},
731
732 /* Qualifiers constraining the value range.
733 First 3 fields:
734 Lower bound, higher bound, unused. */
735
736 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
737 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
738 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
739 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
740 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
741 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
742 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
743
744 /* Qualifiers for miscellaneous purpose.
745 First 3 fields:
746 unused, unused and unused. */
747
748 {0, 0, 0, "lsl", 0},
749 {0, 0, 0, "msl", 0},
750
751 {0, 0, 0, "retrieving", 0},
752 };
753
754 static inline bfd_boolean
755 operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
756 {
757 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
758 ? TRUE : FALSE;
759 }
760
761 static inline bfd_boolean
762 qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
763 {
764 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
765 ? TRUE : FALSE;
766 }
767
768 const char*
769 aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
770 {
771 return aarch64_opnd_qualifiers[qualifier].desc;
772 }
773
774 /* Given an operand qualifier, return the expected data element size
775 of a qualified operand. */
776 unsigned char
777 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
778 {
779 assert (operand_variant_qualifier_p (qualifier) == TRUE);
780 return aarch64_opnd_qualifiers[qualifier].data0;
781 }
782
783 unsigned char
784 aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
785 {
786 assert (operand_variant_qualifier_p (qualifier) == TRUE);
787 return aarch64_opnd_qualifiers[qualifier].data1;
788 }
789
790 aarch64_insn
791 aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
792 {
793 assert (operand_variant_qualifier_p (qualifier) == TRUE);
794 return aarch64_opnd_qualifiers[qualifier].data2;
795 }
796
797 static int
798 get_lower_bound (aarch64_opnd_qualifier_t qualifier)
799 {
800 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
801 return aarch64_opnd_qualifiers[qualifier].data0;
802 }
803
804 static int
805 get_upper_bound (aarch64_opnd_qualifier_t qualifier)
806 {
807 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
808 return aarch64_opnd_qualifiers[qualifier].data1;
809 }
810
811 #ifdef DEBUG_AARCH64
812 void
813 aarch64_verbose (const char *str, ...)
814 {
815 va_list ap;
816 va_start (ap, str);
817 printf ("#### ");
818 vprintf (str, ap);
819 printf ("\n");
820 va_end (ap);
821 }
822
823 static inline void
824 dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
825 {
826 int i;
827 printf ("#### \t");
828 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
829 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
830 printf ("\n");
831 }
832
833 static void
834 dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
835 const aarch64_opnd_qualifier_t *qualifier)
836 {
837 int i;
838 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
839
840 aarch64_verbose ("dump_match_qualifiers:");
841 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
842 curr[i] = opnd[i].qualifier;
843 dump_qualifier_sequence (curr);
844 aarch64_verbose ("against");
845 dump_qualifier_sequence (qualifier);
846 }
847 #endif /* DEBUG_AARCH64 */
848
849 /* This function checks if the given instruction INSN is a destructive
850 instruction based on the usage of the registers. It does not recognize
851 unary destructive instructions. */
852 bfd_boolean
853 aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
854 {
855 int i = 0;
856 const enum aarch64_opnd *opnds = opcode->operands;
857
858 if (opnds[0] == AARCH64_OPND_NIL)
859 return FALSE;
860
861 while (opnds[++i] != AARCH64_OPND_NIL)
862 if (opnds[i] == opnds[0])
863 return TRUE;
864
865 return FALSE;
866 }
867
868 /* TODO improve this, we can have an extra field at the runtime to
869 store the number of operands rather than calculating it every time. */
870
871 int
872 aarch64_num_of_operands (const aarch64_opcode *opcode)
873 {
874 int i = 0;
875 const enum aarch64_opnd *opnds = opcode->operands;
876 while (opnds[i++] != AARCH64_OPND_NIL)
877 ;
878 --i;
879 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
880 return i;
881 }
882
883 /* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
884 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
885
886 N.B. on the entry, it is very likely that only some operands in *INST
887 have had their qualifiers been established.
888
889 If STOP_AT is not -1, the function will only try to match
890 the qualifier sequence for operands before and including the operand
891 of index STOP_AT; and on success *RET will only be filled with the first
892 (STOP_AT+1) qualifiers.
893
894 A couple examples of the matching algorithm:
895
896 X,W,NIL should match
897 X,W,NIL
898
899 NIL,NIL should match
900 X ,NIL
901
902 Apart from serving the main encoding routine, this can also be called
903 during or after the operand decoding. */
904
905 int
906 aarch64_find_best_match (const aarch64_inst *inst,
907 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
908 int stop_at, aarch64_opnd_qualifier_t *ret)
909 {
910 int found = 0;
911 int i, num_opnds;
912 const aarch64_opnd_qualifier_t *qualifiers;
913
914 num_opnds = aarch64_num_of_operands (inst->opcode);
915 if (num_opnds == 0)
916 {
917 DEBUG_TRACE ("SUCCEED: no operand");
918 return 1;
919 }
920
921 if (stop_at < 0 || stop_at >= num_opnds)
922 stop_at = num_opnds - 1;
923
924 /* For each pattern. */
925 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
926 {
927 int j;
928 qualifiers = *qualifiers_list;
929
930 /* Start as positive. */
931 found = 1;
932
933 DEBUG_TRACE ("%d", i);
934 #ifdef DEBUG_AARCH64
935 if (debug_dump)
936 dump_match_qualifiers (inst->operands, qualifiers);
937 #endif
938
939 /* Most opcodes has much fewer patterns in the list.
940 First NIL qualifier indicates the end in the list. */
941 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
942 {
943 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
944 if (i)
945 found = 0;
946 break;
947 }
948
949 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
950 {
951 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
952 {
953 /* Either the operand does not have qualifier, or the qualifier
954 for the operand needs to be deduced from the qualifier
955 sequence.
956 In the latter case, any constraint checking related with
957 the obtained qualifier should be done later in
958 operand_general_constraint_met_p. */
959 continue;
960 }
961 else if (*qualifiers != inst->operands[j].qualifier)
962 {
963 /* Unless the target qualifier can also qualify the operand
964 (which has already had a non-nil qualifier), non-equal
965 qualifiers are generally un-matched. */
966 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
967 continue;
968 else
969 {
970 found = 0;
971 break;
972 }
973 }
974 else
975 continue; /* Equal qualifiers are certainly matched. */
976 }
977
978 /* Qualifiers established. */
979 if (found == 1)
980 break;
981 }
982
983 if (found == 1)
984 {
985 /* Fill the result in *RET. */
986 int j;
987 qualifiers = *qualifiers_list;
988
989 DEBUG_TRACE ("complete qualifiers using list %d", i);
990 #ifdef DEBUG_AARCH64
991 if (debug_dump)
992 dump_qualifier_sequence (qualifiers);
993 #endif
994
995 for (j = 0; j <= stop_at; ++j, ++qualifiers)
996 ret[j] = *qualifiers;
997 for (; j < AARCH64_MAX_OPND_NUM; ++j)
998 ret[j] = AARCH64_OPND_QLF_NIL;
999
1000 DEBUG_TRACE ("SUCCESS");
1001 return 1;
1002 }
1003
1004 DEBUG_TRACE ("FAIL");
1005 return 0;
1006 }
1007
1008 /* Operand qualifier matching and resolving.
1009
1010 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1011 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1012
1013 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1014 succeeds. */
1015
1016 static int
1017 match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1018 {
1019 int i, nops;
1020 aarch64_opnd_qualifier_seq_t qualifiers;
1021
1022 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1023 qualifiers))
1024 {
1025 DEBUG_TRACE ("matching FAIL");
1026 return 0;
1027 }
1028
1029 if (inst->opcode->flags & F_STRICT)
1030 {
1031 /* Require an exact qualifier match, even for NIL qualifiers. */
1032 nops = aarch64_num_of_operands (inst->opcode);
1033 for (i = 0; i < nops; ++i)
1034 if (inst->operands[i].qualifier != qualifiers[i])
1035 return FALSE;
1036 }
1037
1038 /* Update the qualifiers. */
1039 if (update_p == TRUE)
1040 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1041 {
1042 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1043 break;
1044 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1045 "update %s with %s for operand %d",
1046 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1047 aarch64_get_qualifier_name (qualifiers[i]), i);
1048 inst->operands[i].qualifier = qualifiers[i];
1049 }
1050
1051 DEBUG_TRACE ("matching SUCCESS");
1052 return 1;
1053 }
1054
1055 /* Return TRUE if VALUE is a wide constant that can be moved into a general
1056 register by MOVZ.
1057
1058 IS32 indicates whether value is a 32-bit immediate or not.
1059 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1060 amount will be returned in *SHIFT_AMOUNT. */
1061
1062 bfd_boolean
1063 aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1064 {
1065 int amount;
1066
1067 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1068
1069 if (is32)
1070 {
1071 /* Allow all zeros or all ones in top 32-bits, so that
1072 32-bit constant expressions like ~0x80000000 are
1073 permitted. */
1074 uint64_t ext = value;
1075 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1076 /* Immediate out of range. */
1077 return FALSE;
1078 value &= (int64_t) 0xffffffff;
1079 }
1080
1081 /* first, try movz then movn */
1082 amount = -1;
1083 if ((value & ((int64_t) 0xffff << 0)) == value)
1084 amount = 0;
1085 else if ((value & ((int64_t) 0xffff << 16)) == value)
1086 amount = 16;
1087 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1088 amount = 32;
1089 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1090 amount = 48;
1091
1092 if (amount == -1)
1093 {
1094 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1095 return FALSE;
1096 }
1097
1098 if (shift_amount != NULL)
1099 *shift_amount = amount;
1100
1101 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1102
1103 return TRUE;
1104 }
1105
1106 /* Build the accepted values for immediate logical SIMD instructions.
1107
1108 The standard encodings of the immediate value are:
1109 N imms immr SIMD size R S
1110 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1111 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1112 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1113 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1114 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1115 0 11110s 00000r 2 UInt(r) UInt(s)
1116 where all-ones value of S is reserved.
1117
1118 Let's call E the SIMD size.
1119
1120 The immediate value is: S+1 bits '1' rotated to the right by R.
1121
1122 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1123 (remember S != E - 1). */
1124
1125 #define TOTAL_IMM_NB 5334
1126
1127 typedef struct
1128 {
1129 uint64_t imm;
1130 aarch64_insn encoding;
1131 } simd_imm_encoding;
1132
1133 static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1134
1135 static int
1136 simd_imm_encoding_cmp(const void *i1, const void *i2)
1137 {
1138 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1139 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1140
1141 if (imm1->imm < imm2->imm)
1142 return -1;
1143 if (imm1->imm > imm2->imm)
1144 return +1;
1145 return 0;
1146 }
1147
1148 /* immediate bitfield standard encoding
1149 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1150 1 ssssss rrrrrr 64 rrrrrr ssssss
1151 0 0sssss 0rrrrr 32 rrrrr sssss
1152 0 10ssss 00rrrr 16 rrrr ssss
1153 0 110sss 000rrr 8 rrr sss
1154 0 1110ss 0000rr 4 rr ss
1155 0 11110s 00000r 2 r s */
1156 static inline int
1157 encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1158 {
1159 return (is64 << 12) | (r << 6) | s;
1160 }
1161
1162 static void
1163 build_immediate_table (void)
1164 {
1165 uint32_t log_e, e, s, r, s_mask;
1166 uint64_t mask, imm;
1167 int nb_imms;
1168 int is64;
1169
1170 nb_imms = 0;
1171 for (log_e = 1; log_e <= 6; log_e++)
1172 {
1173 /* Get element size. */
1174 e = 1u << log_e;
1175 if (log_e == 6)
1176 {
1177 is64 = 1;
1178 mask = 0xffffffffffffffffull;
1179 s_mask = 0;
1180 }
1181 else
1182 {
1183 is64 = 0;
1184 mask = (1ull << e) - 1;
1185 /* log_e s_mask
1186 1 ((1 << 4) - 1) << 2 = 111100
1187 2 ((1 << 3) - 1) << 3 = 111000
1188 3 ((1 << 2) - 1) << 4 = 110000
1189 4 ((1 << 1) - 1) << 5 = 100000
1190 5 ((1 << 0) - 1) << 6 = 000000 */
1191 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1192 }
1193 for (s = 0; s < e - 1; s++)
1194 for (r = 0; r < e; r++)
1195 {
1196 /* s+1 consecutive bits to 1 (s < 63) */
1197 imm = (1ull << (s + 1)) - 1;
1198 /* rotate right by r */
1199 if (r != 0)
1200 imm = (imm >> r) | ((imm << (e - r)) & mask);
1201 /* replicate the constant depending on SIMD size */
1202 switch (log_e)
1203 {
1204 case 1: imm = (imm << 2) | imm;
1205 /* Fall through. */
1206 case 2: imm = (imm << 4) | imm;
1207 /* Fall through. */
1208 case 3: imm = (imm << 8) | imm;
1209 /* Fall through. */
1210 case 4: imm = (imm << 16) | imm;
1211 /* Fall through. */
1212 case 5: imm = (imm << 32) | imm;
1213 /* Fall through. */
1214 case 6: break;
1215 default: abort ();
1216 }
1217 simd_immediates[nb_imms].imm = imm;
1218 simd_immediates[nb_imms].encoding =
1219 encode_immediate_bitfield(is64, s | s_mask, r);
1220 nb_imms++;
1221 }
1222 }
1223 assert (nb_imms == TOTAL_IMM_NB);
1224 qsort(simd_immediates, nb_imms,
1225 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1226 }
1227
1228 /* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1229 be accepted by logical (immediate) instructions
1230 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1231
1232 ESIZE is the number of bytes in the decoded immediate value.
1233 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1234 VALUE will be returned in *ENCODING. */
1235
1236 bfd_boolean
1237 aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
1238 {
1239 simd_imm_encoding imm_enc;
1240 const simd_imm_encoding *imm_encoding;
1241 static bfd_boolean initialized = FALSE;
1242 uint64_t upper;
1243 int i;
1244
1245 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1246 value, esize);
1247
1248 if (!initialized)
1249 {
1250 build_immediate_table ();
1251 initialized = TRUE;
1252 }
1253
1254 /* Allow all zeros or all ones in top bits, so that
1255 constant expressions like ~1 are permitted. */
1256 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1257 if ((value & ~upper) != value && (value | upper) != value)
1258 return FALSE;
1259
1260 /* Replicate to a full 64-bit value. */
1261 value &= ~upper;
1262 for (i = esize * 8; i < 64; i *= 2)
1263 value |= (value << i);
1264
1265 imm_enc.imm = value;
1266 imm_encoding = (const simd_imm_encoding *)
1267 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1268 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1269 if (imm_encoding == NULL)
1270 {
1271 DEBUG_TRACE ("exit with FALSE");
1272 return FALSE;
1273 }
1274 if (encoding != NULL)
1275 *encoding = imm_encoding->encoding;
1276 DEBUG_TRACE ("exit with TRUE");
1277 return TRUE;
1278 }
1279
1280 /* If 64-bit immediate IMM is in the format of
1281 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1282 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1283 of value "abcdefgh". Otherwise return -1. */
1284 int
1285 aarch64_shrink_expanded_imm8 (uint64_t imm)
1286 {
1287 int i, ret;
1288 uint32_t byte;
1289
1290 ret = 0;
1291 for (i = 0; i < 8; i++)
1292 {
1293 byte = (imm >> (8 * i)) & 0xff;
1294 if (byte == 0xff)
1295 ret |= 1 << i;
1296 else if (byte != 0x00)
1297 return -1;
1298 }
1299 return ret;
1300 }
1301
1302 /* Utility inline functions for operand_general_constraint_met_p. */
1303
1304 static inline void
1305 set_error (aarch64_operand_error *mismatch_detail,
1306 enum aarch64_operand_error_kind kind, int idx,
1307 const char* error)
1308 {
1309 if (mismatch_detail == NULL)
1310 return;
1311 mismatch_detail->kind = kind;
1312 mismatch_detail->index = idx;
1313 mismatch_detail->error = error;
1314 }
1315
1316 static inline void
1317 set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1318 const char* error)
1319 {
1320 if (mismatch_detail == NULL)
1321 return;
1322 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1323 }
1324
1325 static inline void
1326 set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1327 int idx, int lower_bound, int upper_bound,
1328 const char* error)
1329 {
1330 if (mismatch_detail == NULL)
1331 return;
1332 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1333 mismatch_detail->data[0] = lower_bound;
1334 mismatch_detail->data[1] = upper_bound;
1335 }
1336
1337 static inline void
1338 set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1339 int idx, int lower_bound, int upper_bound)
1340 {
1341 if (mismatch_detail == NULL)
1342 return;
1343 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1344 _("immediate value"));
1345 }
1346
1347 static inline void
1348 set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1349 int idx, int lower_bound, int upper_bound)
1350 {
1351 if (mismatch_detail == NULL)
1352 return;
1353 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1354 _("immediate offset"));
1355 }
1356
1357 static inline void
1358 set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1359 int idx, int lower_bound, int upper_bound)
1360 {
1361 if (mismatch_detail == NULL)
1362 return;
1363 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1364 _("register number"));
1365 }
1366
1367 static inline void
1368 set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1369 int idx, int lower_bound, int upper_bound)
1370 {
1371 if (mismatch_detail == NULL)
1372 return;
1373 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1374 _("register element index"));
1375 }
1376
1377 static inline void
1378 set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1379 int idx, int lower_bound, int upper_bound)
1380 {
1381 if (mismatch_detail == NULL)
1382 return;
1383 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1384 _("shift amount"));
1385 }
1386
1387 /* Report that the MUL modifier in operand IDX should be in the range
1388 [LOWER_BOUND, UPPER_BOUND]. */
1389 static inline void
1390 set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1391 int idx, int lower_bound, int upper_bound)
1392 {
1393 if (mismatch_detail == NULL)
1394 return;
1395 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1396 _("multiplier"));
1397 }
1398
1399 static inline void
1400 set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1401 int alignment)
1402 {
1403 if (mismatch_detail == NULL)
1404 return;
1405 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1406 mismatch_detail->data[0] = alignment;
1407 }
1408
1409 static inline void
1410 set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1411 int expected_num)
1412 {
1413 if (mismatch_detail == NULL)
1414 return;
1415 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1416 mismatch_detail->data[0] = expected_num;
1417 }
1418
1419 static inline void
1420 set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1421 const char* error)
1422 {
1423 if (mismatch_detail == NULL)
1424 return;
1425 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1426 }
1427
1428 /* General constraint checking based on operand code.
1429
1430 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1431 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1432
1433 This function has to be called after the qualifiers for all operands
1434 have been resolved.
1435
1436 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1437 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1438 of error message during the disassembling where error message is not
1439 wanted. We avoid the dynamic construction of strings of error messages
1440 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1441 use a combination of error code, static string and some integer data to
1442 represent an error. */
1443
1444 static int
1445 operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1446 enum aarch64_opnd type,
1447 const aarch64_opcode *opcode,
1448 aarch64_operand_error *mismatch_detail)
1449 {
1450 unsigned num, modifiers, shift;
1451 unsigned char size;
1452 int64_t imm, min_value, max_value;
1453 uint64_t uvalue, mask;
1454 const aarch64_opnd_info *opnd = opnds + idx;
1455 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1456
1457 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1458
1459 switch (aarch64_operands[type].op_class)
1460 {
1461 case AARCH64_OPND_CLASS_INT_REG:
1462 /* Check pair reg constraints for cas* instructions. */
1463 if (type == AARCH64_OPND_PAIRREG)
1464 {
1465 assert (idx == 1 || idx == 3);
1466 if (opnds[idx - 1].reg.regno % 2 != 0)
1467 {
1468 set_syntax_error (mismatch_detail, idx - 1,
1469 _("reg pair must start from even reg"));
1470 return 0;
1471 }
1472 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1473 {
1474 set_syntax_error (mismatch_detail, idx,
1475 _("reg pair must be contiguous"));
1476 return 0;
1477 }
1478 break;
1479 }
1480
1481 /* <Xt> may be optional in some IC and TLBI instructions. */
1482 if (type == AARCH64_OPND_Rt_SYS)
1483 {
1484 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1485 == AARCH64_OPND_CLASS_SYSTEM));
1486 if (opnds[1].present
1487 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1488 {
1489 set_other_error (mismatch_detail, idx, _("extraneous register"));
1490 return 0;
1491 }
1492 if (!opnds[1].present
1493 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
1494 {
1495 set_other_error (mismatch_detail, idx, _("missing register"));
1496 return 0;
1497 }
1498 }
1499 switch (qualifier)
1500 {
1501 case AARCH64_OPND_QLF_WSP:
1502 case AARCH64_OPND_QLF_SP:
1503 if (!aarch64_stack_pointer_p (opnd))
1504 {
1505 set_other_error (mismatch_detail, idx,
1506 _("stack pointer register expected"));
1507 return 0;
1508 }
1509 break;
1510 default:
1511 break;
1512 }
1513 break;
1514
1515 case AARCH64_OPND_CLASS_SVE_REG:
1516 switch (type)
1517 {
1518 case AARCH64_OPND_SVE_Zm3_INDEX:
1519 case AARCH64_OPND_SVE_Zm3_22_INDEX:
1520 case AARCH64_OPND_SVE_Zm3_11_INDEX:
1521 case AARCH64_OPND_SVE_Zm4_INDEX:
1522 size = get_operand_fields_width (get_operand_from_code (type));
1523 shift = get_operand_specific_data (&aarch64_operands[type]);
1524 mask = (1 << shift) - 1;
1525 if (opnd->reg.regno > mask)
1526 {
1527 assert (mask == 7 || mask == 15);
1528 set_other_error (mismatch_detail, idx,
1529 mask == 15
1530 ? _("z0-z15 expected")
1531 : _("z0-z7 expected"));
1532 return 0;
1533 }
1534 mask = (1 << (size - shift)) - 1;
1535 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1536 {
1537 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1538 return 0;
1539 }
1540 break;
1541
1542 case AARCH64_OPND_SVE_Zn_INDEX:
1543 size = aarch64_get_qualifier_esize (opnd->qualifier);
1544 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1545 {
1546 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1547 0, 64 / size - 1);
1548 return 0;
1549 }
1550 break;
1551
1552 case AARCH64_OPND_SVE_ZnxN:
1553 case AARCH64_OPND_SVE_ZtxN:
1554 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1555 {
1556 set_other_error (mismatch_detail, idx,
1557 _("invalid register list"));
1558 return 0;
1559 }
1560 break;
1561
1562 default:
1563 break;
1564 }
1565 break;
1566
1567 case AARCH64_OPND_CLASS_PRED_REG:
1568 if (opnd->reg.regno >= 8
1569 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1570 {
1571 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1572 return 0;
1573 }
1574 break;
1575
1576 case AARCH64_OPND_CLASS_COND:
1577 if (type == AARCH64_OPND_COND1
1578 && (opnds[idx].cond->value & 0xe) == 0xe)
1579 {
1580 /* Not allow AL or NV. */
1581 set_syntax_error (mismatch_detail, idx, NULL);
1582 }
1583 break;
1584
1585 case AARCH64_OPND_CLASS_ADDRESS:
1586 /* Check writeback. */
1587 switch (opcode->iclass)
1588 {
1589 case ldst_pos:
1590 case ldst_unscaled:
1591 case ldstnapair_offs:
1592 case ldstpair_off:
1593 case ldst_unpriv:
1594 if (opnd->addr.writeback == 1)
1595 {
1596 set_syntax_error (mismatch_detail, idx,
1597 _("unexpected address writeback"));
1598 return 0;
1599 }
1600 break;
1601 case ldst_imm10:
1602 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1603 {
1604 set_syntax_error (mismatch_detail, idx,
1605 _("unexpected address writeback"));
1606 return 0;
1607 }
1608 break;
1609 case ldst_imm9:
1610 case ldstpair_indexed:
1611 case asisdlsep:
1612 case asisdlsop:
1613 if (opnd->addr.writeback == 0)
1614 {
1615 set_syntax_error (mismatch_detail, idx,
1616 _("address writeback expected"));
1617 return 0;
1618 }
1619 break;
1620 default:
1621 assert (opnd->addr.writeback == 0);
1622 break;
1623 }
1624 switch (type)
1625 {
1626 case AARCH64_OPND_ADDR_SIMM7:
1627 /* Scaled signed 7 bits immediate offset. */
1628 /* Get the size of the data element that is accessed, which may be
1629 different from that of the source register size,
1630 e.g. in strb/ldrb. */
1631 size = aarch64_get_qualifier_esize (opnd->qualifier);
1632 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1633 {
1634 set_offset_out_of_range_error (mismatch_detail, idx,
1635 -64 * size, 63 * size);
1636 return 0;
1637 }
1638 if (!value_aligned_p (opnd->addr.offset.imm, size))
1639 {
1640 set_unaligned_error (mismatch_detail, idx, size);
1641 return 0;
1642 }
1643 break;
1644 case AARCH64_OPND_ADDR_OFFSET:
1645 case AARCH64_OPND_ADDR_SIMM9:
1646 /* Unscaled signed 9 bits immediate offset. */
1647 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1648 {
1649 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1650 return 0;
1651 }
1652 break;
1653
1654 case AARCH64_OPND_ADDR_SIMM9_2:
1655 /* Unscaled signed 9 bits immediate offset, which has to be negative
1656 or unaligned. */
1657 size = aarch64_get_qualifier_esize (qualifier);
1658 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1659 && !value_aligned_p (opnd->addr.offset.imm, size))
1660 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1661 return 1;
1662 set_other_error (mismatch_detail, idx,
1663 _("negative or unaligned offset expected"));
1664 return 0;
1665
1666 case AARCH64_OPND_ADDR_SIMM10:
1667 /* Scaled signed 10 bits immediate offset. */
1668 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1669 {
1670 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1671 return 0;
1672 }
1673 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1674 {
1675 set_unaligned_error (mismatch_detail, idx, 8);
1676 return 0;
1677 }
1678 break;
1679
1680 case AARCH64_OPND_ADDR_SIMM11:
1681 /* Signed 11 bits immediate offset (multiple of 16). */
1682 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
1683 {
1684 set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
1685 return 0;
1686 }
1687
1688 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1689 {
1690 set_unaligned_error (mismatch_detail, idx, 16);
1691 return 0;
1692 }
1693 break;
1694
1695 case AARCH64_OPND_ADDR_SIMM13:
1696 /* Signed 13 bits immediate offset (multiple of 16). */
1697 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
1698 {
1699 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
1700 return 0;
1701 }
1702
1703 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1704 {
1705 set_unaligned_error (mismatch_detail, idx, 16);
1706 return 0;
1707 }
1708 break;
1709
1710 case AARCH64_OPND_SIMD_ADDR_POST:
1711 /* AdvSIMD load/store multiple structures, post-index. */
1712 assert (idx == 1);
1713 if (opnd->addr.offset.is_reg)
1714 {
1715 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1716 return 1;
1717 else
1718 {
1719 set_other_error (mismatch_detail, idx,
1720 _("invalid register offset"));
1721 return 0;
1722 }
1723 }
1724 else
1725 {
1726 const aarch64_opnd_info *prev = &opnds[idx-1];
1727 unsigned num_bytes; /* total number of bytes transferred. */
1728 /* The opcode dependent area stores the number of elements in
1729 each structure to be loaded/stored. */
1730 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1731 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1732 /* Special handling of loading single structure to all lane. */
1733 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1734 * aarch64_get_qualifier_esize (prev->qualifier);
1735 else
1736 num_bytes = prev->reglist.num_regs
1737 * aarch64_get_qualifier_esize (prev->qualifier)
1738 * aarch64_get_qualifier_nelem (prev->qualifier);
1739 if ((int) num_bytes != opnd->addr.offset.imm)
1740 {
1741 set_other_error (mismatch_detail, idx,
1742 _("invalid post-increment amount"));
1743 return 0;
1744 }
1745 }
1746 break;
1747
1748 case AARCH64_OPND_ADDR_REGOFF:
1749 /* Get the size of the data element that is accessed, which may be
1750 different from that of the source register size,
1751 e.g. in strb/ldrb. */
1752 size = aarch64_get_qualifier_esize (opnd->qualifier);
1753 /* It is either no shift or shift by the binary logarithm of SIZE. */
1754 if (opnd->shifter.amount != 0
1755 && opnd->shifter.amount != (int)get_logsz (size))
1756 {
1757 set_other_error (mismatch_detail, idx,
1758 _("invalid shift amount"));
1759 return 0;
1760 }
1761 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1762 operators. */
1763 switch (opnd->shifter.kind)
1764 {
1765 case AARCH64_MOD_UXTW:
1766 case AARCH64_MOD_LSL:
1767 case AARCH64_MOD_SXTW:
1768 case AARCH64_MOD_SXTX: break;
1769 default:
1770 set_other_error (mismatch_detail, idx,
1771 _("invalid extend/shift operator"));
1772 return 0;
1773 }
1774 break;
1775
1776 case AARCH64_OPND_ADDR_UIMM12:
1777 imm = opnd->addr.offset.imm;
1778 /* Get the size of the data element that is accessed, which may be
1779 different from that of the source register size,
1780 e.g. in strb/ldrb. */
1781 size = aarch64_get_qualifier_esize (qualifier);
1782 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1783 {
1784 set_offset_out_of_range_error (mismatch_detail, idx,
1785 0, 4095 * size);
1786 return 0;
1787 }
1788 if (!value_aligned_p (opnd->addr.offset.imm, size))
1789 {
1790 set_unaligned_error (mismatch_detail, idx, size);
1791 return 0;
1792 }
1793 break;
1794
1795 case AARCH64_OPND_ADDR_PCREL14:
1796 case AARCH64_OPND_ADDR_PCREL19:
1797 case AARCH64_OPND_ADDR_PCREL21:
1798 case AARCH64_OPND_ADDR_PCREL26:
1799 imm = opnd->imm.value;
1800 if (operand_need_shift_by_two (get_operand_from_code (type)))
1801 {
1802 /* The offset value in a PC-relative branch instruction is alway
1803 4-byte aligned and is encoded without the lowest 2 bits. */
1804 if (!value_aligned_p (imm, 4))
1805 {
1806 set_unaligned_error (mismatch_detail, idx, 4);
1807 return 0;
1808 }
1809 /* Right shift by 2 so that we can carry out the following check
1810 canonically. */
1811 imm >>= 2;
1812 }
1813 size = get_operand_fields_width (get_operand_from_code (type));
1814 if (!value_fit_signed_field_p (imm, size))
1815 {
1816 set_other_error (mismatch_detail, idx,
1817 _("immediate out of range"));
1818 return 0;
1819 }
1820 break;
1821
1822 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1823 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1824 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1825 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1826 min_value = -8;
1827 max_value = 7;
1828 sve_imm_offset_vl:
1829 assert (!opnd->addr.offset.is_reg);
1830 assert (opnd->addr.preind);
1831 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1832 min_value *= num;
1833 max_value *= num;
1834 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1835 || (opnd->shifter.operator_present
1836 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1837 {
1838 set_other_error (mismatch_detail, idx,
1839 _("invalid addressing mode"));
1840 return 0;
1841 }
1842 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1843 {
1844 set_offset_out_of_range_error (mismatch_detail, idx,
1845 min_value, max_value);
1846 return 0;
1847 }
1848 if (!value_aligned_p (opnd->addr.offset.imm, num))
1849 {
1850 set_unaligned_error (mismatch_detail, idx, num);
1851 return 0;
1852 }
1853 break;
1854
1855 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1856 min_value = -32;
1857 max_value = 31;
1858 goto sve_imm_offset_vl;
1859
1860 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1861 min_value = -256;
1862 max_value = 255;
1863 goto sve_imm_offset_vl;
1864
1865 case AARCH64_OPND_SVE_ADDR_RI_U6:
1866 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1867 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1868 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1869 min_value = 0;
1870 max_value = 63;
1871 sve_imm_offset:
1872 assert (!opnd->addr.offset.is_reg);
1873 assert (opnd->addr.preind);
1874 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1875 min_value *= num;
1876 max_value *= num;
1877 if (opnd->shifter.operator_present
1878 || opnd->shifter.amount_present)
1879 {
1880 set_other_error (mismatch_detail, idx,
1881 _("invalid addressing mode"));
1882 return 0;
1883 }
1884 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1885 {
1886 set_offset_out_of_range_error (mismatch_detail, idx,
1887 min_value, max_value);
1888 return 0;
1889 }
1890 if (!value_aligned_p (opnd->addr.offset.imm, num))
1891 {
1892 set_unaligned_error (mismatch_detail, idx, num);
1893 return 0;
1894 }
1895 break;
1896
1897 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
1898 min_value = -8;
1899 max_value = 7;
1900 goto sve_imm_offset;
1901
1902 case AARCH64_OPND_SVE_ADDR_ZX:
1903 /* Everything is already ensured by parse_operands or
1904 aarch64_ext_sve_addr_rr_lsl (because this is a very specific
1905 argument type). */
1906 assert (opnd->addr.offset.is_reg);
1907 assert (opnd->addr.preind);
1908 assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0);
1909 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
1910 assert (opnd->shifter.operator_present == 0);
1911 break;
1912
1913 case AARCH64_OPND_SVE_ADDR_R:
1914 case AARCH64_OPND_SVE_ADDR_RR:
1915 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1916 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1917 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1918 case AARCH64_OPND_SVE_ADDR_RX:
1919 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1920 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1921 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1922 case AARCH64_OPND_SVE_ADDR_RZ:
1923 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1924 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1925 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1926 modifiers = 1 << AARCH64_MOD_LSL;
1927 sve_rr_operand:
1928 assert (opnd->addr.offset.is_reg);
1929 assert (opnd->addr.preind);
1930 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1931 && opnd->addr.offset.regno == 31)
1932 {
1933 set_other_error (mismatch_detail, idx,
1934 _("index register xzr is not allowed"));
1935 return 0;
1936 }
1937 if (((1 << opnd->shifter.kind) & modifiers) == 0
1938 || (opnd->shifter.amount
1939 != get_operand_specific_data (&aarch64_operands[type])))
1940 {
1941 set_other_error (mismatch_detail, idx,
1942 _("invalid addressing mode"));
1943 return 0;
1944 }
1945 break;
1946
1947 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1948 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1949 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1950 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1951 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1952 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1953 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1954 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1955 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1956 goto sve_rr_operand;
1957
1958 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1959 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1960 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1961 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1962 min_value = 0;
1963 max_value = 31;
1964 goto sve_imm_offset;
1965
1966 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1967 modifiers = 1 << AARCH64_MOD_LSL;
1968 sve_zz_operand:
1969 assert (opnd->addr.offset.is_reg);
1970 assert (opnd->addr.preind);
1971 if (((1 << opnd->shifter.kind) & modifiers) == 0
1972 || opnd->shifter.amount < 0
1973 || opnd->shifter.amount > 3)
1974 {
1975 set_other_error (mismatch_detail, idx,
1976 _("invalid addressing mode"));
1977 return 0;
1978 }
1979 break;
1980
1981 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1982 modifiers = (1 << AARCH64_MOD_SXTW);
1983 goto sve_zz_operand;
1984
1985 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1986 modifiers = 1 << AARCH64_MOD_UXTW;
1987 goto sve_zz_operand;
1988
1989 default:
1990 break;
1991 }
1992 break;
1993
1994 case AARCH64_OPND_CLASS_SIMD_REGLIST:
1995 if (type == AARCH64_OPND_LEt)
1996 {
1997 /* Get the upper bound for the element index. */
1998 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
1999 if (!value_in_range_p (opnd->reglist.index, 0, num))
2000 {
2001 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2002 return 0;
2003 }
2004 }
2005 /* The opcode dependent area stores the number of elements in
2006 each structure to be loaded/stored. */
2007 num = get_opcode_dependent_value (opcode);
2008 switch (type)
2009 {
2010 case AARCH64_OPND_LVt:
2011 assert (num >= 1 && num <= 4);
2012 /* Unless LD1/ST1, the number of registers should be equal to that
2013 of the structure elements. */
2014 if (num != 1 && opnd->reglist.num_regs != num)
2015 {
2016 set_reg_list_error (mismatch_detail, idx, num);
2017 return 0;
2018 }
2019 break;
2020 case AARCH64_OPND_LVt_AL:
2021 case AARCH64_OPND_LEt:
2022 assert (num >= 1 && num <= 4);
2023 /* The number of registers should be equal to that of the structure
2024 elements. */
2025 if (opnd->reglist.num_regs != num)
2026 {
2027 set_reg_list_error (mismatch_detail, idx, num);
2028 return 0;
2029 }
2030 break;
2031 default:
2032 break;
2033 }
2034 break;
2035
2036 case AARCH64_OPND_CLASS_IMMEDIATE:
2037 /* Constraint check on immediate operand. */
2038 imm = opnd->imm.value;
2039 /* E.g. imm_0_31 constrains value to be 0..31. */
2040 if (qualifier_value_in_range_constraint_p (qualifier)
2041 && !value_in_range_p (imm, get_lower_bound (qualifier),
2042 get_upper_bound (qualifier)))
2043 {
2044 set_imm_out_of_range_error (mismatch_detail, idx,
2045 get_lower_bound (qualifier),
2046 get_upper_bound (qualifier));
2047 return 0;
2048 }
2049
2050 switch (type)
2051 {
2052 case AARCH64_OPND_AIMM:
2053 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2054 {
2055 set_other_error (mismatch_detail, idx,
2056 _("invalid shift operator"));
2057 return 0;
2058 }
2059 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2060 {
2061 set_other_error (mismatch_detail, idx,
2062 _("shift amount must be 0 or 12"));
2063 return 0;
2064 }
2065 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2066 {
2067 set_other_error (mismatch_detail, idx,
2068 _("immediate out of range"));
2069 return 0;
2070 }
2071 break;
2072
2073 case AARCH64_OPND_HALF:
2074 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2075 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2076 {
2077 set_other_error (mismatch_detail, idx,
2078 _("invalid shift operator"));
2079 return 0;
2080 }
2081 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2082 if (!value_aligned_p (opnd->shifter.amount, 16))
2083 {
2084 set_other_error (mismatch_detail, idx,
2085 _("shift amount must be a multiple of 16"));
2086 return 0;
2087 }
2088 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2089 {
2090 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2091 0, size * 8 - 16);
2092 return 0;
2093 }
2094 if (opnd->imm.value < 0)
2095 {
2096 set_other_error (mismatch_detail, idx,
2097 _("negative immediate value not allowed"));
2098 return 0;
2099 }
2100 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2101 {
2102 set_other_error (mismatch_detail, idx,
2103 _("immediate out of range"));
2104 return 0;
2105 }
2106 break;
2107
2108 case AARCH64_OPND_IMM_MOV:
2109 {
2110 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2111 imm = opnd->imm.value;
2112 assert (idx == 1);
2113 switch (opcode->op)
2114 {
2115 case OP_MOV_IMM_WIDEN:
2116 imm = ~imm;
2117 /* Fall through. */
2118 case OP_MOV_IMM_WIDE:
2119 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
2120 {
2121 set_other_error (mismatch_detail, idx,
2122 _("immediate out of range"));
2123 return 0;
2124 }
2125 break;
2126 case OP_MOV_IMM_LOG:
2127 if (!aarch64_logical_immediate_p (imm, esize, NULL))
2128 {
2129 set_other_error (mismatch_detail, idx,
2130 _("immediate out of range"));
2131 return 0;
2132 }
2133 break;
2134 default:
2135 assert (0);
2136 return 0;
2137 }
2138 }
2139 break;
2140
2141 case AARCH64_OPND_NZCV:
2142 case AARCH64_OPND_CCMP_IMM:
2143 case AARCH64_OPND_EXCEPTION:
2144 case AARCH64_OPND_TME_UIMM16:
2145 case AARCH64_OPND_UIMM4:
2146 case AARCH64_OPND_UIMM4_ADDG:
2147 case AARCH64_OPND_UIMM7:
2148 case AARCH64_OPND_UIMM3_OP1:
2149 case AARCH64_OPND_UIMM3_OP2:
2150 case AARCH64_OPND_SVE_UIMM3:
2151 case AARCH64_OPND_SVE_UIMM7:
2152 case AARCH64_OPND_SVE_UIMM8:
2153 case AARCH64_OPND_SVE_UIMM8_53:
2154 size = get_operand_fields_width (get_operand_from_code (type));
2155 assert (size < 32);
2156 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2157 {
2158 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2159 (1 << size) - 1);
2160 return 0;
2161 }
2162 break;
2163
2164 case AARCH64_OPND_UIMM10:
2165 /* Scaled unsigned 10 bits immediate offset. */
2166 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2167 {
2168 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2169 return 0;
2170 }
2171
2172 if (!value_aligned_p (opnd->imm.value, 16))
2173 {
2174 set_unaligned_error (mismatch_detail, idx, 16);
2175 return 0;
2176 }
2177 break;
2178
2179 case AARCH64_OPND_SIMM5:
2180 case AARCH64_OPND_SVE_SIMM5:
2181 case AARCH64_OPND_SVE_SIMM5B:
2182 case AARCH64_OPND_SVE_SIMM6:
2183 case AARCH64_OPND_SVE_SIMM8:
2184 size = get_operand_fields_width (get_operand_from_code (type));
2185 assert (size < 32);
2186 if (!value_fit_signed_field_p (opnd->imm.value, size))
2187 {
2188 set_imm_out_of_range_error (mismatch_detail, idx,
2189 -(1 << (size - 1)),
2190 (1 << (size - 1)) - 1);
2191 return 0;
2192 }
2193 break;
2194
2195 case AARCH64_OPND_WIDTH:
2196 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
2197 && opnds[0].type == AARCH64_OPND_Rd);
2198 size = get_upper_bound (qualifier);
2199 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2200 /* lsb+width <= reg.size */
2201 {
2202 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2203 size - opnds[idx-1].imm.value);
2204 return 0;
2205 }
2206 break;
2207
2208 case AARCH64_OPND_LIMM:
2209 case AARCH64_OPND_SVE_LIMM:
2210 {
2211 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2212 uint64_t uimm = opnd->imm.value;
2213 if (opcode->op == OP_BIC)
2214 uimm = ~uimm;
2215 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2216 {
2217 set_other_error (mismatch_detail, idx,
2218 _("immediate out of range"));
2219 return 0;
2220 }
2221 }
2222 break;
2223
2224 case AARCH64_OPND_IMM0:
2225 case AARCH64_OPND_FPIMM0:
2226 if (opnd->imm.value != 0)
2227 {
2228 set_other_error (mismatch_detail, idx,
2229 _("immediate zero expected"));
2230 return 0;
2231 }
2232 break;
2233
2234 case AARCH64_OPND_IMM_ROT1:
2235 case AARCH64_OPND_IMM_ROT2:
2236 case AARCH64_OPND_SVE_IMM_ROT2:
2237 if (opnd->imm.value != 0
2238 && opnd->imm.value != 90
2239 && opnd->imm.value != 180
2240 && opnd->imm.value != 270)
2241 {
2242 set_other_error (mismatch_detail, idx,
2243 _("rotate expected to be 0, 90, 180 or 270"));
2244 return 0;
2245 }
2246 break;
2247
2248 case AARCH64_OPND_IMM_ROT3:
2249 case AARCH64_OPND_SVE_IMM_ROT1:
2250 case AARCH64_OPND_SVE_IMM_ROT3:
2251 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2252 {
2253 set_other_error (mismatch_detail, idx,
2254 _("rotate expected to be 90 or 270"));
2255 return 0;
2256 }
2257 break;
2258
2259 case AARCH64_OPND_SHLL_IMM:
2260 assert (idx == 2);
2261 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2262 if (opnd->imm.value != size)
2263 {
2264 set_other_error (mismatch_detail, idx,
2265 _("invalid shift amount"));
2266 return 0;
2267 }
2268 break;
2269
2270 case AARCH64_OPND_IMM_VLSL:
2271 size = aarch64_get_qualifier_esize (qualifier);
2272 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2273 {
2274 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2275 size * 8 - 1);
2276 return 0;
2277 }
2278 break;
2279
2280 case AARCH64_OPND_IMM_VLSR:
2281 size = aarch64_get_qualifier_esize (qualifier);
2282 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2283 {
2284 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2285 return 0;
2286 }
2287 break;
2288
2289 case AARCH64_OPND_SIMD_IMM:
2290 case AARCH64_OPND_SIMD_IMM_SFT:
2291 /* Qualifier check. */
2292 switch (qualifier)
2293 {
2294 case AARCH64_OPND_QLF_LSL:
2295 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2296 {
2297 set_other_error (mismatch_detail, idx,
2298 _("invalid shift operator"));
2299 return 0;
2300 }
2301 break;
2302 case AARCH64_OPND_QLF_MSL:
2303 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2304 {
2305 set_other_error (mismatch_detail, idx,
2306 _("invalid shift operator"));
2307 return 0;
2308 }
2309 break;
2310 case AARCH64_OPND_QLF_NIL:
2311 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2312 {
2313 set_other_error (mismatch_detail, idx,
2314 _("shift is not permitted"));
2315 return 0;
2316 }
2317 break;
2318 default:
2319 assert (0);
2320 return 0;
2321 }
2322 /* Is the immediate valid? */
2323 assert (idx == 1);
2324 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2325 {
2326 /* uimm8 or simm8 */
2327 if (!value_in_range_p (opnd->imm.value, -128, 255))
2328 {
2329 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
2330 return 0;
2331 }
2332 }
2333 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2334 {
2335 /* uimm64 is not
2336 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2337 ffffffffgggggggghhhhhhhh'. */
2338 set_other_error (mismatch_detail, idx,
2339 _("invalid value for immediate"));
2340 return 0;
2341 }
2342 /* Is the shift amount valid? */
2343 switch (opnd->shifter.kind)
2344 {
2345 case AARCH64_MOD_LSL:
2346 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2347 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
2348 {
2349 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2350 (size - 1) * 8);
2351 return 0;
2352 }
2353 if (!value_aligned_p (opnd->shifter.amount, 8))
2354 {
2355 set_unaligned_error (mismatch_detail, idx, 8);
2356 return 0;
2357 }
2358 break;
2359 case AARCH64_MOD_MSL:
2360 /* Only 8 and 16 are valid shift amount. */
2361 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2362 {
2363 set_other_error (mismatch_detail, idx,
2364 _("shift amount must be 0 or 16"));
2365 return 0;
2366 }
2367 break;
2368 default:
2369 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2370 {
2371 set_other_error (mismatch_detail, idx,
2372 _("invalid shift operator"));
2373 return 0;
2374 }
2375 break;
2376 }
2377 break;
2378
2379 case AARCH64_OPND_FPIMM:
2380 case AARCH64_OPND_SIMD_FPIMM:
2381 case AARCH64_OPND_SVE_FPIMM8:
2382 if (opnd->imm.is_fp == 0)
2383 {
2384 set_other_error (mismatch_detail, idx,
2385 _("floating-point immediate expected"));
2386 return 0;
2387 }
2388 /* The value is expected to be an 8-bit floating-point constant with
2389 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2390 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2391 instruction). */
2392 if (!value_in_range_p (opnd->imm.value, 0, 255))
2393 {
2394 set_other_error (mismatch_detail, idx,
2395 _("immediate out of range"));
2396 return 0;
2397 }
2398 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2399 {
2400 set_other_error (mismatch_detail, idx,
2401 _("invalid shift operator"));
2402 return 0;
2403 }
2404 break;
2405
2406 case AARCH64_OPND_SVE_AIMM:
2407 min_value = 0;
2408 sve_aimm:
2409 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2410 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2411 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2412 uvalue = opnd->imm.value;
2413 shift = opnd->shifter.amount;
2414 if (size == 1)
2415 {
2416 if (shift != 0)
2417 {
2418 set_other_error (mismatch_detail, idx,
2419 _("no shift amount allowed for"
2420 " 8-bit constants"));
2421 return 0;
2422 }
2423 }
2424 else
2425 {
2426 if (shift != 0 && shift != 8)
2427 {
2428 set_other_error (mismatch_detail, idx,
2429 _("shift amount must be 0 or 8"));
2430 return 0;
2431 }
2432 if (shift == 0 && (uvalue & 0xff) == 0)
2433 {
2434 shift = 8;
2435 uvalue = (int64_t) uvalue / 256;
2436 }
2437 }
2438 mask >>= shift;
2439 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2440 {
2441 set_other_error (mismatch_detail, idx,
2442 _("immediate too big for element size"));
2443 return 0;
2444 }
2445 uvalue = (uvalue - min_value) & mask;
2446 if (uvalue > 0xff)
2447 {
2448 set_other_error (mismatch_detail, idx,
2449 _("invalid arithmetic immediate"));
2450 return 0;
2451 }
2452 break;
2453
2454 case AARCH64_OPND_SVE_ASIMM:
2455 min_value = -128;
2456 goto sve_aimm;
2457
2458 case AARCH64_OPND_SVE_I1_HALF_ONE:
2459 assert (opnd->imm.is_fp);
2460 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2461 {
2462 set_other_error (mismatch_detail, idx,
2463 _("floating-point value must be 0.5 or 1.0"));
2464 return 0;
2465 }
2466 break;
2467
2468 case AARCH64_OPND_SVE_I1_HALF_TWO:
2469 assert (opnd->imm.is_fp);
2470 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2471 {
2472 set_other_error (mismatch_detail, idx,
2473 _("floating-point value must be 0.5 or 2.0"));
2474 return 0;
2475 }
2476 break;
2477
2478 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2479 assert (opnd->imm.is_fp);
2480 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2481 {
2482 set_other_error (mismatch_detail, idx,
2483 _("floating-point value must be 0.0 or 1.0"));
2484 return 0;
2485 }
2486 break;
2487
2488 case AARCH64_OPND_SVE_INV_LIMM:
2489 {
2490 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2491 uint64_t uimm = ~opnd->imm.value;
2492 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2493 {
2494 set_other_error (mismatch_detail, idx,
2495 _("immediate out of range"));
2496 return 0;
2497 }
2498 }
2499 break;
2500
2501 case AARCH64_OPND_SVE_LIMM_MOV:
2502 {
2503 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2504 uint64_t uimm = opnd->imm.value;
2505 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2506 {
2507 set_other_error (mismatch_detail, idx,
2508 _("immediate out of range"));
2509 return 0;
2510 }
2511 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2512 {
2513 set_other_error (mismatch_detail, idx,
2514 _("invalid replicated MOV immediate"));
2515 return 0;
2516 }
2517 }
2518 break;
2519
2520 case AARCH64_OPND_SVE_PATTERN_SCALED:
2521 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2522 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2523 {
2524 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2525 return 0;
2526 }
2527 break;
2528
2529 case AARCH64_OPND_SVE_SHLIMM_PRED:
2530 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
2531 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2532 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2533 {
2534 set_imm_out_of_range_error (mismatch_detail, idx,
2535 0, 8 * size - 1);
2536 return 0;
2537 }
2538 break;
2539
2540 case AARCH64_OPND_SVE_SHRIMM_PRED:
2541 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
2542 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2543 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2544 {
2545 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
2546 return 0;
2547 }
2548 break;
2549
2550 default:
2551 break;
2552 }
2553 break;
2554
2555 case AARCH64_OPND_CLASS_SYSTEM:
2556 switch (type)
2557 {
2558 case AARCH64_OPND_PSTATEFIELD:
2559 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
2560 /* MSR UAO, #uimm4
2561 MSR PAN, #uimm4
2562 MSR SSBS,#uimm4
2563 The immediate must be #0 or #1. */
2564 if ((opnd->pstatefield == 0x03 /* UAO. */
2565 || opnd->pstatefield == 0x04 /* PAN. */
2566 || opnd->pstatefield == 0x19 /* SSBS. */
2567 || opnd->pstatefield == 0x1a) /* DIT. */
2568 && opnds[1].imm.value > 1)
2569 {
2570 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2571 return 0;
2572 }
2573 /* MSR SPSel, #uimm4
2574 Uses uimm4 as a control value to select the stack pointer: if
2575 bit 0 is set it selects the current exception level's stack
2576 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2577 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2578 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2579 {
2580 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2581 return 0;
2582 }
2583 break;
2584 default:
2585 break;
2586 }
2587 break;
2588
2589 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2590 /* Get the upper bound for the element index. */
2591 if (opcode->op == OP_FCMLA_ELEM)
2592 /* FCMLA index range depends on the vector size of other operands
2593 and is halfed because complex numbers take two elements. */
2594 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2595 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2596 else
2597 num = 16;
2598 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
2599 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
2600
2601 /* Index out-of-range. */
2602 if (!value_in_range_p (opnd->reglane.index, 0, num))
2603 {
2604 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2605 return 0;
2606 }
2607 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2608 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2609 number is encoded in "size:M:Rm":
2610 size <Vm>
2611 00 RESERVED
2612 01 0:Rm
2613 10 M:Rm
2614 11 RESERVED */
2615 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
2616 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2617 {
2618 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2619 return 0;
2620 }
2621 break;
2622
2623 case AARCH64_OPND_CLASS_MODIFIED_REG:
2624 assert (idx == 1 || idx == 2);
2625 switch (type)
2626 {
2627 case AARCH64_OPND_Rm_EXT:
2628 if (!aarch64_extend_operator_p (opnd->shifter.kind)
2629 && opnd->shifter.kind != AARCH64_MOD_LSL)
2630 {
2631 set_other_error (mismatch_detail, idx,
2632 _("extend operator expected"));
2633 return 0;
2634 }
2635 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2636 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2637 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2638 case. */
2639 if (!aarch64_stack_pointer_p (opnds + 0)
2640 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2641 {
2642 if (!opnd->shifter.operator_present)
2643 {
2644 set_other_error (mismatch_detail, idx,
2645 _("missing extend operator"));
2646 return 0;
2647 }
2648 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2649 {
2650 set_other_error (mismatch_detail, idx,
2651 _("'LSL' operator not allowed"));
2652 return 0;
2653 }
2654 }
2655 assert (opnd->shifter.operator_present /* Default to LSL. */
2656 || opnd->shifter.kind == AARCH64_MOD_LSL);
2657 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2658 {
2659 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2660 return 0;
2661 }
2662 /* In the 64-bit form, the final register operand is written as Wm
2663 for all but the (possibly omitted) UXTX/LSL and SXTX
2664 operators.
2665 N.B. GAS allows X register to be used with any operator as a
2666 programming convenience. */
2667 if (qualifier == AARCH64_OPND_QLF_X
2668 && opnd->shifter.kind != AARCH64_MOD_LSL
2669 && opnd->shifter.kind != AARCH64_MOD_UXTX
2670 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2671 {
2672 set_other_error (mismatch_detail, idx, _("W register expected"));
2673 return 0;
2674 }
2675 break;
2676
2677 case AARCH64_OPND_Rm_SFT:
2678 /* ROR is not available to the shifted register operand in
2679 arithmetic instructions. */
2680 if (!aarch64_shift_operator_p (opnd->shifter.kind))
2681 {
2682 set_other_error (mismatch_detail, idx,
2683 _("shift operator expected"));
2684 return 0;
2685 }
2686 if (opnd->shifter.kind == AARCH64_MOD_ROR
2687 && opcode->iclass != log_shift)
2688 {
2689 set_other_error (mismatch_detail, idx,
2690 _("'ROR' operator not allowed"));
2691 return 0;
2692 }
2693 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2694 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2695 {
2696 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2697 return 0;
2698 }
2699 break;
2700
2701 default:
2702 break;
2703 }
2704 break;
2705
2706 default:
2707 break;
2708 }
2709
2710 return 1;
2711 }
2712
2713 /* Main entrypoint for the operand constraint checking.
2714
2715 Return 1 if operands of *INST meet the constraint applied by the operand
2716 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2717 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2718 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2719 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2720 error kind when it is notified that an instruction does not pass the check).
2721
2722 Un-determined operand qualifiers may get established during the process. */
2723
2724 int
2725 aarch64_match_operands_constraint (aarch64_inst *inst,
2726 aarch64_operand_error *mismatch_detail)
2727 {
2728 int i;
2729
2730 DEBUG_TRACE ("enter");
2731
2732 /* Check for cases where a source register needs to be the same as the
2733 destination register. Do this before matching qualifiers since if
2734 an instruction has both invalid tying and invalid qualifiers,
2735 the error about qualifiers would suggest several alternative
2736 instructions that also have invalid tying. */
2737 i = inst->opcode->tied_operand;
2738 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2739 {
2740 if (mismatch_detail)
2741 {
2742 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2743 mismatch_detail->index = i;
2744 mismatch_detail->error = NULL;
2745 }
2746 return 0;
2747 }
2748
2749 /* Match operands' qualifier.
2750 *INST has already had qualifier establish for some, if not all, of
2751 its operands; we need to find out whether these established
2752 qualifiers match one of the qualifier sequence in
2753 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2754 with the corresponding qualifier in such a sequence.
2755 Only basic operand constraint checking is done here; the more thorough
2756 constraint checking will carried out by operand_general_constraint_met_p,
2757 which has be to called after this in order to get all of the operands'
2758 qualifiers established. */
2759 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2760 {
2761 DEBUG_TRACE ("FAIL on operand qualifier matching");
2762 if (mismatch_detail)
2763 {
2764 /* Return an error type to indicate that it is the qualifier
2765 matching failure; we don't care about which operand as there
2766 are enough information in the opcode table to reproduce it. */
2767 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2768 mismatch_detail->index = -1;
2769 mismatch_detail->error = NULL;
2770 }
2771 return 0;
2772 }
2773
2774 /* Match operands' constraint. */
2775 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2776 {
2777 enum aarch64_opnd type = inst->opcode->operands[i];
2778 if (type == AARCH64_OPND_NIL)
2779 break;
2780 if (inst->operands[i].skip)
2781 {
2782 DEBUG_TRACE ("skip the incomplete operand %d", i);
2783 continue;
2784 }
2785 if (operand_general_constraint_met_p (inst->operands, i, type,
2786 inst->opcode, mismatch_detail) == 0)
2787 {
2788 DEBUG_TRACE ("FAIL on operand %d", i);
2789 return 0;
2790 }
2791 }
2792
2793 DEBUG_TRACE ("PASS");
2794
2795 return 1;
2796 }
2797
2798 /* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2799 Also updates the TYPE of each INST->OPERANDS with the corresponding
2800 value of OPCODE->OPERANDS.
2801
2802 Note that some operand qualifiers may need to be manually cleared by
2803 the caller before it further calls the aarch64_opcode_encode; by
2804 doing this, it helps the qualifier matching facilities work
2805 properly. */
2806
2807 const aarch64_opcode*
2808 aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2809 {
2810 int i;
2811 const aarch64_opcode *old = inst->opcode;
2812
2813 inst->opcode = opcode;
2814
2815 /* Update the operand types. */
2816 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2817 {
2818 inst->operands[i].type = opcode->operands[i];
2819 if (opcode->operands[i] == AARCH64_OPND_NIL)
2820 break;
2821 }
2822
2823 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2824
2825 return old;
2826 }
2827
2828 int
2829 aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2830 {
2831 int i;
2832 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2833 if (operands[i] == operand)
2834 return i;
2835 else if (operands[i] == AARCH64_OPND_NIL)
2836 break;
2837 return -1;
2838 }
2839 \f
2840 /* R0...R30, followed by FOR31. */
2841 #define BANK(R, FOR31) \
2842 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2843 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2844 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2845 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
2846 /* [0][0] 32-bit integer regs with sp Wn
2847 [0][1] 64-bit integer regs with sp Xn sf=1
2848 [1][0] 32-bit integer regs with #0 Wn
2849 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2850 static const char *int_reg[2][2][32] = {
2851 #define R32(X) "w" #X
2852 #define R64(X) "x" #X
2853 { BANK (R32, "wsp"), BANK (R64, "sp") },
2854 { BANK (R32, "wzr"), BANK (R64, "xzr") }
2855 #undef R64
2856 #undef R32
2857 };
2858
2859 /* Names of the SVE vector registers, first with .S suffixes,
2860 then with .D suffixes. */
2861
2862 static const char *sve_reg[2][32] = {
2863 #define ZS(X) "z" #X ".s"
2864 #define ZD(X) "z" #X ".d"
2865 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2866 #undef ZD
2867 #undef ZS
2868 };
2869 #undef BANK
2870
2871 /* Return the integer register name.
2872 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2873
2874 static inline const char *
2875 get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2876 {
2877 const int has_zr = sp_reg_p ? 0 : 1;
2878 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2879 return int_reg[has_zr][is_64][regno];
2880 }
2881
2882 /* Like get_int_reg_name, but IS_64 is always 1. */
2883
2884 static inline const char *
2885 get_64bit_int_reg_name (int regno, int sp_reg_p)
2886 {
2887 const int has_zr = sp_reg_p ? 0 : 1;
2888 return int_reg[has_zr][1][regno];
2889 }
2890
2891 /* Get the name of the integer offset register in OPND, using the shift type
2892 to decide whether it's a word or doubleword. */
2893
2894 static inline const char *
2895 get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2896 {
2897 switch (opnd->shifter.kind)
2898 {
2899 case AARCH64_MOD_UXTW:
2900 case AARCH64_MOD_SXTW:
2901 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2902
2903 case AARCH64_MOD_LSL:
2904 case AARCH64_MOD_SXTX:
2905 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2906
2907 default:
2908 abort ();
2909 }
2910 }
2911
2912 /* Get the name of the SVE vector offset register in OPND, using the operand
2913 qualifier to decide whether the suffix should be .S or .D. */
2914
2915 static inline const char *
2916 get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2917 {
2918 assert (qualifier == AARCH64_OPND_QLF_S_S
2919 || qualifier == AARCH64_OPND_QLF_S_D);
2920 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2921 }
2922
2923 /* Types for expanding an encoded 8-bit value to a floating-point value. */
2924
2925 typedef union
2926 {
2927 uint64_t i;
2928 double d;
2929 } double_conv_t;
2930
2931 typedef union
2932 {
2933 uint32_t i;
2934 float f;
2935 } single_conv_t;
2936
2937 typedef union
2938 {
2939 uint32_t i;
2940 float f;
2941 } half_conv_t;
2942
2943 /* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2944 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2945 (depending on the type of the instruction). IMM8 will be expanded to a
2946 single-precision floating-point value (SIZE == 4) or a double-precision
2947 floating-point value (SIZE == 8). A half-precision floating-point value
2948 (SIZE == 2) is expanded to a single-precision floating-point value. The
2949 expanded value is returned. */
2950
2951 static uint64_t
2952 expand_fp_imm (int size, uint32_t imm8)
2953 {
2954 uint64_t imm = 0;
2955 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2956
2957 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2958 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2959 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2960 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2961 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
2962 if (size == 8)
2963 {
2964 imm = (imm8_7 << (63-32)) /* imm8<7> */
2965 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2966 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2967 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2968 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2969 imm <<= 32;
2970 }
2971 else if (size == 4 || size == 2)
2972 {
2973 imm = (imm8_7 << 31) /* imm8<7> */
2974 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2975 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2976 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2977 }
2978 else
2979 {
2980 /* An unsupported size. */
2981 assert (0);
2982 }
2983
2984 return imm;
2985 }
2986
2987 /* Produce the string representation of the register list operand *OPND
2988 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2989 the register name that comes before the register number, such as "v". */
2990 static void
2991 print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
2992 const char *prefix)
2993 {
2994 const int num_regs = opnd->reglist.num_regs;
2995 const int first_reg = opnd->reglist.first_regno;
2996 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
2997 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
2998 char tb[8]; /* Temporary buffer. */
2999
3000 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
3001 assert (num_regs >= 1 && num_regs <= 4);
3002
3003 /* Prepare the index if any. */
3004 if (opnd->reglist.has_index)
3005 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3006 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
3007 else
3008 tb[0] = '\0';
3009
3010 /* The hyphenated form is preferred for disassembly if there are
3011 more than two registers in the list, and the register numbers
3012 are monotonically increasing in increments of one. */
3013 if (num_regs > 2 && last_reg > first_reg)
3014 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
3015 prefix, last_reg, qlf_name, tb);
3016 else
3017 {
3018 const int reg0 = first_reg;
3019 const int reg1 = (first_reg + 1) & 0x1f;
3020 const int reg2 = (first_reg + 2) & 0x1f;
3021 const int reg3 = (first_reg + 3) & 0x1f;
3022
3023 switch (num_regs)
3024 {
3025 case 1:
3026 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
3027 break;
3028 case 2:
3029 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
3030 prefix, reg1, qlf_name, tb);
3031 break;
3032 case 3:
3033 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3034 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3035 prefix, reg2, qlf_name, tb);
3036 break;
3037 case 4:
3038 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3039 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3040 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
3041 break;
3042 }
3043 }
3044 }
3045
3046 /* Print the register+immediate address in OPND to BUF, which has SIZE
3047 characters. BASE is the name of the base register. */
3048
3049 static void
3050 print_immediate_offset_address (char *buf, size_t size,
3051 const aarch64_opnd_info *opnd,
3052 const char *base)
3053 {
3054 if (opnd->addr.writeback)
3055 {
3056 if (opnd->addr.preind)
3057 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
3058 else
3059 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
3060 }
3061 else
3062 {
3063 if (opnd->shifter.operator_present)
3064 {
3065 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
3066 snprintf (buf, size, "[%s, #%d, mul vl]",
3067 base, opnd->addr.offset.imm);
3068 }
3069 else if (opnd->addr.offset.imm)
3070 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
3071 else
3072 snprintf (buf, size, "[%s]", base);
3073 }
3074 }
3075
3076 /* Produce the string representation of the register offset address operand
3077 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3078 the names of the base and offset registers. */
3079 static void
3080 print_register_offset_address (char *buf, size_t size,
3081 const aarch64_opnd_info *opnd,
3082 const char *base, const char *offset)
3083 {
3084 char tb[16]; /* Temporary buffer. */
3085 bfd_boolean print_extend_p = TRUE;
3086 bfd_boolean print_amount_p = TRUE;
3087 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3088
3089 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3090 || !opnd->shifter.amount_present))
3091 {
3092 /* Not print the shift/extend amount when the amount is zero and
3093 when it is not the special case of 8-bit load/store instruction. */
3094 print_amount_p = FALSE;
3095 /* Likewise, no need to print the shift operator LSL in such a
3096 situation. */
3097 if (opnd->shifter.kind == AARCH64_MOD_LSL)
3098 print_extend_p = FALSE;
3099 }
3100
3101 /* Prepare for the extend/shift. */
3102 if (print_extend_p)
3103 {
3104 if (print_amount_p)
3105 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
3106 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3107 (opnd->shifter.amount % 100));
3108 else
3109 snprintf (tb, sizeof (tb), ", %s", shift_name);
3110 }
3111 else
3112 tb[0] = '\0';
3113
3114 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
3115 }
3116
3117 /* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3118 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3119 PC, PCREL_P and ADDRESS are used to pass in and return information about
3120 the PC-relative address calculation, where the PC value is passed in
3121 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3122 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3123 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3124
3125 The function serves both the disassembler and the assembler diagnostics
3126 issuer, which is the reason why it lives in this file. */
3127
3128 void
3129 aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3130 const aarch64_opcode *opcode,
3131 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
3132 bfd_vma *address, char** notes)
3133 {
3134 unsigned int i, num_conds;
3135 const char *name = NULL;
3136 const aarch64_opnd_info *opnd = opnds + idx;
3137 enum aarch64_modifier_kind kind;
3138 uint64_t addr, enum_value;
3139
3140 buf[0] = '\0';
3141 if (pcrel_p)
3142 *pcrel_p = 0;
3143
3144 switch (opnd->type)
3145 {
3146 case AARCH64_OPND_Rd:
3147 case AARCH64_OPND_Rn:
3148 case AARCH64_OPND_Rm:
3149 case AARCH64_OPND_Rt:
3150 case AARCH64_OPND_Rt2:
3151 case AARCH64_OPND_Rs:
3152 case AARCH64_OPND_Ra:
3153 case AARCH64_OPND_Rt_SYS:
3154 case AARCH64_OPND_PAIRREG:
3155 case AARCH64_OPND_SVE_Rm:
3156 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
3157 the <ic_op>, therefore we use opnd->present to override the
3158 generic optional-ness information. */
3159 if (opnd->type == AARCH64_OPND_Rt_SYS)
3160 {
3161 if (!opnd->present)
3162 break;
3163 }
3164 /* Omit the operand, e.g. RET. */
3165 else if (optional_operand_p (opcode, idx)
3166 && (opnd->reg.regno
3167 == get_optional_operand_default_value (opcode)))
3168 break;
3169 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3170 || opnd->qualifier == AARCH64_OPND_QLF_X);
3171 snprintf (buf, size, "%s",
3172 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3173 break;
3174
3175 case AARCH64_OPND_Rd_SP:
3176 case AARCH64_OPND_Rn_SP:
3177 case AARCH64_OPND_Rt_SP:
3178 case AARCH64_OPND_SVE_Rn_SP:
3179 case AARCH64_OPND_Rm_SP:
3180 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3181 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3182 || opnd->qualifier == AARCH64_OPND_QLF_X
3183 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3184 snprintf (buf, size, "%s",
3185 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3186 break;
3187
3188 case AARCH64_OPND_Rm_EXT:
3189 kind = opnd->shifter.kind;
3190 assert (idx == 1 || idx == 2);
3191 if ((aarch64_stack_pointer_p (opnds)
3192 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3193 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3194 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3195 && kind == AARCH64_MOD_UXTW)
3196 || (opnd->qualifier == AARCH64_OPND_QLF_X
3197 && kind == AARCH64_MOD_UXTX)))
3198 {
3199 /* 'LSL' is the preferred form in this case. */
3200 kind = AARCH64_MOD_LSL;
3201 if (opnd->shifter.amount == 0)
3202 {
3203 /* Shifter omitted. */
3204 snprintf (buf, size, "%s",
3205 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3206 break;
3207 }
3208 }
3209 if (opnd->shifter.amount)
3210 snprintf (buf, size, "%s, %s #%" PRIi64,
3211 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3212 aarch64_operand_modifiers[kind].name,
3213 opnd->shifter.amount);
3214 else
3215 snprintf (buf, size, "%s, %s",
3216 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3217 aarch64_operand_modifiers[kind].name);
3218 break;
3219
3220 case AARCH64_OPND_Rm_SFT:
3221 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3222 || opnd->qualifier == AARCH64_OPND_QLF_X);
3223 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3224 snprintf (buf, size, "%s",
3225 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3226 else
3227 snprintf (buf, size, "%s, %s #%" PRIi64,
3228 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3229 aarch64_operand_modifiers[opnd->shifter.kind].name,
3230 opnd->shifter.amount);
3231 break;
3232
3233 case AARCH64_OPND_Fd:
3234 case AARCH64_OPND_Fn:
3235 case AARCH64_OPND_Fm:
3236 case AARCH64_OPND_Fa:
3237 case AARCH64_OPND_Ft:
3238 case AARCH64_OPND_Ft2:
3239 case AARCH64_OPND_Sd:
3240 case AARCH64_OPND_Sn:
3241 case AARCH64_OPND_Sm:
3242 case AARCH64_OPND_SVE_VZn:
3243 case AARCH64_OPND_SVE_Vd:
3244 case AARCH64_OPND_SVE_Vm:
3245 case AARCH64_OPND_SVE_Vn:
3246 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3247 opnd->reg.regno);
3248 break;
3249
3250 case AARCH64_OPND_Va:
3251 case AARCH64_OPND_Vd:
3252 case AARCH64_OPND_Vn:
3253 case AARCH64_OPND_Vm:
3254 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3255 aarch64_get_qualifier_name (opnd->qualifier));
3256 break;
3257
3258 case AARCH64_OPND_Ed:
3259 case AARCH64_OPND_En:
3260 case AARCH64_OPND_Em:
3261 case AARCH64_OPND_Em16:
3262 case AARCH64_OPND_SM3_IMM2:
3263 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3264 aarch64_get_qualifier_name (opnd->qualifier),
3265 opnd->reglane.index);
3266 break;
3267
3268 case AARCH64_OPND_VdD1:
3269 case AARCH64_OPND_VnD1:
3270 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3271 break;
3272
3273 case AARCH64_OPND_LVn:
3274 case AARCH64_OPND_LVt:
3275 case AARCH64_OPND_LVt_AL:
3276 case AARCH64_OPND_LEt:
3277 print_register_list (buf, size, opnd, "v");
3278 break;
3279
3280 case AARCH64_OPND_SVE_Pd:
3281 case AARCH64_OPND_SVE_Pg3:
3282 case AARCH64_OPND_SVE_Pg4_5:
3283 case AARCH64_OPND_SVE_Pg4_10:
3284 case AARCH64_OPND_SVE_Pg4_16:
3285 case AARCH64_OPND_SVE_Pm:
3286 case AARCH64_OPND_SVE_Pn:
3287 case AARCH64_OPND_SVE_Pt:
3288 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3289 snprintf (buf, size, "p%d", opnd->reg.regno);
3290 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3291 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3292 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3293 aarch64_get_qualifier_name (opnd->qualifier));
3294 else
3295 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3296 aarch64_get_qualifier_name (opnd->qualifier));
3297 break;
3298
3299 case AARCH64_OPND_SVE_Za_5:
3300 case AARCH64_OPND_SVE_Za_16:
3301 case AARCH64_OPND_SVE_Zd:
3302 case AARCH64_OPND_SVE_Zm_5:
3303 case AARCH64_OPND_SVE_Zm_16:
3304 case AARCH64_OPND_SVE_Zn:
3305 case AARCH64_OPND_SVE_Zt:
3306 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3307 snprintf (buf, size, "z%d", opnd->reg.regno);
3308 else
3309 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3310 aarch64_get_qualifier_name (opnd->qualifier));
3311 break;
3312
3313 case AARCH64_OPND_SVE_ZnxN:
3314 case AARCH64_OPND_SVE_ZtxN:
3315 print_register_list (buf, size, opnd, "z");
3316 break;
3317
3318 case AARCH64_OPND_SVE_Zm3_INDEX:
3319 case AARCH64_OPND_SVE_Zm3_22_INDEX:
3320 case AARCH64_OPND_SVE_Zm3_11_INDEX:
3321 case AARCH64_OPND_SVE_Zm4_INDEX:
3322 case AARCH64_OPND_SVE_Zn_INDEX:
3323 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3324 aarch64_get_qualifier_name (opnd->qualifier),
3325 opnd->reglane.index);
3326 break;
3327
3328 case AARCH64_OPND_CRn:
3329 case AARCH64_OPND_CRm:
3330 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
3331 break;
3332
3333 case AARCH64_OPND_IDX:
3334 case AARCH64_OPND_MASK:
3335 case AARCH64_OPND_IMM:
3336 case AARCH64_OPND_IMM_2:
3337 case AARCH64_OPND_WIDTH:
3338 case AARCH64_OPND_UIMM3_OP1:
3339 case AARCH64_OPND_UIMM3_OP2:
3340 case AARCH64_OPND_BIT_NUM:
3341 case AARCH64_OPND_IMM_VLSL:
3342 case AARCH64_OPND_IMM_VLSR:
3343 case AARCH64_OPND_SHLL_IMM:
3344 case AARCH64_OPND_IMM0:
3345 case AARCH64_OPND_IMMR:
3346 case AARCH64_OPND_IMMS:
3347 case AARCH64_OPND_FBITS:
3348 case AARCH64_OPND_TME_UIMM16:
3349 case AARCH64_OPND_SIMM5:
3350 case AARCH64_OPND_SVE_SHLIMM_PRED:
3351 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
3352 case AARCH64_OPND_SVE_SHRIMM_PRED:
3353 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3354 case AARCH64_OPND_SVE_SIMM5:
3355 case AARCH64_OPND_SVE_SIMM5B:
3356 case AARCH64_OPND_SVE_SIMM6:
3357 case AARCH64_OPND_SVE_SIMM8:
3358 case AARCH64_OPND_SVE_UIMM3:
3359 case AARCH64_OPND_SVE_UIMM7:
3360 case AARCH64_OPND_SVE_UIMM8:
3361 case AARCH64_OPND_SVE_UIMM8_53:
3362 case AARCH64_OPND_IMM_ROT1:
3363 case AARCH64_OPND_IMM_ROT2:
3364 case AARCH64_OPND_IMM_ROT3:
3365 case AARCH64_OPND_SVE_IMM_ROT1:
3366 case AARCH64_OPND_SVE_IMM_ROT2:
3367 case AARCH64_OPND_SVE_IMM_ROT3:
3368 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3369 break;
3370
3371 case AARCH64_OPND_SVE_I1_HALF_ONE:
3372 case AARCH64_OPND_SVE_I1_HALF_TWO:
3373 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3374 {
3375 single_conv_t c;
3376 c.i = opnd->imm.value;
3377 snprintf (buf, size, "#%.1f", c.f);
3378 break;
3379 }
3380
3381 case AARCH64_OPND_SVE_PATTERN:
3382 if (optional_operand_p (opcode, idx)
3383 && opnd->imm.value == get_optional_operand_default_value (opcode))
3384 break;
3385 enum_value = opnd->imm.value;
3386 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3387 if (aarch64_sve_pattern_array[enum_value])
3388 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3389 else
3390 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3391 break;
3392
3393 case AARCH64_OPND_SVE_PATTERN_SCALED:
3394 if (optional_operand_p (opcode, idx)
3395 && !opnd->shifter.operator_present
3396 && opnd->imm.value == get_optional_operand_default_value (opcode))
3397 break;
3398 enum_value = opnd->imm.value;
3399 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3400 if (aarch64_sve_pattern_array[opnd->imm.value])
3401 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3402 else
3403 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3404 if (opnd->shifter.operator_present)
3405 {
3406 size_t len = strlen (buf);
3407 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3408 aarch64_operand_modifiers[opnd->shifter.kind].name,
3409 opnd->shifter.amount);
3410 }
3411 break;
3412
3413 case AARCH64_OPND_SVE_PRFOP:
3414 enum_value = opnd->imm.value;
3415 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3416 if (aarch64_sve_prfop_array[enum_value])
3417 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3418 else
3419 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3420 break;
3421
3422 case AARCH64_OPND_IMM_MOV:
3423 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3424 {
3425 case 4: /* e.g. MOV Wd, #<imm32>. */
3426 {
3427 int imm32 = opnd->imm.value;
3428 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3429 }
3430 break;
3431 case 8: /* e.g. MOV Xd, #<imm64>. */
3432 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3433 opnd->imm.value, opnd->imm.value);
3434 break;
3435 default: assert (0);
3436 }
3437 break;
3438
3439 case AARCH64_OPND_FPIMM0:
3440 snprintf (buf, size, "#0.0");
3441 break;
3442
3443 case AARCH64_OPND_LIMM:
3444 case AARCH64_OPND_AIMM:
3445 case AARCH64_OPND_HALF:
3446 case AARCH64_OPND_SVE_INV_LIMM:
3447 case AARCH64_OPND_SVE_LIMM:
3448 case AARCH64_OPND_SVE_LIMM_MOV:
3449 if (opnd->shifter.amount)
3450 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
3451 opnd->shifter.amount);
3452 else
3453 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3454 break;
3455
3456 case AARCH64_OPND_SIMD_IMM:
3457 case AARCH64_OPND_SIMD_IMM_SFT:
3458 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3459 || opnd->shifter.kind == AARCH64_MOD_NONE)
3460 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3461 else
3462 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
3463 aarch64_operand_modifiers[opnd->shifter.kind].name,
3464 opnd->shifter.amount);
3465 break;
3466
3467 case AARCH64_OPND_SVE_AIMM:
3468 case AARCH64_OPND_SVE_ASIMM:
3469 if (opnd->shifter.amount)
3470 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3471 opnd->shifter.amount);
3472 else
3473 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3474 break;
3475
3476 case AARCH64_OPND_FPIMM:
3477 case AARCH64_OPND_SIMD_FPIMM:
3478 case AARCH64_OPND_SVE_FPIMM8:
3479 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3480 {
3481 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3482 {
3483 half_conv_t c;
3484 c.i = expand_fp_imm (2, opnd->imm.value);
3485 snprintf (buf, size, "#%.18e", c.f);
3486 }
3487 break;
3488 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3489 {
3490 single_conv_t c;
3491 c.i = expand_fp_imm (4, opnd->imm.value);
3492 snprintf (buf, size, "#%.18e", c.f);
3493 }
3494 break;
3495 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3496 {
3497 double_conv_t c;
3498 c.i = expand_fp_imm (8, opnd->imm.value);
3499 snprintf (buf, size, "#%.18e", c.d);
3500 }
3501 break;
3502 default: assert (0);
3503 }
3504 break;
3505
3506 case AARCH64_OPND_CCMP_IMM:
3507 case AARCH64_OPND_NZCV:
3508 case AARCH64_OPND_EXCEPTION:
3509 case AARCH64_OPND_UIMM4:
3510 case AARCH64_OPND_UIMM4_ADDG:
3511 case AARCH64_OPND_UIMM7:
3512 case AARCH64_OPND_UIMM10:
3513 if (optional_operand_p (opcode, idx) == TRUE
3514 && (opnd->imm.value ==
3515 (int64_t) get_optional_operand_default_value (opcode)))
3516 /* Omit the operand, e.g. DCPS1. */
3517 break;
3518 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3519 break;
3520
3521 case AARCH64_OPND_COND:
3522 case AARCH64_OPND_COND1:
3523 snprintf (buf, size, "%s", opnd->cond->names[0]);
3524 num_conds = ARRAY_SIZE (opnd->cond->names);
3525 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3526 {
3527 size_t len = strlen (buf);
3528 if (i == 1)
3529 snprintf (buf + len, size - len, " // %s = %s",
3530 opnd->cond->names[0], opnd->cond->names[i]);
3531 else
3532 snprintf (buf + len, size - len, ", %s",
3533 opnd->cond->names[i]);
3534 }
3535 break;
3536
3537 case AARCH64_OPND_ADDR_ADRP:
3538 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3539 + opnd->imm.value;
3540 if (pcrel_p)
3541 *pcrel_p = 1;
3542 if (address)
3543 *address = addr;
3544 /* This is not necessary during the disassembling, as print_address_func
3545 in the disassemble_info will take care of the printing. But some
3546 other callers may be still interested in getting the string in *STR,
3547 so here we do snprintf regardless. */
3548 snprintf (buf, size, "#0x%" PRIx64, addr);
3549 break;
3550
3551 case AARCH64_OPND_ADDR_PCREL14:
3552 case AARCH64_OPND_ADDR_PCREL19:
3553 case AARCH64_OPND_ADDR_PCREL21:
3554 case AARCH64_OPND_ADDR_PCREL26:
3555 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3556 if (pcrel_p)
3557 *pcrel_p = 1;
3558 if (address)
3559 *address = addr;
3560 /* This is not necessary during the disassembling, as print_address_func
3561 in the disassemble_info will take care of the printing. But some
3562 other callers may be still interested in getting the string in *STR,
3563 so here we do snprintf regardless. */
3564 snprintf (buf, size, "#0x%" PRIx64, addr);
3565 break;
3566
3567 case AARCH64_OPND_ADDR_SIMPLE:
3568 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3569 case AARCH64_OPND_SIMD_ADDR_POST:
3570 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3571 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3572 {
3573 if (opnd->addr.offset.is_reg)
3574 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3575 else
3576 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3577 }
3578 else
3579 snprintf (buf, size, "[%s]", name);
3580 break;
3581
3582 case AARCH64_OPND_ADDR_REGOFF:
3583 case AARCH64_OPND_SVE_ADDR_R:
3584 case AARCH64_OPND_SVE_ADDR_RR:
3585 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3586 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3587 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3588 case AARCH64_OPND_SVE_ADDR_RX:
3589 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3590 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3591 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
3592 print_register_offset_address
3593 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3594 get_offset_int_reg_name (opnd));
3595 break;
3596
3597 case AARCH64_OPND_SVE_ADDR_ZX:
3598 print_register_offset_address
3599 (buf, size, opnd,
3600 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3601 get_64bit_int_reg_name (opnd->addr.offset.regno, 0));
3602 break;
3603
3604 case AARCH64_OPND_SVE_ADDR_RZ:
3605 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3606 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3607 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3608 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3609 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3610 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3611 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3612 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3613 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3614 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3615 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3616 print_register_offset_address
3617 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3618 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3619 break;
3620
3621 case AARCH64_OPND_ADDR_SIMM7:
3622 case AARCH64_OPND_ADDR_SIMM9:
3623 case AARCH64_OPND_ADDR_SIMM9_2:
3624 case AARCH64_OPND_ADDR_SIMM10:
3625 case AARCH64_OPND_ADDR_SIMM11:
3626 case AARCH64_OPND_ADDR_SIMM13:
3627 case AARCH64_OPND_ADDR_OFFSET:
3628 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
3629 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3630 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3631 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3632 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3633 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3634 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
3635 case AARCH64_OPND_SVE_ADDR_RI_U6:
3636 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3637 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3638 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
3639 print_immediate_offset_address
3640 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
3641 break;
3642
3643 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3644 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3645 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3646 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3647 print_immediate_offset_address
3648 (buf, size, opnd,
3649 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3650 break;
3651
3652 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3653 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3654 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3655 print_register_offset_address
3656 (buf, size, opnd,
3657 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3658 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3659 break;
3660
3661 case AARCH64_OPND_ADDR_UIMM12:
3662 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3663 if (opnd->addr.offset.imm)
3664 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
3665 else
3666 snprintf (buf, size, "[%s]", name);
3667 break;
3668
3669 case AARCH64_OPND_SYSREG:
3670 for (i = 0; aarch64_sys_regs[i].name; ++i)
3671 {
3672 bfd_boolean exact_match
3673 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3674 == opnd->sysreg.flags;
3675
3676 /* Try and find an exact match, But if that fails, return the first
3677 partial match that was found. */
3678 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3679 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3680 && (name == NULL || exact_match))
3681 {
3682 name = aarch64_sys_regs[i].name;
3683 if (exact_match)
3684 {
3685 if (notes)
3686 *notes = NULL;
3687 break;
3688 }
3689
3690 /* If we didn't match exactly, that means the presense of a flag
3691 indicates what we didn't want for this instruction. e.g. If
3692 F_REG_READ is there, that means we were looking for a write
3693 register. See aarch64_ext_sysreg. */
3694 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
3695 *notes = _("reading from a write-only register");
3696 else if (aarch64_sys_regs[i].flags & F_REG_READ)
3697 *notes = _("writing to a read-only register");
3698 }
3699 }
3700
3701 if (name)
3702 snprintf (buf, size, "%s", name);
3703 else
3704 {
3705 /* Implementation defined system register. */
3706 unsigned int value = opnd->sysreg.value;
3707 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3708 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3709 value & 0x7);
3710 }
3711 break;
3712
3713 case AARCH64_OPND_PSTATEFIELD:
3714 for (i = 0; aarch64_pstatefields[i].name; ++i)
3715 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3716 break;
3717 assert (aarch64_pstatefields[i].name);
3718 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3719 break;
3720
3721 case AARCH64_OPND_SYSREG_AT:
3722 case AARCH64_OPND_SYSREG_DC:
3723 case AARCH64_OPND_SYSREG_IC:
3724 case AARCH64_OPND_SYSREG_TLBI:
3725 case AARCH64_OPND_SYSREG_SR:
3726 snprintf (buf, size, "%s", opnd->sysins_op->name);
3727 break;
3728
3729 case AARCH64_OPND_BARRIER:
3730 snprintf (buf, size, "%s", opnd->barrier->name);
3731 break;
3732
3733 case AARCH64_OPND_BARRIER_ISB:
3734 /* Operand can be omitted, e.g. in DCPS1. */
3735 if (! optional_operand_p (opcode, idx)
3736 || (opnd->barrier->value
3737 != get_optional_operand_default_value (opcode)))
3738 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3739 break;
3740
3741 case AARCH64_OPND_PRFOP:
3742 if (opnd->prfop->name != NULL)
3743 snprintf (buf, size, "%s", opnd->prfop->name);
3744 else
3745 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
3746 break;
3747
3748 case AARCH64_OPND_BARRIER_PSB:
3749 case AARCH64_OPND_BTI_TARGET:
3750 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3751 snprintf (buf, size, "%s", opnd->hint_option->name);
3752 break;
3753
3754 default:
3755 assert (0);
3756 }
3757 }
3758 \f
3759 #define CPENC(op0,op1,crn,crm,op2) \
3760 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3761 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3762 #define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3763 /* for 3.9.10 System Instructions */
3764 #define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3765
3766 #define C0 0
3767 #define C1 1
3768 #define C2 2
3769 #define C3 3
3770 #define C4 4
3771 #define C5 5
3772 #define C6 6
3773 #define C7 7
3774 #define C8 8
3775 #define C9 9
3776 #define C10 10
3777 #define C11 11
3778 #define C12 12
3779 #define C13 13
3780 #define C14 14
3781 #define C15 15
3782
3783 /* TODO there is one more issues need to be resolved
3784 1. handle cpu-implementation-defined system registers. */
3785 const aarch64_sys_reg aarch64_sys_regs [] =
3786 {
3787 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
3788 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
3789 { "elr_el1", CPEN_(0,C0,1), 0 },
3790 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
3791 { "sp_el0", CPEN_(0,C1,0), 0 },
3792 { "spsel", CPEN_(0,C2,0), 0 },
3793 { "daif", CPEN_(3,C2,1), 0 },
3794 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
3795 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
3796 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
3797 { "nzcv", CPEN_(3,C2,0), 0 },
3798 { "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
3799 { "fpcr", CPEN_(3,C4,0), 0 },
3800 { "fpsr", CPEN_(3,C4,1), 0 },
3801 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3802 { "dlr_el0", CPEN_(3,C5,1), 0 },
3803 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3804 { "elr_el2", CPEN_(4,C0,1), 0 },
3805 { "sp_el1", CPEN_(4,C1,0), 0 },
3806 { "spsr_irq", CPEN_(4,C3,0), 0 },
3807 { "spsr_abt", CPEN_(4,C3,1), 0 },
3808 { "spsr_und", CPEN_(4,C3,2), 0 },
3809 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3810 { "spsr_el3", CPEN_(6,C0,0), 0 },
3811 { "elr_el3", CPEN_(6,C0,1), 0 },
3812 { "sp_el2", CPEN_(6,C1,0), 0 },
3813 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3814 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
3815 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3816 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3817 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3818 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3819 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3820 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3821 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3822 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3823 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
3824 { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
3825 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3826 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3827 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3828 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3829 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3830 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3831 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3832 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3833 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3834 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3835 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3836 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3837 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3838 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3839 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3840 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3841 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3842 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3843 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3844 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3845 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3846 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3847 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3848 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3849 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3850 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3851 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3852 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3853 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
3854 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
3855 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3856 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3857 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3858 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3859 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
3860 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
3861 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3862 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3863 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3864 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
3865 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
3866 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3867 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3868 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3869 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3870 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3871 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3872 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3873 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
3874 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3875 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3876 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3877 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3878 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
3879 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3880 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3881 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
3882 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
3883 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
3884 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3885 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
3886 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3887 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3888 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3889 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
3890 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
3891 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
3892 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3893 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3894 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3895 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3896 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3897 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3898 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3899 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3900 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3901 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
3902 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3903 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3904 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3905 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3906 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
3907 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
3908 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
3909 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
3910 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3911 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3912 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
3913 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
3914 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
3915 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
3916 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
3917 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
3918 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
3919 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3920 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3921 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3922 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3923 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
3924 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3925 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3926 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
3927 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
3928 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3929 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3930 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3931 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3932 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
3933 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
3934 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3935 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3936 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
3937 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
3938 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3939 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3940 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
3941 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
3942 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3943 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3944 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
3945 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3946 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3947 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
3948 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
3949 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3950 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
3951 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
3952 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3953 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
3954 { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
3955 { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
3956 { "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
3957 { "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT },
3958 { "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT },
3959 { "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT },
3960 { "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT },
3961 { "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT },
3962 { "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
3963 { "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
3964 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
3965 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
3966 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3967 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3968 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
3969 { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
3970 { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
3971 { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
3972 { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
3973 { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
3974 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
3975 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3976 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3977 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
3978 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3979 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
3980 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
3981 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
3982 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
3983 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
3984 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
3985 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
3986 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
3987 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
3988 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
3989 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
3990 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
3991 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
3992 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
3993 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
3994 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
3995 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
3996 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
3997 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
3998 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
3999 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
4000 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
4001 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
4002 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
4003 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
4004 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
4005 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
4006 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
4007 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
4008 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
4009 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
4010 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
4011 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
4012 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
4013 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
4014 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
4015 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
4016 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
4017 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
4018 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
4019 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
4020 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
4021 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
4022 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
4023 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
4024 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
4025 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
4026 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
4027 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
4028 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
4029 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
4030 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
4031 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
4032 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
4033 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
4034 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
4035 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
4036 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
4037 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
4038 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
4039 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
4040 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
4041 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
4042 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
4043 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
4044 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
4045 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
4046 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
4047 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
4048 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
4049 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
4050 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
4051 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
4052 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
4053 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
4054 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
4055 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
4056 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
4057 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
4058 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
4059 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
4060 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
4061 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
4062 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
4063 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
4064 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
4065 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
4066 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
4067 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
4068 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
4069 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
4070 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
4071 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
4072 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
4073 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
4074 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
4075 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
4076 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
4077 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
4078 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
4079 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
4080 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
4081 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
4082 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
4083 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
4084 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
4085 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
4086 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
4087 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
4088 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
4089 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
4090 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
4091 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
4092 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
4093 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
4094 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
4095 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
4096 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
4097 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
4098 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
4099 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
4100 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
4101 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
4102 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
4103 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
4104 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
4105 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
4106 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
4107 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
4108 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
4109 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
4110 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
4111 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4112 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4113 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4114 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4115 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4116 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4117 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4118 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4119 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4120 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4121 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4122 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4123 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4124 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4125 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4126 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4127 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4128 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4129 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4130 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4131 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4132 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4133 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4134 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4135 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4136 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4137 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4138 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4139 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4140 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4141 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4142 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4143 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4144 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4145 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4146 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4147 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4148 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4149 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4150 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4151 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4152 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4153 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4154 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4155 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4156 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4157 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4158 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4159 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4160 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4161 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4162 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4163 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4164 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4165 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4166 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4167 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4168 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4169 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4170 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4171 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4172 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4173 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4174 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4175 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4176 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4177 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4178 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4179 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
4180
4181 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4182 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4183 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4184 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4185 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4186 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4187 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4188 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4189 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4190 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4191 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
4192 { 0, CPENC(0,0,0,0,0), 0 },
4193 };
4194
4195 bfd_boolean
4196 aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4197 {
4198 return (reg->flags & F_DEPRECATED) != 0;
4199 }
4200
4201 bfd_boolean
4202 aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4203 const aarch64_sys_reg *reg)
4204 {
4205 if (!(reg->flags & F_ARCHEXT))
4206 return TRUE;
4207
4208 /* PAN. Values are from aarch64_sys_regs. */
4209 if (reg->value == CPEN_(0,C2,3)
4210 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4211 return FALSE;
4212
4213 /* SCXTNUM_ELx registers. */
4214 if ((reg->value == CPENC (3, 3, C13, C0, 7)
4215 || reg->value == CPENC (3, 0, C13, C0, 7)
4216 || reg->value == CPENC (3, 4, C13, C0, 7)
4217 || reg->value == CPENC (3, 6, C13, C0, 7)
4218 || reg->value == CPENC (3, 5, C13, C0, 7))
4219 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
4220 return FALSE;
4221
4222 /* ID_PFR2_EL1 register. */
4223 if (reg->value == CPENC(3, 0, C0, C3, 4)
4224 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
4225 return FALSE;
4226
4227 /* SSBS. Values are from aarch64_sys_regs. */
4228 if (reg->value == CPEN_(3,C2,6)
4229 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4230 return FALSE;
4231
4232 /* Virtualization host extensions: system registers. */
4233 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4234 || reg->value == CPENC (3, 4, C13, C0, 1)
4235 || reg->value == CPENC (3, 4, C14, C3, 0)
4236 || reg->value == CPENC (3, 4, C14, C3, 1)
4237 || reg->value == CPENC (3, 4, C14, C3, 2))
4238 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4239 return FALSE;
4240
4241 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4242 if ((reg->value == CPEN_ (5, C0, 0)
4243 || reg->value == CPEN_ (5, C0, 1)
4244 || reg->value == CPENC (3, 5, C1, C0, 0)
4245 || reg->value == CPENC (3, 5, C1, C0, 2)
4246 || reg->value == CPENC (3, 5, C2, C0, 0)
4247 || reg->value == CPENC (3, 5, C2, C0, 1)
4248 || reg->value == CPENC (3, 5, C2, C0, 2)
4249 || reg->value == CPENC (3, 5, C5, C1, 0)
4250 || reg->value == CPENC (3, 5, C5, C1, 1)
4251 || reg->value == CPENC (3, 5, C5, C2, 0)
4252 || reg->value == CPENC (3, 5, C6, C0, 0)
4253 || reg->value == CPENC (3, 5, C10, C2, 0)
4254 || reg->value == CPENC (3, 5, C10, C3, 0)
4255 || reg->value == CPENC (3, 5, C12, C0, 0)
4256 || reg->value == CPENC (3, 5, C13, C0, 1)
4257 || reg->value == CPENC (3, 5, C14, C1, 0))
4258 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4259 return FALSE;
4260
4261 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4262 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4263 || reg->value == CPENC (3, 5, C14, C2, 1)
4264 || reg->value == CPENC (3, 5, C14, C2, 2)
4265 || reg->value == CPENC (3, 5, C14, C3, 0)
4266 || reg->value == CPENC (3, 5, C14, C3, 1)
4267 || reg->value == CPENC (3, 5, C14, C3, 2))
4268 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4269 return FALSE;
4270
4271 /* ARMv8.2 features. */
4272
4273 /* ID_AA64MMFR2_EL1. */
4274 if (reg->value == CPENC (3, 0, C0, C7, 2)
4275 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4276 return FALSE;
4277
4278 /* PSTATE.UAO. */
4279 if (reg->value == CPEN_ (0, C2, 4)
4280 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4281 return FALSE;
4282
4283 /* RAS extension. */
4284
4285 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4286 ERXMISC0_EL1 AND ERXMISC1_EL1. */
4287 if ((reg->value == CPENC (3, 0, C5, C3, 0)
4288 || reg->value == CPENC (3, 0, C5, C3, 1)
4289 || reg->value == CPENC (3, 0, C5, C3, 2)
4290 || reg->value == CPENC (3, 0, C5, C3, 3)
4291 || reg->value == CPENC (3, 0, C5, C4, 0)
4292 || reg->value == CPENC (3, 0, C5, C4, 1)
4293 || reg->value == CPENC (3, 0, C5, C4, 2)
4294 || reg->value == CPENC (3, 0, C5, C4, 3)
4295 || reg->value == CPENC (3, 0, C5, C5, 0)
4296 || reg->value == CPENC (3, 0, C5, C5, 1))
4297 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4298 return FALSE;
4299
4300 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4301 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4302 || reg->value == CPENC (3, 0, C12, C1, 1)
4303 || reg->value == CPENC (3, 4, C12, C1, 1))
4304 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4305 return FALSE;
4306
4307 /* Statistical Profiling extension. */
4308 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4309 || reg->value == CPENC (3, 0, C9, C10, 1)
4310 || reg->value == CPENC (3, 0, C9, C10, 3)
4311 || reg->value == CPENC (3, 0, C9, C10, 7)
4312 || reg->value == CPENC (3, 0, C9, C9, 0)
4313 || reg->value == CPENC (3, 0, C9, C9, 2)
4314 || reg->value == CPENC (3, 0, C9, C9, 3)
4315 || reg->value == CPENC (3, 0, C9, C9, 4)
4316 || reg->value == CPENC (3, 0, C9, C9, 5)
4317 || reg->value == CPENC (3, 0, C9, C9, 6)
4318 || reg->value == CPENC (3, 0, C9, C9, 7)
4319 || reg->value == CPENC (3, 4, C9, C9, 0)
4320 || reg->value == CPENC (3, 5, C9, C9, 0))
4321 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4322 return FALSE;
4323
4324 /* ARMv8.3 Pointer authentication keys. */
4325 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4326 || reg->value == CPENC (3, 0, C2, C1, 1)
4327 || reg->value == CPENC (3, 0, C2, C1, 2)
4328 || reg->value == CPENC (3, 0, C2, C1, 3)
4329 || reg->value == CPENC (3, 0, C2, C2, 0)
4330 || reg->value == CPENC (3, 0, C2, C2, 1)
4331 || reg->value == CPENC (3, 0, C2, C2, 2)
4332 || reg->value == CPENC (3, 0, C2, C2, 3)
4333 || reg->value == CPENC (3, 0, C2, C3, 0)
4334 || reg->value == CPENC (3, 0, C2, C3, 1))
4335 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4336 return FALSE;
4337
4338 /* SVE. */
4339 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4340 || reg->value == CPENC (3, 0, C1, C2, 0)
4341 || reg->value == CPENC (3, 4, C1, C2, 0)
4342 || reg->value == CPENC (3, 6, C1, C2, 0)
4343 || reg->value == CPENC (3, 5, C1, C2, 0)
4344 || reg->value == CPENC (3, 0, C0, C0, 7))
4345 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4346 return FALSE;
4347
4348 /* ARMv8.4 features. */
4349
4350 /* PSTATE.DIT. */
4351 if (reg->value == CPEN_ (3, C2, 5)
4352 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4353 return FALSE;
4354
4355 /* Virtualization extensions. */
4356 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4357 || reg->value == CPENC(3, 4, C2, C6, 0)
4358 || reg->value == CPENC(3, 4, C14, C4, 0)
4359 || reg->value == CPENC(3, 4, C14, C4, 2)
4360 || reg->value == CPENC(3, 4, C14, C4, 1)
4361 || reg->value == CPENC(3, 4, C14, C5, 0)
4362 || reg->value == CPENC(3, 4, C14, C5, 2)
4363 || reg->value == CPENC(3, 4, C14, C5, 1)
4364 || reg->value == CPENC(3, 4, C1, C3, 1)
4365 || reg->value == CPENC(3, 4, C2, C2, 0))
4366 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4367 return FALSE;
4368
4369 /* ARMv8.4 TLB instructions. */
4370 if ((reg->value == CPENS (0, C8, C1, 0)
4371 || reg->value == CPENS (0, C8, C1, 1)
4372 || reg->value == CPENS (0, C8, C1, 2)
4373 || reg->value == CPENS (0, C8, C1, 3)
4374 || reg->value == CPENS (0, C8, C1, 5)
4375 || reg->value == CPENS (0, C8, C1, 7)
4376 || reg->value == CPENS (4, C8, C4, 0)
4377 || reg->value == CPENS (4, C8, C4, 4)
4378 || reg->value == CPENS (4, C8, C1, 1)
4379 || reg->value == CPENS (4, C8, C1, 5)
4380 || reg->value == CPENS (4, C8, C1, 6)
4381 || reg->value == CPENS (6, C8, C1, 1)
4382 || reg->value == CPENS (6, C8, C1, 5)
4383 || reg->value == CPENS (4, C8, C1, 0)
4384 || reg->value == CPENS (4, C8, C1, 4)
4385 || reg->value == CPENS (6, C8, C1, 0)
4386 || reg->value == CPENS (0, C8, C6, 1)
4387 || reg->value == CPENS (0, C8, C6, 3)
4388 || reg->value == CPENS (0, C8, C6, 5)
4389 || reg->value == CPENS (0, C8, C6, 7)
4390 || reg->value == CPENS (0, C8, C2, 1)
4391 || reg->value == CPENS (0, C8, C2, 3)
4392 || reg->value == CPENS (0, C8, C2, 5)
4393 || reg->value == CPENS (0, C8, C2, 7)
4394 || reg->value == CPENS (0, C8, C5, 1)
4395 || reg->value == CPENS (0, C8, C5, 3)
4396 || reg->value == CPENS (0, C8, C5, 5)
4397 || reg->value == CPENS (0, C8, C5, 7)
4398 || reg->value == CPENS (4, C8, C0, 2)
4399 || reg->value == CPENS (4, C8, C0, 6)
4400 || reg->value == CPENS (4, C8, C4, 2)
4401 || reg->value == CPENS (4, C8, C4, 6)
4402 || reg->value == CPENS (4, C8, C4, 3)
4403 || reg->value == CPENS (4, C8, C4, 7)
4404 || reg->value == CPENS (4, C8, C6, 1)
4405 || reg->value == CPENS (4, C8, C6, 5)
4406 || reg->value == CPENS (4, C8, C2, 1)
4407 || reg->value == CPENS (4, C8, C2, 5)
4408 || reg->value == CPENS (4, C8, C5, 1)
4409 || reg->value == CPENS (4, C8, C5, 5)
4410 || reg->value == CPENS (6, C8, C6, 1)
4411 || reg->value == CPENS (6, C8, C6, 5)
4412 || reg->value == CPENS (6, C8, C2, 1)
4413 || reg->value == CPENS (6, C8, C2, 5)
4414 || reg->value == CPENS (6, C8, C5, 1)
4415 || reg->value == CPENS (6, C8, C5, 5))
4416 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4417 return FALSE;
4418
4419 /* Random Number Instructions. For now they are available
4420 (and optional) only with ARMv8.5-A. */
4421 if ((reg->value == CPENC (3, 3, C2, C4, 0)
4422 || reg->value == CPENC (3, 3, C2, C4, 1))
4423 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
4424 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
4425 return FALSE;
4426
4427 /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
4428 if ((reg->value == CPENC (3, 3, C4, C2, 7)
4429 || reg->value == CPENC (3, 0, C6, C6, 1)
4430 || reg->value == CPENC (3, 0, C6, C5, 0)
4431 || reg->value == CPENC (3, 4, C6, C5, 0)
4432 || reg->value == CPENC (3, 6, C6, C6, 0)
4433 || reg->value == CPENC (3, 5, C6, C6, 0)
4434 || reg->value == CPENC (3, 0, C1, C0, 5)
4435 || reg->value == CPENC (3, 0, C1, C0, 6))
4436 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
4437 return FALSE;
4438
4439 return TRUE;
4440 }
4441
4442 /* The CPENC below is fairly misleading, the fields
4443 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4444 by ins_pstatefield, which just shifts the value by the width of the fields
4445 in a loop. So if you CPENC them only the first value will be set, the rest
4446 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4447 value of 0b110000000001000000 (0x30040) while what you want is
4448 0b011010 (0x1a). */
4449 const aarch64_sys_reg aarch64_pstatefields [] =
4450 {
4451 { "spsel", 0x05, 0 },
4452 { "daifset", 0x1e, 0 },
4453 { "daifclr", 0x1f, 0 },
4454 { "pan", 0x04, F_ARCHEXT },
4455 { "uao", 0x03, F_ARCHEXT },
4456 { "ssbs", 0x19, F_ARCHEXT },
4457 { "dit", 0x1a, F_ARCHEXT },
4458 { "tco", 0x1c, F_ARCHEXT },
4459 { 0, CPENC(0,0,0,0,0), 0 },
4460 };
4461
4462 bfd_boolean
4463 aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4464 const aarch64_sys_reg *reg)
4465 {
4466 if (!(reg->flags & F_ARCHEXT))
4467 return TRUE;
4468
4469 /* PAN. Values are from aarch64_pstatefields. */
4470 if (reg->value == 0x04
4471 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4472 return FALSE;
4473
4474 /* UAO. Values are from aarch64_pstatefields. */
4475 if (reg->value == 0x03
4476 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4477 return FALSE;
4478
4479 /* SSBS. Values are from aarch64_pstatefields. */
4480 if (reg->value == 0x19
4481 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4482 return FALSE;
4483
4484 /* DIT. Values are from aarch64_pstatefields. */
4485 if (reg->value == 0x1a
4486 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4487 return FALSE;
4488
4489 /* TCO. Values are from aarch64_pstatefields. */
4490 if (reg->value == 0x1c
4491 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4492 return FALSE;
4493
4494 return TRUE;
4495 }
4496
4497 const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4498 {
4499 { "ialluis", CPENS(0,C7,C1,0), 0 },
4500 { "iallu", CPENS(0,C7,C5,0), 0 },
4501 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
4502 { 0, CPENS(0,0,0,0), 0 }
4503 };
4504
4505 const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4506 {
4507 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
4508 { "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
4509 { "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
4510 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
4511 { "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
4512 { "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
4513 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
4514 { "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
4515 { "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
4516 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
4517 { "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
4518 { "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
4519 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
4520 { "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
4521 { "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
4522 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
4523 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
4524 { "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
4525 { "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
4526 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
4527 { "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
4528 { "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
4529 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
4530 { "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
4531 { "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
4532 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
4533 { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
4534 { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
4535 { 0, CPENS(0,0,0,0), 0 }
4536 };
4537
4538 const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4539 {
4540 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4541 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4542 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4543 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4544 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4545 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4546 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4547 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4548 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4549 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4550 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4551 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
4552 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4553 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
4554 { 0, CPENS(0,0,0,0), 0 }
4555 };
4556
4557 const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4558 {
4559 { "vmalle1", CPENS(0,C8,C7,0), 0 },
4560 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4561 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4562 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
4563 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
4564 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4565 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4566 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4567 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4568 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4569 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4570 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4571 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4572 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
4573 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4574 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
4575 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4576 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
4577 { "alle2", CPENS(4,C8,C7,0), 0 },
4578 { "alle2is", CPENS(4,C8,C3,0), 0 },
4579 { "alle1", CPENS(4,C8,C7,4), 0 },
4580 { "alle1is", CPENS(4,C8,C3,4), 0 },
4581 { "alle3", CPENS(6,C8,C7,0), 0 },
4582 { "alle3is", CPENS(6,C8,C3,0), 0 },
4583 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4584 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4585 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4586 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4587 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4588 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4589 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4590 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
4591
4592 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4593 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4594 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4595 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4596 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4597 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4598 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4599 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4600 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4601 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4602 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4603 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4604 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4605 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4606 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4607 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4608
4609 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4610 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4611 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4612 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4613 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4614 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4615 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4616 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4617 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4618 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4619 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4620 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4621 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4622 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4623 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4624 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4625 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4626 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4627 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4628 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4629 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4630 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4631 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4632 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4633 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4634 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4635 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4636 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4637 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4638 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4639
4640 { 0, CPENS(0,0,0,0), 0 }
4641 };
4642
4643 const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4644 {
4645 /* RCTX is somewhat unique in a way that it has different values
4646 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4647 Thus op2 is masked out and instead encoded directly in the
4648 aarch64_opcode_table entries for the respective instructions. */
4649 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4650
4651 { 0, CPENS(0,0,0,0), 0 }
4652 };
4653
4654 bfd_boolean
4655 aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4656 {
4657 return (sys_ins_reg->flags & F_HASXT) != 0;
4658 }
4659
4660 extern bfd_boolean
4661 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4662 const aarch64_sys_ins_reg *reg)
4663 {
4664 if (!(reg->flags & F_ARCHEXT))
4665 return TRUE;
4666
4667 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4668 if (reg->value == CPENS (3, C7, C12, 1)
4669 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4670 return FALSE;
4671
4672 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4673 if (reg->value == CPENS (3, C7, C13, 1)
4674 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4675 return FALSE;
4676
4677 /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
4678 if ((reg->value == CPENS (0, C7, C6, 3)
4679 || reg->value == CPENS (0, C7, C6, 4)
4680 || reg->value == CPENS (0, C7, C10, 4)
4681 || reg->value == CPENS (0, C7, C14, 4)
4682 || reg->value == CPENS (3, C7, C10, 3)
4683 || reg->value == CPENS (3, C7, C12, 3)
4684 || reg->value == CPENS (3, C7, C13, 3)
4685 || reg->value == CPENS (3, C7, C14, 3)
4686 || reg->value == CPENS (3, C7, C4, 3)
4687 || reg->value == CPENS (0, C7, C6, 5)
4688 || reg->value == CPENS (0, C7, C6, 6)
4689 || reg->value == CPENS (0, C7, C10, 6)
4690 || reg->value == CPENS (0, C7, C14, 6)
4691 || reg->value == CPENS (3, C7, C10, 5)
4692 || reg->value == CPENS (3, C7, C12, 5)
4693 || reg->value == CPENS (3, C7, C13, 5)
4694 || reg->value == CPENS (3, C7, C14, 5)
4695 || reg->value == CPENS (3, C7, C4, 4))
4696 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4697 return FALSE;
4698
4699 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4700 if ((reg->value == CPENS (0, C7, C9, 0)
4701 || reg->value == CPENS (0, C7, C9, 1))
4702 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4703 return FALSE;
4704
4705 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4706 if (reg->value == CPENS (3, C7, C3, 0)
4707 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4708 return FALSE;
4709
4710 return TRUE;
4711 }
4712
4713 #undef C0
4714 #undef C1
4715 #undef C2
4716 #undef C3
4717 #undef C4
4718 #undef C5
4719 #undef C6
4720 #undef C7
4721 #undef C8
4722 #undef C9
4723 #undef C10
4724 #undef C11
4725 #undef C12
4726 #undef C13
4727 #undef C14
4728 #undef C15
4729
4730 #define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4731 #define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4732
4733 static enum err_type
4734 verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4735 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4736 bfd_boolean encoding ATTRIBUTE_UNUSED,
4737 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4738 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4739 {
4740 int t = BITS (insn, 4, 0);
4741 int n = BITS (insn, 9, 5);
4742 int t2 = BITS (insn, 14, 10);
4743
4744 if (BIT (insn, 23))
4745 {
4746 /* Write back enabled. */
4747 if ((t == n || t2 == n) && n != 31)
4748 return ERR_UND;
4749 }
4750
4751 if (BIT (insn, 22))
4752 {
4753 /* Load */
4754 if (t == t2)
4755 return ERR_UND;
4756 }
4757
4758 return ERR_OK;
4759 }
4760
4761 /* Verifier for vector by element 3 operands functions where the
4762 conditions `if sz:L == 11 then UNDEFINED` holds. */
4763
4764 static enum err_type
4765 verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
4766 bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
4767 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4768 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4769 {
4770 const aarch64_insn undef_pattern = 0x3;
4771 aarch64_insn value;
4772
4773 assert (inst->opcode);
4774 assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
4775 value = encoding ? inst->value : insn;
4776 assert (value);
4777
4778 if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
4779 return ERR_UND;
4780
4781 return ERR_OK;
4782 }
4783
4784 /* Initialize an instruction sequence insn_sequence with the instruction INST.
4785 If INST is NULL the given insn_sequence is cleared and the sequence is left
4786 uninitialized. */
4787
4788 void
4789 init_insn_sequence (const struct aarch64_inst *inst,
4790 aarch64_instr_sequence *insn_sequence)
4791 {
4792 int num_req_entries = 0;
4793 insn_sequence->next_insn = 0;
4794 insn_sequence->num_insns = num_req_entries;
4795 if (insn_sequence->instr)
4796 XDELETE (insn_sequence->instr);
4797 insn_sequence->instr = NULL;
4798
4799 if (inst)
4800 {
4801 insn_sequence->instr = XNEW (aarch64_inst);
4802 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4803 }
4804
4805 /* Handle all the cases here. May need to think of something smarter than
4806 a giant if/else chain if this grows. At that time, a lookup table may be
4807 best. */
4808 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4809 num_req_entries = 1;
4810
4811 if (insn_sequence->current_insns)
4812 XDELETEVEC (insn_sequence->current_insns);
4813 insn_sequence->current_insns = NULL;
4814
4815 if (num_req_entries != 0)
4816 {
4817 size_t size = num_req_entries * sizeof (aarch64_inst);
4818 insn_sequence->current_insns
4819 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4820 memset (insn_sequence->current_insns, 0, size);
4821 }
4822 }
4823
4824
4825 /* This function verifies that the instruction INST adheres to its specified
4826 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4827 returned and MISMATCH_DETAIL contains the reason why verification failed.
4828
4829 The function is called both during assembly and disassembly. If assembling
4830 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4831 and will contain the PC of the current instruction w.r.t to the section.
4832
4833 If ENCODING and PC=0 then you are at a start of a section. The constraints
4834 are verified against the given state insn_sequence which is updated as it
4835 transitions through the verification. */
4836
4837 enum err_type
4838 verify_constraints (const struct aarch64_inst *inst,
4839 const aarch64_insn insn ATTRIBUTE_UNUSED,
4840 bfd_vma pc,
4841 bfd_boolean encoding,
4842 aarch64_operand_error *mismatch_detail,
4843 aarch64_instr_sequence *insn_sequence)
4844 {
4845 assert (inst);
4846 assert (inst->opcode);
4847
4848 const struct aarch64_opcode *opcode = inst->opcode;
4849 if (!opcode->constraints && !insn_sequence->instr)
4850 return ERR_OK;
4851
4852 assert (insn_sequence);
4853
4854 enum err_type res = ERR_OK;
4855
4856 /* This instruction puts a constraint on the insn_sequence. */
4857 if (opcode->flags & F_SCAN)
4858 {
4859 if (insn_sequence->instr)
4860 {
4861 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4862 mismatch_detail->error = _("instruction opens new dependency "
4863 "sequence without ending previous one");
4864 mismatch_detail->index = -1;
4865 mismatch_detail->non_fatal = TRUE;
4866 res = ERR_VFI;
4867 }
4868
4869 init_insn_sequence (inst, insn_sequence);
4870 return res;
4871 }
4872
4873 /* Verify constraints on an existing sequence. */
4874 if (insn_sequence->instr)
4875 {
4876 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4877 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4878 closed a previous one that we should have. */
4879 if (!encoding && pc == 0)
4880 {
4881 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4882 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4883 mismatch_detail->index = -1;
4884 mismatch_detail->non_fatal = TRUE;
4885 res = ERR_VFI;
4886 /* Reset the sequence. */
4887 init_insn_sequence (NULL, insn_sequence);
4888 return res;
4889 }
4890
4891 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4892 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4893 {
4894 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4895 instruction for better error messages. */
4896 if (!opcode->avariant
4897 || !(*opcode->avariant &
4898 (AARCH64_FEATURE_SVE | AARCH64_FEATURE_SVE2)))
4899 {
4900 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4901 mismatch_detail->error = _("SVE instruction expected after "
4902 "`movprfx'");
4903 mismatch_detail->index = -1;
4904 mismatch_detail->non_fatal = TRUE;
4905 res = ERR_VFI;
4906 goto done;
4907 }
4908
4909 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4910 instruction that is allowed to be used with a MOVPRFX. */
4911 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4912 {
4913 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4914 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4915 "expected");
4916 mismatch_detail->index = -1;
4917 mismatch_detail->non_fatal = TRUE;
4918 res = ERR_VFI;
4919 goto done;
4920 }
4921
4922 /* Next check for usage of the predicate register. */
4923 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
4924 aarch64_opnd_info blk_pred, inst_pred;
4925 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4926 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
4927 bfd_boolean predicated = FALSE;
4928 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4929
4930 /* Determine if the movprfx instruction used is predicated or not. */
4931 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4932 {
4933 predicated = TRUE;
4934 blk_pred = insn_sequence->instr->operands[1];
4935 }
4936
4937 unsigned char max_elem_size = 0;
4938 unsigned char current_elem_size;
4939 int num_op_used = 0, last_op_usage = 0;
4940 int i, inst_pred_idx = -1;
4941 int num_ops = aarch64_num_of_operands (opcode);
4942 for (i = 0; i < num_ops; i++)
4943 {
4944 aarch64_opnd_info inst_op = inst->operands[i];
4945 switch (inst_op.type)
4946 {
4947 case AARCH64_OPND_SVE_Zd:
4948 case AARCH64_OPND_SVE_Zm_5:
4949 case AARCH64_OPND_SVE_Zm_16:
4950 case AARCH64_OPND_SVE_Zn:
4951 case AARCH64_OPND_SVE_Zt:
4952 case AARCH64_OPND_SVE_Vm:
4953 case AARCH64_OPND_SVE_Vn:
4954 case AARCH64_OPND_Va:
4955 case AARCH64_OPND_Vn:
4956 case AARCH64_OPND_Vm:
4957 case AARCH64_OPND_Sn:
4958 case AARCH64_OPND_Sm:
4959 case AARCH64_OPND_Rn:
4960 case AARCH64_OPND_Rm:
4961 case AARCH64_OPND_Rn_SP:
4962 case AARCH64_OPND_Rt_SP:
4963 case AARCH64_OPND_Rm_SP:
4964 if (inst_op.reg.regno == blk_dest.reg.regno)
4965 {
4966 num_op_used++;
4967 last_op_usage = i;
4968 }
4969 current_elem_size
4970 = aarch64_get_qualifier_esize (inst_op.qualifier);
4971 if (current_elem_size > max_elem_size)
4972 max_elem_size = current_elem_size;
4973 break;
4974 case AARCH64_OPND_SVE_Pd:
4975 case AARCH64_OPND_SVE_Pg3:
4976 case AARCH64_OPND_SVE_Pg4_5:
4977 case AARCH64_OPND_SVE_Pg4_10:
4978 case AARCH64_OPND_SVE_Pg4_16:
4979 case AARCH64_OPND_SVE_Pm:
4980 case AARCH64_OPND_SVE_Pn:
4981 case AARCH64_OPND_SVE_Pt:
4982 inst_pred = inst_op;
4983 inst_pred_idx = i;
4984 break;
4985 default:
4986 break;
4987 }
4988 }
4989
4990 assert (max_elem_size != 0);
4991 aarch64_opnd_info inst_dest = inst->operands[0];
4992 /* Determine the size that should be used to compare against the
4993 movprfx size. */
4994 current_elem_size
4995 = opcode->constraints & C_MAX_ELEM
4996 ? max_elem_size
4997 : aarch64_get_qualifier_esize (inst_dest.qualifier);
4998
4999 /* If movprfx is predicated do some extra checks. */
5000 if (predicated)
5001 {
5002 /* The instruction must be predicated. */
5003 if (inst_pred_idx < 0)
5004 {
5005 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5006 mismatch_detail->error = _("predicated instruction expected "
5007 "after `movprfx'");
5008 mismatch_detail->index = -1;
5009 mismatch_detail->non_fatal = TRUE;
5010 res = ERR_VFI;
5011 goto done;
5012 }
5013
5014 /* The instruction must have a merging predicate. */
5015 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
5016 {
5017 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5018 mismatch_detail->error = _("merging predicate expected due "
5019 "to preceding `movprfx'");
5020 mismatch_detail->index = inst_pred_idx;
5021 mismatch_detail->non_fatal = TRUE;
5022 res = ERR_VFI;
5023 goto done;
5024 }
5025
5026 /* The same register must be used in instruction. */
5027 if (blk_pred.reg.regno != inst_pred.reg.regno)
5028 {
5029 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5030 mismatch_detail->error = _("predicate register differs "
5031 "from that in preceding "
5032 "`movprfx'");
5033 mismatch_detail->index = inst_pred_idx;
5034 mismatch_detail->non_fatal = TRUE;
5035 res = ERR_VFI;
5036 goto done;
5037 }
5038 }
5039
5040 /* Destructive operations by definition must allow one usage of the
5041 same register. */
5042 int allowed_usage
5043 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
5044
5045 /* Operand is not used at all. */
5046 if (num_op_used == 0)
5047 {
5048 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5049 mismatch_detail->error = _("output register of preceding "
5050 "`movprfx' not used in current "
5051 "instruction");
5052 mismatch_detail->index = 0;
5053 mismatch_detail->non_fatal = TRUE;
5054 res = ERR_VFI;
5055 goto done;
5056 }
5057
5058 /* We now know it's used, now determine exactly where it's used. */
5059 if (blk_dest.reg.regno != inst_dest.reg.regno)
5060 {
5061 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5062 mismatch_detail->error = _("output register of preceding "
5063 "`movprfx' expected as output");
5064 mismatch_detail->index = 0;
5065 mismatch_detail->non_fatal = TRUE;
5066 res = ERR_VFI;
5067 goto done;
5068 }
5069
5070 /* Operand used more than allowed for the specific opcode type. */
5071 if (num_op_used > allowed_usage)
5072 {
5073 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5074 mismatch_detail->error = _("output register of preceding "
5075 "`movprfx' used as input");
5076 mismatch_detail->index = last_op_usage;
5077 mismatch_detail->non_fatal = TRUE;
5078 res = ERR_VFI;
5079 goto done;
5080 }
5081
5082 /* Now the only thing left is the qualifiers checks. The register
5083 must have the same maximum element size. */
5084 if (inst_dest.qualifier
5085 && blk_dest.qualifier
5086 && current_elem_size
5087 != aarch64_get_qualifier_esize (blk_dest.qualifier))
5088 {
5089 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5090 mismatch_detail->error = _("register size not compatible with "
5091 "previous `movprfx'");
5092 mismatch_detail->index = 0;
5093 mismatch_detail->non_fatal = TRUE;
5094 res = ERR_VFI;
5095 goto done;
5096 }
5097 }
5098
5099 done:
5100 /* Add the new instruction to the sequence. */
5101 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
5102 inst, sizeof (aarch64_inst));
5103
5104 /* Check if sequence is now full. */
5105 if (insn_sequence->next_insn >= insn_sequence->num_insns)
5106 {
5107 /* Sequence is full, but we don't have anything special to do for now,
5108 so clear and reset it. */
5109 init_insn_sequence (NULL, insn_sequence);
5110 }
5111 }
5112
5113 return res;
5114 }
5115
5116
5117 /* Return true if VALUE cannot be moved into an SVE register using DUP
5118 (with any element size, not just ESIZE) and if using DUPM would
5119 therefore be OK. ESIZE is the number of bytes in the immediate. */
5120
5121 bfd_boolean
5122 aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
5123 {
5124 int64_t svalue = uvalue;
5125 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
5126
5127 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
5128 return FALSE;
5129 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
5130 {
5131 svalue = (int32_t) uvalue;
5132 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
5133 {
5134 svalue = (int16_t) uvalue;
5135 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
5136 return FALSE;
5137 }
5138 }
5139 if ((svalue & 0xff) == 0)
5140 svalue /= 256;
5141 return svalue < -128 || svalue >= 128;
5142 }
5143
5144 /* Include the opcode description table as well as the operand description
5145 table. */
5146 #define VERIFIER(x) verify_##x
5147 #include "aarch64-tbl.h"
GDB Binutils - Deliverables
This page took 0.282214 seconds and 5 git commands to generate.