1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2017 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
25 #include "opcode/aarch64.h"
27 /* Instruction fields.
28 Keep synced with fields. */
29 enum aarch64_field_kind
145 /* Field description. */
152 typedef struct aarch64_field aarch64_field
;
154 extern const aarch64_field fields
[];
156 /* Operand description. */
158 struct aarch64_operand
160 enum aarch64_operand_class op_class
;
162 /* Name of the operand code; used mainly for the purpose of internal
168 /* The associated instruction bit-fields; no operand has more than 4
170 enum aarch64_field_kind fields
[4];
172 /* Brief description */
176 typedef struct aarch64_operand aarch64_operand
;
178 extern const aarch64_operand aarch64_operands
[];
182 #define OPD_F_HAS_INSERTER 0x00000001
183 #define OPD_F_HAS_EXTRACTOR 0x00000002
184 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
185 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
186 value by 2 to get the value
187 of an immediate operand. */
188 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
189 #define OPD_F_OD_MASK 0x00000060 /* Operand-dependent data. */
190 #define OPD_F_OD_LSB 5
191 #define OPD_F_NO_ZR 0x00000080 /* ZR index not allowed. */
193 static inline bfd_boolean
194 operand_has_inserter (const aarch64_operand
*operand
)
196 return (operand
->flags
& OPD_F_HAS_INSERTER
) ? TRUE
: FALSE
;
199 static inline bfd_boolean
200 operand_has_extractor (const aarch64_operand
*operand
)
202 return (operand
->flags
& OPD_F_HAS_EXTRACTOR
) ? TRUE
: FALSE
;
205 static inline bfd_boolean
206 operand_need_sign_extension (const aarch64_operand
*operand
)
208 return (operand
->flags
& OPD_F_SEXT
) ? TRUE
: FALSE
;
211 static inline bfd_boolean
212 operand_need_shift_by_two (const aarch64_operand
*operand
)
214 return (operand
->flags
& OPD_F_SHIFT_BY_2
) ? TRUE
: FALSE
;
217 static inline bfd_boolean
218 operand_maybe_stack_pointer (const aarch64_operand
*operand
)
220 return (operand
->flags
& OPD_F_MAYBE_SP
) ? TRUE
: FALSE
;
223 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
224 static inline unsigned int
225 get_operand_specific_data (const aarch64_operand
*operand
)
227 return (operand
->flags
& OPD_F_OD_MASK
) >> OPD_F_OD_LSB
;
230 /* Return the total width of the operand *OPERAND. */
231 static inline unsigned
232 get_operand_fields_width (const aarch64_operand
*operand
)
236 while (operand
->fields
[i
] != FLD_NIL
)
237 width
+= fields
[operand
->fields
[i
++]].width
;
238 assert (width
> 0 && width
< 32);
242 static inline const aarch64_operand
*
243 get_operand_from_code (enum aarch64_opnd code
)
245 return aarch64_operands
+ code
;
248 /* Operand qualifier and operand constraint checking. */
250 int aarch64_match_operands_constraint (aarch64_inst
*,
251 aarch64_operand_error
*);
253 /* Operand qualifier related functions. */
254 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t
);
255 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t
);
256 aarch64_insn
aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t
);
257 int aarch64_find_best_match (const aarch64_inst
*,
258 const aarch64_opnd_qualifier_seq_t
*,
259 int, aarch64_opnd_qualifier_t
*);
262 reset_operand_qualifier (aarch64_inst
*inst
, int idx
)
264 assert (idx
>=0 && idx
< aarch64_num_of_operands (inst
->opcode
));
265 inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
268 /* Inline functions operating on instruction bit-field(s). */
270 /* Generate a mask that has WIDTH number of consecutive 1s. */
272 static inline aarch64_insn
275 return ((aarch64_insn
) 1 << width
) - 1;
278 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
280 gen_sub_field (enum aarch64_field_kind kind
, int lsb_rel
, int width
, aarch64_field
*ret
)
282 const aarch64_field
*field
= &fields
[kind
];
283 if (lsb_rel
< 0 || width
<= 0 || lsb_rel
+ width
> field
->width
)
285 ret
->lsb
= field
->lsb
+ lsb_rel
;
290 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
294 insert_field_2 (const aarch64_field
*field
, aarch64_insn
*code
,
295 aarch64_insn value
, aarch64_insn mask
)
297 assert (field
->width
< 32 && field
->width
>= 1 && field
->lsb
>= 0
298 && field
->lsb
+ field
->width
<= 32);
299 value
&= gen_mask (field
->width
);
300 value
<<= field
->lsb
;
301 /* In some opcodes, field can be part of the base opcode, e.g. the size
302 field in FADD. The following helps avoid corrupt the base opcode. */
307 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
308 mask of the opcode. */
310 static inline aarch64_insn
311 extract_field_2 (const aarch64_field
*field
, aarch64_insn code
,
315 /* Clear any bit that is a part of the base opcode. */
317 value
= (code
>> field
->lsb
) & gen_mask (field
->width
);
321 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
325 insert_field (enum aarch64_field_kind kind
, aarch64_insn
*code
,
326 aarch64_insn value
, aarch64_insn mask
)
328 insert_field_2 (&fields
[kind
], code
, value
, mask
);
331 /* Extract field KIND of CODE and return the value. MASK can be zero or the
332 base mask of the opcode. */
334 static inline aarch64_insn
335 extract_field (enum aarch64_field_kind kind
, aarch64_insn code
,
338 return extract_field_2 (&fields
[kind
], code
, mask
);
342 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...);
344 /* Inline functions selecting operand to do the encoding/decoding for a
345 certain instruction bit-field. */
347 /* Select the operand to do the encoding/decoding of the 'sf' field.
348 The heuristic-based rule is that the result operand is respected more. */
351 select_operand_for_sf_field_coding (const aarch64_opcode
*opcode
)
354 if (aarch64_get_operand_class (opcode
->operands
[0])
355 == AARCH64_OPND_CLASS_INT_REG
)
358 else if (aarch64_get_operand_class (opcode
->operands
[1])
359 == AARCH64_OPND_CLASS_INT_REG
)
360 /* e.g. float2fix. */
363 { assert (0); abort (); }
367 /* Select the operand to do the encoding/decoding of the 'type' field in
368 the floating-point instructions.
369 The heuristic-based rule is that the source operand is respected more. */
372 select_operand_for_fptype_field_coding (const aarch64_opcode
*opcode
)
375 if (aarch64_get_operand_class (opcode
->operands
[1])
376 == AARCH64_OPND_CLASS_FP_REG
)
379 else if (aarch64_get_operand_class (opcode
->operands
[0])
380 == AARCH64_OPND_CLASS_FP_REG
)
381 /* e.g. float2fix. */
384 { assert (0); abort (); }
388 /* Select the operand to do the encoding/decoding of the 'size' field in
389 the AdvSIMD scalar instructions.
390 The heuristic-based rule is that the destination operand is respected
394 select_operand_for_scalar_size_field_coding (const aarch64_opcode
*opcode
)
396 int src_size
= 0, dst_size
= 0;
397 if (aarch64_get_operand_class (opcode
->operands
[0])
398 == AARCH64_OPND_CLASS_SISD_REG
)
399 dst_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][0]);
400 if (aarch64_get_operand_class (opcode
->operands
[1])
401 == AARCH64_OPND_CLASS_SISD_REG
)
402 src_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][1]);
403 if (src_size
== dst_size
&& src_size
== 0)
404 { assert (0); abort (); }
405 /* When the result is not a sisd register or it is a long operantion. */
406 if (dst_size
== 0 || dst_size
== src_size
<< 1)
412 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
413 the AdvSIMD instructions. */
415 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode
*);
419 aarch64_insn
aarch64_get_operand_modifier_value (enum aarch64_modifier_kind
);
420 enum aarch64_modifier_kind
421 aarch64_get_operand_modifier_from_value (aarch64_insn
, bfd_boolean
);
424 bfd_boolean
aarch64_wide_constant_p (int64_t, int, unsigned int *);
425 bfd_boolean
aarch64_logical_immediate_p (uint64_t, int, aarch64_insn
*);
426 int aarch64_shrink_expanded_imm8 (uint64_t);
428 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
430 copy_operand_info (aarch64_inst
*inst
, int dst
, int src
)
432 assert (dst
>= 0 && src
>= 0 && dst
< AARCH64_MAX_OPND_NUM
433 && src
< AARCH64_MAX_OPND_NUM
);
434 memcpy (&inst
->operands
[dst
], &inst
->operands
[src
],
435 sizeof (aarch64_opnd_info
));
436 inst
->operands
[dst
].idx
= dst
;
439 /* A primitive log caculator. */
441 static inline unsigned int
442 get_logsz (unsigned int size
)
444 const unsigned char ls
[16] =
445 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
451 assert (ls
[size
- 1] != (unsigned char)-1);
455 #endif /* OPCODES_AARCH64_OPC_H */