1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
25 #include "opcode/aarch64.h"
27 /* Instruction fields.
28 Keep synced with fields. */
29 enum aarch64_field_kind
151 /* Field description. */
158 typedef struct aarch64_field aarch64_field
;
160 extern const aarch64_field fields
[];
162 /* Operand description. */
164 struct aarch64_operand
166 enum aarch64_operand_class op_class
;
168 /* Name of the operand code; used mainly for the purpose of internal
174 /* The associated instruction bit-fields; no operand has more than 4
176 enum aarch64_field_kind fields
[4];
178 /* Brief description */
182 typedef struct aarch64_operand aarch64_operand
;
184 extern const aarch64_operand aarch64_operands
[];
187 verify_constraints (const struct aarch64_inst
*, const aarch64_insn
, bfd_vma
,
188 bfd_boolean
, aarch64_operand_error
*, aarch64_instr_sequence
*);
192 #define OPD_F_HAS_INSERTER 0x00000001
193 #define OPD_F_HAS_EXTRACTOR 0x00000002
194 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
195 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
196 value by 2 to get the value
197 of an immediate operand. */
198 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
199 #define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
200 #define OPD_F_OD_LSB 5
201 #define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
203 /* Register flags. */
206 #define F_DEPRECATED (1 << 0) /* Deprecated system register. */
209 #define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
212 #define F_HASXT (1 << 2) /* System instruction register <Xt>
216 #define F_REG_READ (1 << 3) /* Register can only be used to read values
220 #define F_REG_WRITE (1 << 4) /* Register can only be written to but not
223 /* HINT operand flags. */
224 #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
226 /* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
227 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
228 #define HINT_FLAG(val) (val >> 8)
229 #define HINT_VAL(val) (val & 0xff)
231 static inline bfd_boolean
232 operand_has_inserter (const aarch64_operand
*operand
)
234 return (operand
->flags
& OPD_F_HAS_INSERTER
) ? TRUE
: FALSE
;
237 static inline bfd_boolean
238 operand_has_extractor (const aarch64_operand
*operand
)
240 return (operand
->flags
& OPD_F_HAS_EXTRACTOR
) ? TRUE
: FALSE
;
243 static inline bfd_boolean
244 operand_need_sign_extension (const aarch64_operand
*operand
)
246 return (operand
->flags
& OPD_F_SEXT
) ? TRUE
: FALSE
;
249 static inline bfd_boolean
250 operand_need_shift_by_two (const aarch64_operand
*operand
)
252 return (operand
->flags
& OPD_F_SHIFT_BY_2
) ? TRUE
: FALSE
;
255 static inline bfd_boolean
256 operand_maybe_stack_pointer (const aarch64_operand
*operand
)
258 return (operand
->flags
& OPD_F_MAYBE_SP
) ? TRUE
: FALSE
;
261 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
262 static inline unsigned int
263 get_operand_specific_data (const aarch64_operand
*operand
)
265 return (operand
->flags
& OPD_F_OD_MASK
) >> OPD_F_OD_LSB
;
268 /* Return the width of field number N of operand *OPERAND. */
269 static inline unsigned
270 get_operand_field_width (const aarch64_operand
*operand
, unsigned n
)
272 assert (operand
->fields
[n
] != FLD_NIL
);
273 return fields
[operand
->fields
[n
]].width
;
276 /* Return the total width of the operand *OPERAND. */
277 static inline unsigned
278 get_operand_fields_width (const aarch64_operand
*operand
)
282 while (operand
->fields
[i
] != FLD_NIL
)
283 width
+= fields
[operand
->fields
[i
++]].width
;
284 assert (width
> 0 && width
< 32);
288 static inline const aarch64_operand
*
289 get_operand_from_code (enum aarch64_opnd code
)
291 return aarch64_operands
+ code
;
294 /* Operand qualifier and operand constraint checking. */
296 int aarch64_match_operands_constraint (aarch64_inst
*,
297 aarch64_operand_error
*);
299 /* Operand qualifier related functions. */
300 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t
);
301 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t
);
302 aarch64_insn
aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t
);
303 int aarch64_find_best_match (const aarch64_inst
*,
304 const aarch64_opnd_qualifier_seq_t
*,
305 int, aarch64_opnd_qualifier_t
*);
308 reset_operand_qualifier (aarch64_inst
*inst
, int idx
)
310 assert (idx
>=0 && idx
< aarch64_num_of_operands (inst
->opcode
));
311 inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
314 /* Inline functions operating on instruction bit-field(s). */
316 /* Generate a mask that has WIDTH number of consecutive 1s. */
318 static inline aarch64_insn
321 return ((aarch64_insn
) 1 << width
) - 1;
324 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
326 gen_sub_field (enum aarch64_field_kind kind
, int lsb_rel
, int width
, aarch64_field
*ret
)
328 const aarch64_field
*field
= &fields
[kind
];
329 if (lsb_rel
< 0 || width
<= 0 || lsb_rel
+ width
> field
->width
)
331 ret
->lsb
= field
->lsb
+ lsb_rel
;
336 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
340 insert_field_2 (const aarch64_field
*field
, aarch64_insn
*code
,
341 aarch64_insn value
, aarch64_insn mask
)
343 assert (field
->width
< 32 && field
->width
>= 1 && field
->lsb
>= 0
344 && field
->lsb
+ field
->width
<= 32);
345 value
&= gen_mask (field
->width
);
346 value
<<= field
->lsb
;
347 /* In some opcodes, field can be part of the base opcode, e.g. the size
348 field in FADD. The following helps avoid corrupt the base opcode. */
353 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
354 mask of the opcode. */
356 static inline aarch64_insn
357 extract_field_2 (const aarch64_field
*field
, aarch64_insn code
,
361 /* Clear any bit that is a part of the base opcode. */
363 value
= (code
>> field
->lsb
) & gen_mask (field
->width
);
367 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
371 insert_field (enum aarch64_field_kind kind
, aarch64_insn
*code
,
372 aarch64_insn value
, aarch64_insn mask
)
374 insert_field_2 (&fields
[kind
], code
, value
, mask
);
377 /* Extract field KIND of CODE and return the value. MASK can be zero or the
378 base mask of the opcode. */
380 static inline aarch64_insn
381 extract_field (enum aarch64_field_kind kind
, aarch64_insn code
,
384 return extract_field_2 (&fields
[kind
], code
, mask
);
388 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...);
390 /* Inline functions selecting operand to do the encoding/decoding for a
391 certain instruction bit-field. */
393 /* Select the operand to do the encoding/decoding of the 'sf' field.
394 The heuristic-based rule is that the result operand is respected more. */
397 select_operand_for_sf_field_coding (const aarch64_opcode
*opcode
)
400 if (aarch64_get_operand_class (opcode
->operands
[0])
401 == AARCH64_OPND_CLASS_INT_REG
)
404 else if (aarch64_get_operand_class (opcode
->operands
[1])
405 == AARCH64_OPND_CLASS_INT_REG
)
406 /* e.g. float2fix. */
409 { assert (0); abort (); }
413 /* Select the operand to do the encoding/decoding of the 'type' field in
414 the floating-point instructions.
415 The heuristic-based rule is that the source operand is respected more. */
418 select_operand_for_fptype_field_coding (const aarch64_opcode
*opcode
)
421 if (aarch64_get_operand_class (opcode
->operands
[1])
422 == AARCH64_OPND_CLASS_FP_REG
)
425 else if (aarch64_get_operand_class (opcode
->operands
[0])
426 == AARCH64_OPND_CLASS_FP_REG
)
427 /* e.g. float2fix. */
430 { assert (0); abort (); }
434 /* Select the operand to do the encoding/decoding of the 'size' field in
435 the AdvSIMD scalar instructions.
436 The heuristic-based rule is that the destination operand is respected
440 select_operand_for_scalar_size_field_coding (const aarch64_opcode
*opcode
)
442 int src_size
= 0, dst_size
= 0;
443 if (aarch64_get_operand_class (opcode
->operands
[0])
444 == AARCH64_OPND_CLASS_SISD_REG
)
445 dst_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][0]);
446 if (aarch64_get_operand_class (opcode
->operands
[1])
447 == AARCH64_OPND_CLASS_SISD_REG
)
448 src_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][1]);
449 if (src_size
== dst_size
&& src_size
== 0)
450 { assert (0); abort (); }
451 /* When the result is not a sisd register or it is a long operantion. */
452 if (dst_size
== 0 || dst_size
== src_size
<< 1)
458 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
459 the AdvSIMD instructions. */
461 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode
*);
465 aarch64_insn
aarch64_get_operand_modifier_value (enum aarch64_modifier_kind
);
466 enum aarch64_modifier_kind
467 aarch64_get_operand_modifier_from_value (aarch64_insn
, bfd_boolean
);
470 bfd_boolean
aarch64_wide_constant_p (int64_t, int, unsigned int *);
471 bfd_boolean
aarch64_logical_immediate_p (uint64_t, int, aarch64_insn
*);
472 int aarch64_shrink_expanded_imm8 (uint64_t);
474 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
476 copy_operand_info (aarch64_inst
*inst
, int dst
, int src
)
478 assert (dst
>= 0 && src
>= 0 && dst
< AARCH64_MAX_OPND_NUM
479 && src
< AARCH64_MAX_OPND_NUM
);
480 memcpy (&inst
->operands
[dst
], &inst
->operands
[src
],
481 sizeof (aarch64_opnd_info
));
482 inst
->operands
[dst
].idx
= dst
;
485 /* A primitive log caculator. */
487 static inline unsigned int
488 get_logsz (unsigned int size
)
490 const unsigned char ls
[16] =
491 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
497 assert (ls
[size
- 1] != (unsigned char)-1);
501 #endif /* OPCODES_AARCH64_OPC_H */