1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2019 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
25 #include "opcode/aarch64.h"
27 /* Instruction fields.
28 Keep synced with fields. */
29 enum aarch64_field_kind
158 /* Field description. */
165 typedef struct aarch64_field aarch64_field
;
167 extern const aarch64_field fields
[];
169 /* Operand description. */
171 struct aarch64_operand
173 enum aarch64_operand_class op_class
;
175 /* Name of the operand code; used mainly for the purpose of internal
181 /* The associated instruction bit-fields; no operand has more than 4
183 enum aarch64_field_kind fields
[4];
185 /* Brief description */
189 typedef struct aarch64_operand aarch64_operand
;
191 extern const aarch64_operand aarch64_operands
[];
194 verify_constraints (const struct aarch64_inst
*, const aarch64_insn
, bfd_vma
,
195 bfd_boolean
, aarch64_operand_error
*, aarch64_instr_sequence
*);
199 #define OPD_F_HAS_INSERTER 0x00000001
200 #define OPD_F_HAS_EXTRACTOR 0x00000002
201 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
202 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
203 value by 2 to get the value
204 of an immediate operand. */
205 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
206 #define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
207 #define OPD_F_OD_LSB 5
208 #define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
209 #define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
210 value by 4 to get the value
211 of an immediate operand. */
214 /* Register flags. */
217 #define F_DEPRECATED (1 << 0) /* Deprecated system register. */
220 #define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
223 #define F_HASXT (1 << 2) /* System instruction register <Xt>
227 #define F_REG_READ (1 << 3) /* Register can only be used to read values
231 #define F_REG_WRITE (1 << 4) /* Register can only be written to but not
234 /* HINT operand flags. */
235 #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
237 /* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
238 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
239 #define HINT_FLAG(val) (val >> 8)
240 #define HINT_VAL(val) (val & 0xff)
242 static inline bfd_boolean
243 operand_has_inserter (const aarch64_operand
*operand
)
245 return (operand
->flags
& OPD_F_HAS_INSERTER
) ? TRUE
: FALSE
;
248 static inline bfd_boolean
249 operand_has_extractor (const aarch64_operand
*operand
)
251 return (operand
->flags
& OPD_F_HAS_EXTRACTOR
) ? TRUE
: FALSE
;
254 static inline bfd_boolean
255 operand_need_sign_extension (const aarch64_operand
*operand
)
257 return (operand
->flags
& OPD_F_SEXT
) ? TRUE
: FALSE
;
260 static inline bfd_boolean
261 operand_need_shift_by_two (const aarch64_operand
*operand
)
263 return (operand
->flags
& OPD_F_SHIFT_BY_2
) ? TRUE
: FALSE
;
266 static inline bfd_boolean
267 operand_need_shift_by_four (const aarch64_operand
*operand
)
269 return (operand
->flags
& OPD_F_SHIFT_BY_4
) ? TRUE
: FALSE
;
272 static inline bfd_boolean
273 operand_maybe_stack_pointer (const aarch64_operand
*operand
)
275 return (operand
->flags
& OPD_F_MAYBE_SP
) ? TRUE
: FALSE
;
278 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
279 static inline unsigned int
280 get_operand_specific_data (const aarch64_operand
*operand
)
282 return (operand
->flags
& OPD_F_OD_MASK
) >> OPD_F_OD_LSB
;
285 /* Return the width of field number N of operand *OPERAND. */
286 static inline unsigned
287 get_operand_field_width (const aarch64_operand
*operand
, unsigned n
)
289 assert (operand
->fields
[n
] != FLD_NIL
);
290 return fields
[operand
->fields
[n
]].width
;
293 /* Return the total width of the operand *OPERAND. */
294 static inline unsigned
295 get_operand_fields_width (const aarch64_operand
*operand
)
299 while (operand
->fields
[i
] != FLD_NIL
)
300 width
+= fields
[operand
->fields
[i
++]].width
;
301 assert (width
> 0 && width
< 32);
305 static inline const aarch64_operand
*
306 get_operand_from_code (enum aarch64_opnd code
)
308 return aarch64_operands
+ code
;
311 /* Operand qualifier and operand constraint checking. */
313 int aarch64_match_operands_constraint (aarch64_inst
*,
314 aarch64_operand_error
*);
316 /* Operand qualifier related functions. */
317 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t
);
318 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t
);
319 aarch64_insn
aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t
);
320 int aarch64_find_best_match (const aarch64_inst
*,
321 const aarch64_opnd_qualifier_seq_t
*,
322 int, aarch64_opnd_qualifier_t
*);
325 reset_operand_qualifier (aarch64_inst
*inst
, int idx
)
327 assert (idx
>=0 && idx
< aarch64_num_of_operands (inst
->opcode
));
328 inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
331 /* Inline functions operating on instruction bit-field(s). */
333 /* Generate a mask that has WIDTH number of consecutive 1s. */
335 static inline aarch64_insn
338 return ((aarch64_insn
) 1 << width
) - 1;
341 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
343 gen_sub_field (enum aarch64_field_kind kind
, int lsb_rel
, int width
, aarch64_field
*ret
)
345 const aarch64_field
*field
= &fields
[kind
];
346 if (lsb_rel
< 0 || width
<= 0 || lsb_rel
+ width
> field
->width
)
348 ret
->lsb
= field
->lsb
+ lsb_rel
;
353 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
357 insert_field_2 (const aarch64_field
*field
, aarch64_insn
*code
,
358 aarch64_insn value
, aarch64_insn mask
)
360 assert (field
->width
< 32 && field
->width
>= 1 && field
->lsb
>= 0
361 && field
->lsb
+ field
->width
<= 32);
362 value
&= gen_mask (field
->width
);
363 value
<<= field
->lsb
;
364 /* In some opcodes, field can be part of the base opcode, e.g. the size
365 field in FADD. The following helps avoid corrupt the base opcode. */
370 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
371 mask of the opcode. */
373 static inline aarch64_insn
374 extract_field_2 (const aarch64_field
*field
, aarch64_insn code
,
378 /* Clear any bit that is a part of the base opcode. */
380 value
= (code
>> field
->lsb
) & gen_mask (field
->width
);
384 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
388 insert_field (enum aarch64_field_kind kind
, aarch64_insn
*code
,
389 aarch64_insn value
, aarch64_insn mask
)
391 insert_field_2 (&fields
[kind
], code
, value
, mask
);
394 /* Extract field KIND of CODE and return the value. MASK can be zero or the
395 base mask of the opcode. */
397 static inline aarch64_insn
398 extract_field (enum aarch64_field_kind kind
, aarch64_insn code
,
401 return extract_field_2 (&fields
[kind
], code
, mask
);
405 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...);
407 /* Inline functions selecting operand to do the encoding/decoding for a
408 certain instruction bit-field. */
410 /* Select the operand to do the encoding/decoding of the 'sf' field.
411 The heuristic-based rule is that the result operand is respected more. */
414 select_operand_for_sf_field_coding (const aarch64_opcode
*opcode
)
417 if (aarch64_get_operand_class (opcode
->operands
[0])
418 == AARCH64_OPND_CLASS_INT_REG
)
421 else if (aarch64_get_operand_class (opcode
->operands
[1])
422 == AARCH64_OPND_CLASS_INT_REG
)
423 /* e.g. float2fix. */
426 { assert (0); abort (); }
430 /* Select the operand to do the encoding/decoding of the 'type' field in
431 the floating-point instructions.
432 The heuristic-based rule is that the source operand is respected more. */
435 select_operand_for_fptype_field_coding (const aarch64_opcode
*opcode
)
438 if (aarch64_get_operand_class (opcode
->operands
[1])
439 == AARCH64_OPND_CLASS_FP_REG
)
442 else if (aarch64_get_operand_class (opcode
->operands
[0])
443 == AARCH64_OPND_CLASS_FP_REG
)
444 /* e.g. float2fix. */
447 { assert (0); abort (); }
451 /* Select the operand to do the encoding/decoding of the 'size' field in
452 the AdvSIMD scalar instructions.
453 The heuristic-based rule is that the destination operand is respected
457 select_operand_for_scalar_size_field_coding (const aarch64_opcode
*opcode
)
459 int src_size
= 0, dst_size
= 0;
460 if (aarch64_get_operand_class (opcode
->operands
[0])
461 == AARCH64_OPND_CLASS_SISD_REG
)
462 dst_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][0]);
463 if (aarch64_get_operand_class (opcode
->operands
[1])
464 == AARCH64_OPND_CLASS_SISD_REG
)
465 src_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][1]);
466 if (src_size
== dst_size
&& src_size
== 0)
467 { assert (0); abort (); }
468 /* When the result is not a sisd register or it is a long operantion. */
469 if (dst_size
== 0 || dst_size
== src_size
<< 1)
475 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
476 the AdvSIMD instructions. */
478 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode
*);
482 aarch64_insn
aarch64_get_operand_modifier_value (enum aarch64_modifier_kind
);
483 enum aarch64_modifier_kind
484 aarch64_get_operand_modifier_from_value (aarch64_insn
, bfd_boolean
);
487 bfd_boolean
aarch64_wide_constant_p (int64_t, int, unsigned int *);
488 bfd_boolean
aarch64_logical_immediate_p (uint64_t, int, aarch64_insn
*);
489 int aarch64_shrink_expanded_imm8 (uint64_t);
491 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
493 copy_operand_info (aarch64_inst
*inst
, int dst
, int src
)
495 assert (dst
>= 0 && src
>= 0 && dst
< AARCH64_MAX_OPND_NUM
496 && src
< AARCH64_MAX_OPND_NUM
);
497 memcpy (&inst
->operands
[dst
], &inst
->operands
[src
],
498 sizeof (aarch64_opnd_info
));
499 inst
->operands
[dst
].idx
= dst
;
502 /* A primitive log caculator. */
504 static inline unsigned int
505 get_logsz (unsigned int size
)
507 const unsigned char ls
[16] =
508 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
514 assert (ls
[size
- 1] != (unsigned char)-1);
518 #endif /* OPCODES_AARCH64_OPC_H */