opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2020 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm6_2,
  71   FLD_imm4,
  72   FLD_imm4_2,
  73   FLD_imm4_3,
  74   FLD_imm5,
  75   FLD_imm7,
  76   FLD_imm8,
  77   FLD_imm9,
  78   FLD_imm12,
  79   FLD_imm14,
  80   FLD_imm16,
  81   FLD_imm16_2,
  82   FLD_imm26,
  83   FLD_imms,
  84   FLD_immr,
  85   FLD_immb,
  86   FLD_immh,
  87   FLD_S_imm10,
  88   FLD_N,
  89   FLD_index,
  90   FLD_index2,
  91   FLD_sf,
  92   FLD_lse_sz,
  93   FLD_H,
  94   FLD_L,
  95   FLD_M,
  96   FLD_b5,
  97   FLD_b40,
  98   FLD_scale,
  99   FLD_SVE_M_4,
 100   FLD_SVE_M_14,
 101   FLD_SVE_M_16,
 102   FLD_SVE_N,
 103   FLD_SVE_Pd,
 104   FLD_SVE_Pg3,
 105   FLD_SVE_Pg4_5,
 106   FLD_SVE_Pg4_10,
 107   FLD_SVE_Pg4_16,
 108   FLD_SVE_Pm,
 109   FLD_SVE_Pn,
 110   FLD_SVE_Pt,
 111   FLD_SVE_Rm,
 112   FLD_SVE_Rn,
 113   FLD_SVE_Vd,
 114   FLD_SVE_Vm,
 115   FLD_SVE_Vn,
 116   FLD_SVE_Za_5,
 117   FLD_SVE_Za_16,
 118   FLD_SVE_Zd,
 119   FLD_SVE_Zm_5,
 120   FLD_SVE_Zm_16,
 121   FLD_SVE_Zn,
 122   FLD_SVE_Zt,
 123   FLD_SVE_i1,
 124   FLD_SVE_i3h,
 125   FLD_SVE_i3l,
 126   FLD_SVE_i3h2,
 127   FLD_SVE_i2h,
 128   FLD_SVE_imm3,
 129   FLD_SVE_imm4,
 130   FLD_SVE_imm5,
 131   FLD_SVE_imm5b,
 132   FLD_SVE_imm6,
 133   FLD_SVE_imm7,
 134   FLD_SVE_imm8,
 135   FLD_SVE_imm9,
 136   FLD_SVE_immr,
 137   FLD_SVE_imms,
 138   FLD_SVE_msz,
 139   FLD_SVE_pattern,
 140   FLD_SVE_prfop,
 141   FLD_SVE_rot1,
 142   FLD_SVE_rot2,
 143   FLD_SVE_rot3,
 144   FLD_SVE_sz,
 145   FLD_SVE_size,
 146   FLD_SVE_sz2,
 147   FLD_SVE_tsz,
 148   FLD_SVE_tszh,
 149   FLD_SVE_tszl_8,
 150   FLD_SVE_tszl_19,
 151   FLD_SVE_xs_14,
 152   FLD_SVE_xs_22,
 153   FLD_rotate1,
 154   FLD_rotate2,
 155   FLD_rotate3,
 156   FLD_SM3_imm2,
 157   FLD_sz
 158 };
 159
 160 /* Field description.  */
 161 struct aarch64_field
 162 {
 163   int lsb;
 164   int width;
 165 };
 166
 167 typedef struct aarch64_field aarch64_field;
 168
 169 extern const aarch64_field fields[];
 170 \f
 171 /* Operand description.  */
 172
 173 struct aarch64_operand
 174 {
 175   enum aarch64_operand_class op_class;
 176
 177   /* Name of the operand code; used mainly for the purpose of internal
 178      debugging.  */
 179   const char *name;
 180
 181   unsigned int flags;
 182
 183   /* The associated instruction bit-fields; no operand has more than 4
 184      bit-fields */
 185   enum aarch64_field_kind fields[4];
 186
 187   /* Brief description */
 188   const char *desc;
 189 };
 190
 191 typedef struct aarch64_operand aarch64_operand;
 192
 193 extern const aarch64_operand aarch64_operands[];
 194
 195 enum err_type
 196 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 197                     bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
 198
 199 /* Operand flags.  */
 200
 201 #define OPD_F_HAS_INSERTER      0x00000001
 202 #define OPD_F_HAS_EXTRACTOR     0x00000002
 203 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 204 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 205                                                    value by 2 to get the value
 206                                                    of an immediate operand.  */
 207 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 208 #define OPD_F_OD_MASK           0x000000e0      /* Operand-dependent data.  */
 209 #define OPD_F_OD_LSB            5
 210 #define OPD_F_NO_ZR             0x00000100      /* ZR index not allowed.  */
 211 #define OPD_F_SHIFT_BY_4        0x00000200      /* Need to left shift the field
 212                                                    value by 4 to get the value
 213                                                    of an immediate operand.  */
 214
 215
 216 /* Register flags.  */
 217
 218 #undef F_DEPRECATED
 219 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 220
 221 #undef F_ARCHEXT
 222 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 223
 224 #undef F_HASXT
 225 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 226                                      operand.  */
 227
 228 #undef F_REG_READ
 229 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 230                                      out of.  */
 231
 232 #undef F_REG_WRITE
 233 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 234                                      read from.  */
 235
 236 /* HINT operand flags.  */
 237 #define HINT_OPD_F_NOPRINT      (1 << 0)  /* Should not be printed.  */
 238
 239 /* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
 240 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
 241 #define HINT_FLAG(val) (val >> 8)
 242 #define HINT_VAL(val) (val & 0xff)
 243
 244 static inline bfd_boolean
 245 operand_has_inserter (const aarch64_operand *operand)
 246 {
 247   return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
 248 }
 249
 250 static inline bfd_boolean
 251 operand_has_extractor (const aarch64_operand *operand)
 252 {
 253   return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
 254 }
 255
 256 static inline bfd_boolean
 257 operand_need_sign_extension (const aarch64_operand *operand)
 258 {
 259   return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
 260 }
 261
 262 static inline bfd_boolean
 263 operand_need_shift_by_two (const aarch64_operand *operand)
 264 {
 265   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 266 }
 267
 268 static inline bfd_boolean
 269 operand_need_shift_by_four (const aarch64_operand *operand)
 270 {
 271   return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
 272 }
 273
 274 static inline bfd_boolean
 275 operand_maybe_stack_pointer (const aarch64_operand *operand)
 276 {
 277   return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
 278 }
 279
 280 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 281 static inline unsigned int
 282 get_operand_specific_data (const aarch64_operand *operand)
 283 {
 284   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 285 }
 286
 287 /* Return the width of field number N of operand *OPERAND.  */
 288 static inline unsigned
 289 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 290 {
 291   assert (operand->fields[n] != FLD_NIL);
 292   return fields[operand->fields[n]].width;
 293 }
 294
 295 /* Return the total width of the operand *OPERAND.  */
 296 static inline unsigned
 297 get_operand_fields_width (const aarch64_operand *operand)
 298 {
 299   int i = 0;
 300   unsigned width = 0;
 301   while (operand->fields[i] != FLD_NIL)
 302     width += fields[operand->fields[i++]].width;
 303   assert (width > 0 && width < 32);
 304   return width;
 305 }
 306
 307 static inline const aarch64_operand *
 308 get_operand_from_code (enum aarch64_opnd code)
 309 {
 310   return aarch64_operands + code;
 311 }
 312 \f
 313 /* Operand qualifier and operand constraint checking.  */
 314
 315 int aarch64_match_operands_constraint (aarch64_inst *,
 316                                        aarch64_operand_error *);
 317
 318 /* Operand qualifier related functions.  */
 319 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 320 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 321 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 322 int aarch64_find_best_match (const aarch64_inst *,
 323                              const aarch64_opnd_qualifier_seq_t *,
 324                              int, aarch64_opnd_qualifier_t *);
 325
 326 static inline void
 327 reset_operand_qualifier (aarch64_inst *inst, int idx)
 328 {
 329   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 330   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 331 }
 332 \f
 333 /* Inline functions operating on instruction bit-field(s).  */
 334
 335 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 336
 337 static inline aarch64_insn
 338 gen_mask (int width)
 339 {
 340   return ((aarch64_insn) 1 << width) - 1;
 341 }
 342
 343 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 344 static inline int
 345 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 346 {
 347   const aarch64_field *field = &fields[kind];
 348   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 349     return 0;
 350   ret->lsb = field->lsb + lsb_rel;
 351   ret->width = width;
 352   return 1;
 353 }
 354
 355 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 356    of the opcode.  */
 357
 358 static inline void
 359 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 360                 aarch64_insn value, aarch64_insn mask)
 361 {
 362   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 363           && field->lsb + field->width <= 32);
 364   value &= gen_mask (field->width);
 365   value <<= field->lsb;
 366   /* In some opcodes, field can be part of the base opcode, e.g. the size
 367      field in FADD.  The following helps avoid corrupt the base opcode.  */
 368   value &= ~mask;
 369   *code |= value;
 370 }
 371
 372 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 373    mask of the opcode.  */
 374
 375 static inline aarch64_insn
 376 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 377                  aarch64_insn mask)
 378 {
 379   aarch64_insn value;
 380   /* Clear any bit that is a part of the base opcode.  */
 381   code &= ~mask;
 382   value = (code >> field->lsb) & gen_mask (field->width);
 383   return value;
 384 }
 385
 386 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 387    of the opcode.  */
 388
 389 static inline void
 390 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 391               aarch64_insn value, aarch64_insn mask)
 392 {
 393   insert_field_2 (&fields[kind], code, value, mask);
 394 }
 395
 396 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 397    base mask of the opcode.  */
 398
 399 static inline aarch64_insn
 400 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 401                aarch64_insn mask)
 402 {
 403   return extract_field_2 (&fields[kind], code, mask);
 404 }
 405
 406 extern aarch64_insn
 407 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 408 \f
 409 /* Inline functions selecting operand to do the encoding/decoding for a
 410    certain instruction bit-field.  */
 411
 412 /* Select the operand to do the encoding/decoding of the 'sf' field.
 413    The heuristic-based rule is that the result operand is respected more.  */
 414
 415 static inline int
 416 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 417 {
 418   int idx = -1;
 419   if (aarch64_get_operand_class (opcode->operands[0])
 420       == AARCH64_OPND_CLASS_INT_REG)
 421     /* normal case.  */
 422     idx = 0;
 423   else if (aarch64_get_operand_class (opcode->operands[1])
 424            == AARCH64_OPND_CLASS_INT_REG)
 425     /* e.g. float2fix.  */
 426     idx = 1;
 427   else
 428     { assert (0); abort (); }
 429   return idx;
 430 }
 431
 432 /* Select the operand to do the encoding/decoding of the 'type' field in
 433    the floating-point instructions.
 434    The heuristic-based rule is that the source operand is respected more.  */
 435
 436 static inline int
 437 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 438 {
 439   int idx;
 440   if (aarch64_get_operand_class (opcode->operands[1])
 441       == AARCH64_OPND_CLASS_FP_REG)
 442     /* normal case.  */
 443     idx = 1;
 444   else if (aarch64_get_operand_class (opcode->operands[0])
 445            == AARCH64_OPND_CLASS_FP_REG)
 446     /* e.g. float2fix.  */
 447     idx = 0;
 448   else
 449     { assert (0); abort (); }
 450   return idx;
 451 }
 452
 453 /* Select the operand to do the encoding/decoding of the 'size' field in
 454    the AdvSIMD scalar instructions.
 455    The heuristic-based rule is that the destination operand is respected
 456    more.  */
 457
 458 static inline int
 459 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 460 {
 461   int src_size = 0, dst_size = 0;
 462   if (aarch64_get_operand_class (opcode->operands[0])
 463       == AARCH64_OPND_CLASS_SISD_REG)
 464     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 465   if (aarch64_get_operand_class (opcode->operands[1])
 466       == AARCH64_OPND_CLASS_SISD_REG)
 467     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 468   if (src_size == dst_size && src_size == 0)
 469     { assert (0); abort (); }
 470   /* When the result is not a sisd register or it is a long operantion.  */
 471   if (dst_size == 0 || dst_size == src_size << 1)
 472     return 1;
 473   else
 474     return 0;
 475 }
 476
 477 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 478    the AdvSIMD instructions.  */
 479
 480 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 481 \f
 482 /* Miscellaneous.  */
 483
 484 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 485 enum aarch64_modifier_kind
 486 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 487
 488
 489 bfd_boolean aarch64_wide_constant_p (uint64_t, int, unsigned int *);
 490 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 491 int aarch64_shrink_expanded_imm8 (uint64_t);
 492
 493 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 494 static inline void
 495 copy_operand_info (aarch64_inst *inst, int dst, int src)
 496 {
 497   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 498           && src < AARCH64_MAX_OPND_NUM);
 499   memcpy (&inst->operands[dst], &inst->operands[src],
 500           sizeof (aarch64_opnd_info));
 501   inst->operands[dst].idx = dst;
 502 }
 503
 504 /* A primitive log caculator.  */
 505
 506 static inline unsigned int
 507 get_logsz (unsigned int size)
 508 {
 509   const unsigned char ls[16] =
 510     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 511   if (size > 16)
 512     {
 513       assert (0);
 514       return -1;
 515     }
 516   assert (ls[size - 1] != (unsigned char)-1);
 517   return ls[size - 1];
 518 }
 519
 520 #endif /* OPCODES_AARCH64_OPC_H */