opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2019 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm6_2,
  71   FLD_imm4,
  72   FLD_imm4_2,
  73   FLD_imm4_3,
  74   FLD_imm5,
  75   FLD_imm7,
  76   FLD_imm8,
  77   FLD_imm9,
  78   FLD_imm12,
  79   FLD_imm14,
  80   FLD_imm16,
  81   FLD_imm26,
  82   FLD_imms,
  83   FLD_immr,
  84   FLD_immb,
  85   FLD_immh,
  86   FLD_S_imm10,
  87   FLD_N,
  88   FLD_index,
  89   FLD_index2,
  90   FLD_sf,
  91   FLD_lse_sz,
  92   FLD_H,
  93   FLD_L,
  94   FLD_M,
  95   FLD_b5,
  96   FLD_b40,
  97   FLD_scale,
  98   FLD_SVE_M_4,
  99   FLD_SVE_M_14,
 100   FLD_SVE_M_16,
 101   FLD_SVE_N,
 102   FLD_SVE_Pd,
 103   FLD_SVE_Pg3,
 104   FLD_SVE_Pg4_5,
 105   FLD_SVE_Pg4_10,
 106   FLD_SVE_Pg4_16,
 107   FLD_SVE_Pm,
 108   FLD_SVE_Pn,
 109   FLD_SVE_Pt,
 110   FLD_SVE_Rm,
 111   FLD_SVE_Rn,
 112   FLD_SVE_Vd,
 113   FLD_SVE_Vm,
 114   FLD_SVE_Vn,
 115   FLD_SVE_Za_5,
 116   FLD_SVE_Za_16,
 117   FLD_SVE_Zd,
 118   FLD_SVE_Zm_5,
 119   FLD_SVE_Zm_16,
 120   FLD_SVE_Zn,
 121   FLD_SVE_Zt,
 122   FLD_SVE_i1,
 123   FLD_SVE_i3h,
 124   FLD_SVE_i3l,
 125   FLD_SVE_i3h2,
 126   FLD_SVE_i2h,
 127   FLD_SVE_imm3,
 128   FLD_SVE_imm4,
 129   FLD_SVE_imm5,
 130   FLD_SVE_imm5b,
 131   FLD_SVE_imm6,
 132   FLD_SVE_imm7,
 133   FLD_SVE_imm8,
 134   FLD_SVE_imm9,
 135   FLD_SVE_immr,
 136   FLD_SVE_imms,
 137   FLD_SVE_msz,
 138   FLD_SVE_pattern,
 139   FLD_SVE_prfop,
 140   FLD_SVE_rot1,
 141   FLD_SVE_rot2,
 142   FLD_SVE_rot3,
 143   FLD_SVE_sz,
 144   FLD_SVE_size,
 145   FLD_SVE_sz2,
 146   FLD_SVE_tsz,
 147   FLD_SVE_tszh,
 148   FLD_SVE_tszl_8,
 149   FLD_SVE_tszl_19,
 150   FLD_SVE_xs_14,
 151   FLD_SVE_xs_22,
 152   FLD_rotate1,
 153   FLD_rotate2,
 154   FLD_rotate3,
 155   FLD_SM3_imm2,
 156   FLD_sz
 157 };
 158
 159 /* Field description.  */
 160 struct aarch64_field
 161 {
 162   int lsb;
 163   int width;
 164 };
 165
 166 typedef struct aarch64_field aarch64_field;
 167
 168 extern const aarch64_field fields[];
 169 \f
 170 /* Operand description.  */
 171
 172 struct aarch64_operand
 173 {
 174   enum aarch64_operand_class op_class;
 175
 176   /* Name of the operand code; used mainly for the purpose of internal
 177      debugging.  */
 178   const char *name;
 179
 180   unsigned int flags;
 181
 182   /* The associated instruction bit-fields; no operand has more than 4
 183      bit-fields */
 184   enum aarch64_field_kind fields[4];
 185
 186   /* Brief description */
 187   const char *desc;
 188 };
 189
 190 typedef struct aarch64_operand aarch64_operand;
 191
 192 extern const aarch64_operand aarch64_operands[];
 193
 194 enum err_type
 195 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 196                     bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
 197
 198 /* Operand flags.  */
 199
 200 #define OPD_F_HAS_INSERTER      0x00000001
 201 #define OPD_F_HAS_EXTRACTOR     0x00000002
 202 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 203 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 204                                                    value by 2 to get the value
 205                                                    of an immediate operand.  */
 206 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 207 #define OPD_F_OD_MASK           0x000000e0      /* Operand-dependent data.  */
 208 #define OPD_F_OD_LSB            5
 209 #define OPD_F_NO_ZR             0x00000100      /* ZR index not allowed.  */
 210 #define OPD_F_SHIFT_BY_4        0x00000200      /* Need to left shift the field
 211                                                    value by 4 to get the value
 212                                                    of an immediate operand.  */
 213
 214
 215 /* Register flags.  */
 216
 217 #undef F_DEPRECATED
 218 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 219
 220 #undef F_ARCHEXT
 221 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 222
 223 #undef F_HASXT
 224 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 225                                      operand.  */
 226
 227 #undef F_REG_READ
 228 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 229                                      out of.  */
 230
 231 #undef F_REG_WRITE
 232 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 233                                      read from.  */
 234
 235 /* HINT operand flags.  */
 236 #define HINT_OPD_F_NOPRINT      (1 << 0)  /* Should not be printed.  */
 237
 238 /* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
 239 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
 240 #define HINT_FLAG(val) (val >> 8)
 241 #define HINT_VAL(val) (val & 0xff)
 242
 243 static inline bfd_boolean
 244 operand_has_inserter (const aarch64_operand *operand)
 245 {
 246   return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
 247 }
 248
 249 static inline bfd_boolean
 250 operand_has_extractor (const aarch64_operand *operand)
 251 {
 252   return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
 253 }
 254
 255 static inline bfd_boolean
 256 operand_need_sign_extension (const aarch64_operand *operand)
 257 {
 258   return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
 259 }
 260
 261 static inline bfd_boolean
 262 operand_need_shift_by_two (const aarch64_operand *operand)
 263 {
 264   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 265 }
 266
 267 static inline bfd_boolean
 268 operand_need_shift_by_four (const aarch64_operand *operand)
 269 {
 270   return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
 271 }
 272
 273 static inline bfd_boolean
 274 operand_maybe_stack_pointer (const aarch64_operand *operand)
 275 {
 276   return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
 277 }
 278
 279 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 280 static inline unsigned int
 281 get_operand_specific_data (const aarch64_operand *operand)
 282 {
 283   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 284 }
 285
 286 /* Return the width of field number N of operand *OPERAND.  */
 287 static inline unsigned
 288 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 289 {
 290   assert (operand->fields[n] != FLD_NIL);
 291   return fields[operand->fields[n]].width;
 292 }
 293
 294 /* Return the total width of the operand *OPERAND.  */
 295 static inline unsigned
 296 get_operand_fields_width (const aarch64_operand *operand)
 297 {
 298   int i = 0;
 299   unsigned width = 0;
 300   while (operand->fields[i] != FLD_NIL)
 301     width += fields[operand->fields[i++]].width;
 302   assert (width > 0 && width < 32);
 303   return width;
 304 }
 305
 306 static inline const aarch64_operand *
 307 get_operand_from_code (enum aarch64_opnd code)
 308 {
 309   return aarch64_operands + code;
 310 }
 311 \f
 312 /* Operand qualifier and operand constraint checking.  */
 313
 314 int aarch64_match_operands_constraint (aarch64_inst *,
 315                                        aarch64_operand_error *);
 316
 317 /* Operand qualifier related functions.  */
 318 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 319 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 320 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 321 int aarch64_find_best_match (const aarch64_inst *,
 322                              const aarch64_opnd_qualifier_seq_t *,
 323                              int, aarch64_opnd_qualifier_t *);
 324
 325 static inline void
 326 reset_operand_qualifier (aarch64_inst *inst, int idx)
 327 {
 328   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 329   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 330 }
 331 \f
 332 /* Inline functions operating on instruction bit-field(s).  */
 333
 334 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 335
 336 static inline aarch64_insn
 337 gen_mask (int width)
 338 {
 339   return ((aarch64_insn) 1 << width) - 1;
 340 }
 341
 342 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 343 static inline int
 344 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 345 {
 346   const aarch64_field *field = &fields[kind];
 347   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 348     return 0;
 349   ret->lsb = field->lsb + lsb_rel;
 350   ret->width = width;
 351   return 1;
 352 }
 353
 354 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 355    of the opcode.  */
 356
 357 static inline void
 358 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 359                 aarch64_insn value, aarch64_insn mask)
 360 {
 361   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 362           && field->lsb + field->width <= 32);
 363   value &= gen_mask (field->width);
 364   value <<= field->lsb;
 365   /* In some opcodes, field can be part of the base opcode, e.g. the size
 366      field in FADD.  The following helps avoid corrupt the base opcode.  */
 367   value &= ~mask;
 368   *code |= value;
 369 }
 370
 371 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 372    mask of the opcode.  */
 373
 374 static inline aarch64_insn
 375 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 376                  aarch64_insn mask)
 377 {
 378   aarch64_insn value;
 379   /* Clear any bit that is a part of the base opcode.  */
 380   code &= ~mask;
 381   value = (code >> field->lsb) & gen_mask (field->width);
 382   return value;
 383 }
 384
 385 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 386    of the opcode.  */
 387
 388 static inline void
 389 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 390               aarch64_insn value, aarch64_insn mask)
 391 {
 392   insert_field_2 (&fields[kind], code, value, mask);
 393 }
 394
 395 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 396    base mask of the opcode.  */
 397
 398 static inline aarch64_insn
 399 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 400                aarch64_insn mask)
 401 {
 402   return extract_field_2 (&fields[kind], code, mask);
 403 }
 404
 405 extern aarch64_insn
 406 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 407 \f
 408 /* Inline functions selecting operand to do the encoding/decoding for a
 409    certain instruction bit-field.  */
 410
 411 /* Select the operand to do the encoding/decoding of the 'sf' field.
 412    The heuristic-based rule is that the result operand is respected more.  */
 413
 414 static inline int
 415 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 416 {
 417   int idx = -1;
 418   if (aarch64_get_operand_class (opcode->operands[0])
 419       == AARCH64_OPND_CLASS_INT_REG)
 420     /* normal case.  */
 421     idx = 0;
 422   else if (aarch64_get_operand_class (opcode->operands[1])
 423            == AARCH64_OPND_CLASS_INT_REG)
 424     /* e.g. float2fix.  */
 425     idx = 1;
 426   else
 427     { assert (0); abort (); }
 428   return idx;
 429 }
 430
 431 /* Select the operand to do the encoding/decoding of the 'type' field in
 432    the floating-point instructions.
 433    The heuristic-based rule is that the source operand is respected more.  */
 434
 435 static inline int
 436 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 437 {
 438   int idx;
 439   if (aarch64_get_operand_class (opcode->operands[1])
 440       == AARCH64_OPND_CLASS_FP_REG)
 441     /* normal case.  */
 442     idx = 1;
 443   else if (aarch64_get_operand_class (opcode->operands[0])
 444            == AARCH64_OPND_CLASS_FP_REG)
 445     /* e.g. float2fix.  */
 446     idx = 0;
 447   else
 448     { assert (0); abort (); }
 449   return idx;
 450 }
 451
 452 /* Select the operand to do the encoding/decoding of the 'size' field in
 453    the AdvSIMD scalar instructions.
 454    The heuristic-based rule is that the destination operand is respected
 455    more.  */
 456
 457 static inline int
 458 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 459 {
 460   int src_size = 0, dst_size = 0;
 461   if (aarch64_get_operand_class (opcode->operands[0])
 462       == AARCH64_OPND_CLASS_SISD_REG)
 463     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 464   if (aarch64_get_operand_class (opcode->operands[1])
 465       == AARCH64_OPND_CLASS_SISD_REG)
 466     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 467   if (src_size == dst_size && src_size == 0)
 468     { assert (0); abort (); }
 469   /* When the result is not a sisd register or it is a long operantion.  */
 470   if (dst_size == 0 || dst_size == src_size << 1)
 471     return 1;
 472   else
 473     return 0;
 474 }
 475
 476 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 477    the AdvSIMD instructions.  */
 478
 479 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 480 \f
 481 /* Miscellaneous.  */
 482
 483 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 484 enum aarch64_modifier_kind
 485 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 486
 487
 488 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
 489 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 490 int aarch64_shrink_expanded_imm8 (uint64_t);
 491
 492 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 493 static inline void
 494 copy_operand_info (aarch64_inst *inst, int dst, int src)
 495 {
 496   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 497           && src < AARCH64_MAX_OPND_NUM);
 498   memcpy (&inst->operands[dst], &inst->operands[src],
 499           sizeof (aarch64_opnd_info));
 500   inst->operands[dst].idx = dst;
 501 }
 502
 503 /* A primitive log caculator.  */
 504
 505 static inline unsigned int
 506 get_logsz (unsigned int size)
 507 {
 508   const unsigned char ls[16] =
 509     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 510   if (size > 16)
 511     {
 512       assert (0);
 513       return -1;
 514     }
 515   assert (ls[size - 1] != (unsigned char)-1);
 516   return ls[size - 1];
 517 }
 518
 519 #endif /* OPCODES_AARCH64_OPC_H */