[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED
[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.h
1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2016 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
23
24 #include <string.h>
25 #include "opcode/aarch64.h"
26
27 /* Instruction fields.
28 Keep synced with fields. */
29 enum aarch64_field_kind
30 {
31 FLD_NIL,
32 FLD_cond2,
33 FLD_nzcv,
34 FLD_defgh,
35 FLD_abc,
36 FLD_imm19,
37 FLD_immhi,
38 FLD_immlo,
39 FLD_size,
40 FLD_vldst_size,
41 FLD_op,
42 FLD_Q,
43 FLD_Rt,
44 FLD_Rd,
45 FLD_Rn,
46 FLD_Rt2,
47 FLD_Ra,
48 FLD_op2,
49 FLD_CRm,
50 FLD_CRn,
51 FLD_op1,
52 FLD_op0,
53 FLD_imm3,
54 FLD_cond,
55 FLD_opcode,
56 FLD_cmode,
57 FLD_asisdlso_opcode,
58 FLD_len,
59 FLD_Rm,
60 FLD_Rs,
61 FLD_option,
62 FLD_S,
63 FLD_hw,
64 FLD_opc,
65 FLD_opc1,
66 FLD_shift,
67 FLD_type,
68 FLD_ldst_size,
69 FLD_imm6,
70 FLD_imm4,
71 FLD_imm5,
72 FLD_imm7,
73 FLD_imm8,
74 FLD_imm9,
75 FLD_imm12,
76 FLD_imm14,
77 FLD_imm16,
78 FLD_imm26,
79 FLD_imms,
80 FLD_immr,
81 FLD_immb,
82 FLD_immh,
83 FLD_N,
84 FLD_index,
85 FLD_index2,
86 FLD_sf,
87 FLD_lse_sz,
88 FLD_H,
89 FLD_L,
90 FLD_M,
91 FLD_b5,
92 FLD_b40,
93 FLD_scale,
94 FLD_SVE_Pd,
95 FLD_SVE_Pg3,
96 FLD_SVE_Pg4_5,
97 FLD_SVE_Pg4_10,
98 FLD_SVE_Pg4_16,
99 FLD_SVE_Pm,
100 FLD_SVE_Pn,
101 FLD_SVE_Pt,
102 FLD_SVE_Za_5,
103 FLD_SVE_Za_16,
104 FLD_SVE_Zd,
105 FLD_SVE_Zm_5,
106 FLD_SVE_Zm_16,
107 FLD_SVE_Zn,
108 FLD_SVE_Zt,
109 FLD_SVE_imm4,
110 FLD_SVE_pattern,
111 FLD_SVE_prfop,
112 FLD_SVE_tszh,
113 };
114
115 /* Field description. */
116 struct aarch64_field
117 {
118 int lsb;
119 int width;
120 };
121
122 typedef struct aarch64_field aarch64_field;
123
124 extern const aarch64_field fields[];
125 \f
126 /* Operand description. */
127
128 struct aarch64_operand
129 {
130 enum aarch64_operand_class op_class;
131
132 /* Name of the operand code; used mainly for the purpose of internal
133 debugging. */
134 const char *name;
135
136 unsigned int flags;
137
138 /* The associated instruction bit-fields; no operand has more than 4
139 bit-fields */
140 enum aarch64_field_kind fields[4];
141
142 /* Brief description */
143 const char *desc;
144 };
145
146 typedef struct aarch64_operand aarch64_operand;
147
148 extern const aarch64_operand aarch64_operands[];
149
150 /* Operand flags. */
151
152 #define OPD_F_HAS_INSERTER 0x00000001
153 #define OPD_F_HAS_EXTRACTOR 0x00000002
154 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
155 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
156 value by 2 to get the value
157 of an immediate operand. */
158 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
159
160 static inline bfd_boolean
161 operand_has_inserter (const aarch64_operand *operand)
162 {
163 return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
164 }
165
166 static inline bfd_boolean
167 operand_has_extractor (const aarch64_operand *operand)
168 {
169 return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
170 }
171
172 static inline bfd_boolean
173 operand_need_sign_extension (const aarch64_operand *operand)
174 {
175 return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
176 }
177
178 static inline bfd_boolean
179 operand_need_shift_by_two (const aarch64_operand *operand)
180 {
181 return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
182 }
183
184 static inline bfd_boolean
185 operand_maybe_stack_pointer (const aarch64_operand *operand)
186 {
187 return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
188 }
189
190 /* Return the total width of the operand *OPERAND. */
191 static inline unsigned
192 get_operand_fields_width (const aarch64_operand *operand)
193 {
194 int i = 0;
195 unsigned width = 0;
196 while (operand->fields[i] != FLD_NIL)
197 width += fields[operand->fields[i++]].width;
198 assert (width > 0 && width < 32);
199 return width;
200 }
201
202 static inline const aarch64_operand *
203 get_operand_from_code (enum aarch64_opnd code)
204 {
205 return aarch64_operands + code;
206 }
207 \f
208 /* Operand qualifier and operand constraint checking. */
209
210 int aarch64_match_operands_constraint (aarch64_inst *,
211 aarch64_operand_error *);
212
213 /* Operand qualifier related functions. */
214 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
215 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
216 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
217 int aarch64_find_best_match (const aarch64_inst *,
218 const aarch64_opnd_qualifier_seq_t *,
219 int, aarch64_opnd_qualifier_t *);
220
221 static inline void
222 reset_operand_qualifier (aarch64_inst *inst, int idx)
223 {
224 assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
225 inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
226 }
227 \f
228 /* Inline functions operating on instruction bit-field(s). */
229
230 /* Generate a mask that has WIDTH number of consecutive 1s. */
231
232 static inline aarch64_insn
233 gen_mask (int width)
234 {
235 return ((aarch64_insn) 1 << width) - 1;
236 }
237
238 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
239 static inline int
240 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
241 {
242 const aarch64_field *field = &fields[kind];
243 if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
244 return 0;
245 ret->lsb = field->lsb + lsb_rel;
246 ret->width = width;
247 return 1;
248 }
249
250 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
251 of the opcode. */
252
253 static inline void
254 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
255 aarch64_insn value, aarch64_insn mask)
256 {
257 assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
258 && field->lsb + field->width <= 32);
259 value &= gen_mask (field->width);
260 value <<= field->lsb;
261 /* In some opcodes, field can be part of the base opcode, e.g. the size
262 field in FADD. The following helps avoid corrupt the base opcode. */
263 value &= ~mask;
264 *code |= value;
265 }
266
267 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
268 mask of the opcode. */
269
270 static inline aarch64_insn
271 extract_field_2 (const aarch64_field *field, aarch64_insn code,
272 aarch64_insn mask)
273 {
274 aarch64_insn value;
275 /* Clear any bit that is a part of the base opcode. */
276 code &= ~mask;
277 value = (code >> field->lsb) & gen_mask (field->width);
278 return value;
279 }
280
281 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
282 of the opcode. */
283
284 static inline void
285 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
286 aarch64_insn value, aarch64_insn mask)
287 {
288 insert_field_2 (&fields[kind], code, value, mask);
289 }
290
291 /* Extract field KIND of CODE and return the value. MASK can be zero or the
292 base mask of the opcode. */
293
294 static inline aarch64_insn
295 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
296 aarch64_insn mask)
297 {
298 return extract_field_2 (&fields[kind], code, mask);
299 }
300 \f
301 /* Inline functions selecting operand to do the encoding/decoding for a
302 certain instruction bit-field. */
303
304 /* Select the operand to do the encoding/decoding of the 'sf' field.
305 The heuristic-based rule is that the result operand is respected more. */
306
307 static inline int
308 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
309 {
310 int idx = -1;
311 if (aarch64_get_operand_class (opcode->operands[0])
312 == AARCH64_OPND_CLASS_INT_REG)
313 /* normal case. */
314 idx = 0;
315 else if (aarch64_get_operand_class (opcode->operands[1])
316 == AARCH64_OPND_CLASS_INT_REG)
317 /* e.g. float2fix. */
318 idx = 1;
319 else
320 { assert (0); abort (); }
321 return idx;
322 }
323
324 /* Select the operand to do the encoding/decoding of the 'type' field in
325 the floating-point instructions.
326 The heuristic-based rule is that the source operand is respected more. */
327
328 static inline int
329 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
330 {
331 int idx;
332 if (aarch64_get_operand_class (opcode->operands[1])
333 == AARCH64_OPND_CLASS_FP_REG)
334 /* normal case. */
335 idx = 1;
336 else if (aarch64_get_operand_class (opcode->operands[0])
337 == AARCH64_OPND_CLASS_FP_REG)
338 /* e.g. float2fix. */
339 idx = 0;
340 else
341 { assert (0); abort (); }
342 return idx;
343 }
344
345 /* Select the operand to do the encoding/decoding of the 'size' field in
346 the AdvSIMD scalar instructions.
347 The heuristic-based rule is that the destination operand is respected
348 more. */
349
350 static inline int
351 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
352 {
353 int src_size = 0, dst_size = 0;
354 if (aarch64_get_operand_class (opcode->operands[0])
355 == AARCH64_OPND_CLASS_SISD_REG)
356 dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
357 if (aarch64_get_operand_class (opcode->operands[1])
358 == AARCH64_OPND_CLASS_SISD_REG)
359 src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
360 if (src_size == dst_size && src_size == 0)
361 { assert (0); abort (); }
362 /* When the result is not a sisd register or it is a long operantion. */
363 if (dst_size == 0 || dst_size == src_size << 1)
364 return 1;
365 else
366 return 0;
367 }
368
369 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
370 the AdvSIMD instructions. */
371
372 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
373 \f
374 /* Miscellaneous. */
375
376 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
377 enum aarch64_modifier_kind
378 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
379
380
381 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
382 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
383 int aarch64_shrink_expanded_imm8 (uint64_t);
384
385 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
386 static inline void
387 copy_operand_info (aarch64_inst *inst, int dst, int src)
388 {
389 assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
390 && src < AARCH64_MAX_OPND_NUM);
391 memcpy (&inst->operands[dst], &inst->operands[src],
392 sizeof (aarch64_opnd_info));
393 inst->operands[dst].idx = dst;
394 }
395
396 /* A primitive log caculator. */
397
398 static inline unsigned int
399 get_logsz (unsigned int size)
400 {
401 const unsigned char ls[16] =
402 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
403 if (size > 16)
404 {
405 assert (0);
406 return -1;
407 }
408 assert (ls[size - 1] != (unsigned char)-1);
409 return ls[size - 1];
410 }
411
412 #endif /* OPCODES_AARCH64_OPC_H */
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