opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm6_2,
  71   FLD_imm4,
  72   FLD_imm4_2,
  73   FLD_imm5,
  74   FLD_imm7,
  75   FLD_imm8,
  76   FLD_imm9,
  77   FLD_imm12,
  78   FLD_imm14,
  79   FLD_imm16,
  80   FLD_imm26,
  81   FLD_imms,
  82   FLD_immr,
  83   FLD_immb,
  84   FLD_immh,
  85   FLD_S_imm10,
  86   FLD_N,
  87   FLD_index,
  88   FLD_index2,
  89   FLD_sf,
  90   FLD_lse_sz,
  91   FLD_H,
  92   FLD_L,
  93   FLD_M,
  94   FLD_b5,
  95   FLD_b40,
  96   FLD_scale,
  97   FLD_SVE_M_4,
  98   FLD_SVE_M_14,
  99   FLD_SVE_M_16,
 100   FLD_SVE_N,
 101   FLD_SVE_Pd,
 102   FLD_SVE_Pg3,
 103   FLD_SVE_Pg4_5,
 104   FLD_SVE_Pg4_10,
 105   FLD_SVE_Pg4_16,
 106   FLD_SVE_Pm,
 107   FLD_SVE_Pn,
 108   FLD_SVE_Pt,
 109   FLD_SVE_Rm,
 110   FLD_SVE_Rn,
 111   FLD_SVE_Vd,
 112   FLD_SVE_Vm,
 113   FLD_SVE_Vn,
 114   FLD_SVE_Za_5,
 115   FLD_SVE_Za_16,
 116   FLD_SVE_Zd,
 117   FLD_SVE_Zm_5,
 118   FLD_SVE_Zm_16,
 119   FLD_SVE_Zn,
 120   FLD_SVE_Zt,
 121   FLD_SVE_i1,
 122   FLD_SVE_i3h,
 123   FLD_SVE_imm3,
 124   FLD_SVE_imm4,
 125   FLD_SVE_imm5,
 126   FLD_SVE_imm5b,
 127   FLD_SVE_imm6,
 128   FLD_SVE_imm7,
 129   FLD_SVE_imm8,
 130   FLD_SVE_imm9,
 131   FLD_SVE_immr,
 132   FLD_SVE_imms,
 133   FLD_SVE_msz,
 134   FLD_SVE_pattern,
 135   FLD_SVE_prfop,
 136   FLD_SVE_rot1,
 137   FLD_SVE_rot2,
 138   FLD_SVE_sz,
 139   FLD_SVE_tsz,
 140   FLD_SVE_tszh,
 141   FLD_SVE_tszl_8,
 142   FLD_SVE_tszl_19,
 143   FLD_SVE_xs_14,
 144   FLD_SVE_xs_22,
 145   FLD_rotate1,
 146   FLD_rotate2,
 147   FLD_rotate3,
 148   FLD_SM3_imm2
 149 };
 150
 151 /* Field description.  */
 152 struct aarch64_field
 153 {
 154   int lsb;
 155   int width;
 156 };
 157
 158 typedef struct aarch64_field aarch64_field;
 159
 160 extern const aarch64_field fields[];
 161 \f
 162 /* Operand description.  */
 163
 164 struct aarch64_operand
 165 {
 166   enum aarch64_operand_class op_class;
 167
 168   /* Name of the operand code; used mainly for the purpose of internal
 169      debugging.  */
 170   const char *name;
 171
 172   unsigned int flags;
 173
 174   /* The associated instruction bit-fields; no operand has more than 4
 175      bit-fields */
 176   enum aarch64_field_kind fields[4];
 177
 178   /* Brief description */
 179   const char *desc;
 180 };
 181
 182 typedef struct aarch64_operand aarch64_operand;
 183
 184 extern const aarch64_operand aarch64_operands[];
 185
 186 /* Operand flags.  */
 187
 188 #define OPD_F_HAS_INSERTER      0x00000001
 189 #define OPD_F_HAS_EXTRACTOR     0x00000002
 190 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 191 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 192                                                    value by 2 to get the value
 193                                                    of an immediate operand.  */
 194 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 195 #define OPD_F_OD_MASK           0x000000e0      /* Operand-dependent data.  */
 196 #define OPD_F_OD_LSB            5
 197 #define OPD_F_NO_ZR             0x00000100      /* ZR index not allowed.  */
 198
 199 /* Register flags.  */
 200
 201 #undef F_DEPRECATED
 202 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 203
 204 #undef F_ARCHEXT
 205 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 206
 207 #undef F_HASXT
 208 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 209                                      operand.  */
 210
 211 #undef F_REG_READ
 212 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 213                                      out of.  */
 214
 215 #undef F_REG_WRITE
 216 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 217                                      read from.  */
 218
 219 static inline bfd_boolean
 220 operand_has_inserter (const aarch64_operand *operand)
 221 {
 222   return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
 223 }
 224
 225 static inline bfd_boolean
 226 operand_has_extractor (const aarch64_operand *operand)
 227 {
 228   return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
 229 }
 230
 231 static inline bfd_boolean
 232 operand_need_sign_extension (const aarch64_operand *operand)
 233 {
 234   return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
 235 }
 236
 237 static inline bfd_boolean
 238 operand_need_shift_by_two (const aarch64_operand *operand)
 239 {
 240   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 241 }
 242
 243 static inline bfd_boolean
 244 operand_maybe_stack_pointer (const aarch64_operand *operand)
 245 {
 246   return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
 247 }
 248
 249 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 250 static inline unsigned int
 251 get_operand_specific_data (const aarch64_operand *operand)
 252 {
 253   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 254 }
 255
 256 /* Return the width of field number N of operand *OPERAND.  */
 257 static inline unsigned
 258 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 259 {
 260   assert (operand->fields[n] != FLD_NIL);
 261   return fields[operand->fields[n]].width;
 262 }
 263
 264 /* Return the total width of the operand *OPERAND.  */
 265 static inline unsigned
 266 get_operand_fields_width (const aarch64_operand *operand)
 267 {
 268   int i = 0;
 269   unsigned width = 0;
 270   while (operand->fields[i] != FLD_NIL)
 271     width += fields[operand->fields[i++]].width;
 272   assert (width > 0 && width < 32);
 273   return width;
 274 }
 275
 276 static inline const aarch64_operand *
 277 get_operand_from_code (enum aarch64_opnd code)
 278 {
 279   return aarch64_operands + code;
 280 }
 281 \f
 282 /* Operand qualifier and operand constraint checking.  */
 283
 284 int aarch64_match_operands_constraint (aarch64_inst *,
 285                                        aarch64_operand_error *);
 286
 287 /* Operand qualifier related functions.  */
 288 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 289 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 290 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 291 int aarch64_find_best_match (const aarch64_inst *,
 292                              const aarch64_opnd_qualifier_seq_t *,
 293                              int, aarch64_opnd_qualifier_t *);
 294
 295 static inline void
 296 reset_operand_qualifier (aarch64_inst *inst, int idx)
 297 {
 298   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 299   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 300 }
 301 \f
 302 /* Inline functions operating on instruction bit-field(s).  */
 303
 304 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 305
 306 static inline aarch64_insn
 307 gen_mask (int width)
 308 {
 309   return ((aarch64_insn) 1 << width) - 1;
 310 }
 311
 312 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 313 static inline int
 314 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 315 {
 316   const aarch64_field *field = &fields[kind];
 317   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 318     return 0;
 319   ret->lsb = field->lsb + lsb_rel;
 320   ret->width = width;
 321   return 1;
 322 }
 323
 324 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 325    of the opcode.  */
 326
 327 static inline void
 328 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 329                 aarch64_insn value, aarch64_insn mask)
 330 {
 331   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 332           && field->lsb + field->width <= 32);
 333   value &= gen_mask (field->width);
 334   value <<= field->lsb;
 335   /* In some opcodes, field can be part of the base opcode, e.g. the size
 336      field in FADD.  The following helps avoid corrupt the base opcode.  */
 337   value &= ~mask;
 338   *code |= value;
 339 }
 340
 341 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 342    mask of the opcode.  */
 343
 344 static inline aarch64_insn
 345 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 346                  aarch64_insn mask)
 347 {
 348   aarch64_insn value;
 349   /* Clear any bit that is a part of the base opcode.  */
 350   code &= ~mask;
 351   value = (code >> field->lsb) & gen_mask (field->width);
 352   return value;
 353 }
 354
 355 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 356    of the opcode.  */
 357
 358 static inline void
 359 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 360               aarch64_insn value, aarch64_insn mask)
 361 {
 362   insert_field_2 (&fields[kind], code, value, mask);
 363 }
 364
 365 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 366    base mask of the opcode.  */
 367
 368 static inline aarch64_insn
 369 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 370                aarch64_insn mask)
 371 {
 372   return extract_field_2 (&fields[kind], code, mask);
 373 }
 374
 375 extern aarch64_insn
 376 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 377 \f
 378 /* Inline functions selecting operand to do the encoding/decoding for a
 379    certain instruction bit-field.  */
 380
 381 /* Select the operand to do the encoding/decoding of the 'sf' field.
 382    The heuristic-based rule is that the result operand is respected more.  */
 383
 384 static inline int
 385 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 386 {
 387   int idx = -1;
 388   if (aarch64_get_operand_class (opcode->operands[0])
 389       == AARCH64_OPND_CLASS_INT_REG)
 390     /* normal case.  */
 391     idx = 0;
 392   else if (aarch64_get_operand_class (opcode->operands[1])
 393            == AARCH64_OPND_CLASS_INT_REG)
 394     /* e.g. float2fix.  */
 395     idx = 1;
 396   else
 397     { assert (0); abort (); }
 398   return idx;
 399 }
 400
 401 /* Select the operand to do the encoding/decoding of the 'type' field in
 402    the floating-point instructions.
 403    The heuristic-based rule is that the source operand is respected more.  */
 404
 405 static inline int
 406 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 407 {
 408   int idx;
 409   if (aarch64_get_operand_class (opcode->operands[1])
 410       == AARCH64_OPND_CLASS_FP_REG)
 411     /* normal case.  */
 412     idx = 1;
 413   else if (aarch64_get_operand_class (opcode->operands[0])
 414            == AARCH64_OPND_CLASS_FP_REG)
 415     /* e.g. float2fix.  */
 416     idx = 0;
 417   else
 418     { assert (0); abort (); }
 419   return idx;
 420 }
 421
 422 /* Select the operand to do the encoding/decoding of the 'size' field in
 423    the AdvSIMD scalar instructions.
 424    The heuristic-based rule is that the destination operand is respected
 425    more.  */
 426
 427 static inline int
 428 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 429 {
 430   int src_size = 0, dst_size = 0;
 431   if (aarch64_get_operand_class (opcode->operands[0])
 432       == AARCH64_OPND_CLASS_SISD_REG)
 433     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 434   if (aarch64_get_operand_class (opcode->operands[1])
 435       == AARCH64_OPND_CLASS_SISD_REG)
 436     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 437   if (src_size == dst_size && src_size == 0)
 438     { assert (0); abort (); }
 439   /* When the result is not a sisd register or it is a long operantion.  */
 440   if (dst_size == 0 || dst_size == src_size << 1)
 441     return 1;
 442   else
 443     return 0;
 444 }
 445
 446 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 447    the AdvSIMD instructions.  */
 448
 449 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 450 \f
 451 /* Miscellaneous.  */
 452
 453 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 454 enum aarch64_modifier_kind
 455 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 456
 457
 458 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
 459 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 460 int aarch64_shrink_expanded_imm8 (uint64_t);
 461
 462 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 463 static inline void
 464 copy_operand_info (aarch64_inst *inst, int dst, int src)
 465 {
 466   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 467           && src < AARCH64_MAX_OPND_NUM);
 468   memcpy (&inst->operands[dst], &inst->operands[src],
 469           sizeof (aarch64_opnd_info));
 470   inst->operands[dst].idx = dst;
 471 }
 472
 473 /* A primitive log caculator.  */
 474
 475 static inline unsigned int
 476 get_logsz (unsigned int size)
 477 {
 478   const unsigned char ls[16] =
 479     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 480   if (size > 16)
 481     {
 482       assert (0);
 483       return -1;
 484     }
 485   assert (ls[size - 1] != (unsigned char)-1);
 486   return ls[size - 1];
 487 }
 488
 489 #endif /* OPCODES_AARCH64_OPC_H */