opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2018 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep synced with fields.  */
  29 enum aarch64_field_kind
  30 {
  31   FLD_NIL,
  32   FLD_cond2,
  33   FLD_nzcv,
  34   FLD_defgh,
  35   FLD_abc,
  36   FLD_imm19,
  37   FLD_immhi,
  38   FLD_immlo,
  39   FLD_size,
  40   FLD_vldst_size,
  41   FLD_op,
  42   FLD_Q,
  43   FLD_Rt,
  44   FLD_Rd,
  45   FLD_Rn,
  46   FLD_Rt2,
  47   FLD_Ra,
  48   FLD_op2,
  49   FLD_CRm,
  50   FLD_CRn,
  51   FLD_op1,
  52   FLD_op0,
  53   FLD_imm3,
  54   FLD_cond,
  55   FLD_opcode,
  56   FLD_cmode,
  57   FLD_asisdlso_opcode,
  58   FLD_len,
  59   FLD_Rm,
  60   FLD_Rs,
  61   FLD_option,
  62   FLD_S,
  63   FLD_hw,
  64   FLD_opc,
  65   FLD_opc1,
  66   FLD_shift,
  67   FLD_type,
  68   FLD_ldst_size,
  69   FLD_imm6,
  70   FLD_imm6_2,
  71   FLD_imm4,
  72   FLD_imm4_2,
  73   FLD_imm5,
  74   FLD_imm7,
  75   FLD_imm8,
  76   FLD_imm9,
  77   FLD_imm12,
  78   FLD_imm14,
  79   FLD_imm16,
  80   FLD_imm26,
  81   FLD_imms,
  82   FLD_immr,
  83   FLD_immb,
  84   FLD_immh,
  85   FLD_S_imm10,
  86   FLD_N,
  87   FLD_index,
  88   FLD_index2,
  89   FLD_sf,
  90   FLD_lse_sz,
  91   FLD_H,
  92   FLD_L,
  93   FLD_M,
  94   FLD_b5,
  95   FLD_b40,
  96   FLD_scale,
  97   FLD_SVE_M_4,
  98   FLD_SVE_M_14,
  99   FLD_SVE_M_16,
 100   FLD_SVE_N,
 101   FLD_SVE_Pd,
 102   FLD_SVE_Pg3,
 103   FLD_SVE_Pg4_5,
 104   FLD_SVE_Pg4_10,
 105   FLD_SVE_Pg4_16,
 106   FLD_SVE_Pm,
 107   FLD_SVE_Pn,
 108   FLD_SVE_Pt,
 109   FLD_SVE_Rm,
 110   FLD_SVE_Rn,
 111   FLD_SVE_Vd,
 112   FLD_SVE_Vm,
 113   FLD_SVE_Vn,
 114   FLD_SVE_Za_5,
 115   FLD_SVE_Za_16,
 116   FLD_SVE_Zd,
 117   FLD_SVE_Zm_5,
 118   FLD_SVE_Zm_16,
 119   FLD_SVE_Zn,
 120   FLD_SVE_Zt,
 121   FLD_SVE_i1,
 122   FLD_SVE_i3h,
 123   FLD_SVE_imm3,
 124   FLD_SVE_imm4,
 125   FLD_SVE_imm5,
 126   FLD_SVE_imm5b,
 127   FLD_SVE_imm6,
 128   FLD_SVE_imm7,
 129   FLD_SVE_imm8,
 130   FLD_SVE_imm9,
 131   FLD_SVE_immr,
 132   FLD_SVE_imms,
 133   FLD_SVE_msz,
 134   FLD_SVE_pattern,
 135   FLD_SVE_prfop,
 136   FLD_SVE_rot1,
 137   FLD_SVE_rot2,
 138   FLD_SVE_sz,
 139   FLD_SVE_tsz,
 140   FLD_SVE_tszh,
 141   FLD_SVE_tszl_8,
 142   FLD_SVE_tszl_19,
 143   FLD_SVE_xs_14,
 144   FLD_SVE_xs_22,
 145   FLD_rotate1,
 146   FLD_rotate2,
 147   FLD_rotate3,
 148   FLD_SM3_imm2
 149 };
 150
 151 /* Field description.  */
 152 struct aarch64_field
 153 {
 154   int lsb;
 155   int width;
 156 };
 157
 158 typedef struct aarch64_field aarch64_field;
 159
 160 extern const aarch64_field fields[];
 161 \f
 162 /* Operand description.  */
 163
 164 struct aarch64_operand
 165 {
 166   enum aarch64_operand_class op_class;
 167
 168   /* Name of the operand code; used mainly for the purpose of internal
 169      debugging.  */
 170   const char *name;
 171
 172   unsigned int flags;
 173
 174   /* The associated instruction bit-fields; no operand has more than 4
 175      bit-fields */
 176   enum aarch64_field_kind fields[4];
 177
 178   /* Brief description */
 179   const char *desc;
 180 };
 181
 182 typedef struct aarch64_operand aarch64_operand;
 183
 184 extern const aarch64_operand aarch64_operands[];
 185
 186 enum err_type
 187 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 188                     bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
 189
 190 /* Operand flags.  */
 191
 192 #define OPD_F_HAS_INSERTER      0x00000001
 193 #define OPD_F_HAS_EXTRACTOR     0x00000002
 194 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 195 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 196                                                    value by 2 to get the value
 197                                                    of an immediate operand.  */
 198 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 199 #define OPD_F_OD_MASK           0x000000e0      /* Operand-dependent data.  */
 200 #define OPD_F_OD_LSB            5
 201 #define OPD_F_NO_ZR             0x00000100      /* ZR index not allowed.  */
 202
 203 /* Register flags.  */
 204
 205 #undef F_DEPRECATED
 206 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 207
 208 #undef F_ARCHEXT
 209 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 210
 211 #undef F_HASXT
 212 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 213                                      operand.  */
 214
 215 #undef F_REG_READ
 216 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 217                                      out of.  */
 218
 219 #undef F_REG_WRITE
 220 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 221                                      read from.  */
 222
 223 /* HINT operand flags.  */
 224 #define HINT_OPD_F_NOPRINT      (1 << 0)  /* Should not be printed.  */
 225
 226 /* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
 227 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
 228 #define HINT_FLAG(val) (val >> 8)
 229 #define HINT_VAL(val) (val & 0xff)
 230
 231 static inline bfd_boolean
 232 operand_has_inserter (const aarch64_operand *operand)
 233 {
 234   return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
 235 }
 236
 237 static inline bfd_boolean
 238 operand_has_extractor (const aarch64_operand *operand)
 239 {
 240   return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
 241 }
 242
 243 static inline bfd_boolean
 244 operand_need_sign_extension (const aarch64_operand *operand)
 245 {
 246   return (operand->flags & OPD_F_SEXT) ? TRUE : FALSE;
 247 }
 248
 249 static inline bfd_boolean
 250 operand_need_shift_by_two (const aarch64_operand *operand)
 251 {
 252   return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
 253 }
 254
 255 static inline bfd_boolean
 256 operand_maybe_stack_pointer (const aarch64_operand *operand)
 257 {
 258   return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
 259 }
 260
 261 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 262 static inline unsigned int
 263 get_operand_specific_data (const aarch64_operand *operand)
 264 {
 265   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 266 }
 267
 268 /* Return the width of field number N of operand *OPERAND.  */
 269 static inline unsigned
 270 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 271 {
 272   assert (operand->fields[n] != FLD_NIL);
 273   return fields[operand->fields[n]].width;
 274 }
 275
 276 /* Return the total width of the operand *OPERAND.  */
 277 static inline unsigned
 278 get_operand_fields_width (const aarch64_operand *operand)
 279 {
 280   int i = 0;
 281   unsigned width = 0;
 282   while (operand->fields[i] != FLD_NIL)
 283     width += fields[operand->fields[i++]].width;
 284   assert (width > 0 && width < 32);
 285   return width;
 286 }
 287
 288 static inline const aarch64_operand *
 289 get_operand_from_code (enum aarch64_opnd code)
 290 {
 291   return aarch64_operands + code;
 292 }
 293 \f
 294 /* Operand qualifier and operand constraint checking.  */
 295
 296 int aarch64_match_operands_constraint (aarch64_inst *,
 297                                        aarch64_operand_error *);
 298
 299 /* Operand qualifier related functions.  */
 300 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 301 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 302 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 303 int aarch64_find_best_match (const aarch64_inst *,
 304                              const aarch64_opnd_qualifier_seq_t *,
 305                              int, aarch64_opnd_qualifier_t *);
 306
 307 static inline void
 308 reset_operand_qualifier (aarch64_inst *inst, int idx)
 309 {
 310   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 311   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 312 }
 313 \f
 314 /* Inline functions operating on instruction bit-field(s).  */
 315
 316 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 317
 318 static inline aarch64_insn
 319 gen_mask (int width)
 320 {
 321   return ((aarch64_insn) 1 << width) - 1;
 322 }
 323
 324 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 325 static inline int
 326 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 327 {
 328   const aarch64_field *field = &fields[kind];
 329   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 330     return 0;
 331   ret->lsb = field->lsb + lsb_rel;
 332   ret->width = width;
 333   return 1;
 334 }
 335
 336 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 337    of the opcode.  */
 338
 339 static inline void
 340 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 341                 aarch64_insn value, aarch64_insn mask)
 342 {
 343   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 344           && field->lsb + field->width <= 32);
 345   value &= gen_mask (field->width);
 346   value <<= field->lsb;
 347   /* In some opcodes, field can be part of the base opcode, e.g. the size
 348      field in FADD.  The following helps avoid corrupt the base opcode.  */
 349   value &= ~mask;
 350   *code |= value;
 351 }
 352
 353 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 354    mask of the opcode.  */
 355
 356 static inline aarch64_insn
 357 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 358                  aarch64_insn mask)
 359 {
 360   aarch64_insn value;
 361   /* Clear any bit that is a part of the base opcode.  */
 362   code &= ~mask;
 363   value = (code >> field->lsb) & gen_mask (field->width);
 364   return value;
 365 }
 366
 367 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 368    of the opcode.  */
 369
 370 static inline void
 371 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 372               aarch64_insn value, aarch64_insn mask)
 373 {
 374   insert_field_2 (&fields[kind], code, value, mask);
 375 }
 376
 377 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 378    base mask of the opcode.  */
 379
 380 static inline aarch64_insn
 381 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 382                aarch64_insn mask)
 383 {
 384   return extract_field_2 (&fields[kind], code, mask);
 385 }
 386
 387 extern aarch64_insn
 388 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 389 \f
 390 /* Inline functions selecting operand to do the encoding/decoding for a
 391    certain instruction bit-field.  */
 392
 393 /* Select the operand to do the encoding/decoding of the 'sf' field.
 394    The heuristic-based rule is that the result operand is respected more.  */
 395
 396 static inline int
 397 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 398 {
 399   int idx = -1;
 400   if (aarch64_get_operand_class (opcode->operands[0])
 401       == AARCH64_OPND_CLASS_INT_REG)
 402     /* normal case.  */
 403     idx = 0;
 404   else if (aarch64_get_operand_class (opcode->operands[1])
 405            == AARCH64_OPND_CLASS_INT_REG)
 406     /* e.g. float2fix.  */
 407     idx = 1;
 408   else
 409     { assert (0); abort (); }
 410   return idx;
 411 }
 412
 413 /* Select the operand to do the encoding/decoding of the 'type' field in
 414    the floating-point instructions.
 415    The heuristic-based rule is that the source operand is respected more.  */
 416
 417 static inline int
 418 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 419 {
 420   int idx;
 421   if (aarch64_get_operand_class (opcode->operands[1])
 422       == AARCH64_OPND_CLASS_FP_REG)
 423     /* normal case.  */
 424     idx = 1;
 425   else if (aarch64_get_operand_class (opcode->operands[0])
 426            == AARCH64_OPND_CLASS_FP_REG)
 427     /* e.g. float2fix.  */
 428     idx = 0;
 429   else
 430     { assert (0); abort (); }
 431   return idx;
 432 }
 433
 434 /* Select the operand to do the encoding/decoding of the 'size' field in
 435    the AdvSIMD scalar instructions.
 436    The heuristic-based rule is that the destination operand is respected
 437    more.  */
 438
 439 static inline int
 440 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 441 {
 442   int src_size = 0, dst_size = 0;
 443   if (aarch64_get_operand_class (opcode->operands[0])
 444       == AARCH64_OPND_CLASS_SISD_REG)
 445     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 446   if (aarch64_get_operand_class (opcode->operands[1])
 447       == AARCH64_OPND_CLASS_SISD_REG)
 448     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 449   if (src_size == dst_size && src_size == 0)
 450     { assert (0); abort (); }
 451   /* When the result is not a sisd register or it is a long operantion.  */
 452   if (dst_size == 0 || dst_size == src_size << 1)
 453     return 1;
 454   else
 455     return 0;
 456 }
 457
 458 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 459    the AdvSIMD instructions.  */
 460
 461 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 462 \f
 463 /* Miscellaneous.  */
 464
 465 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 466 enum aarch64_modifier_kind
 467 aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
 468
 469
 470 bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
 471 bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 472 int aarch64_shrink_expanded_imm8 (uint64_t);
 473
 474 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 475 static inline void
 476 copy_operand_info (aarch64_inst *inst, int dst, int src)
 477 {
 478   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 479           && src < AARCH64_MAX_OPND_NUM);
 480   memcpy (&inst->operands[dst], &inst->operands[src],
 481           sizeof (aarch64_opnd_info));
 482   inst->operands[dst].idx = dst;
 483 }
 484
 485 /* A primitive log caculator.  */
 486
 487 static inline unsigned int
 488 get_logsz (unsigned int size)
 489 {
 490   const unsigned char ls[16] =
 491     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 492   if (size > 16)
 493     {
 494       assert (0);
 495       return -1;
 496     }
 497   assert (ls[size - 1] != (unsigned char)-1);
 498   return ls[size - 1];
 499 }
 500
 501 #endif /* OPCODES_AARCH64_OPC_H */