opcodes/aarch64-tbl.h

   1 /* aarch64-tbl.h -- AArch64 opcode description table and instruction
   2    operand description table.
   3    Copyright (C) 2012-2015 Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #include "aarch64-opc.h"
  23
  24 /* Operand type.  */
  25
  26 #define OPND(x) AARCH64_OPND_##x
  27 #define OP0() {}
  28 #define OP1(a) {OPND(a)}
  29 #define OP2(a,b) {OPND(a), OPND(b)}
  30 #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
  31 #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)}
  32 #define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)}
  33
  34 #define QLF(x) AARCH64_OPND_QLF_##x
  35 #define QLF1(a) {QLF(a)}
  36 #define QLF2(a,b) {QLF(a), QLF(b)}
  37 #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)}
  38 #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)}
  39 #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)}
  40
  41 /* Qualifiers list.  */
  42
  43 /* e.g. MSR <systemreg>, <Xt>.  */
  44 #define QL_SRC_X                \
  45 {                               \
  46   QLF2(NIL,X),                  \
  47 }
  48
  49 /* e.g. MRS <Xt>, <systemreg>.  */
  50 #define QL_DST_X                \
  51 {                               \
  52   QLF2(X,NIL),                  \
  53 }
  54
  55 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}.  */
  56 #define QL_SYS                  \
  57 {                               \
  58   QLF5(NIL,NIL,NIL,NIL,X),      \
  59 }
  60
  61 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>.  */
  62 #define QL_SYSL                 \
  63 {                               \
  64   QLF5(X,NIL,NIL,NIL,NIL),      \
  65 }
  66
  67 /* e.g. ADRP <Xd>, <label>.  */
  68 #define QL_ADRP                 \
  69 {                               \
  70   QLF2(X,NIL),                  \
  71 }
  72
  73 /* e.g. B.<cond> <label>.  */
  74 #define QL_PCREL_NIL            \
  75 {                               \
  76   QLF1(NIL),                    \
  77 }
  78
  79 /* e.g. TBZ <Xt>, #<imm>, <label>.  */
  80 #define QL_PCREL_14             \
  81 {                               \
  82   QLF3(X,imm_0_63,NIL),         \
  83 }
  84
  85 /* e.g. BL <label>.  */
  86 #define QL_PCREL_26             \
  87 {                               \
  88   QLF1(NIL),                    \
  89 }
  90
  91 /* e.g. LDRSW <Xt>, <label>.  */
  92 #define QL_X_PCREL              \
  93 {                               \
  94   QLF2(X,NIL),                  \
  95 }
  96
  97 /* e.g. LDR <Wt>, <label>.  */
  98 #define QL_R_PCREL              \
  99 {                               \
 100   QLF2(W,NIL),                  \
 101   QLF2(X,NIL),                  \
 102 }
 103
 104 /* e.g. LDR <Dt>, <label>.  */
 105 #define QL_FP_PCREL             \
 106 {                               \
 107   QLF2(S_S,NIL),                \
 108   QLF2(S_D,NIL),                \
 109   QLF2(S_Q,NIL),                \
 110 }
 111
 112 /* e.g. PRFM <prfop>, <label>.  */
 113 #define QL_PRFM_PCREL           \
 114 {                               \
 115   QLF2(NIL,NIL),                \
 116 }
 117
 118 /* e.g. BR <Xn>.  */
 119 #define QL_I1X                  \
 120 {                               \
 121   QLF1(X),                      \
 122 }
 123
 124 /* e.g. RBIT <Wd>, <Wn>.  */
 125 #define QL_I2SAME               \
 126 {                               \
 127   QLF2(W,W),                    \
 128   QLF2(X,X),                    \
 129 }
 130
 131 /* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}.  */
 132 #define QL_I2_EXT               \
 133 {                               \
 134   QLF2(W,W),                    \
 135   QLF2(X,W),                    \
 136   QLF2(X,X),                    \
 137 }
 138
 139 /* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP.  */
 140 #define QL_I2SP                 \
 141 {                               \
 142   QLF2(WSP,W),                  \
 143   QLF2(W,WSP),                  \
 144   QLF2(SP,X),                   \
 145   QLF2(X,SP),                   \
 146 }
 147
 148 /* e.g. REV <Wd>, <Wn>.  */
 149 #define QL_I2SAMEW              \
 150 {                               \
 151   QLF2(W,W),                    \
 152 }
 153
 154 /* e.g. REV32 <Xd>, <Xn>.  */
 155 #define QL_I2SAMEX              \
 156 {                               \
 157   QLF2(X,X),                    \
 158 }
 159
 160 #define QL_I2SAMER              \
 161 {                               \
 162   QLF2(W,W),                    \
 163   QLF2(X,X),                    \
 164 }
 165
 166 /* e.g. CRC32B <Wd>, <Wn>, <Wm>.  */
 167 #define QL_I3SAMEW              \
 168 {                               \
 169   QLF3(W,W,W),                  \
 170 }
 171
 172 /* e.g. SMULH <Xd>, <Xn>, <Xm>.  */
 173 #define QL_I3SAMEX              \
 174 {                               \
 175   QLF3(X,X,X),                  \
 176 }
 177
 178 /* e.g. CRC32X <Wd>, <Wn>, <Xm>.  */
 179 #define QL_I3WWX                \
 180 {                               \
 181   QLF3(W,W,X),                  \
 182 }
 183
 184 /* e.g. UDIV <Xd>, <Xn>, <Xm>.  */
 185 #define QL_I3SAMER              \
 186 {                               \
 187   QLF3(W,W,W),                  \
 188   QLF3(X,X,X),                  \
 189 }
 190
 191 /* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}.  */
 192 #define QL_I3_EXT               \
 193 {                               \
 194   QLF3(W,W,W),                  \
 195   QLF3(X,X,W),                  \
 196   QLF3(X,X,X),                  \
 197 }
 198
 199 /* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>.  */
 200 #define QL_I4SAMER              \
 201 {                               \
 202   QLF4(W,W,W,W),                \
 203   QLF4(X,X,X,X),                \
 204 }
 205
 206 /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>.  */
 207 #define QL_I3SAMEL              \
 208 {                               \
 209   QLF3(X,W,W),                  \
 210 }
 211
 212 /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>.  */
 213 #define QL_I4SAMEL              \
 214 {                               \
 215   QLF4(X,W,W,X),                \
 216 }
 217
 218 /* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>.  */
 219 #define QL_CSEL                 \
 220 {                               \
 221   QLF4(W, W, W, NIL),           \
 222   QLF4(X, X, X, NIL),           \
 223 }
 224
 225 /* e.g. CSET <Wd>, <cond>.  */
 226 #define QL_DST_R                        \
 227 {                               \
 228   QLF2(W, NIL),                 \
 229   QLF2(X, NIL),                 \
 230 }
 231
 232 /* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.  */
 233 #define QL_BF                   \
 234 {                               \
 235   QLF4(W,W,imm_0_31,imm_0_31),  \
 236   QLF4(X,X,imm_0_63,imm_0_63),  \
 237 }
 238
 239 /* e.g. BFC <Wd>, #<immr>, #<imms>.  */
 240 #define QL_BF1                                  \
 241 {                                               \
 242   QLF3 (W, imm_0_31, imm_1_32),                 \
 243   QLF3 (X, imm_0_63, imm_1_64),                 \
 244 }
 245
 246 /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>.  */
 247 #define QL_BF2                  \
 248 {                               \
 249   QLF4(W,W,imm_0_31,imm_1_32),  \
 250   QLF4(X,X,imm_0_63,imm_1_64),  \
 251 }
 252
 253 /* e.g. SCVTF <Sd>, <Xn>, #<fbits>.  */
 254 #define QL_FIX2FP               \
 255 {                               \
 256   QLF3(S_D,W,imm_1_32),         \
 257   QLF3(S_S,W,imm_1_32),         \
 258   QLF3(S_D,X,imm_1_64),         \
 259   QLF3(S_S,X,imm_1_64),         \
 260 }
 261
 262 /* e.g. SCVTF <Hd>, <Xn>, #<fbits>.  */
 263 #define QL_FIX2FP_H                     \
 264 {                                       \
 265   QLF3 (S_H, W, imm_1_32),              \
 266   QLF3 (S_H, X, imm_1_64),              \
 267 }
 268
 269 /* e.g. FCVTZS <Wd>, <Dn>, #<fbits>.  */
 270 #define QL_FP2FIX               \
 271 {                               \
 272   QLF3(W,S_D,imm_1_32),         \
 273   QLF3(W,S_S,imm_1_32),         \
 274   QLF3(X,S_D,imm_1_64),         \
 275   QLF3(X,S_S,imm_1_64),         \
 276 }
 277
 278 /* e.g. FCVTZS <Wd>, <Hn>, #<fbits>.  */
 279 #define QL_FP2FIX_H                     \
 280 {                                       \
 281   QLF3 (W, S_H, imm_1_32),              \
 282   QLF3 (X, S_H, imm_1_64),              \
 283 }
 284
 285 /* e.g. SCVTF <Dd>, <Wn>.  */
 286 #define QL_INT2FP               \
 287 {                               \
 288   QLF2(S_D,W),                  \
 289   QLF2(S_S,W),                  \
 290   QLF2(S_D,X),                  \
 291   QLF2(S_S,X),                  \
 292 }
 293
 294 /* e.g. SCVTF <Hd>, <Wn>.  */
 295 #define QL_INT2FP_H                     \
 296 {                                       \
 297   QLF2 (S_H, W),                        \
 298   QLF2 (S_H, X),                        \
 299 }
 300
 301 /* e.g. FCVTNS <Xd>, <Dn>.  */
 302 #define QL_FP2INT               \
 303 {                               \
 304   QLF2(W,S_D),                  \
 305   QLF2(W,S_S),                  \
 306   QLF2(X,S_D),                  \
 307   QLF2(X,S_S),                  \
 308 }
 309
 310 /* e.g. FCVTNS <Hd>, <Wn>.  */
 311 #define QL_FP2INT_H                     \
 312 {                                       \
 313   QLF2 (W, S_H),                        \
 314   QLF2 (X, S_H),                        \
 315 }
 316
 317 /* e.g. FMOV <Xd>, <Vn>.D[1].  */
 318 #define QL_XVD1                 \
 319 {                               \
 320   QLF2(X,S_D),                  \
 321 }
 322
 323 /* e.g. FMOV <Vd>.D[1], <Xn>.  */
 324 #define QL_VD1X                 \
 325 {                               \
 326   QLF2(S_D,X),                  \
 327 }
 328
 329 /* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>.  */
 330 #define QL_EXTR                 \
 331 {                               \
 332   QLF4(W,W,W,imm_0_31),         \
 333   QLF4(X,X,X,imm_0_63),         \
 334 }
 335
 336 /* e.g. LSL <Wd>, <Wn>, #<uimm>.  */
 337 #define QL_SHIFT                \
 338 {                               \
 339   QLF3(W,W,imm_0_31),           \
 340   QLF3(X,X,imm_0_63),           \
 341 }
 342
 343 /* e.g. UXTH <Xd>, <Wn>.  */
 344 #define QL_EXT                  \
 345 {                               \
 346   QLF2(W,W),                    \
 347   QLF2(X,W),                    \
 348 }
 349
 350 /* e.g. UXTW <Xd>, <Wn>.  */
 351 #define QL_EXT_W                \
 352 {                               \
 353   QLF2(X,W),                    \
 354 }
 355
 356 /* e.g. SQSHL <V><d>, <V><n>, #<shift>.  */
 357 #define QL_SSHIFT               \
 358 {                               \
 359   QLF3(S_B , S_B , S_B ),       \
 360   QLF3(S_H , S_H , S_H ),       \
 361   QLF3(S_S , S_S , S_S ),       \
 362   QLF3(S_D , S_D , S_D )        \
 363 }
 364
 365 /* e.g. SSHR <V><d>, <V><n>, #<shift>.  */
 366 #define QL_SSHIFT_D             \
 367 {                               \
 368   QLF3(S_D , S_D , S_D )        \
 369 }
 370
 371 /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>.  */
 372 #define QL_SSHIFT_SD            \
 373 {                               \
 374   QLF3(S_S , S_S , S_S ),       \
 375   QLF3(S_D , S_D , S_D )        \
 376 }
 377
 378 /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>.  */
 379 #define QL_SSHIFTN              \
 380 {                               \
 381   QLF3(S_B , S_H , S_B ),       \
 382   QLF3(S_H , S_S , S_H ),       \
 383   QLF3(S_S , S_D , S_S ),       \
 384 }
 385
 386 /* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>.
 387    The register operand variant qualifiers are deliberately used for the
 388    immediate operand to ease the operand encoding/decoding and qualifier
 389    sequence matching.  */
 390 #define QL_VSHIFT               \
 391 {                               \
 392   QLF3(V_8B , V_8B , V_8B ),    \
 393   QLF3(V_16B, V_16B, V_16B),    \
 394   QLF3(V_4H , V_4H , V_4H ),    \
 395   QLF3(V_8H , V_8H , V_8H ),    \
 396   QLF3(V_2S , V_2S , V_2S ),    \
 397   QLF3(V_4S , V_4S , V_4S ),    \
 398   QLF3(V_2D , V_2D , V_2D )     \
 399 }
 400
 401 /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>.  */
 402 #define QL_VSHIFT_SD            \
 403 {                               \
 404   QLF3(V_2S , V_2S , V_2S ),    \
 405   QLF3(V_4S , V_4S , V_4S ),    \
 406   QLF3(V_2D , V_2D , V_2D )     \
 407 }
 408
 409 /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>.  */
 410 #define QL_VSHIFTN              \
 411 {                               \
 412   QLF3(V_8B , V_8H , V_8B ),    \
 413   QLF3(V_4H , V_4S , V_4H ),    \
 414   QLF3(V_2S , V_2D , V_2S ),    \
 415 }
 416
 417 /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>.  */
 418 #define QL_VSHIFTN2             \
 419 {                               \
 420   QLF3(V_16B, V_8H, V_16B),     \
 421   QLF3(V_8H , V_4S , V_8H ),    \
 422   QLF3(V_4S , V_2D , V_4S ),    \
 423 }
 424
 425 /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>.
 426    the 3rd qualifier is used to help the encoding.  */
 427 #define QL_VSHIFTL              \
 428 {                               \
 429   QLF3(V_8H , V_8B , V_8B ),    \
 430   QLF3(V_4S , V_4H , V_4H ),    \
 431   QLF3(V_2D , V_2S , V_2S ),    \
 432 }
 433
 434 /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>.  */
 435 #define QL_VSHIFTL2             \
 436 {                               \
 437   QLF3(V_8H , V_16B, V_16B),    \
 438   QLF3(V_4S , V_8H , V_8H ),    \
 439   QLF3(V_2D , V_4S , V_4S ),    \
 440 }
 441
 442 /* e.g. TBL.  */
 443 #define QL_TABLE                \
 444 {                               \
 445   QLF3(V_8B , V_16B, V_8B ),    \
 446   QLF3(V_16B, V_16B, V_16B),    \
 447 }
 448
 449 /* e.g. SHA1H.  */
 450 #define QL_2SAMES               \
 451 {                               \
 452   QLF2(S_S, S_S),               \
 453 }
 454
 455 /* e.g. ABS <V><d>, <V><n>.  */
 456 #define QL_2SAMED               \
 457 {                               \
 458   QLF2(S_D, S_D),               \
 459 }
 460
 461 /* e.g. CMGT <V><d>, <V><n>, #0.  */
 462 #define QL_SISD_CMP_0           \
 463 {                               \
 464   QLF3(S_D, S_D, NIL),          \
 465 }
 466
 467 /* e.g. FCMEQ <V><d>, <V><n>, #0.  */
 468 #define QL_SISD_FCMP_0          \
 469 {                               \
 470   QLF3(S_S, S_S, NIL),          \
 471   QLF3(S_D, S_D, NIL),          \
 472 }
 473
 474 /* e.g. FCMEQ <V><d>, <V><n>, #0.  */
 475 #define QL_SISD_FCMP_H_0        \
 476 {                               \
 477   QLF3 (S_H, S_H, NIL),         \
 478 }
 479
 480 /* e.g. FMAXNMP <V><d>, <Vn>.<T>.  */
 481 #define QL_SISD_PAIR            \
 482 {                               \
 483   QLF2(S_S, V_2S),              \
 484   QLF2(S_D, V_2D),              \
 485 }
 486
 487 /* e.g. ADDP <V><d>, <Vn>.<T>.  */
 488 #define QL_SISD_PAIR_D          \
 489 {                               \
 490   QLF2(S_D, V_2D),              \
 491 }
 492
 493 /* e.g. DUP <V><d>, <Vn>.<T>[<index>].  */
 494 #define QL_S_2SAME              \
 495 {                               \
 496   QLF2(S_B, S_B),               \
 497   QLF2(S_H, S_H),               \
 498   QLF2(S_S, S_S),               \
 499   QLF2(S_D, S_D),               \
 500 }
 501
 502 /* e.g. FCVTNS <V><d>, <V><n>.  */
 503 #define QL_S_2SAMESD            \
 504 {                               \
 505   QLF2(S_S, S_S),               \
 506   QLF2(S_D, S_D),               \
 507 }
 508
 509 /* e.g. FCVTNS <V><d>, <V><n>.  */
 510 #define QL_S_2SAMEH             \
 511 {                               \
 512   QLF2 (S_H, S_H),              \
 513 }
 514
 515 /* e.g. SQXTN <Vb><d>, <Va><n>.  */
 516 #define QL_SISD_NARROW          \
 517 {                               \
 518   QLF2(S_B, S_H),               \
 519   QLF2(S_H, S_S),               \
 520   QLF2(S_S, S_D),               \
 521 }
 522
 523 /* e.g. FCVTXN <Vb><d>, <Va><n>.  */
 524 #define QL_SISD_NARROW_S        \
 525 {                               \
 526   QLF2(S_S, S_D),               \
 527 }
 528
 529 /* e.g. FCVT.  */
 530 #define QL_FCVT                 \
 531 {                               \
 532   QLF2(S_S, S_H),               \
 533   QLF2(S_S, S_D),               \
 534   QLF2(S_D, S_H),               \
 535   QLF2(S_D, S_S),               \
 536   QLF2(S_H, S_S),               \
 537   QLF2(S_H, S_D),               \
 538 }
 539
 540 /* FMOV <Dd>, <Dn>.  */
 541 #define QL_FP2                  \
 542 {                               \
 543   QLF2(S_S, S_S),               \
 544   QLF2(S_D, S_D),               \
 545 }
 546
 547 /* FMOV <Hd>, <Hn>.  */
 548 #define QL_FP2_H                \
 549 {                               \
 550   QLF2 (S_H, S_H),              \
 551 }
 552
 553 /* e.g. SQADD <V><d>, <V><n>, <V><m>.  */
 554 #define QL_S_3SAME              \
 555 {                               \
 556   QLF3(S_B, S_B, S_B),          \
 557   QLF3(S_H, S_H, S_H),          \
 558   QLF3(S_S, S_S, S_S),          \
 559   QLF3(S_D, S_D, S_D),          \
 560 }
 561
 562 /* e.g. CMGE <V><d>, <V><n>, <V><m>.  */
 563 #define QL_S_3SAMED             \
 564 {                               \
 565   QLF3(S_D, S_D, S_D),          \
 566 }
 567
 568 /* e.g. SQDMULH <V><d>, <V><n>, <V><m>.  */
 569 #define QL_SISD_HS              \
 570 {                               \
 571   QLF3(S_H, S_H, S_H),          \
 572   QLF3(S_S, S_S, S_S),          \
 573 }
 574
 575 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>.  */
 576 #define QL_SISDL_HS             \
 577 {                               \
 578   QLF3(S_S, S_H, S_H),          \
 579   QLF3(S_D, S_S, S_S),          \
 580 }
 581
 582 /* FMUL <Sd>, <Sn>, <Sm>.  */
 583 #define QL_FP3                  \
 584 {                               \
 585   QLF3(S_S, S_S, S_S),          \
 586   QLF3(S_D, S_D, S_D),          \
 587 }
 588
 589 /* FMUL <Hd>, <Hn>, <Hm>.  */
 590 #define QL_FP3_H                \
 591 {                               \
 592   QLF3 (S_H, S_H, S_H),         \
 593 }
 594
 595 /* FMADD <Dd>, <Dn>, <Dm>, <Da>.  */
 596 #define QL_FP4                  \
 597 {                               \
 598   QLF4(S_S, S_S, S_S, S_S),     \
 599   QLF4(S_D, S_D, S_D, S_D),     \
 600 }
 601
 602 /* FMADD <Hd>, <Hn>, <Hm>, <Ha>.  */
 603 #define QL_FP4_H                \
 604 {                               \
 605   QLF4 (S_H, S_H, S_H, S_H),    \
 606 }
 607
 608 /* e.g. FCMP <Dn>, #0.0.  */
 609 #define QL_DST_SD                       \
 610 {                               \
 611   QLF2(S_S, NIL),               \
 612   QLF2(S_D, NIL),               \
 613 }
 614
 615 /* e.g. FCMP <Hn>, #0.0.  */
 616 #define QL_DST_H                \
 617 {                               \
 618   QLF2 (S_H, NIL),              \
 619 }
 620
 621 /* FCSEL <Sd>, <Sn>, <Sm>, <cond>.  */
 622 #define QL_FP_COND              \
 623 {                               \
 624   QLF4(S_S, S_S, S_S, NIL),     \
 625   QLF4(S_D, S_D, S_D, NIL),     \
 626 }
 627
 628 /* FCSEL <Hd>, <Hn>, <Hm>, <cond>.  */
 629 #define QL_FP_COND_H            \
 630 {                               \
 631   QLF4 (S_H, S_H, S_H, NIL),    \
 632 }
 633
 634 /* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>.  */
 635 #define QL_CCMP                 \
 636 {                               \
 637   QLF4(W, W, NIL, NIL),         \
 638   QLF4(X, X, NIL, NIL),         \
 639 }
 640
 641 /* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>,  */
 642 #define QL_CCMP_IMM             \
 643 {                               \
 644   QLF4(W, NIL, NIL, NIL),       \
 645   QLF4(X, NIL, NIL, NIL),       \
 646 }
 647
 648 /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>.  */
 649 #define QL_FCCMP                \
 650 {                               \
 651   QLF4(S_S, S_S, NIL, NIL),     \
 652   QLF4(S_D, S_D, NIL, NIL),     \
 653 }
 654
 655 /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>.  */
 656 #define QL_FCCMP_H              \
 657 {                               \
 658   QLF4 (S_H, S_H, NIL, NIL),    \
 659 }
 660
 661 /* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>].  */
 662 #define QL_DUP_VX               \
 663 {                               \
 664   QLF2(V_8B , S_B ),            \
 665   QLF2(V_16B, S_B ),            \
 666   QLF2(V_4H , S_H ),            \
 667   QLF2(V_8H , S_H ),            \
 668   QLF2(V_2S , S_S ),            \
 669   QLF2(V_4S , S_S ),            \
 670   QLF2(V_2D , S_D ),            \
 671 }
 672
 673 /* e.g. DUP <Vd>.<T>, <Wn>.  */
 674 #define QL_DUP_VR               \
 675 {                               \
 676   QLF2(V_8B , W ),              \
 677   QLF2(V_16B, W ),              \
 678   QLF2(V_4H , W ),              \
 679   QLF2(V_8H , W ),              \
 680   QLF2(V_2S , W ),              \
 681   QLF2(V_4S , W ),              \
 682   QLF2(V_2D , X ),              \
 683 }
 684
 685 /* e.g. INS <Vd>.<Ts>[<index>], <Wn>.  */
 686 #define QL_INS_XR               \
 687 {                               \
 688   QLF2(S_H , W ),               \
 689   QLF2(S_S , W ),               \
 690   QLF2(S_D , X ),               \
 691   QLF2(S_B , W ),               \
 692 }
 693
 694 /* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>].  */
 695 #define QL_SMOV                 \
 696 {                               \
 697   QLF2(W , S_H),                \
 698   QLF2(X , S_H),                \
 699   QLF2(X , S_S),                \
 700   QLF2(W , S_B),                \
 701   QLF2(X , S_B),                \
 702 }
 703
 704 /* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>].  */
 705 #define QL_UMOV                 \
 706 {                               \
 707   QLF2(W , S_H),                \
 708   QLF2(W , S_S),                \
 709   QLF2(X , S_D),                \
 710   QLF2(W , S_B),                \
 711 }
 712
 713 /* e.g. MOV <Wd>, <Vn>.<Ts>[<index>].  */
 714 #define QL_MOV                  \
 715 {                               \
 716   QLF2(W , S_S),                \
 717   QLF2(X , S_D),                \
 718 }
 719
 720 /* e.g. SUQADD <Vd>.<T>, <Vn>.<T>.  */
 721 #define QL_V2SAME               \
 722 {                               \
 723   QLF2(V_8B , V_8B ),           \
 724   QLF2(V_16B, V_16B),           \
 725   QLF2(V_4H , V_4H ),           \
 726   QLF2(V_8H , V_8H ),           \
 727   QLF2(V_2S , V_2S ),           \
 728   QLF2(V_4S , V_4S ),           \
 729   QLF2(V_2D , V_2D ),           \
 730 }
 731
 732 /* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>.  */
 733 #define QL_V2SAMES              \
 734 {                               \
 735   QLF2(V_2S , V_2S ),           \
 736   QLF2(V_4S , V_4S ),           \
 737 }
 738
 739 /* e.g. REV32 <Vd>.<T>, <Vn>.<T>.  */
 740 #define QL_V2SAMEBH             \
 741 {                               \
 742   QLF2(V_8B , V_8B ),           \
 743   QLF2(V_16B, V_16B),           \
 744   QLF2(V_4H , V_4H ),           \
 745   QLF2(V_8H , V_8H ),           \
 746 }
 747
 748 /* e.g. FRINTN <Vd>.<T>, <Vn>.<T>.  */
 749 #define QL_V2SAMESD             \
 750 {                               \
 751   QLF2(V_2S , V_2S ),           \
 752   QLF2(V_4S , V_4S ),           \
 753   QLF2(V_2D , V_2D ),           \
 754 }
 755
 756 /* e.g. REV64 <Vd>.<T>, <Vn>.<T>.  */
 757 #define QL_V2SAMEBHS            \
 758 {                               \
 759   QLF2(V_8B , V_8B ),           \
 760   QLF2(V_16B, V_16B),           \
 761   QLF2(V_4H , V_4H ),           \
 762   QLF2(V_8H , V_8H ),           \
 763   QLF2(V_2S , V_2S ),           \
 764   QLF2(V_4S , V_4S ),           \
 765 }
 766
 767 /* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0.  */
 768 #define QL_V2SAMEH              \
 769 {                               \
 770   QLF2 (V_4H, V_4H),            \
 771   QLF2 (V_8H, V_8H),            \
 772 }
 773
 774 /* e.g. REV16 <Vd>.<T>, <Vn>.<T>.  */
 775 #define QL_V2SAMEB              \
 776 {                               \
 777   QLF2(V_8B , V_8B ),           \
 778   QLF2(V_16B, V_16B),           \
 779 }
 780
 781 /* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>.  */
 782 #define QL_V2PAIRWISELONGBHS            \
 783 {                               \
 784   QLF2(V_4H , V_8B ),           \
 785   QLF2(V_8H , V_16B),           \
 786   QLF2(V_2S , V_4H ),           \
 787   QLF2(V_4S , V_8H ),           \
 788   QLF2(V_1D , V_2S ),           \
 789   QLF2(V_2D , V_4S ),           \
 790 }
 791
 792 /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>.  */
 793 #define QL_V2LONGBHS            \
 794 {                               \
 795   QLF2(V_8H , V_8B ),           \
 796   QLF2(V_4S , V_4H ),           \
 797   QLF2(V_2D , V_2S ),           \
 798 }
 799
 800 /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>.  */
 801 #define QL_V2LONGBHS2           \
 802 {                               \
 803   QLF2(V_8H , V_16B),           \
 804   QLF2(V_4S , V_8H ),           \
 805   QLF2(V_2D , V_4S ),           \
 806 }
 807
 808 /* */
 809 #define QL_V3SAME               \
 810 {                               \
 811   QLF3(V_8B , V_8B , V_8B ),    \
 812   QLF3(V_16B, V_16B, V_16B),    \
 813   QLF3(V_4H , V_4H , V_4H ),    \
 814   QLF3(V_8H , V_8H , V_8H ),    \
 815   QLF3(V_2S , V_2S , V_2S ),    \
 816   QLF3(V_4S , V_4S , V_4S ),    \
 817   QLF3(V_2D , V_2D , V_2D )     \
 818 }
 819
 820 /* e.g. SHADD.  */
 821 #define QL_V3SAMEBHS            \
 822 {                               \
 823   QLF3(V_8B , V_8B , V_8B ),    \
 824   QLF3(V_16B, V_16B, V_16B),    \
 825   QLF3(V_4H , V_4H , V_4H ),    \
 826   QLF3(V_8H , V_8H , V_8H ),    \
 827   QLF3(V_2S , V_2S , V_2S ),    \
 828   QLF3(V_4S , V_4S , V_4S ),    \
 829 }
 830
 831 /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
 832 #define QL_V2NARRS              \
 833 {                               \
 834   QLF2(V_2S , V_2D ),           \
 835 }
 836
 837 /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
 838 #define QL_V2NARRS2             \
 839 {                               \
 840   QLF2(V_4S , V_2D ),           \
 841 }
 842
 843 /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
 844 #define QL_V2NARRHS             \
 845 {                               \
 846   QLF2(V_4H , V_4S ),           \
 847   QLF2(V_2S , V_2D ),           \
 848 }
 849
 850 /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
 851 #define QL_V2NARRHS2            \
 852 {                               \
 853   QLF2(V_8H , V_4S ),           \
 854   QLF2(V_4S , V_2D ),           \
 855 }
 856
 857 /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>.  */
 858 #define QL_V2LONGHS             \
 859 {                               \
 860   QLF2(V_4S , V_4H ),           \
 861   QLF2(V_2D , V_2S ),           \
 862 }
 863
 864 /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>.  */
 865 #define QL_V2LONGHS2            \
 866 {                               \
 867   QLF2(V_4S , V_8H ),           \
 868   QLF2(V_2D , V_4S ),           \
 869 }
 870
 871 /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
 872 #define QL_V2NARRBHS            \
 873 {                               \
 874   QLF2(V_8B , V_8H ),           \
 875   QLF2(V_4H , V_4S ),           \
 876   QLF2(V_2S , V_2D ),           \
 877 }
 878
 879 /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
 880 #define QL_V2NARRBHS2           \
 881 {                               \
 882   QLF2(V_16B, V_8H ),           \
 883   QLF2(V_8H , V_4S ),           \
 884   QLF2(V_4S , V_2D ),           \
 885 }
 886
 887 /* e.g. ORR.  */
 888 #define QL_V2SAMEB              \
 889 {                               \
 890   QLF2(V_8B , V_8B ),           \
 891   QLF2(V_16B, V_16B),           \
 892 }
 893
 894 /* e.g. AESE.  */
 895 #define QL_V2SAME16B            \
 896 {                               \
 897   QLF2(V_16B, V_16B),           \
 898 }
 899
 900 /* e.g. SHA1SU1.  */
 901 #define QL_V2SAME4S             \
 902 {                               \
 903   QLF2(V_4S, V_4S),             \
 904 }
 905
 906 /* e.g. SHA1SU0.  */
 907 #define QL_V3SAME4S             \
 908 {                               \
 909   QLF3(V_4S, V_4S, V_4S),       \
 910 }
 911
 912 /* e.g. SHADD.  */
 913 #define QL_V3SAMEB              \
 914 {                               \
 915   QLF3(V_8B , V_8B , V_8B ),    \
 916   QLF3(V_16B, V_16B, V_16B),    \
 917 }
 918
 919 /* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>.  */
 920 #define QL_VEXT                 \
 921 {                                       \
 922   QLF4(V_8B , V_8B , V_8B , imm_0_7),   \
 923   QLF4(V_16B, V_16B, V_16B, imm_0_15),  \
 924 }
 925
 926 /* e.g. .  */
 927 #define QL_V3SAMEHS             \
 928 {                               \
 929   QLF3(V_4H , V_4H , V_4H ),    \
 930   QLF3(V_8H , V_8H , V_8H ),    \
 931   QLF3(V_2S , V_2S , V_2S ),    \
 932   QLF3(V_4S , V_4S , V_4S ),    \
 933 }
 934
 935 /* */
 936 #define QL_V3SAMESD             \
 937 {                               \
 938   QLF3(V_2S , V_2S , V_2S ),    \
 939   QLF3(V_4S , V_4S , V_4S ),    \
 940   QLF3(V_2D , V_2D , V_2D )     \
 941 }
 942
 943 /* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>.  */
 944 #define QL_V3SAMEH              \
 945 {                               \
 946   QLF3 (V_4H , V_4H , V_4H ),   \
 947   QLF3 (V_8H , V_8H , V_8H ),   \
 948 }
 949
 950 /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>.  */
 951 #define QL_V3LONGHS             \
 952 {                               \
 953   QLF3(V_4S , V_4H , V_4H ),    \
 954   QLF3(V_2D , V_2S , V_2S ),    \
 955 }
 956
 957 /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>.  */
 958 #define QL_V3LONGHS2            \
 959 {                               \
 960   QLF3(V_4S , V_8H , V_8H ),    \
 961   QLF3(V_2D , V_4S , V_4S ),    \
 962 }
 963
 964 /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>.  */
 965 #define QL_V3LONGBHS            \
 966 {                               \
 967   QLF3(V_8H , V_8B , V_8B ),    \
 968   QLF3(V_4S , V_4H , V_4H ),    \
 969   QLF3(V_2D , V_2S , V_2S ),    \
 970 }
 971
 972 /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>.  */
 973 #define QL_V3LONGBHS2           \
 974 {                               \
 975   QLF3(V_8H , V_16B , V_16B ),  \
 976   QLF3(V_4S , V_8H , V_8H ),    \
 977   QLF3(V_2D , V_4S , V_4S ),    \
 978 }
 979
 980 /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>.  */
 981 #define QL_V3WIDEBHS            \
 982 {                               \
 983   QLF3(V_8H , V_8H , V_8B ),    \
 984   QLF3(V_4S , V_4S , V_4H ),    \
 985   QLF3(V_2D , V_2D , V_2S ),    \
 986 }
 987
 988 /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>.  */
 989 #define QL_V3WIDEBHS2           \
 990 {                               \
 991   QLF3(V_8H , V_8H , V_16B ),   \
 992   QLF3(V_4S , V_4S , V_8H ),    \
 993   QLF3(V_2D , V_2D , V_4S ),    \
 994 }
 995
 996 /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>.  */
 997 #define QL_V3NARRBHS            \
 998 {                               \
 999   QLF3(V_8B , V_8H , V_8H ),    \
1000   QLF3(V_4H , V_4S , V_4S ),    \
1001   QLF3(V_2S , V_2D , V_2D ),    \
1002 }
1003
1004 /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>.  */
1005 #define QL_V3NARRBHS2           \
1006 {                               \
1007   QLF3(V_16B , V_8H , V_8H ),   \
1008   QLF3(V_8H , V_4S , V_4S ),    \
1009   QLF3(V_4S , V_2D , V_2D ),    \
1010 }
1011
1012 /* e.g. PMULL.  */
1013 #define QL_V3LONGB              \
1014 {                               \
1015   QLF3(V_8H , V_8B , V_8B ),    \
1016 }
1017
1018 /* e.g. PMULL crypto.  */
1019 #define QL_V3LONGD              \
1020 {                               \
1021   QLF3(V_1Q , V_1D , V_1D ),    \
1022 }
1023
1024 /* e.g. PMULL2.  */
1025 #define QL_V3LONGB2             \
1026 {                               \
1027   QLF3(V_8H , V_16B, V_16B),    \
1028 }
1029
1030 /* e.g. PMULL2 crypto.  */
1031 #define QL_V3LONGD2             \
1032 {                               \
1033   QLF3(V_1Q , V_2D , V_2D ),    \
1034 }
1035
1036 /* e.g. SHA1C.  */
1037 #define QL_SHAUPT               \
1038 {                               \
1039   QLF3(S_Q, S_S, V_4S),         \
1040 }
1041
1042 /* e.g. SHA256H2.  */
1043 #define QL_SHA256UPT            \
1044 {                               \
1045   QLF3(S_Q, S_Q, V_4S),         \
1046 }
1047
1048 /* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}].  */
1049 #define QL_W1_LDST_EXC          \
1050 {                               \
1051   QLF2(W, NIL),                 \
1052 }
1053
1054 /* e.g. LDXR <Xt>, [<Xn|SP>{,#0}].  */
1055 #define QL_R1NIL                \
1056 {                               \
1057   QLF2(W, NIL),                 \
1058   QLF2(X, NIL),                 \
1059 }
1060
1061 /* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}].  */
1062 #define QL_W2_LDST_EXC          \
1063 {                               \
1064   QLF3(W, W, NIL),              \
1065 }
1066
1067 /* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}].  */
1068 #define QL_R2_LDST_EXC          \
1069 {                               \
1070   QLF3(W, W, NIL),              \
1071   QLF3(W, X, NIL),              \
1072 }
1073
1074 /* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}].  */
1075 #define QL_R2NIL                \
1076 {                               \
1077   QLF3(W, W, NIL),              \
1078   QLF3(X, X, NIL),              \
1079 }
1080
1081 /* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}].  */
1082 #define QL_R4NIL                \
1083 {                               \
1084   QLF5(W, W, W, W, NIL),        \
1085   QLF5(X, X, X, X, NIL),        \
1086 }
1087
1088 /* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}].  */
1089 #define QL_R3_LDST_EXC          \
1090 {                               \
1091   QLF4(W, W, W, NIL),           \
1092   QLF4(W, X, X, NIL),           \
1093 }
1094
1095 /* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1096 #define QL_LDST_FP              \
1097 {                               \
1098   QLF2(S_B, S_B),               \
1099   QLF2(S_H, S_H),               \
1100   QLF2(S_S, S_S),               \
1101   QLF2(S_D, S_D),               \
1102   QLF2(S_Q, S_Q),               \
1103 }
1104
1105 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1106 #define QL_LDST_R               \
1107 {                               \
1108   QLF2(W, S_S),                 \
1109   QLF2(X, S_D),                 \
1110 }
1111
1112 /* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1113 #define QL_LDST_W8              \
1114 {                               \
1115   QLF2(W, S_B),                 \
1116 }
1117
1118 /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1119 #define QL_LDST_R8              \
1120 {                               \
1121   QLF2(W, S_B),                 \
1122   QLF2(X, S_B),                 \
1123 }
1124
1125 /* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1126 #define QL_LDST_W16             \
1127 {                               \
1128   QLF2(W, S_H),                 \
1129 }
1130
1131 /* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1132 #define QL_LDST_X32             \
1133 {                               \
1134   QLF2(X, S_S),                 \
1135 }
1136
1137 /* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1138 #define QL_LDST_R16             \
1139 {                               \
1140   QLF2(W, S_H),                 \
1141   QLF2(X, S_H),                 \
1142 }
1143
1144 /* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
1145 #define QL_LDST_PRFM            \
1146 {                               \
1147   QLF2(NIL, S_D),               \
1148 }
1149
1150 /* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}].  */
1151 #define QL_LDST_PAIR_X32        \
1152 {                               \
1153   QLF3(X, X, S_S),              \
1154 }
1155
1156 /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!.  */
1157 #define QL_LDST_PAIR_R          \
1158 {                               \
1159   QLF3(W, W, S_S),              \
1160   QLF3(X, X, S_D),              \
1161 }
1162
1163 /* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}].  */
1164 #define QL_LDST_PAIR_FP         \
1165 {                               \
1166   QLF3(S_S, S_S, S_S),          \
1167   QLF3(S_D, S_D, S_D),          \
1168   QLF3(S_Q, S_Q, S_Q),          \
1169 }
1170
1171 /* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>].  */
1172 #define QL_SIMD_LDST            \
1173 {                               \
1174   QLF2(V_8B, NIL),              \
1175   QLF2(V_16B, NIL),             \
1176   QLF2(V_4H, NIL),              \
1177   QLF2(V_8H, NIL),              \
1178   QLF2(V_2S, NIL),              \
1179   QLF2(V_4S, NIL),              \
1180   QLF2(V_2D, NIL),              \
1181 }
1182
1183 /* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>].  */
1184 #define QL_SIMD_LDST_ANY        \
1185 {                               \
1186   QLF2(V_8B, NIL),              \
1187   QLF2(V_16B, NIL),             \
1188   QLF2(V_4H, NIL),              \
1189   QLF2(V_8H, NIL),              \
1190   QLF2(V_2S, NIL),              \
1191   QLF2(V_4S, NIL),              \
1192   QLF2(V_1D, NIL),              \
1193   QLF2(V_2D, NIL),              \
1194 }
1195
1196 /* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>].  */
1197 #define QL_SIMD_LDSTONE         \
1198 {                               \
1199   QLF2(S_B, NIL),               \
1200   QLF2(S_H, NIL),               \
1201   QLF2(S_S, NIL),               \
1202   QLF2(S_D, NIL),               \
1203 }
1204
1205 /* e.g. ADDV <V><d>, <Vn>.<T>.  */
1206 #define QL_XLANES               \
1207 {                               \
1208   QLF2(S_B, V_8B),              \
1209   QLF2(S_B, V_16B),             \
1210   QLF2(S_H, V_4H),              \
1211   QLF2(S_H, V_8H),              \
1212   QLF2(S_S, V_4S),              \
1213 }
1214
1215 /* e.g. FMINV <V><d>, <Vn>.<T>.  */
1216 #define QL_XLANES_FP            \
1217 {                               \
1218   QLF2(S_S, V_4S),              \
1219 }
1220
1221 /* e.g. FMINV <V><d>, <Vn>.<T>.  */
1222 #define QL_XLANES_FP_H          \
1223 {                               \
1224   QLF2 (S_H, V_4H),             \
1225   QLF2 (S_H, V_8H),             \
1226 }
1227
1228 /* e.g. SADDLV <V><d>, <Vn>.<T>.  */
1229 #define QL_XLANES_L             \
1230 {                               \
1231   QLF2(S_H, V_8B),              \
1232   QLF2(S_H, V_16B),             \
1233   QLF2(S_S, V_4H),              \
1234   QLF2(S_S, V_8H),              \
1235   QLF2(S_D, V_4S),              \
1236 }
1237
1238 /* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>].  */
1239 #define QL_ELEMENT              \
1240 {                               \
1241   QLF3(V_4H, V_4H, S_H),        \
1242   QLF3(V_8H, V_8H, S_H),        \
1243   QLF3(V_2S, V_2S, S_S),        \
1244   QLF3(V_4S, V_4S, S_S),        \
1245 }
1246
1247 /* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].  */
1248 #define QL_ELEMENT_L            \
1249 {                               \
1250   QLF3(V_4S, V_4H, S_H),        \
1251   QLF3(V_2D, V_2S, S_S),        \
1252 }
1253
1254 /* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].  */
1255 #define QL_ELEMENT_L2           \
1256 {                               \
1257   QLF3(V_4S, V_8H, S_H),        \
1258   QLF3(V_2D, V_4S, S_S),        \
1259 }
1260
1261 /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>].  */
1262 #define QL_ELEMENT_FP           \
1263 {                               \
1264   QLF3(V_2S, V_2S, S_S),        \
1265   QLF3(V_4S, V_4S, S_S),        \
1266   QLF3(V_2D, V_2D, S_D),        \
1267 }
1268
1269 /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>].  */
1270 #define QL_ELEMENT_FP_H         \
1271 {                               \
1272   QLF3 (V_4H, V_4H, S_H),       \
1273   QLF3 (V_8H, V_8H, S_H),       \
1274 }
1275
1276 /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}.  */
1277 #define QL_SIMD_IMM_S0W         \
1278 {                               \
1279   QLF2(V_2S, LSL),              \
1280   QLF2(V_4S, LSL),              \
1281 }
1282
1283 /* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>.  */
1284 #define QL_SIMD_IMM_S1W         \
1285 {                               \
1286   QLF2(V_2S, MSL),              \
1287   QLF2(V_4S, MSL),              \
1288 }
1289
1290 /* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}.  */
1291 #define QL_SIMD_IMM_S0H         \
1292 {                               \
1293   QLF2(V_4H, LSL),              \
1294   QLF2(V_8H, LSL),              \
1295 }
1296
1297 /* e.g. FMOV <Vd>.<T>, #<imm>.  */
1298 #define QL_SIMD_IMM_S           \
1299 {                               \
1300   QLF2(V_2S, NIL),              \
1301   QLF2(V_4S, NIL),              \
1302 }
1303
1304 /* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}.  */
1305 #define QL_SIMD_IMM_B           \
1306 {                               \
1307   QLF2(V_8B, LSL),              \
1308   QLF2(V_16B, LSL),             \
1309 }
1310 /* e.g. MOVI <Dd>, #<imm>.  */
1311 #define QL_SIMD_IMM_D           \
1312 {                               \
1313   QLF2(S_D, NIL),               \
1314 }
1315
1316 /* e.g. MOVI <Vd>.2D, #<imm>.  */
1317 #define QL_SIMD_IMM_V2D         \
1318 {                               \
1319   QLF2(V_2D, NIL),              \
1320 }
1321 \f
1322 /* Opcode table.  */
1323
1324 static const aarch64_feature_set aarch64_feature_v8 =
1325   AARCH64_FEATURE (AARCH64_FEATURE_V8, 0);
1326 static const aarch64_feature_set aarch64_feature_fp =
1327   AARCH64_FEATURE (AARCH64_FEATURE_FP, 0);
1328 static const aarch64_feature_set aarch64_feature_simd =
1329   AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0);
1330 static const aarch64_feature_set aarch64_feature_crypto =
1331   AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0);
1332 static const aarch64_feature_set aarch64_feature_crc =
1333   AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
1334 static const aarch64_feature_set aarch64_feature_lse =
1335   AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
1336 static const aarch64_feature_set aarch64_feature_lor =
1337   AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
1338 static const aarch64_feature_set aarch64_feature_rdma =
1339   AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
1340 static const aarch64_feature_set aarch64_feature_ras =
1341   AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0);
1342 static const aarch64_feature_set aarch64_feature_v8_2 =
1343   AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
1344 static const aarch64_feature_set aarch64_feature_fp_f16 =
1345   AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
1346 static const aarch64_feature_set aarch64_feature_simd_f16 =
1347   AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0);
1348 static const aarch64_feature_set aarch64_feature_stat_profile =
1349   AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
1350
1351 #define CORE    &aarch64_feature_v8
1352 #define FP      &aarch64_feature_fp
1353 #define SIMD    &aarch64_feature_simd
1354 #define CRYPTO  &aarch64_feature_crypto
1355 #define CRC     &aarch64_feature_crc
1356 #define LSE     &aarch64_feature_lse
1357 #define LOR     &aarch64_feature_lor
1358 #define RDMA    &aarch64_feature_rdma
1359 #define FP_F16  &aarch64_feature_fp_f16
1360 #define SIMD_F16        &aarch64_feature_simd_f16
1361 #define RAS     &aarch64_feature_ras
1362 #define STAT_PROFILE    &aarch64_feature_stat_profile
1363 #define ARMV8_2 &aarch64_feature_v8_2
1364
1365 struct aarch64_opcode aarch64_opcode_table[] =
1366 {
1367   /* Add/subtract (with carry).  */
1368   {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1369   {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
1370   {"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1371   {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1372   {"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1373   {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry, 0, CORE, OP2 (Rd, Rm), QL_I2SAME, F_ALIAS | F_SF},
1374   /* Add/subtract (extended register).  */
1375   {"add", 0x0b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
1376   {"adds", 0x2b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
1377   {"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
1378   {"sub", 0x4b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd_SP, Rn_SP, Rm_EXT), QL_I3_EXT, F_SF},
1379   {"subs", 0x6b200000, 0x7fe00000, addsub_ext, 0, CORE, OP3 (Rd, Rn_SP, Rm_EXT), QL_I3_EXT, F_HAS_ALIAS | F_SF},
1380   {"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext, 0, CORE, OP2 (Rn_SP, Rm_EXT), QL_I2_EXT, F_ALIAS | F_SF},
1381   /* Add/subtract (immediate).  */
1382   {"add", 0x11000000, 0x7f000000, addsub_imm, OP_ADD, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
1383   {"mov", 0x11000000, 0x7ffffc00, addsub_imm, 0, CORE, OP2 (Rd_SP, Rn_SP), QL_I2SP, F_ALIAS | F_SF},
1384   {"adds", 0x31000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
1385   {"cmn", 0x3100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
1386   {"sub", 0x51000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF},
1387   {"subs", 0x71000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
1388   {"cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, CORE, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF},
1389   /* Add/subtract (shifted register).  */
1390   {"add", 0xb000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
1391   {"adds", 0x2b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1392   {"cmn", 0x2b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1393   {"sub", 0x4b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1394   {"neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1395   {"subs", 0x6b000000, 0x7f200000, addsub_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
1396   {"cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1397   {"negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF},
1398   /* AdvSIMD across lanes.  */
1399   {"saddlv", 0xe303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
1400   {"smaxv", 0xe30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1401   {"sminv", 0xe31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1402   {"addv", 0xe31b800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1403   {"uaddlv", 0x2e303800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ},
1404   {"umaxv", 0x2e30a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1405   {"uminv", 0x2e31a800, 0xbf3ffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES, F_SIZEQ},
1406   {"fmaxnmv", 0x2e30c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
1407   {"fmaxnmv", 0xe30c800, 0xbffffc00, asimdall, 0, SIMD_F16,
1408    OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
1409   {"fmaxv", 0x2e30f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
1410   {"fmaxv", 0xe30f800, 0xbffffc00, asimdall, 0, SIMD_F16,
1411    OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
1412   {"fminnmv", 0x2eb0c800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
1413   {"fminnmv", 0xeb0c800, 0xbffffc00, asimdall, 0, SIMD_F16,
1414    OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
1415   {"fminv", 0x2eb0f800, 0xbfbffc00, asimdall, 0, SIMD, OP2 (Fd, Vn), QL_XLANES_FP, F_SIZEQ},
1416   {"fminv", 0xeb0f800, 0xbffffc00, asimdall, 0, SIMD_F16,
1417    OP2 (Fd, Vn), QL_XLANES_FP_H, F_SIZEQ},
1418   /* AdvSIMD three different.  */
1419   {"saddl", 0x0e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1420   {"saddl2", 0x4e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1421   {"saddw", 0x0e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1422   {"saddw2", 0x4e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1423   {"ssubl", 0x0e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1424   {"ssubl2", 0x4e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1425   {"ssubw", 0x0e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1426   {"ssubw2", 0x4e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1427   {"addhn", 0x0e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1428   {"addhn2", 0x4e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1429   {"sabal", 0x0e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1430   {"sabal2", 0x4e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1431   {"subhn", 0x0e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1432   {"subhn2", 0x4e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1433   {"sabdl", 0x0e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1434   {"sabdl2", 0x4e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1435   {"smlal", 0x0e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1436   {"smlal2", 0x4e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1437   {"sqdmlal", 0x0e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
1438   {"sqdmlal2", 0x4e209000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
1439   {"smlsl", 0x0e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1440   {"smlsl2", 0x4e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1441   {"sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
1442   {"sqdmlsl2", 0x4e20b000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
1443   {"smull", 0x0e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1444   {"smull2", 0x4e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1445   {"sqdmull", 0x0e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS, F_SIZEQ},
1446   {"sqdmull2", 0x4e20d000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGHS2, F_SIZEQ},
1447   {"pmull", 0x0e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB, 0},
1448   {"pmull", 0x0ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD, 0},
1449   {"pmull2", 0x4e20e000, 0xffe0fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGB2, 0},
1450   {"pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3LONGD2, 0},
1451   {"uaddl", 0x2e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1452   {"uaddl2", 0x6e200000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1453   {"uaddw", 0x2e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1454   {"uaddw2", 0x6e201000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1455   {"usubl", 0x2e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1456   {"usubl2", 0x6e202000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1457   {"usubw", 0x2e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS, F_SIZEQ},
1458   {"usubw2", 0x6e203000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3WIDEBHS2, F_SIZEQ},
1459   {"raddhn", 0x2e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1460   {"raddhn2", 0x6e204000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1461   {"uabal", 0x2e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1462   {"uabal2", 0x6e205000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1463   {"rsubhn", 0x2e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS, F_SIZEQ},
1464   {"rsubhn2", 0x6e206000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3NARRBHS2, F_SIZEQ},
1465   {"uabdl", 0x2e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1466   {"uabdl2", 0x6e207000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1467   {"umlal", 0x2e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1468   {"umlal2", 0x6e208000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1469   {"umlsl", 0x2e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1470   {"umlsl2", 0x6e20a000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1471   {"umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ},
1472   {"umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ},
1473   /* AdvSIMD vector x indexed element.  */
1474   {"smlal", 0x0f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1475   {"smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1476   {"sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1477   {"sqdmlal2", 0x4f003000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1478   {"smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1479   {"smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1480   {"sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1481   {"sqdmlsl2", 0x4f007000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1482   {"mul", 0xf008000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1483   {"smull", 0x0f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1484   {"smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1485   {"sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1486   {"sqdmull2", 0x4f00b000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1487   {"sqdmulh", 0xf00c000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1488   {"sqrdmulh", 0xf00d000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1489   {"fmla", 0xf801000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
1490   {"fmla", 0xf001000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1491    OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
1492   {"fmls", 0xf805000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
1493   {"fmls", 0xf005000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1494    OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
1495   {"fmul", 0xf809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
1496   {"fmul", 0xf009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1497    OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
1498   {"mla", 0x2f000000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1499   {"umlal", 0x2f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1500   {"umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1501   {"mls", 0x2f004000, 0xbf00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1502   {"umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1503   {"umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1504   {"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
1505   {"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
1506   {"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
1507   {"fmulx", 0x2f009000, 0xbfe0fc00, asimdelem, 0, SIMD_F16,
1508    OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ},
1509   {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1510   {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
1511   /* AdvSIMD EXT.  */
1512   {"ext", 0x2e000000, 0xbfe08400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
1513   /* AdvSIMD modified immediate.  */
1514   {"movi", 0xf000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1515   {"orr", 0xf001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1516   {"movi", 0xf008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1517   {"orr", 0xf009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1518   {"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
1519   {"movi", 0xf00e400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ},
1520   {"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ},
1521   {"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1522   {"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
1523   {"mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1524   {"bic", 0x2f009400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
1525   {"mvni", 0x2f00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
1526   {"movi", 0x2f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Sd, SIMD_IMM), QL_SIMD_IMM_D, F_SIZEQ},
1527   {"movi", 0x6f00e400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM), QL_SIMD_IMM_V2D, F_SIZEQ},
1528   {"fmov", 0x6f00f400, 0xfff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_V2D, F_SIZEQ},
1529   /* AdvSIMD copy.  */
1530   {"dup", 0xe000400, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, En), QL_DUP_VX, F_T},
1531   {"dup", 0xe000c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Vd, Rn), QL_DUP_VR, F_T},
1532   {"smov", 0xe002c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_SMOV, F_GPRSIZE_IN_Q},
1533   {"umov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_UMOV, F_HAS_ALIAS | F_GPRSIZE_IN_Q},
1534   {"mov", 0xe003c00, 0xbfe0fc00, asimdins, 0, SIMD, OP2 (Rd, En), QL_MOV, F_ALIAS | F_GPRSIZE_IN_Q},
1535   {"ins", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_HAS_ALIAS},
1536   {"mov", 0x4e001c00, 0xffe0fc00, asimdins, 0, SIMD, OP2 (Ed, Rn), QL_INS_XR, F_ALIAS},
1537   {"ins", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS},
1538   {"mov", 0x6e000400, 0xffe08400, asimdins, 0, SIMD, OP2 (Ed, En), QL_S_2SAME, F_ALIAS},
1539   /* AdvSIMD two-reg misc.  */
1540   {"rev64", 0xe200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
1541   {"rev16", 0xe201800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
1542   {"saddlp", 0xe202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1543   {"suqadd", 0xe203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1544   {"cls", 0xe204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
1545   {"cnt", 0xe205800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
1546   {"sadalp", 0xe206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1547   {"sqabs", 0xe207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1548   {"cmgt", 0xe208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1549   {"cmeq", 0xe209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1550   {"cmlt", 0xe20a800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1551   {"abs", 0xe20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1552   {"xtn", 0xe212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1553   {"xtn2", 0x4e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1554   {"sqxtn", 0xe214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1555   {"sqxtn2", 0x4e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1556   {"fcvtn", 0xe216800, 0xffbffc00, asimdmisc, OP_FCVTN, SIMD, OP2 (Vd, Vn), QL_V2NARRHS, F_MISC},
1557   {"fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc, OP_FCVTN2, SIMD, OP2 (Vd, Vn), QL_V2NARRHS2, F_MISC},
1558   {"fcvtl", 0xe217800, 0xffbffc00, asimdmisc, OP_FCVTL, SIMD, OP2 (Vd, Vn), QL_V2LONGHS, F_MISC},
1559   {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc, OP_FCVTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGHS2, F_MISC},
1560   {"frintn", 0xe218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1561   {"frintn", 0xe798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1562    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1563   {"frintm", 0xe219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1564   {"frintm", 0xe799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1565    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1566   {"fcvtns", 0xe21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1567   {"fcvtns", 0xe79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1568    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1569   {"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1570   {"fcvtms", 0xe79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1571    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1572   {"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1573   {"fcvtas", 0xe79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1574    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1575   {"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1576   {"scvtf", 0xe79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1577    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1578   {"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
1579   {"fcmgt", 0xef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1580    OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
1581   {"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
1582   {"fcmeq", 0xef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1583    OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
1584   {"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
1585   {"fcmlt", 0xef8e800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1586    OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
1587   {"fabs", 0xea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1588   {"fabs", 0xef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1589    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1590   {"frintp", 0xea18800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1591   {"frintp", 0xef98800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1592    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1593   {"frintz", 0xea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1594   {"frintz", 0xef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1595    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1596   {"fcvtps", 0xea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1597   {"fcvtps", 0xef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1598    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1599   {"fcvtzs", 0xea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1600   {"fcvtzs", 0xef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1601    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1602   {"urecpe", 0xea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
1603   {"frecpe", 0xea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1604   {"frecpe", 0xef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1605    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1606   {"rev32", 0x2e200800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBH, F_SIZEQ},
1607   {"uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1608   {"usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1609   {"clz", 0x2e204800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ},
1610   {"uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ},
1611   {"sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1612   {"cmge", 0x2e208800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1613   {"cmle", 0x2e209800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, IMM0), QL_V2SAME, F_SIZEQ},
1614   {"neg", 0x2e20b800, 0xbf3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAME, F_SIZEQ},
1615   {"sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1616   {"sqxtun2", 0x6e212800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1617   {"shll", 0x2e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS, F_SIZEQ},
1618   {"shll2", 0x6e213800, 0xff3ffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, SHLL_IMM), QL_V2LONGBHS2, F_SIZEQ},
1619   {"uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS, F_SIZEQ},
1620   {"uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRBHS2, F_SIZEQ},
1621   {"fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS, 0},
1622   {"fcvtxn2", 0x6e616800, 0xfffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2NARRS2, 0},
1623   {"frinta", 0x2e218800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1624   {"frinta", 0x2e798800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1625    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1626   {"frintx", 0x2e219800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1627   {"frintx", 0x2e799800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1628    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1629   {"fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1630   {"fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1631    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1632   {"fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1633   {"fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1634    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1635   {"fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1636   {"fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1637    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1638   {"ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1639   {"ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1640    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1641   {"not", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_HAS_ALIAS},
1642   {"mvn", 0x2e205800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ | F_ALIAS},
1643   {"rbit", 0x2e605800, 0xbffffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ},
1644   {"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
1645   {"fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1646    OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
1647   {"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP3 (Vd, Vn, FPIMM0), QL_V2SAMESD, F_SIZEQ},
1648   {"fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1649    OP3 (Vd, Vn, FPIMM0), QL_V2SAMEH, F_SIZEQ},
1650   {"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1651   {"fneg", 0x2ef8f800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1652    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1653   {"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1654   {"frinti", 0x2ef99800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1655    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1656   {"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1657   {"fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1658    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1659   {"fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1660   {"fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc, 0, SIMD_F16,
1661    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1662   {"ursqrte", 0x2ea1c800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMES, F_SIZEQ},
1663   {"frsqrte", 0x2ea1d800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1664   {"frsqrte", 0x2ef9d800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1665    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1666   {"fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc, 0, SIMD, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ},
1667   {"fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc, 0, SIMD_F16,
1668    OP2 (Vd, Vn), QL_V2SAMEH, F_SIZEQ},
1669   /* AdvSIMD ZIP/UZP/TRN.  */
1670   {"uzp1", 0xe001800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1671   {"trn1", 0xe002800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1672   {"zip1", 0xe003800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1673   {"uzp2", 0xe005800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1674   {"trn2", 0xe006800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1675   {"zip2", 0xe007800, 0xbf20fc00, asimdperm, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1676   /* AdvSIMD three same.  */
1677   {"shadd", 0xe200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1678   {"sqadd", 0xe200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1679   {"srhadd", 0xe201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1680   {"shsub", 0xe202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1681   {"sqsub", 0xe202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1682   {"cmgt", 0xe203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1683   {"cmge", 0xe203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1684   {"sshl", 0xe204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1685   {"sqshl", 0xe204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1686   {"srshl", 0xe205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1687   {"sqrshl", 0xe205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1688   {"smax", 0xe206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1689   {"smin", 0xe206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1690   {"sabd", 0xe207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1691   {"saba", 0xe207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1692   {"add", 0xe208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1693   {"cmtst", 0xe208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1694   {"mla", 0xe209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1695   {"mul", 0xe209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1696   {"smaxp", 0xe20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1697   {"sminp", 0xe20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1698   {"sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1699   {"addp", 0xe20bc00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1700   {"fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1701   {"fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1702    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1703   {"fmla", 0xe20cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1704   {"fmla", 0xe400c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1705    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1706   {"fadd", 0xe20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1707   {"fadd", 0xe401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1708    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1709   {"fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1710   {"fmulx", 0xe401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1711    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1712   {"fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1713   {"fcmeq", 0xe402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1714    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1715   {"fmax", 0xe20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1716   {"fmax", 0xe403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1717    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1718   {"frecps", 0xe20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1719   {"frecps", 0xe403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1720    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1721   {"and", 0xe201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1722   {"bic", 0xe601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1723   {"fminnm", 0xea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1724   {"fminnm", 0xec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1725    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1726   {"fmls", 0xea0cc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1727   {"fmls", 0xec00c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1728    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1729   {"fsub", 0xea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1730   {"fsub", 0xec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1731    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1732   {"fmin", 0xea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1733   {"fmin", 0xec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1734    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1735   {"frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1736   {"frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1737    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1738   {"orr", 0xea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_HAS_ALIAS | F_SIZEQ},
1739   {"mov", 0xea01c00, 0xbfe0fc00, asimdsame, OP_MOV_V, SIMD, OP2 (Vd, Vn), QL_V2SAMEB, F_ALIAS | F_CONV},
1740   {"orn", 0xee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1741   {"uhadd", 0x2e200400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1742   {"uqadd", 0x2e200c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1743   {"urhadd", 0x2e201400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1744   {"uhsub", 0x2e202400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1745   {"uqsub", 0x2e202c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1746   {"cmhi", 0x2e203400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1747   {"cmhs", 0x2e203c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1748   {"ushl", 0x2e204400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1749   {"uqshl", 0x2e204c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1750   {"urshl", 0x2e205400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1751   {"uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1752   {"umax", 0x2e206400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1753   {"umin", 0x2e206c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1754   {"uabd", 0x2e207400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1755   {"uaba", 0x2e207c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1756   {"sub", 0x2e208400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1757   {"cmeq", 0x2e208c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAME, F_SIZEQ},
1758   {"mls", 0x2e209400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1759   {"pmul", 0x2e209c00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1760   {"umaxp", 0x2e20a400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1761   {"uminp", 0x2e20ac00, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEBHS, F_SIZEQ},
1762   {"sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1763   {"fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1764   {"fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1765    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1766   {"faddp", 0x2e20d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1767   {"faddp", 0x2e401400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1768    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1769   {"fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1770   {"fmul", 0x2e401c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1771    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1772   {"fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1773   {"fcmge", 0x2e402400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1774    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1775   {"facge", 0x2e20ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1776   {"facge", 0x2e402c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1777    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1778   {"fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1779   {"fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1780    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1781   {"fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1782   {"fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1783    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1784   {"eor", 0x2e201c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1785   {"bsl", 0x2e601c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1786   {"fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1787   {"fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1788    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1789   {"fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1790   {"fabd", 0x2ec01400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1791    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1792   {"fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1793   {"fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1794    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1795   {"facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1796   {"facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1797    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1798   {"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
1799   {"fminp", 0x2ec03400, 0xbfe0fc00, asimdsame, 0, SIMD_F16,
1800    OP3 (Vd, Vn, Vm), QL_V3SAMEH, F_SIZEQ},
1801   {"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1802   {"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
1803   /* AdvSIMD three same extension.  */
1804   {"sqrdmlah", 0x2e008400, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1805   {"sqrdmlsh", 0x2e008c00, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
1806   /* AdvSIMD shift by immediate.  */
1807   {"sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1808   {"ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1809   {"srshr", 0xf002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1810   {"srsra", 0xf003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1811   {"shl", 0xf005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1812   {"sqshl", 0xf007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1813   {"shrn", 0xf008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1814   {"shrn2", 0x4f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1815   {"rshrn", 0xf008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1816   {"rshrn2", 0x4f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1817   {"sqshrn", 0xf009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1818   {"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1819   {"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1820   {"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1821   {"sshll", 0xf00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
1822   {"sxtl", 0xf00a400, 0xff87fc00, asimdshf, OP_SXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
1823   {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
1824   {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf, OP_SXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
1825   {"scvtf", 0xf00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
1826   {"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
1827   {"ushr", 0x2f000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1828   {"usra", 0x2f001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1829   {"urshr", 0x2f002400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1830   {"ursra", 0x2f003400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1831   {"sri", 0x2f004400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
1832   {"sli", 0x2f005400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1833   {"sqshlu", 0x2f006400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1834   {"uqshl", 0x2f007400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFT, 0},
1835   {"sqshrun", 0x2f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1836   {"sqshrun2", 0x6f008400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1837   {"sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1838   {"sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1839   {"uqshrn", 0x2f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1840   {"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1841   {"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN, 0},
1842   {"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFTN2, 0},
1843   {"ushll", 0x2f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL, F_HAS_ALIAS},
1844   {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf, OP_UXTL, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS, F_ALIAS | F_CONV},
1845   {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSL), QL_VSHIFTL2, F_HAS_ALIAS},
1846   {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf, OP_UXTL2, SIMD, OP2 (Vd, Vn), QL_V2LONGBHS2, F_ALIAS | F_CONV},
1847   {"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
1848   {"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT_SD, 0},
1849   /* AdvSIMD TBL/TBX.  */
1850   {"tbl", 0xe000000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
1851   {"tbx", 0xe001000, 0xbfe09c00, asimdtbl, 0, SIMD, OP3 (Vd, LVn, Vm), QL_TABLE, F_SIZEQ},
1852   /* AdvSIMD scalar three different.  */
1853   {"sqdmlal", 0x5e209000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
1854   {"sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
1855   {"sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE},
1856   /* AdvSIMD scalar x indexed element.  */
1857   {"sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
1858   {"sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
1859   {"sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE},
1860   {"sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1861   {"sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1862   {"fmla", 0x5f801000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
1863   {"fmla", 0x5f001000, 0xffc0f400, asisdelem, 0, SIMD_F16,
1864    OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
1865   {"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
1866   {"fmls", 0x5f005000, 0xffc0f400, asisdelem, 0, SIMD_F16,
1867    OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
1868   {"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
1869   {"fmul", 0x5f009000, 0xffc0f400, asisdelem, 0, SIMD_F16,
1870    OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
1871   {"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
1872   {"fmulx", 0x7f009000, 0xffc0f400, asisdelem, 0, SIMD_F16,
1873    OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
1874   {"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1875   {"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
1876   /* AdvSIMD load/store multiple structures.  */
1877   {"st4", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1878   {"st1", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1879   {"st2", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1880   {"st3", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1881   {"ld4", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1882   {"ld1", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1883   {"ld2", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1884   {"ld3", 0xc400000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1885   /* AdvSIMD load/store multiple structures (post-indexed).  */
1886   {"st4", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1887   {"st1", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1888   {"st2", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1889   {"st3", 0xc800000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1890   {"ld4", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
1891   {"ld1", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1892   {"ld2", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(2)},
1893   {"ld3", 0xcc00000, 0xbfe00000, asisdlsep, 0, SIMD, OP2 (LVt, SIMD_ADDR_POST), QL_SIMD_LDST, F_SIZEQ | F_OD(3)},
1894   /* AdvSIMD load/store single structure.  */
1895   {"st1", 0xd000000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
1896   {"st3", 0xd002000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
1897   {"st2", 0xd200000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
1898   {"st4", 0xd202000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
1899   {"ld1", 0xd400000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(1)},
1900   {"ld3", 0xd402000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(3)},
1901   {"ld1r", 0xd40c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1902   {"ld3r", 0xd40e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)},
1903   {"ld2", 0xd600000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(2)},
1904   {"ld4", 0xd602000, 0xbfff2000, asisdlso, 0, SIMD, OP2 (LEt, SIMD_ADDR_SIMPLE), QL_SIMD_LDSTONE, F_OD(4)},
1905   {"ld2r", 0xd60c000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)},
1906   {"ld4r", 0xd60e000, 0xbfffe000, asisdlso, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)},
1907   /* AdvSIMD load/store single structure (post-indexed).  */
1908   {"st1", 0xd800000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)},
1909   {"st3", 0xd802000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)},
1910   {"st2", 0xda00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)},
1911   {"st4", 0xda02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)},
1912   {"ld1", 0xdc00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(1)},
1913   {"ld3", 0xdc02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(3)},
1914   {"ld1r", 0xdc0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
1915   {"ld3r", 0xdc0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(3)},
1916   {"ld2", 0xde00000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(2)},
1917   {"ld4", 0xde02000, 0xbfe02000, asisdlsop, 0, SIMD, OP2 (LEt, SIMD_ADDR_POST), QL_SIMD_LDSTONE, F_OD(4)},
1918   {"ld2r", 0xde0c000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(2)},
1919   {"ld4r", 0xde0e000, 0xbfe0e000, asisdlsop, 0, SIMD, OP2 (LVt_AL, SIMD_ADDR_POST), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(4)},
1920   /* AdvSIMD scalar two-reg misc.  */
1921   {"suqadd", 0x5e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1922   {"sqabs", 0x5e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1923   {"cmgt", 0x5e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1924   {"cmeq", 0x5e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1925   {"cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1926   {"abs", 0x5e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE},
1927   {"sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
1928   {"fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1929   {"fcvtns", 0x5e79a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1930    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1931   {"fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1932   {"fcvtms", 0x5e79b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1933    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1934   {"fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1935   {"fcvtas", 0x5e79c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1936    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1937   {"scvtf", 0x5e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1938   {"scvtf", 0x5e79d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1939    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1940   {"fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
1941   {"fcmgt", 0x5ef8c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1942    OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
1943   {"fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
1944   {"fcmeq", 0x5ef8d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1945    OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
1946   {"fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
1947   {"fcmlt", 0x5ef8e800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1948    OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
1949   {"fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1950   {"fcvtps", 0x5ef9a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1951    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1952   {"fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1953   {"fcvtzs", 0x5ef9b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1954    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1955   {"frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1956   {"frecpe", 0x5ef9d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1957    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1958   {"frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1959   {"frecpx", 0x5ef9f800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1960    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1961   {"usqadd", 0x7e203800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1962   {"sqneg", 0x7e207800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAME, F_SSIZE},
1963   {"cmge", 0x7e208800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1964   {"cmle", 0x7e209800, 0xff3ffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, IMM0), QL_SISD_CMP_0, F_SSIZE},
1965   {"neg", 0x7e20b800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_2SAMED, F_SSIZE},
1966   {"sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
1967   {"uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW, F_SSIZE},
1968   {"fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc, OP_FCVTXN_S, SIMD, OP2 (Sd, Sn), QL_SISD_NARROW_S, F_MISC},
1969   {"fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1970   {"fcvtnu", 0x7e79a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1971    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1972   {"fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1973   {"fcvtmu", 0x7e79b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1974    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1975   {"fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1976   {"fcvtau", 0x7e79c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1977    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1978   {"ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1979   {"ucvtf", 0x7e79d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1980    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1981   {"fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
1982   {"fcmge", 0x7ef8c800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1983    OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
1984   {"fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc, 0, SIMD, OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_0, F_SSIZE},
1985   {"fcmle", 0x7ef8d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1986    OP3 (Sd, Sn, FPIMM0), QL_SISD_FCMP_H_0, F_SSIZE},
1987   {"fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1988   {"fcvtpu", 0x7ef9a800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1989    OP2 (Sd, Sn), QL_SISD_FCMP_H_0, F_SSIZE},
1990   {"fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1991   {"fcvtzu", 0x7ef9b800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1992    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1993   {"frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc, 0, SIMD, OP2 (Sd, Sn), QL_S_2SAMESD, F_SSIZE},
1994   {"frsqrte", 0x7ef9d800, 0xfffffc00, asisdmisc, 0, SIMD_F16,
1995    OP2 (Sd, Sn), QL_S_2SAMEH, F_SSIZE},
1996   /* AdvSIMD scalar copy.  */
1997   {"dup", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_HAS_ALIAS},
1998   {"mov", 0x5e000400, 0xffe0fc00, asisdone, 0, SIMD, OP2 (Sd, En), QL_S_2SAME, F_ALIAS},
1999   /* AdvSIMD scalar pairwise.  */
2000   {"addp", 0x5e31b800, 0xff3ffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR_D, F_SIZEQ},
2001   {"fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
2002   {"faddp", 0x7e30d800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
2003   {"fmaxp", 0x7e30f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
2004   {"fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
2005   {"fminp", 0x7eb0f800, 0xffbffc00, asisdpair, 0, SIMD, OP2 (Sd, Vn), QL_SISD_PAIR, F_SIZEQ},
2006   /* AdvSIMD scalar three same.  */
2007   {"sqadd", 0x5e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2008   {"sqsub", 0x5e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2009   {"sqshl", 0x5e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2010   {"sqrshl", 0x5e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2011   {"sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
2012   {"fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
2013   {"fmulx", 0x5e401c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2014    OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
2015   {"fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
2016   {"fcmeq", 0x5e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2017    OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
2018   {"frecps", 0x5e20fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
2019   {"frecps", 0x5e403c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2020    OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
2021   {"frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
2022   {"frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2023    OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
2024   {"cmgt", 0x5ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2025   {"cmge", 0x5ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2026   {"sshl", 0x5ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2027   {"srshl", 0x5ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2028   {"add", 0x5ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2029   {"cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2030   {"uqadd", 0x7e200c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2031   {"uqsub", 0x7e202c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2032   {"uqshl", 0x7e204c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2033   {"uqrshl", 0x7e205c00, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAME, F_SSIZE},
2034   {"sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
2035   {"fcmge", 0x7e20e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
2036   {"fcmge", 0x7e402400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2037    OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
2038   {"facge", 0x7e20ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
2039   {"facge", 0x7e402c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2040    OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
2041   {"fabd", 0x7ea0d400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
2042   {"fabd", 0x7ec01400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2043    OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
2044   {"fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
2045   {"fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2046    OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
2047   {"facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_FP3, F_SSIZE},
2048   {"facgt", 0x7ec02c00, 0xffe0fc00, asisdsame, 0, SIMD_F16,
2049    OP3 (Sd, Sn, Sm), QL_FP3_H, F_SSIZE},
2050   {"cmhi", 0x7ee03400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2051   {"cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2052   {"ushl", 0x7ee04400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2053   {"urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2054   {"sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2055   {"cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
2056   /* AdvSIMDs scalar three same extension.  */
2057   {"sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
2058   {"sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
2059   /* AdvSIMD scalar shift by immediate.  */
2060   {"sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2061   {"ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2062   {"srshr", 0x5f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2063   {"srsra", 0x5f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2064   {"shl", 0x5f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0},
2065   {"sqshl", 0x5f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
2066   {"sqshrn", 0x5f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2067   {"sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2068   {"scvtf", 0x5f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
2069   {"fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
2070   {"ushr", 0x7f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2071   {"usra", 0x7f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2072   {"urshr", 0x7f002400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2073   {"ursra", 0x7f003400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2074   {"sri", 0x7f004400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
2075   {"sli", 0x7f005400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT_D, 0},
2076   {"sqshlu", 0x7f006400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
2077   {"uqshl", 0x7f007400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSL), QL_SSHIFT, 0},
2078   {"sqshrun", 0x7f008400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2079   {"sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2080   {"uqshrn", 0x7f009400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2081   {"uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFTN, 0},
2082   {"ucvtf", 0x7f00e400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
2083   {"fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_SD, 0},
2084   /* Bitfield.  */
2085   {"sbfm", 0x13000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
2086   {"sbfiz", 0x13000000, 0x7f800000, bitfield, OP_SBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2087   {"sbfx", 0x13000000, 0x7f800000, bitfield, OP_SBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2088   {"sxtb", 0x13001c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N},
2089   {"sxth", 0x13003c00, 0x7fbffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT, F_ALIAS | F_P3 | F_SF | F_N},
2090   {"sxtw", 0x93407c00, 0xfffffc00, bitfield, 0, CORE, OP2 (Rd, Rn), QL_EXT_W, F_ALIAS | F_P3},
2091   {"asr", 0x13000000, 0x7f800000, bitfield, OP_ASR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
2092   {"bfm", 0x33000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
2093   {"bfi", 0x33000000, 0x7f800000, bitfield, OP_BFI, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2094   {"bfc", 0x330003e0, 0x7f8003e0, bitfield, OP_BFC, ARMV8_2,
2095    OP3 (Rd, IMM, WIDTH), QL_BF1, F_ALIAS | F_P2 | F_CONV},
2096   {"bfxil", 0x33000000, 0x7f800000, bitfield, OP_BFXIL, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2097   {"ubfm", 0x53000000, 0x7f800000, bitfield, 0, CORE, OP4 (Rd, Rn, IMMR, IMMS), QL_BF, F_HAS_ALIAS | F_SF | F_N},
2098   {"ubfiz", 0x53000000, 0x7f800000, bitfield, OP_UBFIZ, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2099   {"ubfx", 0x53000000, 0x7f800000, bitfield, OP_UBFX, CORE, OP4 (Rd, Rn, IMM, WIDTH), QL_BF2, F_ALIAS | F_P1 | F_CONV},
2100   {"uxtb", 0x53001c00, 0xfffffc00, bitfield, OP_UXTB, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3},
2101   {"uxth", 0x53003c00, 0xfffffc00, bitfield, OP_UXTH, CORE, OP2 (Rd, Rn), QL_I2SAMEW, F_ALIAS | F_P3},
2102   {"lsl", 0x53000000, 0x7f800000, bitfield, OP_LSL_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
2103   {"lsr", 0x53000000, 0x7f800000, bitfield, OP_LSR_IMM, CORE, OP3 (Rd, Rn, IMM), QL_SHIFT, F_ALIAS | F_P2 | F_CONV},
2104   /* Unconditional branch (immediate).  */
2105   {"b", 0x14000000, 0xfc000000, branch_imm, OP_B, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0},
2106   {"bl", 0x94000000, 0xfc000000, branch_imm, OP_BL, CORE, OP1 (ADDR_PCREL26), QL_PCREL_26, 0},
2107   /* Unconditional branch (register).  */
2108   {"br", 0xd61f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0},
2109   {"blr", 0xd63f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, 0},
2110   {"ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, CORE, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)},
2111   {"eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0},
2112   {"drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, CORE, OP0 (), {}, 0},
2113   /* Compare & branch (immediate).  */
2114   {"cbz", 0x34000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF},
2115   {"cbnz", 0x35000000, 0x7f000000, compbranch, 0, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF},
2116   /* Conditional branch (immediate).  */
2117   {"b.c", 0x54000000, 0xff000010, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND},
2118   /* Conditional compare (immediate).  */
2119   {"ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF},
2120   {"ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm, 0, CORE, OP4 (Rn, CCMP_IMM, NZCV, COND), QL_CCMP_IMM, F_SF},
2121   /* Conditional compare (register).  */
2122   {"ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
2123   {"ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg, 0, CORE, OP4 (Rn, Rm, NZCV, COND), QL_CCMP, F_SF},
2124   /* Conditional select.  */
2125   {"csel", 0x1a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF},
2126   {"csinc", 0x1a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
2127   {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
2128   {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
2129   {"csinv", 0x5a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
2130   {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
2131   {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
2132   {"csneg", 0x5a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
2133   {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
2134   /* Crypto AES.  */
2135   {"aese", 0x4e284800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2136   {"aesd", 0x4e285800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2137   {"aesmc", 0x4e286800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2138   {"aesimc", 0x4e287800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
2139   /* Crypto two-reg SHA.  */
2140   {"sha1h", 0x5e280800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Fd, Fn), QL_2SAMES, 0},
2141   {"sha1su1", 0x5e281800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0},
2142   {"sha256su0", 0x5e282800, 0xfffffc00, cryptosha2, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME4S, 0},
2143   /* Crypto three-reg SHA.  */
2144   {"sha1c", 0x5e000000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
2145   {"sha1p", 0x5e001000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
2146   {"sha1m", 0x5e002000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHAUPT, 0},
2147   {"sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0},
2148   {"sha256h", 0x5e004000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0},
2149   {"sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Fd, Fn, Vm), QL_SHA256UPT, 0},
2150   {"sha256su1", 0x5e006000, 0xffe0fc00, cryptosha3, 0, CRYPTO, OP3 (Vd, Vn, Vm), QL_V3SAME4S, 0},
2151   /* Data-processing (1 source).  */
2152   {"rbit", 0x5ac00000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2153   {"rev16", 0x5ac00400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2154   {"rev", 0x5ac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEW, 0},
2155   {"rev", 0xdac00c00, 0xfffffc00, dp_1src, 0, CORE,
2156    OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_HAS_ALIAS | F_P1},
2157   {"rev64", 0xdac00c00, 0xfffffc00, dp_1src, 0, ARMV8_2,
2158    OP2 (Rd, Rn), QL_I2SAMEX, F_SF | F_ALIAS},
2159   {"clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2160   {"cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAME, F_SF},
2161   {"rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, CORE, OP2 (Rd, Rn), QL_I2SAMEX, 0},
2162   /* Data-processing (2 source).  */
2163   {"udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
2164   {"sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF},
2165   {"lslv", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2166   {"lsl", 0x1ac02000, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2167   {"lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2168   {"lsr", 0x1ac02400, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2169   {"asrv", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2170   {"asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2171   {"rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
2172   {"ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
2173   /* CRC instructions.  */
2174   {"crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2175   {"crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2176   {"crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2177   {"crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
2178   {"crc32cb", 0x1ac05000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2179   {"crc32ch", 0x1ac05400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2180   {"crc32cw", 0x1ac05800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
2181   {"crc32cx", 0x9ac05c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
2182   /* Data-processing (3 source).  */
2183   {"madd", 0x1b000000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
2184   {"mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},
2185   {"msub", 0x1b008000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
2186   {"mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},
2187   {"smaddl", 0x9b200000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2188   {"smull", 0x9b207c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2189   {"smsubl", 0x9b208000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2190   {"smnegl", 0x9b20fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2191   {"smulh", 0x9b407c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0},
2192   {"umaddl", 0x9ba00000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2193   {"umull", 0x9ba07c00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2194   {"umsubl", 0x9ba08000, 0xffe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS},
2195   {"umnegl", 0x9ba0fc00, 0xffe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEL, F_ALIAS},
2196   {"umulh", 0x9bc07c00, 0xffe08000, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMEX, 0},
2197   /* Excep'n generation.  */
2198   {"svc", 0xd4000001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2199   {"hvc", 0xd4000002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2200   {"smc", 0xd4000003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2201   {"brk", 0xd4200000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2202   {"hlt", 0xd4400000, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, 0},
2203   {"dcps1", 0xd4a00001, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
2204   {"dcps2", 0xd4a00002, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
2205   {"dcps3", 0xd4a00003, 0xffe0001f, exception, 0, CORE, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)},
2206   /* Extract.  */
2207   {"extr", 0x13800000, 0x7fa00000, extract, 0, CORE, OP4 (Rd, Rn, Rm, IMMS), QL_EXTR, F_HAS_ALIAS | F_SF | F_N},
2208   {"ror", 0x13800000, 0x7fa00000, extract, OP_ROR_IMM, CORE, OP3 (Rd, Rm, IMMS), QL_SHIFT, F_ALIAS | F_CONV},
2209   /* Floating-point<->fixed-point conversions.  */
2210   {"scvtf", 0x1e020000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
2211   {"scvtf", 0x1ec20000, 0x7f3f0000, float2fix, 0, FP_F16,
2212    OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF},
2213   {"ucvtf", 0x1e030000, 0x7f3f0000, float2fix, 0, FP, OP3 (Fd, Rn, FBITS), QL_FIX2FP, F_FPTYPE | F_SF},
2214   {"ucvtf", 0x1ec30000, 0x7f3f0000, float2fix, 0, FP_F16,
2215    OP3 (Fd, Rn, FBITS), QL_FIX2FP_H, F_FPTYPE | F_SF},
2216   {"fcvtzs", 0x1e180000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
2217   {"fcvtzs", 0x1ed80000, 0x7f3f0000, float2fix, 0, FP_F16,
2218    OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF},
2219   {"fcvtzu", 0x1e190000, 0x7f3f0000, float2fix, 0, FP, OP3 (Rd, Fn, FBITS), QL_FP2FIX, F_FPTYPE | F_SF},
2220   {"fcvtzu", 0x1ed90000, 0x7f3f0000, float2fix, 0, FP_F16,
2221    OP3 (Rd, Fn, FBITS), QL_FP2FIX_H, F_FPTYPE | F_SF},
2222   /* Floating-point<->integer conversions.  */
2223   {"fcvtns", 0x1e200000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2224   {"fcvtns", 0x1ee00000, 0x7f3ffc00, float2int, 0, FP_F16,
2225    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2226   {"fcvtnu", 0x1e210000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2227   {"fcvtnu", 0x1ee10000, 0x7f3ffc00, float2int, 0, FP_F16,
2228    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2229   {"scvtf", 0x1e220000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
2230   {"scvtf", 0x1ee20000, 0x7f3ffc00, float2int, 0, FP_F16,
2231    OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
2232   {"ucvtf", 0x1e230000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
2233   {"ucvtf", 0x1ee30000, 0x7f3ffc00, float2int, 0, FP_F16,
2234    OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
2235   {"fcvtas", 0x1e240000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2236   {"fcvtas", 0x1ee40000, 0x7f3ffc00, float2int, 0, FP_F16,
2237    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2238   {"fcvtau", 0x1e250000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2239   {"fcvtau", 0x1ee50000, 0x7f3ffc00, float2int, 0, FP_F16,
2240    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2241   {"fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2242   {"fmov", 0x1ee60000, 0x7f3ffc00, float2int, 0, FP_F16,
2243    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2244   {"fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, FP, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF},
2245   {"fmov", 0x1ee70000, 0x7f3ffc00, float2int, 0, FP_F16,
2246    OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF},
2247   {"fcvtps", 0x1e280000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2248   {"fcvtps", 0x1ee80000, 0x7f3ffc00, float2int, 0, FP_F16,
2249    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2250   {"fcvtpu", 0x1e290000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2251   {"fcvtpu", 0x1ee90000, 0x7f3ffc00, float2int, 0, FP_F16,
2252    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2253   {"fcvtms", 0x1e300000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2254   {"fcvtms", 0x1ef00000, 0x7f3ffc00, float2int, 0, FP_F16,
2255    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2256   {"fcvtmu", 0x1e310000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2257   {"fcvtmu", 0x1ef10000, 0x7f3ffc00, float2int, 0, FP_F16,
2258    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2259   {"fcvtzs", 0x1e380000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2260   {"fcvtzs", 0x1ef80000, 0x7f3ffc00, float2int, 0, FP_F16,
2261    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2262   {"fcvtzu", 0x1e390000, 0x7f3ffc00, float2int, 0, FP, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF},
2263   {"fcvtzu", 0x1ef90000, 0x7f3ffc00, float2int, 0, FP_F16,
2264    OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF},
2265   {"fmov", 0x9eae0000, 0xfffffc00, float2int, 0, FP, OP2 (Rd, VnD1), QL_XVD1, 0},
2266   {"fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, FP, OP2 (VdD1, Rn), QL_VD1X, 0},
2267   /* Floating-point conditional compare.  */
2268   {"fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
2269   {"fccmp", 0x1ee00400, 0xff200c10, floatccmp, 0, FP_F16,
2270    OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE},
2271   {"fccmpe", 0x1e200410, 0xff200c10, floatccmp, 0, FP, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE},
2272   {"fccmpe", 0x1ee00410, 0xff200c10, floatccmp, 0, FP_F16,
2273    OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE},
2274   /* Floating-point compare.  */
2275   {"fcmp", 0x1e202000, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
2276   {"fcmp", 0x1ee02000, 0xff20fc1f, floatcmp, 0, FP_F16,
2277    OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE},
2278   {"fcmpe", 0x1e202010, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, Fm), QL_FP2, F_FPTYPE},
2279   {"fcmpe", 0x1ee02010, 0xff20fc1f, floatcmp, 0, FP_F16,
2280    OP2 (Fn, Fm), QL_FP2_H, F_FPTYPE},
2281   {"fcmp", 0x1e202008, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
2282   {"fcmp", 0x1ee02008, 0xff20fc1f, floatcmp, 0, FP_F16,
2283    OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE},
2284   {"fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, FP, OP2 (Fn, FPIMM0), QL_DST_SD, F_FPTYPE},
2285   {"fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp, 0, FP_F16,
2286    OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE},
2287   /* Floating-point data-processing (1 source).  */
2288   {"fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2289   {"fmov", 0x1ee04000, 0xff3ffc00, floatdp1, 0, FP_F16,
2290    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2291   {"fabs", 0x1e20c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2292   {"fabs", 0x1ee0c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2293    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2294   {"fneg", 0x1e214000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2295   {"fneg", 0x1ee14000, 0xff3ffc00, floatdp1, 0, FP_F16,
2296    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2297   {"fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2298   {"fsqrt", 0x1ee1c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2299    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2300   {"fcvt", 0x1e224000, 0xff3e7c00, floatdp1, OP_FCVT, FP, OP2 (Fd, Fn), QL_FCVT, F_FPTYPE | F_MISC},
2301   {"frintn", 0x1e244000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2302   {"frintn", 0x1ee44000, 0xff3ffc00, floatdp1, 0, FP_F16,
2303    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2304   {"frintp", 0x1e24c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2305   {"frintp", 0x1ee4c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2306    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2307   {"frintm", 0x1e254000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2308   {"frintm", 0x1ee54000, 0xff3ffc00, floatdp1, 0, FP_F16,
2309    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2310   {"frintz", 0x1e25c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2311   {"frintz", 0x1ee5c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2312    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2313   {"frinta", 0x1e264000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2314   {"frinta", 0x1ee64000, 0xff3ffc00, floatdp1, 0, FP_F16,
2315    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2316   {"frintx", 0x1e274000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2317   {"frintx", 0x1ee74000, 0xff3ffc00, floatdp1, 0, FP_F16,
2318    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2319   {"frinti", 0x1e27c000, 0xff3ffc00, floatdp1, 0, FP, OP2 (Fd, Fn), QL_FP2, F_FPTYPE},
2320   {"frinti", 0x1ee7c000, 0xff3ffc00, floatdp1, 0, FP_F16,
2321    OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE},
2322   /* Floating-point data-processing (2 source).  */
2323   {"fmul", 0x1e200800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
2324   {"fmul", 0x1ee00800, 0xff20fc00, floatdp2, 0, FP_F16,
2325    OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
2326   {"fdiv", 0x1e201800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
2327   {"fdiv", 0x1ee01800, 0xff20fc00, floatdp2, 0, FP_F16,
2328    OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
2329   {"fadd", 0x1e202800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
2330   {"fadd", 0x1ee02800, 0xff20fc00, floatdp2, 0, FP_F16,
2331    OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
2332   {"fsub", 0x1e203800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
2333   {"fsub", 0x1ee03800, 0xff20fc00, floatdp2, 0, FP_F16,
2334    OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
2335   {"fmax", 0x1e204800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
2336   {"fmax", 0x1ee04800, 0xff20fc00, floatdp2, 0, FP_F16,
2337    OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
2338   {"fmin", 0x1e205800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
2339   {"fmin", 0x1ee05800, 0xff20fc00, floatdp2, 0, FP_F16,
2340    OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
2341   {"fmaxnm", 0x1e206800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
2342   {"fmaxnm", 0x1ee06800, 0xff20fc00, floatdp2, 0, FP_F16,
2343    OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
2344   {"fminnm", 0x1e207800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
2345   {"fminnm", 0x1ee07800, 0xff20fc00, floatdp2, 0, FP_F16,
2346    OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
2347   {"fnmul", 0x1e208800, 0xff20fc00, floatdp2, 0, FP, OP3 (Fd, Fn, Fm), QL_FP3, F_FPTYPE},
2348   {"fnmul", 0x1ee08800, 0xff20fc00, floatdp2, 0, FP_F16,
2349    OP3 (Fd, Fn, Fm), QL_FP3_H, F_FPTYPE},
2350   /* Floating-point data-processing (3 source).  */
2351   {"fmadd", 0x1f000000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
2352   {"fmadd", 0x1fc00000, 0xff208000, floatdp3, 0, FP_F16,
2353    OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
2354   {"fmsub", 0x1f008000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
2355   {"fmsub", 0x1fc08000, 0xff208000, floatdp3, 0, FP_F16,
2356    OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
2357   {"fnmadd", 0x1f200000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
2358   {"fnmadd", 0x1fe00000, 0xff208000, floatdp3, 0, FP_F16,
2359    OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
2360   {"fnmsub", 0x1f208000, 0xff208000, floatdp3, 0, FP, OP4 (Fd, Fn, Fm, Fa), QL_FP4, F_FPTYPE},
2361   {"fnmsub", 0x1fe08000, 0xff208000, floatdp3, 0, FP_F16,
2362    OP4 (Fd, Fn, Fm, Fa), QL_FP4_H, F_FPTYPE},
2363   /* Floating-point immediate.  */
2364   {"fmov", 0x1e201000, 0xff201fe0, floatimm, 0, FP, OP2 (Fd, FPIMM), QL_DST_SD, F_FPTYPE},
2365   {"fmov", 0x1ee01000, 0xff201fe0, floatimm, 0, FP_F16,
2366    OP2 (Fd, FPIMM), QL_DST_H, F_FPTYPE},
2367   /* Floating-point conditional select.  */
2368   {"fcsel", 0x1e200c00, 0xff200c00, floatsel, 0, FP, OP4 (Fd, Fn, Fm, COND), QL_FP_COND, F_FPTYPE},
2369   {"fcsel", 0x1ee00c00, 0xff200c00, floatsel, 0, FP_F16,
2370    OP4 (Fd, Fn, Fm, COND), QL_FP_COND_H, F_FPTYPE},
2371   /* Load/store register (immediate indexed).  */
2372   {"strb", 0x38000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2373   {"ldrb", 0x38400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2374   {"ldrsb", 0x38800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
2375   {"str", 0x3c000400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2376   {"ldr", 0x3c400400, 0x3f600400, ldst_imm9, 0, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2377   {"strh", 0x78000400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2378   {"ldrh", 0x78400400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2379   {"ldrsh", 0x78800400, 0xffa00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
2380   {"str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2381   {"ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2382   {"ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
2383   /* Load/store register (unsigned immediate).  */
2384   {"strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0},
2385   {"ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0},
2386   {"ldrsb", 0x39800000, 0xff800000, ldst_pos, OP_LDRSB_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R8, F_LDS_SIZE},
2387   {"str", 0x3d000000, 0x3f400000, ldst_pos, OP_STRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0},
2388   {"ldr", 0x3d400000, 0x3f400000, ldst_pos, OP_LDRF_POS, CORE, OP2 (Ft, ADDR_UIMM12), QL_LDST_FP, 0},
2389   {"strh", 0x79000000, 0xffc00000, ldst_pos, OP_STRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0},
2390   {"ldrh", 0x79400000, 0xffc00000, ldst_pos, OP_LDRH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_W16, 0},
2391   {"ldrsh", 0x79800000, 0xff800000, ldst_pos, OP_LDRSH_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R16, F_LDS_SIZE},
2392   {"str", 0xb9000000, 0xbfc00000, ldst_pos, OP_STR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q},
2393   {"ldr", 0xb9400000, 0xbfc00000, ldst_pos, OP_LDR_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_R, F_GPRSIZE_IN_Q},
2394   {"ldrsw", 0xb9800000, 0xffc00000, ldst_pos, OP_LDRSW_POS, CORE, OP2 (Rt, ADDR_UIMM12), QL_LDST_X32, 0},
2395   {"prfm", 0xf9800000, 0xffc00000, ldst_pos, OP_PRFM_POS, CORE, OP2 (PRFOP, ADDR_UIMM12), QL_LDST_PRFM, 0},
2396   /* Load/store register (register offset).  */
2397   {"strb", 0x38200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0},
2398   {"ldrb", 0x38600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W8, 0},
2399   {"ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R8, F_LDS_SIZE},
2400   {"str", 0x3c200800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0},
2401   {"ldr", 0x3c600800, 0x3f600c00, ldst_regoff, 0, CORE, OP2 (Ft, ADDR_REGOFF), QL_LDST_FP, 0},
2402   {"strh", 0x78200800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0},
2403   {"ldrh", 0x78600800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_W16, 0},
2404   {"ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R16, F_LDS_SIZE},
2405   {"str", 0xb8200800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q},
2406   {"ldr", 0xb8600800, 0xbfe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_R, F_GPRSIZE_IN_Q},
2407   {"ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (Rt, ADDR_REGOFF), QL_LDST_X32, 0},
2408   {"prfm", 0xf8a00800, 0xffe00c00, ldst_regoff, 0, CORE, OP2 (PRFOP, ADDR_REGOFF), QL_LDST_PRFM, 0},
2409   /* Load/store register (unprivileged).  */
2410   {"sttrb", 0x38000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2411   {"ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2412   {"ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
2413   {"sttrh", 0x78000800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2414   {"ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2415   {"ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
2416   {"sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2417   {"ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2418   {"ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv, 0, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
2419   /* Load/store register (unscaled immediate).  */
2420   {"sturb", 0x38000000, 0xffe00c00, ldst_unscaled, OP_STURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2421   {"ldurb", 0x38400000, 0xffe00c00, ldst_unscaled, OP_LDURB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W8, 0},
2422   {"ldursb", 0x38800000, 0xffa00c00, ldst_unscaled, OP_LDURSB, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R8, F_LDS_SIZE},
2423   {"stur", 0x3c000000, 0x3f600c00, ldst_unscaled, OP_STURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2424   {"ldur", 0x3c400000, 0x3f600c00, ldst_unscaled, OP_LDURV, CORE, OP2 (Ft, ADDR_SIMM9), QL_LDST_FP, 0},
2425   {"sturh", 0x78000000, 0xffe00c00, ldst_unscaled, OP_STURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2426   {"ldurh", 0x78400000, 0xffe00c00, ldst_unscaled, OP_LDURH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_W16, 0},
2427   {"ldursh", 0x78800000, 0xffa00c00, ldst_unscaled, OP_LDURSH, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R16, F_LDS_SIZE},
2428   {"stur", 0xb8000000, 0xbfe00c00, ldst_unscaled, OP_STUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2429   {"ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q},
2430   {"ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, CORE, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0},
2431   {"prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, CORE, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0},
2432   /* Load/store exclusive.  */
2433   {"stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2434   {"stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2435   {"ldxrb", 0x85f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2436   {"ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2437   {"stlrb", 0x89ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2438   {"ldarb", 0x8dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2439   {"stxrh", 0x48007c00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2440   {"stlxrh", 0x4800fc00, 0xffe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2441   {"ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2442   {"ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2443   {"stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2444   {"ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2445   {"stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
2446   {"stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q},
2447   {"stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q},
2448   {"stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, CORE, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q},
2449   {"ldxr", 0x885f7c00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2450   {"ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2451   {"ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
2452   {"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q},
2453   {"stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2454   {"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, CORE, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2455   /* Limited Ordering Regions load/store instructions.  */
2456   {"ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2457   {"ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2458   {"ldlarh", 0x48df7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2459   {"stllr", 0x889f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q},
2460   {"stllrb", 0x089f7c00, 0xffe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2461   {"stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, 0, LOR, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0},
2462   /* Load/store no-allocate pair (offset).  */
2463   {"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2464   {"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2465   {"stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2466   {"ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2467   /* Load/store register pair (offset).  */
2468   {"stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2469   {"ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2470   {"stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2471   {"ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2472   {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0},
2473   /* Load/store register pair (indexed).  */
2474   {"stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2475   {"ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF},
2476   {"stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2477   {"ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, CORE, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0},
2478   {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0},
2479   /* Load register (literal).  */
2480   {"ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q},
2481   {"ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, CORE, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0},
2482   {"ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, CORE, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0},
2483   {"prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, CORE, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0},
2484   /* Logical (immediate).  */
2485   {"and", 0x12000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
2486   {"bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF},
2487   {"orr", 0x32000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
2488   {"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV},
2489   {"eor", 0x52000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF},
2490   {"ands", 0x72000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF},
2491   {"tst", 0x7200001f, 0x7f80001f, log_imm, 0, CORE, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF},
2492   /* Logical (shifted register).  */
2493   {"and", 0xa000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2494   {"bic", 0xa200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2495   {"orr", 0x2a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
2496   {"mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm), QL_I2SAMER, F_ALIAS | F_SF},
2497   {"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, CORE, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO},
2498   {"orn", 0x2a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
2499   {"mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, CORE, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
2500   {"eor", 0x4a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2501   {"eon", 0x4a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2502   {"ands", 0x6a000000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF},
2503   {"tst", 0x6a00001f, 0x7f20001f, log_shift, 0, CORE, OP2 (Rn, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF},
2504   {"bics", 0x6a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF},
2505   /* LSE extension (atomic).  */
2506   {"casb", 0x8a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2507   {"cash", 0x48a07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2508   {"cas", 0x88a07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2509   {"casab", 0x8e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2510   {"caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2511   {"casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2512   {"casah", 0x48e07c00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2513   {"caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2514   {"casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2515   {"casa", 0x88e07c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2516   {"casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2517   {"casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2518   {"casp", 0x8207c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2519   {"caspa", 0x8607c00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2520   {"caspl", 0x820fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2521   {"caspal", 0x860fc00, 0xbfe0fc00, lse_atomic, 0, LSE, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_R4NIL, F_LSE_SZ},
2522   {"swpb", 0x38208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2523   {"swph", 0x78208000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2524   {"swp", 0xb8208000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2525   {"swpab", 0x38a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2526   {"swplb", 0x38608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2527   {"swpalb", 0x38e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2528   {"swpah", 0x78a08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2529   {"swplh", 0x78608000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2530   {"swpalh", 0x78e08000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2531   {"swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2532   {"swpl", 0xb8608000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2533   {"swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2534   {"ldaddb", 0x38200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2535   {"ldaddh", 0x78200000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2536   {"ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2537   {"ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2538   {"ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2539   {"ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2540   {"ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2541   {"ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2542   {"ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2543   {"ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2544   {"ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2545   {"ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2546   {"ldclrb", 0x38201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2547   {"ldclrh", 0x78201000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2548   {"ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2549   {"ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2550   {"ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2551   {"ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2552   {"ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2553   {"ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2554   {"ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2555   {"ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2556   {"ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2557   {"ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2558   {"ldeorb", 0x38202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2559   {"ldeorh", 0x78202000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2560   {"ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2561   {"ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2562   {"ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2563   {"ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2564   {"ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2565   {"ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2566   {"ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2567   {"ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2568   {"ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2569   {"ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2570   {"ldsetb", 0x38203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2571   {"ldseth", 0x78203000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2572   {"ldset", 0xb8203000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2573   {"ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2574   {"ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2575   {"ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2576   {"ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2577   {"ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2578   {"ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2579   {"ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2580   {"ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2581   {"ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2582   {"ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2583   {"ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2584   {"ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2585   {"ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2586   {"ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2587   {"ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2588   {"ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2589   {"ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2590   {"ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2591   {"ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2592   {"ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2593   {"ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2594   {"ldsminb", 0x38205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2595   {"ldsminh", 0x78205000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2596   {"ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2597   {"ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2598   {"ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2599   {"ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2600   {"ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2601   {"ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2602   {"ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2603   {"ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2604   {"ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2605   {"ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2606   {"ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2607   {"ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2608   {"ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2609   {"ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2610   {"ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2611   {"ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2612   {"ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2613   {"ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2614   {"ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2615   {"ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2616   {"ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2617   {"ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2618   {"lduminb", 0x38207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2619   {"lduminh", 0x78207000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2620   {"ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2621   {"lduminab", 0x38a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2622   {"lduminlb", 0x38607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2623   {"lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2624   {"lduminah", 0x78a07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2625   {"lduminlh", 0x78607000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, F_HAS_ALIAS},
2626   {"lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0},
2627   {"ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2628   {"lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ | F_HAS_ALIAS},
2629   {"lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic, 0, LSE, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2NIL, F_LSE_SZ},
2630   {"staddb", 0x3820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2631   {"staddh", 0x7820001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2632   {"stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2633   {"staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2634   {"staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2635   {"staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2636   {"stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2637   {"stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2638   {"stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2639   {"stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2640   {"stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2641   {"stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2642   {"steorb", 0x3820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2643   {"steorh", 0x7820201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2644   {"steor", 0xb820201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2645   {"steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2646   {"steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2647   {"steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2648   {"stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2649   {"stseth", 0x7820301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2650   {"stset", 0xb820301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2651   {"stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2652   {"stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2653   {"stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2654   {"stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2655   {"stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2656   {"stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2657   {"stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2658   {"stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2659   {"stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2660   {"stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2661   {"stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2662   {"stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2663   {"stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2664   {"stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2665   {"stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2666   {"stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2667   {"stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2668   {"stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2669   {"stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2670   {"stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2671   {"stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2672   {"stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2673   {"stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2674   {"stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2675   {"stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2676   {"stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_W1_LDST_EXC, F_ALIAS},
2677   {"stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic, 0, LSE, OP2 (Rs, ADDR_SIMPLE), QL_R1NIL, F_LSE_SZ | F_ALIAS},
2678   /* Move wide (immediate).  */
2679   {"movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
2680   {"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV},
2681   {"movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS},
2682   {"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV},
2683   {"movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF},
2684   /* PC-rel. addressing.  */
2685   {"adr", 0x10000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0},
2686   {"adrp", 0x90000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0},
2687   /* System.  */
2688   {"msr", 0xd500401f, 0xfff8f01f, ic_system, 0, CORE, OP2 (PSTATEFIELD, UIMM4), {}, 0},
2689   {"hint", 0xd503201f, 0xfffff01f, ic_system, 0, CORE, OP1 (UIMM7), {}, F_HAS_ALIAS},
2690   {"nop", 0xd503201f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2691   {"yield", 0xd503203f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2692   {"wfe", 0xd503205f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2693   {"wfi", 0xd503207f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2694   {"sev", 0xd503209f, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2695   {"sevl", 0xd50320bf, 0xffffffff, ic_system, 0, CORE, OP0 (), {}, F_ALIAS},
2696   {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS},
2697   {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE,
2698    OP1 (BARRIER_PSB), {}, F_ALIAS },
2699   {"clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, CORE, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
2700   {"dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
2701   {"dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER), {}, 0},
2702   {"isb", 0xd50330df, 0xfffff0ff, ic_system, 0, CORE, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)},
2703   {"sys", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP5 (UIMM3_OP1, Cn, Cm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)},
2704   {"at", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS},
2705   {"dc", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS},
2706   {"ic", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
2707   {"tlbi", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
2708   {"msr", 0xd5000000, 0xffe00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0},
2709   {"sysl", 0xd5280000, 0xfff80000, ic_system, 0, CORE, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0},
2710   {"mrs", 0xd5200000, 0xffe00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0},
2711   /* Test & branch (immediate).  */
2712   {"tbz", 0x36000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
2713   {"tbnz", 0x37000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
2714   /* The old UAL conditional branch mnemonics (to aid portability).  */
2715   {"beq", 0x54000000, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2716   {"bne", 0x54000001, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2717   {"bcs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2718   {"bhs", 0x54000002, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2719   {"bcc", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2720   {"blo", 0x54000003, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2721   {"bmi", 0x54000004, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2722   {"bpl", 0x54000005, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2723   {"bvs", 0x54000006, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2724   {"bvc", 0x54000007, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2725   {"bhi", 0x54000008, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2726   {"bls", 0x54000009, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2727   {"bge", 0x5400000a, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2728   {"blt", 0x5400000b, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2729   {"bgt", 0x5400000c, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2730   {"ble", 0x5400000d, 0xff00001f, condbranch, 0, CORE, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO},
2731
2732   {0, 0, 0, 0, 0, 0, {}, {}, 0},
2733 };
2734
2735 #ifdef AARCH64_OPERANDS
2736 #undef AARCH64_OPERANDS
2737 #endif
2738
2739 /* Macro-based operand decription; this will be fed into aarch64-gen for it
2740    to generate the structure aarch64_operands and the function
2741    aarch64_insert_operand and aarch64_extract_operand.
2742
2743    These inserters and extracters in the description execute the conversion
2744    between the aarch64_opnd_info and value in the operand-related instruction
2745    field(s).  */
2746
2747 /* Y expects arguments (left to right) to be operand class, inserter/extractor
2748    name suffix, operand name, flags, related bitfield(s) and description.
2749    X only differs from Y by having the operand inserter and extractor names
2750    listed separately.  */
2751
2752 #define AARCH64_OPERANDS                                                \
2753     Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register")        \
2754     Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register")        \
2755     Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register")        \
2756     Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register")        \
2757     Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register")      \
2758     Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register")        \
2759     Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register")        \
2760     X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt),     \
2761       "an integer register")                                            \
2762     Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd),               \
2763       "an integer or stack pointer register")                           \
2764     Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn),               \
2765       "an integer or stack pointer register")                           \
2766     X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(),                    \
2767       "the second reg of a pair")                                       \
2768     Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(),                     \
2769       "an integer register with optional extension")                    \
2770     Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(),                      \
2771       "an integer register with optional shift")                        \
2772     Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register")   \
2773     Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register")   \
2774     Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register")   \
2775     Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register")   \
2776     Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register")      \
2777     Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \
2778     Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register")    \
2779     Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register")    \
2780     Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register")    \
2781     Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register")    \
2782     Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register")    \
2783     Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register")    \
2784     Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd),                              \
2785       "the top half of a 128-bit FP/SIMD register")                     \
2786     Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn),                              \
2787       "the top half of a 128-bit FP/SIMD register")                     \
2788     Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd),                        \
2789       "a SIMD vector element")                                          \
2790     Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn),                        \
2791       "a SIMD vector element")                                          \
2792     Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm),                        \
2793       "a SIMD vector element")                                          \
2794     Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn),                       \
2795       "a SIMD vector register list")                                    \
2796     Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(),                        \
2797       "a SIMD vector register list")                                    \
2798     Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(),                   \
2799       "a SIMD vector register list")                                    \
2800     Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(),                       \
2801       "a SIMD vector element list")                                     \
2802     Y(CP_REG, regno, "Cn", 0, F(FLD_CRn),                               \
2803       "a 4-bit opcode field named for historical reasons C0 - C15")     \
2804     Y(CP_REG, regno, "Cm", 0, F(FLD_CRm),                               \
2805       "a 4-bit opcode field named for historical reasons C0 - C15")     \
2806     Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4),                            \
2807       "an immediate as the index of the least significant byte")        \
2808     Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(),                 \
2809       "a left shift amount for an AdvSIMD register")                    \
2810     Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(),                 \
2811       "a right shift amount for an AdvSIMD register")                   \
2812     Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(),              \
2813       "an immediate")                                                   \
2814     Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(),          \
2815       "an 8-bit unsigned immediate with optional shift")                \
2816     Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(),            \
2817       "an 8-bit floating-point constant")                               \
2818     X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(),                   \
2819       "an immediate shift amount of 8, 16 or 32")                       \
2820     X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0")                             \
2821     X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0")                         \
2822     Y(IMMEDIATE, imm, "FPIMM", 0, F(FLD_imm8),                          \
2823       "an 8-bit floating-point constant")                               \
2824     Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr),                           \
2825       "the right rotate amount")                                        \
2826     Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6),                           \
2827       "the leftmost bit number to be moved from the source")            \
2828     Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6),                          \
2829       "the width of the bit-field")                                     \
2830     Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate")            \
2831     Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1),                       \
2832       "a 3-bit unsigned immediate")                                     \
2833     Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2),                       \
2834       "a 3-bit unsigned immediate")                                     \
2835     Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm),                           \
2836       "a 4-bit unsigned immediate")                                     \
2837     Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2),                  \
2838       "a 7-bit unsigned immediate")                                     \
2839     Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40),                 \
2840       "the bit number to be tested")                                    \
2841     Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16),                     \
2842       "a 16-bit unsigned immediate")                                    \
2843     Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5),                       \
2844       "a 5-bit unsigned immediate")                                     \
2845     Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv),                           \
2846       "a flag bit specifier giving an alternative value for each flag") \
2847     Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms),           \
2848       "Logical immediate")                                              \
2849     Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12),               \
2850       "a 12-bit unsigned immediate with optional left shift of 12 bits")\
2851     Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16),                     \
2852       "a 16-bit immediate with optional left shift")                    \
2853     Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale),                       \
2854       "the number of bits after the binary point in the fixed-point value")\
2855     X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate")               \
2856     Y(COND, cond, "COND", 0, F(), "a condition")                        \
2857     Y(COND, cond, "COND1", 0, F(),                                      \
2858       "one of the standard conditions, excluding AL and NV.")           \
2859     X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\
2860       "21-bit PC-relative address of a 4KB page")                       \
2861     Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2,      \
2862       F(FLD_imm14), "14-bit PC-relative address")                       \
2863     Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2,      \
2864       F(FLD_imm19), "19-bit PC-relative address")                       \
2865     Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \
2866       "21-bit PC-relative address")                                     \
2867     Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2,      \
2868       F(FLD_imm26), "26-bit PC-relative address")                       \
2869     Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(),                      \
2870       "an address with base register (no offset)")                      \
2871     Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(),                      \
2872       "an address with register offset")                                \
2873     Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2),      \
2874       "an address with 7-bit signed immediate offset")                  \
2875     Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index),       \
2876       "an address with 9-bit signed immediate offset")                  \
2877     Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index),     \
2878       "an address with 9-bit negative or unaligned immediate offset")   \
2879     Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12),      \
2880       "an address with scaled, unsigned immediate offset")              \
2881     Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(),                 \
2882       "an address with base register (no offset)")                      \
2883     Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(),                \
2884       "a post-indexed address with immediate or register increment")    \
2885     Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register")            \
2886     Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(),                       \
2887       "a PSTATE field name")                                            \
2888     Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(),                           \
2889       "an address translation operation specifier")                     \
2890     Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(),                           \
2891       "a data cache maintenance operation specifier")                   \
2892     Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(),                           \
2893       "an instruction cache maintenance operation specifier")           \
2894     Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(),                         \
2895       "a TBL invalidation operation specifier")                         \
2896     Y(SYSTEM, barrier, "BARRIER", 0, F(),                               \
2897       "a barrier option name")                                          \
2898     Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(),                           \
2899       "the ISB option name SY or an optional 4-bit unsigned immediate") \
2900     Y(SYSTEM, prfop, "PRFOP", 0, F(),                                   \
2901       "a prefetch operation specifier")                                 \
2902     Y (SYSTEM, hint, "BARRIER_PSB", 0, F (),                            \
2903       "the PSB option name CSYNC")