1 /* aarch64-tbl.h -- AArch64 opcode description table and instruction
2 operand description table.
3 Copyright (C) 2012-2015 Free Software Foundation, Inc.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
22 #include "aarch64-opc.h"
26 #define OPND(x) AARCH64_OPND_##x
28 #define OP1(a) {OPND(a)}
29 #define OP2(a,b) {OPND(a), OPND(b)}
30 #define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
31 #define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)}
32 #define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)}
34 #define QLF(x) AARCH64_OPND_QLF_##x
35 #define QLF1(a) {QLF(a)}
36 #define QLF2(a,b) {QLF(a), QLF(b)}
37 #define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)}
38 #define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)}
39 #define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)}
41 /* Qualifiers list. */
43 /* e.g. MSR <systemreg>, <Xt>. */
49 /* e.g. MRS <Xt>, <systemreg>. */
55 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
58 QLF5(NIL,NIL,NIL,NIL,X), \
61 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
64 QLF5(X,NIL,NIL,NIL,NIL), \
67 /* e.g. ADRP <Xd>, <label>. */
73 /* e.g. B.<cond> <label>. */
74 #define QL_PCREL_NIL \
79 /* e.g. TBZ <Xt>, #<imm>, <label>. */
82 QLF3(X,imm_0_63,NIL), \
85 /* e.g. BL <label>. */
91 /* e.g. LDRSW <Xt>, <label>. */
97 /* e.g. LDR <Wt>, <label>. */
104 /* e.g. LDR <Dt>, <label>. */
105 #define QL_FP_PCREL \
112 /* e.g. PRFM <prfop>, <label>. */
113 #define QL_PRFM_PCREL \
124 /* e.g. RBIT <Wd>, <Wn>. */
131 /* e.g. CMN <Wn|WSP>, <Wm>{, <extend> {#<amount>}}. */
139 /* e.g. MOV <Wd|WSP>, <Wn|WSP>, at least one SP. */
148 /* e.g. REV <Wd>, <Wn>. */
154 /* e.g. REV32 <Xd>, <Xn>. */
166 /* e.g. CRC32B <Wd>, <Wn>, <Wm>. */
172 /* e.g. SMULH <Xd>, <Xn>, <Xm>. */
178 /* e.g. CRC32X <Wd>, <Wn>, <Xm>. */
184 /* e.g. UDIV <Xd>, <Xn>, <Xm>. */
191 /* e.g. ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}. */
199 /* e.g. MADD <Xd>, <Xn>, <Xm>, <Xa>. */
206 /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */
212 /* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */
218 /* e.g. CSINC <Xd>, <Xn>, <Xm>, <cond>. */
221 QLF4(W, W, W, NIL), \
222 QLF4(X, X, X, NIL), \
225 /* e.g. CSET <Wd>, <cond>. */
232 /* e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>. */
235 QLF4(W,W,imm_0_31,imm_0_31), \
236 QLF4(X,X,imm_0_63,imm_0_63), \
239 /* e.g. BFC <Wd>, #<immr>, #<imms>. */
242 QLF3 (W, imm_0_31, imm_1_32), \
243 QLF3 (X, imm_0_63, imm_1_64), \
246 /* e.g. UBFIZ <Wd>, <Wn>, #<lsb>, #<width>. */
249 QLF4(W,W,imm_0_31,imm_1_32), \
250 QLF4(X,X,imm_0_63,imm_1_64), \
253 /* e.g. SCVTF <Sd>, <Xn>, #<fbits>. */
256 QLF3(S_D,W,imm_1_32), \
257 QLF3(S_S,W,imm_1_32), \
258 QLF3(S_D,X,imm_1_64), \
259 QLF3(S_S,X,imm_1_64), \
262 /* e.g. SCVTF <Hd>, <Xn>, #<fbits>. */
263 #define QL_FIX2FP_H \
265 QLF3 (S_H, W, imm_1_32), \
266 QLF3 (S_H, X, imm_1_64), \
269 /* e.g. FCVTZS <Wd>, <Dn>, #<fbits>. */
272 QLF3(W,S_D,imm_1_32), \
273 QLF3(W,S_S,imm_1_32), \
274 QLF3(X,S_D,imm_1_64), \
275 QLF3(X,S_S,imm_1_64), \
278 /* e.g. FCVTZS <Wd>, <Hn>, #<fbits>. */
279 #define QL_FP2FIX_H \
281 QLF3 (W, S_H, imm_1_32), \
282 QLF3 (X, S_H, imm_1_64), \
285 /* e.g. SCVTF <Dd>, <Wn>. */
294 /* e.g. SCVTF <Hd>, <Wn>. */
295 #define QL_INT2FP_H \
301 /* e.g. FCVTNS <Xd>, <Dn>. */
310 /* e.g. FCVTNS <Hd>, <Wn>. */
311 #define QL_FP2INT_H \
317 /* e.g. FMOV <Xd>, <Vn>.D[1]. */
323 /* e.g. FMOV <Vd>.D[1], <Xn>. */
329 /* e.g. EXTR <Xd>, <Xn>, <Xm>, #<lsb>. */
332 QLF4(W,W,W,imm_0_31), \
333 QLF4(X,X,X,imm_0_63), \
336 /* e.g. LSL <Wd>, <Wn>, #<uimm>. */
339 QLF3(W,W,imm_0_31), \
340 QLF3(X,X,imm_0_63), \
343 /* e.g. UXTH <Xd>, <Wn>. */
350 /* e.g. UXTW <Xd>, <Wn>. */
356 /* e.g. SQSHL <V><d>, <V><n>, #<shift>. */
359 QLF3(S_B , S_B , S_B ), \
360 QLF3(S_H , S_H , S_H ), \
361 QLF3(S_S , S_S , S_S ), \
362 QLF3(S_D , S_D , S_D ) \
365 /* e.g. SSHR <V><d>, <V><n>, #<shift>. */
366 #define QL_SSHIFT_D \
368 QLF3(S_D , S_D , S_D ) \
371 /* e.g. UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
372 #define QL_SSHIFT_SD \
374 QLF3(S_S , S_S , S_S ), \
375 QLF3(S_D , S_D , S_D ) \
378 /* e.g. SQSHRUN <Vb><d>, <Va><n>, #<shift>. */
381 QLF3(S_B , S_H , S_B ), \
382 QLF3(S_H , S_S , S_H ), \
383 QLF3(S_S , S_D , S_S ), \
386 /* e.g. SSHR <Vd>.<T>, <Vn>.<T>, #<shift>.
387 The register operand variant qualifiers are deliberately used for the
388 immediate operand to ease the operand encoding/decoding and qualifier
389 sequence matching. */
392 QLF3(V_8B , V_8B , V_8B ), \
393 QLF3(V_16B, V_16B, V_16B), \
394 QLF3(V_4H , V_4H , V_4H ), \
395 QLF3(V_8H , V_8H , V_8H ), \
396 QLF3(V_2S , V_2S , V_2S ), \
397 QLF3(V_4S , V_4S , V_4S ), \
398 QLF3(V_2D , V_2D , V_2D ) \
401 /* e.g. SCVTF <Vd>.<T>, <Vn>.<T>, #<fbits>. */
402 #define QL_VSHIFT_SD \
404 QLF3(V_2S , V_2S , V_2S ), \
405 QLF3(V_4S , V_4S , V_4S ), \
406 QLF3(V_2D , V_2D , V_2D ) \
409 /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */
412 QLF3(V_8B , V_8H , V_8B ), \
413 QLF3(V_4H , V_4S , V_4H ), \
414 QLF3(V_2S , V_2D , V_2S ), \
417 /* e.g. SHRN<Q> <Vd>.<Tb>, <Vn>.<Ta>, #<shift>. */
418 #define QL_VSHIFTN2 \
420 QLF3(V_16B, V_8H, V_16B), \
421 QLF3(V_8H , V_4S , V_8H ), \
422 QLF3(V_4S , V_2D , V_4S ), \
425 /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>.
426 the 3rd qualifier is used to help the encoding. */
429 QLF3(V_8H , V_8B , V_8B ), \
430 QLF3(V_4S , V_4H , V_4H ), \
431 QLF3(V_2D , V_2S , V_2S ), \
434 /* e.g. SSHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
435 #define QL_VSHIFTL2 \
437 QLF3(V_8H , V_16B, V_16B), \
438 QLF3(V_4S , V_8H , V_8H ), \
439 QLF3(V_2D , V_4S , V_4S ), \
445 QLF3(V_8B , V_16B, V_8B ), \
446 QLF3(V_16B, V_16B, V_16B), \
455 /* e.g. ABS <V><d>, <V><n>. */
461 /* e.g. CMGT <V><d>, <V><n>, #0. */
462 #define QL_SISD_CMP_0 \
464 QLF3(S_D, S_D, NIL), \
467 /* e.g. FCMEQ <V><d>, <V><n>, #0. */
468 #define QL_SISD_FCMP_0 \
470 QLF3(S_S, S_S, NIL), \
471 QLF3(S_D, S_D, NIL), \
474 /* e.g. FCMEQ <V><d>, <V><n>, #0. */
475 #define QL_SISD_FCMP_H_0 \
477 QLF3 (S_H, S_H, NIL), \
480 /* e.g. FMAXNMP <V><d>, <Vn>.<T>. */
481 #define QL_SISD_PAIR \
487 /* e.g. ADDP <V><d>, <Vn>.<T>. */
488 #define QL_SISD_PAIR_D \
493 /* e.g. DUP <V><d>, <Vn>.<T>[<index>]. */
502 /* e.g. FCVTNS <V><d>, <V><n>. */
503 #define QL_S_2SAMESD \
509 /* e.g. FCVTNS <V><d>, <V><n>. */
510 #define QL_S_2SAMEH \
515 /* e.g. SQXTN <Vb><d>, <Va><n>. */
516 #define QL_SISD_NARROW \
523 /* e.g. FCVTXN <Vb><d>, <Va><n>. */
524 #define QL_SISD_NARROW_S \
540 /* FMOV <Dd>, <Dn>. */
547 /* FMOV <Hd>, <Hn>. */
553 /* e.g. SQADD <V><d>, <V><n>, <V><m>. */
556 QLF3(S_B, S_B, S_B), \
557 QLF3(S_H, S_H, S_H), \
558 QLF3(S_S, S_S, S_S), \
559 QLF3(S_D, S_D, S_D), \
562 /* e.g. CMGE <V><d>, <V><n>, <V><m>. */
563 #define QL_S_3SAMED \
565 QLF3(S_D, S_D, S_D), \
568 /* e.g. SQDMULH <V><d>, <V><n>, <V><m>. */
571 QLF3(S_H, S_H, S_H), \
572 QLF3(S_S, S_S, S_S), \
575 /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vb><m>. */
576 #define QL_SISDL_HS \
578 QLF3(S_S, S_H, S_H), \
579 QLF3(S_D, S_S, S_S), \
582 /* FMUL <Sd>, <Sn>, <Sm>. */
585 QLF3(S_S, S_S, S_S), \
586 QLF3(S_D, S_D, S_D), \
589 /* FMUL <Hd>, <Hn>, <Hm>. */
592 QLF3 (S_H, S_H, S_H), \
595 /* FMADD <Dd>, <Dn>, <Dm>, <Da>. */
598 QLF4(S_S, S_S, S_S, S_S), \
599 QLF4(S_D, S_D, S_D, S_D), \
602 /* FMADD <Hd>, <Hn>, <Hm>, <Ha>. */
605 QLF4 (S_H, S_H, S_H, S_H), \
608 /* e.g. FCMP <Dn>, #0.0. */
615 /* e.g. FCMP <Hn>, #0.0. */
621 /* FCSEL <Sd>, <Sn>, <Sm>, <cond>. */
624 QLF4(S_S, S_S, S_S, NIL), \
625 QLF4(S_D, S_D, S_D, NIL), \
628 /* FCSEL <Hd>, <Hn>, <Hm>, <cond>. */
629 #define QL_FP_COND_H \
631 QLF4 (S_H, S_H, S_H, NIL), \
634 /* e.g. CCMN <Xn>, <Xm>, #<nzcv>, <cond>. */
637 QLF4(W, W, NIL, NIL), \
638 QLF4(X, X, NIL, NIL), \
641 /* e.g. CCMN <Xn>, #<imm>, #<nzcv>, <cond>, */
642 #define QL_CCMP_IMM \
644 QLF4(W, NIL, NIL, NIL), \
645 QLF4(X, NIL, NIL, NIL), \
648 /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */
651 QLF4(S_S, S_S, NIL, NIL), \
652 QLF4(S_D, S_D, NIL, NIL), \
655 /* e.g. FCCMP <Sn>, <Sm>, #<nzcv>, <cond>. */
658 QLF4 (S_H, S_H, NIL, NIL), \
661 /* e.g. DUP <Vd>.<T>, <Vn>.<Ts>[<index>]. */
673 /* e.g. DUP <Vd>.<T>, <Wn>. */
685 /* e.g. INS <Vd>.<Ts>[<index>], <Wn>. */
694 /* e.g. SMOV <Wd>, <Vn>.<Ts>[<index>]. */
704 /* e.g. UMOV <Wd>, <Vn>.<Ts>[<index>]. */
713 /* e.g. MOV <Wd>, <Vn>.<Ts>[<index>]. */
720 /* e.g. SUQADD <Vd>.<T>, <Vn>.<T>. */
723 QLF2(V_8B , V_8B ), \
724 QLF2(V_16B, V_16B), \
725 QLF2(V_4H , V_4H ), \
726 QLF2(V_8H , V_8H ), \
727 QLF2(V_2S , V_2S ), \
728 QLF2(V_4S , V_4S ), \
729 QLF2(V_2D , V_2D ), \
732 /* e.g. URSQRTE <Vd>.<T>, <Vn>.<T>. */
735 QLF2(V_2S , V_2S ), \
736 QLF2(V_4S , V_4S ), \
739 /* e.g. REV32 <Vd>.<T>, <Vn>.<T>. */
740 #define QL_V2SAMEBH \
742 QLF2(V_8B , V_8B ), \
743 QLF2(V_16B, V_16B), \
744 QLF2(V_4H , V_4H ), \
745 QLF2(V_8H , V_8H ), \
748 /* e.g. FRINTN <Vd>.<T>, <Vn>.<T>. */
749 #define QL_V2SAMESD \
751 QLF2(V_2S , V_2S ), \
752 QLF2(V_4S , V_4S ), \
753 QLF2(V_2D , V_2D ), \
756 /* e.g. REV64 <Vd>.<T>, <Vn>.<T>. */
757 #define QL_V2SAMEBHS \
759 QLF2(V_8B , V_8B ), \
760 QLF2(V_16B, V_16B), \
761 QLF2(V_4H , V_4H ), \
762 QLF2(V_8H , V_8H ), \
763 QLF2(V_2S , V_2S ), \
764 QLF2(V_4S , V_4S ), \
767 /* e.g. FCMGT <Vd>.<T>, <Vd>.<T>>, #0.0. */
774 /* e.g. REV16 <Vd>.<T>, <Vn>.<T>. */
777 QLF2(V_8B , V_8B ), \
778 QLF2(V_16B, V_16B), \
781 /* e.g. SADDLP <Vd>.<Ta>, <Vn>.<Tb>. */
782 #define QL_V2PAIRWISELONGBHS \
784 QLF2(V_4H , V_8B ), \
785 QLF2(V_8H , V_16B), \
786 QLF2(V_2S , V_4H ), \
787 QLF2(V_4S , V_8H ), \
788 QLF2(V_1D , V_2S ), \
789 QLF2(V_2D , V_4S ), \
792 /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
793 #define QL_V2LONGBHS \
795 QLF2(V_8H , V_8B ), \
796 QLF2(V_4S , V_4H ), \
797 QLF2(V_2D , V_2S ), \
800 /* e.g. SHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #<shift>. */
801 #define QL_V2LONGBHS2 \
803 QLF2(V_8H , V_16B), \
804 QLF2(V_4S , V_8H ), \
805 QLF2(V_2D , V_4S ), \
811 QLF3(V_8B , V_8B , V_8B ), \
812 QLF3(V_16B, V_16B, V_16B), \
813 QLF3(V_4H , V_4H , V_4H ), \
814 QLF3(V_8H , V_8H , V_8H ), \
815 QLF3(V_2S , V_2S , V_2S ), \
816 QLF3(V_4S , V_4S , V_4S ), \
817 QLF3(V_2D , V_2D , V_2D ) \
821 #define QL_V3SAMEBHS \
823 QLF3(V_8B , V_8B , V_8B ), \
824 QLF3(V_16B, V_16B, V_16B), \
825 QLF3(V_4H , V_4H , V_4H ), \
826 QLF3(V_8H , V_8H , V_8H ), \
827 QLF3(V_2S , V_2S , V_2S ), \
828 QLF3(V_4S , V_4S , V_4S ), \
831 /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
834 QLF2(V_2S , V_2D ), \
837 /* e.g. FCVTXN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
838 #define QL_V2NARRS2 \
840 QLF2(V_4S , V_2D ), \
843 /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
844 #define QL_V2NARRHS \
846 QLF2(V_4H , V_4S ), \
847 QLF2(V_2S , V_2D ), \
850 /* e.g. FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
851 #define QL_V2NARRHS2 \
853 QLF2(V_8H , V_4S ), \
854 QLF2(V_4S , V_2D ), \
857 /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
858 #define QL_V2LONGHS \
860 QLF2(V_4S , V_4H ), \
861 QLF2(V_2D , V_2S ), \
864 /* e.g. FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>. */
865 #define QL_V2LONGHS2 \
867 QLF2(V_4S , V_8H ), \
868 QLF2(V_2D , V_4S ), \
871 /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
872 #define QL_V2NARRBHS \
874 QLF2(V_8B , V_8H ), \
875 QLF2(V_4H , V_4S ), \
876 QLF2(V_2S , V_2D ), \
879 /* e.g. XTN<Q> <Vd>.<Tb>, <Vn>.<Ta>. */
880 #define QL_V2NARRBHS2 \
882 QLF2(V_16B, V_8H ), \
883 QLF2(V_8H , V_4S ), \
884 QLF2(V_4S , V_2D ), \
890 QLF2(V_8B , V_8B ), \
891 QLF2(V_16B, V_16B), \
895 #define QL_V2SAME16B \
897 QLF2(V_16B, V_16B), \
901 #define QL_V2SAME4S \
907 #define QL_V3SAME4S \
909 QLF3(V_4S, V_4S, V_4S), \
915 QLF3(V_8B , V_8B , V_8B ), \
916 QLF3(V_16B, V_16B, V_16B), \
919 /* e.g. EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>. */
922 QLF4(V_8B , V_8B , V_8B , imm_0_7), \
923 QLF4(V_16B, V_16B, V_16B, imm_0_15), \
927 #define QL_V3SAMEHS \
929 QLF3(V_4H , V_4H , V_4H ), \
930 QLF3(V_8H , V_8H , V_8H ), \
931 QLF3(V_2S , V_2S , V_2S ), \
932 QLF3(V_4S , V_4S , V_4S ), \
936 #define QL_V3SAMESD \
938 QLF3(V_2S , V_2S , V_2S ), \
939 QLF3(V_4S , V_4S , V_4S ), \
940 QLF3(V_2D , V_2D , V_2D ) \
943 /* e.g. FMAXNM <Vd>.<T>, <Vn>.<T>, <Vm>.<T>. */
946 QLF3 (V_4H , V_4H , V_4H ), \
947 QLF3 (V_8H , V_8H , V_8H ), \
950 /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
951 #define QL_V3LONGHS \
953 QLF3(V_4S , V_4H , V_4H ), \
954 QLF3(V_2D , V_2S , V_2S ), \
957 /* e.g. SQDMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
958 #define QL_V3LONGHS2 \
960 QLF3(V_4S , V_8H , V_8H ), \
961 QLF3(V_2D , V_4S , V_4S ), \
964 /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
965 #define QL_V3LONGBHS \
967 QLF3(V_8H , V_8B , V_8B ), \
968 QLF3(V_4S , V_4H , V_4H ), \
969 QLF3(V_2D , V_2S , V_2S ), \
972 /* e.g. SADDL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>. */
973 #define QL_V3LONGBHS2 \
975 QLF3(V_8H , V_16B , V_16B ), \
976 QLF3(V_4S , V_8H , V_8H ), \
977 QLF3(V_2D , V_4S , V_4S ), \
980 /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */
981 #define QL_V3WIDEBHS \
983 QLF3(V_8H , V_8H , V_8B ), \
984 QLF3(V_4S , V_4S , V_4H ), \
985 QLF3(V_2D , V_2D , V_2S ), \
988 /* e.g. SADDW<Q> <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>. */
989 #define QL_V3WIDEBHS2 \
991 QLF3(V_8H , V_8H , V_16B ), \
992 QLF3(V_4S , V_4S , V_8H ), \
993 QLF3(V_2D , V_2D , V_4S ), \
996 /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */
997 #define QL_V3NARRBHS \
999 QLF3(V_8B , V_8H , V_8H ), \
1000 QLF3(V_4H , V_4S , V_4S ), \
1001 QLF3(V_2S , V_2D , V_2D ), \
1004 /* e.g. ADDHN<Q> <Vd>.<Tb>, <Vn>.<Ta>, <Vm>.<Ta>. */
1005 #define QL_V3NARRBHS2 \
1007 QLF3(V_16B , V_8H , V_8H ), \
1008 QLF3(V_8H , V_4S , V_4S ), \
1009 QLF3(V_4S , V_2D , V_2D ), \
1013 #define QL_V3LONGB \
1015 QLF3(V_8H , V_8B , V_8B ), \
1018 /* e.g. PMULL crypto. */
1019 #define QL_V3LONGD \
1021 QLF3(V_1Q , V_1D , V_1D ), \
1025 #define QL_V3LONGB2 \
1027 QLF3(V_8H , V_16B, V_16B), \
1030 /* e.g. PMULL2 crypto. */
1031 #define QL_V3LONGD2 \
1033 QLF3(V_1Q , V_2D , V_2D ), \
1039 QLF3(S_Q, S_S, V_4S), \
1042 /* e.g. SHA256H2. */
1043 #define QL_SHA256UPT \
1045 QLF3(S_Q, S_Q, V_4S), \
1048 /* e.g. LDXRB <Wt>, [<Xn|SP>{,#0}]. */
1049 #define QL_W1_LDST_EXC \
1054 /* e.g. LDXR <Xt>, [<Xn|SP>{,#0}]. */
1061 /* e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
1062 #define QL_W2_LDST_EXC \
1067 /* e.g. STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]. */
1068 #define QL_R2_LDST_EXC \
1074 /* e.g. LDXP <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1081 /* e.g. CASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */
1084 QLF5(W, W, W, W, NIL), \
1085 QLF5(X, X, X, X, NIL), \
1088 /* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */
1089 #define QL_R3_LDST_EXC \
1091 QLF4(W, W, W, NIL), \
1092 QLF4(W, X, X, NIL), \
1095 /* e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1096 #define QL_LDST_FP \
1105 /* e.g. STR <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1112 /* e.g. STRB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1113 #define QL_LDST_W8 \
1118 /* e.g. LDRSB <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1119 #define QL_LDST_R8 \
1125 /* e.g. STRH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1126 #define QL_LDST_W16 \
1131 /* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1132 #define QL_LDST_X32 \
1137 /* e.g. LDRSH <Wt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1138 #define QL_LDST_R16 \
1144 /* e.g. PRFM <prfop>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
1145 #define QL_LDST_PRFM \
1150 /* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */
1151 #define QL_LDST_PAIR_X32 \
1156 /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */
1157 #define QL_LDST_PAIR_R \
1163 /* e.g. STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}]. */
1164 #define QL_LDST_PAIR_FP \
1166 QLF3(S_S, S_S, S_S), \
1167 QLF3(S_D, S_D, S_D), \
1168 QLF3(S_Q, S_Q, S_Q), \
1171 /* e.g. LD3 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */
1172 #define QL_SIMD_LDST \
1183 /* e.g. LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>]. */
1184 #define QL_SIMD_LDST_ANY \
1196 /* e.g. LD4 {<Vt>.<T>, <Vt2a>.<T>, <Vt3a>.<T>, <Vt4a>.<T>}[<index>], [<Xn|SP>]. */
1197 #define QL_SIMD_LDSTONE \
1205 /* e.g. ADDV <V><d>, <Vn>.<T>. */
1215 /* e.g. FMINV <V><d>, <Vn>.<T>. */
1216 #define QL_XLANES_FP \
1221 /* e.g. FMINV <V><d>, <Vn>.<T>. */
1222 #define QL_XLANES_FP_H \
1228 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
1229 #define QL_XLANES_L \
1238 /* e.g. MUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>]. */
1239 #define QL_ELEMENT \
1241 QLF3(V_4H, V_4H, S_H), \
1242 QLF3(V_8H, V_8H, S_H), \
1243 QLF3(V_2S, V_2S, S_S), \
1244 QLF3(V_4S, V_4S, S_S), \
1247 /* e.g. SMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */
1248 #define QL_ELEMENT_L \
1250 QLF3(V_4S, V_4H, S_H), \
1251 QLF3(V_2D, V_2S, S_S), \
1254 /* e.g. SMLAL2 <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>]. */
1255 #define QL_ELEMENT_L2 \
1257 QLF3(V_4S, V_8H, S_H), \
1258 QLF3(V_2D, V_4S, S_S), \
1261 /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */
1262 #define QL_ELEMENT_FP \
1264 QLF3(V_2S, V_2S, S_S), \
1265 QLF3(V_4S, V_4S, S_S), \
1266 QLF3(V_2D, V_2D, S_D), \
1269 /* e.g. FMLA <V><d>, <V><n>, <Vm>.<Ts>[<index>]. */
1270 #define QL_ELEMENT_FP_H \
1272 QLF3 (V_4H, V_4H, S_H), \
1273 QLF3 (V_8H, V_8H, S_H), \
1276 /* e.g. MOVI <Vd>.4S, #<imm8> {, LSL #<amount>}. */
1277 #define QL_SIMD_IMM_S0W \
1283 /* e.g. MOVI <Vd>.4S, #<imm8>, MSL #<amount>. */
1284 #define QL_SIMD_IMM_S1W \
1290 /* e.g. MOVI <Vd>.4H, #<imm8> {, LSL #<amount>}. */
1291 #define QL_SIMD_IMM_S0H \
1297 /* e.g. FMOV <Vd>.<T>, #<imm>. */
1298 #define QL_SIMD_IMM_S \
1304 /* e.g. MOVI <Vd>.8B, #<imm8> {, LSL #<amount>}. */
1305 #define QL_SIMD_IMM_B \
1310 /* e.g. MOVI <Dd>, #<imm>. */
1311 #define QL_SIMD_IMM_D \
1316 /* e.g. FMOV <Vd>.<T>, #<imm>. */
1317 #define QL_SIMD_IMM_H \
1323 /* e.g. MOVI <Vd>.2D, #<imm>. */
1324 #define QL_SIMD_IMM_V2D \
1331 static const aarch64_feature_set aarch64_feature_v8
=
1332 AARCH64_FEATURE (AARCH64_FEATURE_V8
, 0);
1333 static const aarch64_feature_set aarch64_feature_fp
=
1334 AARCH64_FEATURE (AARCH64_FEATURE_FP
, 0);
1335 static const aarch64_feature_set aarch64_feature_simd
=
1336 AARCH64_FEATURE (AARCH64_FEATURE_SIMD
, 0);
1337 static const aarch64_feature_set aarch64_feature_crypto
=
1338 AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
, 0);
1339 static const aarch64_feature_set aarch64_feature_crc
=
1340 AARCH64_FEATURE (AARCH64_FEATURE_CRC
, 0);
1341 static const aarch64_feature_set aarch64_feature_lse
=
1342 AARCH64_FEATURE (AARCH64_FEATURE_LSE
, 0);
1343 static const aarch64_feature_set aarch64_feature_lor
=
1344 AARCH64_FEATURE (AARCH64_FEATURE_LOR
, 0);
1345 static const aarch64_feature_set aarch64_feature_rdma
=
1346 AARCH64_FEATURE (AARCH64_FEATURE_RDMA
, 0);
1347 static const aarch64_feature_set aarch64_feature_ras
=
1348 AARCH64_FEATURE (AARCH64_FEATURE_RAS
, 0);
1349 static const aarch64_feature_set aarch64_feature_v8_2
=
1350 AARCH64_FEATURE (AARCH64_FEATURE_V8_2
, 0);
1351 static const aarch64_feature_set aarch64_feature_fp_f16
=
1352 AARCH64_FEATURE (AARCH64_FEATURE_F16
| AARCH64_FEATURE_FP
, 0);
1353 static const aarch64_feature_set aarch64_feature_simd_f16
=
1354 AARCH64_FEATURE (AARCH64_FEATURE_F16
| AARCH64_FEATURE_SIMD
, 0);
1355 static const aarch64_feature_set aarch64_feature_stat_profile
=
1356 AARCH64_FEATURE (AARCH64_FEATURE_PROFILE
, 0);
1358 #define CORE &aarch64_feature_v8
1359 #define FP &aarch64_feature_fp
1360 #define SIMD &aarch64_feature_simd
1361 #define CRYPTO &aarch64_feature_crypto
1362 #define CRC &aarch64_feature_crc
1363 #define LSE &aarch64_feature_lse
1364 #define LOR &aarch64_feature_lor
1365 #define RDMA &aarch64_feature_rdma
1366 #define FP_F16 &aarch64_feature_fp_f16
1367 #define SIMD_F16 &aarch64_feature_simd_f16
1368 #define RAS &aarch64_feature_ras
1369 #define STAT_PROFILE &aarch64_feature_stat_profile
1370 #define ARMV8_2 &aarch64_feature_v8_2
1372 struct aarch64_opcode aarch64_opcode_table
[] =
1374 /* Add/subtract (with carry). */
1375 {"adc", 0x1a000000, 0x7fe0fc00, addsub_carry
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
},
1376 {"adcs", 0x3a000000, 0x7fe0fc00, addsub_carry
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
},
1377 {"sbc", 0x5a000000, 0x7fe0fc00, addsub_carry
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_HAS_ALIAS
| F_SF
},
1378 {"ngc", 0x5a0003e0, 0x7fe0ffe0, addsub_carry
, 0, CORE
, OP2 (Rd
, Rm
), QL_I2SAME
, F_ALIAS
| F_SF
},
1379 {"sbcs", 0x7a000000, 0x7fe0fc00, addsub_carry
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_HAS_ALIAS
| F_SF
},
1380 {"ngcs", 0x7a0003e0, 0x7fe0ffe0, addsub_carry
, 0, CORE
, OP2 (Rd
, Rm
), QL_I2SAME
, F_ALIAS
| F_SF
},
1381 /* Add/subtract (extended register). */
1382 {"add", 0x0b200000, 0x7fe00000, addsub_ext
, 0, CORE
, OP3 (Rd_SP
, Rn_SP
, Rm_EXT
), QL_I3_EXT
, F_SF
},
1383 {"adds", 0x2b200000, 0x7fe00000, addsub_ext
, 0, CORE
, OP3 (Rd
, Rn_SP
, Rm_EXT
), QL_I3_EXT
, F_HAS_ALIAS
| F_SF
},
1384 {"cmn", 0x2b20001f, 0x7fe0001f, addsub_ext
, 0, CORE
, OP2 (Rn_SP
, Rm_EXT
), QL_I2_EXT
, F_ALIAS
| F_SF
},
1385 {"sub", 0x4b200000, 0x7fe00000, addsub_ext
, 0, CORE
, OP3 (Rd_SP
, Rn_SP
, Rm_EXT
), QL_I3_EXT
, F_SF
},
1386 {"subs", 0x6b200000, 0x7fe00000, addsub_ext
, 0, CORE
, OP3 (Rd
, Rn_SP
, Rm_EXT
), QL_I3_EXT
, F_HAS_ALIAS
| F_SF
},
1387 {"cmp", 0x6b20001f, 0x7fe0001f, addsub_ext
, 0, CORE
, OP2 (Rn_SP
, Rm_EXT
), QL_I2_EXT
, F_ALIAS
| F_SF
},
1388 /* Add/subtract (immediate). */
1389 {"add", 0x11000000, 0x7f000000, addsub_imm
, OP_ADD
, CORE
, OP3 (Rd_SP
, Rn_SP
, AIMM
), QL_R2NIL
, F_HAS_ALIAS
| F_SF
},
1390 {"mov", 0x11000000, 0x7ffffc00, addsub_imm
, 0, CORE
, OP2 (Rd_SP
, Rn_SP
), QL_I2SP
, F_ALIAS
| F_SF
},
1391 {"adds", 0x31000000, 0x7f000000, addsub_imm
, 0, CORE
, OP3 (Rd
, Rn_SP
, AIMM
), QL_R2NIL
, F_HAS_ALIAS
| F_SF
},
1392 {"cmn", 0x3100001f, 0x7f00001f, addsub_imm
, 0, CORE
, OP2 (Rn_SP
, AIMM
), QL_R1NIL
, F_ALIAS
| F_SF
},
1393 {"sub", 0x51000000, 0x7f000000, addsub_imm
, 0, CORE
, OP3 (Rd_SP
, Rn_SP
, AIMM
), QL_R2NIL
, F_SF
},
1394 {"subs", 0x71000000, 0x7f000000, addsub_imm
, 0, CORE
, OP3 (Rd
, Rn_SP
, AIMM
), QL_R2NIL
, F_HAS_ALIAS
| F_SF
},
1395 {"cmp", 0x7100001f, 0x7f00001f, addsub_imm
, 0, CORE
, OP2 (Rn_SP
, AIMM
), QL_R1NIL
, F_ALIAS
| F_SF
},
1396 /* Add/subtract (shifted register). */
1397 {"add", 0xb000000, 0x7f200000, addsub_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_SF
},
1398 {"adds", 0x2b000000, 0x7f200000, addsub_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_HAS_ALIAS
| F_SF
},
1399 {"cmn", 0x2b00001f, 0x7f20001f, addsub_shift
, 0, CORE
, OP2 (Rn
, Rm_SFT
), QL_I2SAME
, F_ALIAS
| F_SF
},
1400 {"sub", 0x4b000000, 0x7f200000, addsub_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_HAS_ALIAS
| F_SF
},
1401 {"neg", 0x4b0003e0, 0x7f2003e0, addsub_shift
, 0, CORE
, OP2 (Rd
, Rm_SFT
), QL_I2SAME
, F_ALIAS
| F_SF
},
1402 {"subs", 0x6b000000, 0x7f200000, addsub_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_HAS_ALIAS
| F_SF
},
1403 {"cmp", 0x6b00001f, 0x7f20001f, addsub_shift
, 0, CORE
, OP2 (Rn
, Rm_SFT
), QL_I2SAME
, F_ALIAS
| F_SF
},
1404 {"negs", 0x6b0003e0, 0x7f2003e0, addsub_shift
, 0, CORE
, OP2 (Rd
, Rm_SFT
), QL_I2SAME
, F_ALIAS
| F_SF
},
1405 /* AdvSIMD across lanes. */
1406 {"saddlv", 0xe303800, 0xbf3ffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES_L
, F_SIZEQ
},
1407 {"smaxv", 0xe30a800, 0xbf3ffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES
, F_SIZEQ
},
1408 {"sminv", 0xe31a800, 0xbf3ffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES
, F_SIZEQ
},
1409 {"addv", 0xe31b800, 0xbf3ffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES
, F_SIZEQ
},
1410 {"uaddlv", 0x2e303800, 0xbf3ffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES_L
, F_SIZEQ
},
1411 {"umaxv", 0x2e30a800, 0xbf3ffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES
, F_SIZEQ
},
1412 {"uminv", 0x2e31a800, 0xbf3ffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES
, F_SIZEQ
},
1413 {"fmaxnmv", 0x2e30c800, 0xbfbffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES_FP
, F_SIZEQ
},
1414 {"fmaxnmv", 0xe30c800, 0xbffffc00, asimdall
, 0, SIMD_F16
,
1415 OP2 (Fd
, Vn
), QL_XLANES_FP_H
, F_SIZEQ
},
1416 {"fmaxv", 0x2e30f800, 0xbfbffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES_FP
, F_SIZEQ
},
1417 {"fmaxv", 0xe30f800, 0xbffffc00, asimdall
, 0, SIMD_F16
,
1418 OP2 (Fd
, Vn
), QL_XLANES_FP_H
, F_SIZEQ
},
1419 {"fminnmv", 0x2eb0c800, 0xbfbffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES_FP
, F_SIZEQ
},
1420 {"fminnmv", 0xeb0c800, 0xbffffc00, asimdall
, 0, SIMD_F16
,
1421 OP2 (Fd
, Vn
), QL_XLANES_FP_H
, F_SIZEQ
},
1422 {"fminv", 0x2eb0f800, 0xbfbffc00, asimdall
, 0, SIMD
, OP2 (Fd
, Vn
), QL_XLANES_FP
, F_SIZEQ
},
1423 {"fminv", 0xeb0f800, 0xbffffc00, asimdall
, 0, SIMD_F16
,
1424 OP2 (Fd
, Vn
), QL_XLANES_FP_H
, F_SIZEQ
},
1425 /* AdvSIMD three different. */
1426 {"saddl", 0x0e200000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1427 {"saddl2", 0x4e200000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1428 {"saddw", 0x0e201000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3WIDEBHS
, F_SIZEQ
},
1429 {"saddw2", 0x4e201000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3WIDEBHS2
, F_SIZEQ
},
1430 {"ssubl", 0x0e202000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1431 {"ssubl2", 0x4e202000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1432 {"ssubw", 0x0e203000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3WIDEBHS
, F_SIZEQ
},
1433 {"ssubw2", 0x4e203000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3WIDEBHS2
, F_SIZEQ
},
1434 {"addhn", 0x0e204000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3NARRBHS
, F_SIZEQ
},
1435 {"addhn2", 0x4e204000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3NARRBHS2
, F_SIZEQ
},
1436 {"sabal", 0x0e205000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1437 {"sabal2", 0x4e205000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1438 {"subhn", 0x0e206000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3NARRBHS
, F_SIZEQ
},
1439 {"subhn2", 0x4e206000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3NARRBHS2
, F_SIZEQ
},
1440 {"sabdl", 0x0e207000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1441 {"sabdl2", 0x4e207000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1442 {"smlal", 0x0e208000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1443 {"smlal2", 0x4e208000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1444 {"sqdmlal", 0x0e209000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGHS
, F_SIZEQ
},
1445 {"sqdmlal2", 0x4e209000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGHS2
, F_SIZEQ
},
1446 {"smlsl", 0x0e20a000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1447 {"smlsl2", 0x4e20a000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1448 {"sqdmlsl", 0x0e20b000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGHS
, F_SIZEQ
},
1449 {"sqdmlsl2", 0x4e20b000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGHS2
, F_SIZEQ
},
1450 {"smull", 0x0e20c000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1451 {"smull2", 0x4e20c000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1452 {"sqdmull", 0x0e20d000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGHS
, F_SIZEQ
},
1453 {"sqdmull2", 0x4e20d000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGHS2
, F_SIZEQ
},
1454 {"pmull", 0x0e20e000, 0xffe0fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGB
, 0},
1455 {"pmull", 0x0ee0e000, 0xffe0fc00, asimddiff
, 0, CRYPTO
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGD
, 0},
1456 {"pmull2", 0x4e20e000, 0xffe0fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGB2
, 0},
1457 {"pmull2", 0x4ee0e000, 0xffe0fc00, asimddiff
, 0, CRYPTO
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGD2
, 0},
1458 {"uaddl", 0x2e200000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1459 {"uaddl2", 0x6e200000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1460 {"uaddw", 0x2e201000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3WIDEBHS
, F_SIZEQ
},
1461 {"uaddw2", 0x6e201000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3WIDEBHS2
, F_SIZEQ
},
1462 {"usubl", 0x2e202000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1463 {"usubl2", 0x6e202000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1464 {"usubw", 0x2e203000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3WIDEBHS
, F_SIZEQ
},
1465 {"usubw2", 0x6e203000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3WIDEBHS2
, F_SIZEQ
},
1466 {"raddhn", 0x2e204000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3NARRBHS
, F_SIZEQ
},
1467 {"raddhn2", 0x6e204000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3NARRBHS2
, F_SIZEQ
},
1468 {"uabal", 0x2e205000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1469 {"uabal2", 0x6e205000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1470 {"rsubhn", 0x2e206000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3NARRBHS
, F_SIZEQ
},
1471 {"rsubhn2", 0x6e206000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3NARRBHS2
, F_SIZEQ
},
1472 {"uabdl", 0x2e207000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1473 {"uabdl2", 0x6e207000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1474 {"umlal", 0x2e208000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1475 {"umlal2", 0x6e208000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1476 {"umlsl", 0x2e20a000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1477 {"umlsl2", 0x6e20a000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1478 {"umull", 0x2e20c000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS
, F_SIZEQ
},
1479 {"umull2", 0x6e20c000, 0xff20fc00, asimddiff
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3LONGBHS2
, F_SIZEQ
},
1480 /* AdvSIMD vector x indexed element. */
1481 {"smlal", 0x0f002000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L
, F_SIZEQ
},
1482 {"smlal2", 0x4f002000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L2
, F_SIZEQ
},
1483 {"sqdmlal", 0x0f003000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L
, F_SIZEQ
},
1484 {"sqdmlal2", 0x4f003000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L2
, F_SIZEQ
},
1485 {"smlsl", 0x0f006000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L
, F_SIZEQ
},
1486 {"smlsl2", 0x4f006000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L2
, F_SIZEQ
},
1487 {"sqdmlsl", 0x0f007000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L
, F_SIZEQ
},
1488 {"sqdmlsl2", 0x4f007000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L2
, F_SIZEQ
},
1489 {"mul", 0xf008000, 0xbf00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT
, F_SIZEQ
},
1490 {"smull", 0x0f00a000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L
, F_SIZEQ
},
1491 {"smull2", 0x4f00a000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L2
, F_SIZEQ
},
1492 {"sqdmull", 0x0f00b000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L
, F_SIZEQ
},
1493 {"sqdmull2", 0x4f00b000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L2
, F_SIZEQ
},
1494 {"sqdmulh", 0xf00c000, 0xbf00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT
, F_SIZEQ
},
1495 {"sqrdmulh", 0xf00d000, 0xbf00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT
, F_SIZEQ
},
1496 {"fmla", 0xf801000, 0xbf80f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_FP
, F_SIZEQ
},
1497 {"fmla", 0xf001000, 0xbfe0fc00, asimdelem
, 0, SIMD_F16
,
1498 OP3 (Vd
, Vn
, Em
), QL_ELEMENT_FP_H
, F_SIZEQ
},
1499 {"fmls", 0xf805000, 0xbf80f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_FP
, F_SIZEQ
},
1500 {"fmls", 0xf005000, 0xbfe0fc00, asimdelem
, 0, SIMD_F16
,
1501 OP3 (Vd
, Vn
, Em
), QL_ELEMENT_FP_H
, F_SIZEQ
},
1502 {"fmul", 0xf809000, 0xbf80f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_FP
, F_SIZEQ
},
1503 {"fmul", 0xf009000, 0xbfe0fc00, asimdelem
, 0, SIMD_F16
,
1504 OP3 (Vd
, Vn
, Em
), QL_ELEMENT_FP_H
, F_SIZEQ
},
1505 {"mla", 0x2f000000, 0xbf00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT
, F_SIZEQ
},
1506 {"umlal", 0x2f002000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L
, F_SIZEQ
},
1507 {"umlal2", 0x6f002000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L2
, F_SIZEQ
},
1508 {"mls", 0x2f004000, 0xbf00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT
, F_SIZEQ
},
1509 {"umlsl", 0x2f006000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L
, F_SIZEQ
},
1510 {"umlsl2", 0x6f006000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L2
, F_SIZEQ
},
1511 {"umull", 0x2f00a000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L
, F_SIZEQ
},
1512 {"umull2", 0x6f00a000, 0xff00f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_L2
, F_SIZEQ
},
1513 {"fmulx", 0x2f809000, 0xbf80f400, asimdelem
, 0, SIMD
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT_FP
, F_SIZEQ
},
1514 {"fmulx", 0x2f009000, 0xbfe0fc00, asimdelem
, 0, SIMD_F16
,
1515 OP3 (Vd
, Vn
, Em
), QL_ELEMENT_FP_H
, F_SIZEQ
},
1516 {"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem
, 0, RDMA
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT
, F_SIZEQ
},
1517 {"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem
, 0, RDMA
, OP3 (Vd
, Vn
, Em
), QL_ELEMENT
, F_SIZEQ
},
1519 {"ext", 0x2e000000, 0xbfe08400, asimdext
, 0, SIMD
, OP4 (Vd
, Vn
, Vm
, IDX
), QL_VEXT
, F_SIZEQ
},
1520 /* AdvSIMD modified immediate. */
1521 {"movi", 0xf000400, 0xbff89c00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S0W
, F_SIZEQ
},
1522 {"orr", 0xf001400, 0xbff89c00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S0W
, F_SIZEQ
},
1523 {"movi", 0xf008400, 0xbff8dc00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S0H
, F_SIZEQ
},
1524 {"orr", 0xf009400, 0xbff8dc00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S0H
, F_SIZEQ
},
1525 {"movi", 0xf00c400, 0xbff8ec00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S1W
, F_SIZEQ
},
1526 {"movi", 0xf00e400, 0xbff8fc00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_B
, F_SIZEQ
},
1527 {"fmov", 0xf00f400, 0xbff8fc00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_FPIMM
), QL_SIMD_IMM_S
, F_SIZEQ
},
1528 {"fmov", 0xf00fc00, 0xbff8fc00, asimdimm
, 0, SIMD_F16
,
1529 OP2 (Vd
, SIMD_FPIMM
), QL_SIMD_IMM_H
, F_SIZEQ
},
1530 {"mvni", 0x2f000400, 0xbff89c00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S0W
, F_SIZEQ
},
1531 {"bic", 0x2f001400, 0xbff89c00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S0W
, F_SIZEQ
},
1532 {"mvni", 0x2f008400, 0xbff8dc00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S0H
, F_SIZEQ
},
1533 {"bic", 0x2f009400, 0xbff8dc00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S0H
, F_SIZEQ
},
1534 {"mvni", 0x2f00c400, 0xbff8ec00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM_SFT
), QL_SIMD_IMM_S1W
, F_SIZEQ
},
1535 {"movi", 0x2f00e400, 0xfff8fc00, asimdimm
, 0, SIMD
, OP2 (Sd
, SIMD_IMM
), QL_SIMD_IMM_D
, F_SIZEQ
},
1536 {"movi", 0x6f00e400, 0xfff8fc00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_IMM
), QL_SIMD_IMM_V2D
, F_SIZEQ
},
1537 {"fmov", 0x6f00f400, 0xfff8fc00, asimdimm
, 0, SIMD
, OP2 (Vd
, SIMD_FPIMM
), QL_SIMD_IMM_V2D
, F_SIZEQ
},
1539 {"dup", 0xe000400, 0xbfe0fc00, asimdins
, 0, SIMD
, OP2 (Vd
, En
), QL_DUP_VX
, F_T
},
1540 {"dup", 0xe000c00, 0xbfe0fc00, asimdins
, 0, SIMD
, OP2 (Vd
, Rn
), QL_DUP_VR
, F_T
},
1541 {"smov", 0xe002c00, 0xbfe0fc00, asimdins
, 0, SIMD
, OP2 (Rd
, En
), QL_SMOV
, F_GPRSIZE_IN_Q
},
1542 {"umov", 0xe003c00, 0xbfe0fc00, asimdins
, 0, SIMD
, OP2 (Rd
, En
), QL_UMOV
, F_HAS_ALIAS
| F_GPRSIZE_IN_Q
},
1543 {"mov", 0xe003c00, 0xbfe0fc00, asimdins
, 0, SIMD
, OP2 (Rd
, En
), QL_MOV
, F_ALIAS
| F_GPRSIZE_IN_Q
},
1544 {"ins", 0x4e001c00, 0xffe0fc00, asimdins
, 0, SIMD
, OP2 (Ed
, Rn
), QL_INS_XR
, F_HAS_ALIAS
},
1545 {"mov", 0x4e001c00, 0xffe0fc00, asimdins
, 0, SIMD
, OP2 (Ed
, Rn
), QL_INS_XR
, F_ALIAS
},
1546 {"ins", 0x6e000400, 0xffe08400, asimdins
, 0, SIMD
, OP2 (Ed
, En
), QL_S_2SAME
, F_HAS_ALIAS
},
1547 {"mov", 0x6e000400, 0xffe08400, asimdins
, 0, SIMD
, OP2 (Ed
, En
), QL_S_2SAME
, F_ALIAS
},
1548 /* AdvSIMD two-reg misc. */
1549 {"rev64", 0xe200800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEBHS
, F_SIZEQ
},
1550 {"rev16", 0xe201800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEB
, F_SIZEQ
},
1551 {"saddlp", 0xe202800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2PAIRWISELONGBHS
, F_SIZEQ
},
1552 {"suqadd", 0xe203800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAME
, F_SIZEQ
},
1553 {"cls", 0xe204800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEBHS
, F_SIZEQ
},
1554 {"cnt", 0xe205800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEB
, F_SIZEQ
},
1555 {"sadalp", 0xe206800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2PAIRWISELONGBHS
, F_SIZEQ
},
1556 {"sqabs", 0xe207800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAME
, F_SIZEQ
},
1557 {"cmgt", 0xe208800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, IMM0
), QL_V2SAME
, F_SIZEQ
},
1558 {"cmeq", 0xe209800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, IMM0
), QL_V2SAME
, F_SIZEQ
},
1559 {"cmlt", 0xe20a800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, IMM0
), QL_V2SAME
, F_SIZEQ
},
1560 {"abs", 0xe20b800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAME
, F_SIZEQ
},
1561 {"xtn", 0xe212800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRBHS
, F_SIZEQ
},
1562 {"xtn2", 0x4e212800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRBHS2
, F_SIZEQ
},
1563 {"sqxtn", 0xe214800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRBHS
, F_SIZEQ
},
1564 {"sqxtn2", 0x4e214800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRBHS2
, F_SIZEQ
},
1565 {"fcvtn", 0xe216800, 0xffbffc00, asimdmisc
, OP_FCVTN
, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRHS
, F_MISC
},
1566 {"fcvtn2", 0x4e216800, 0xffbffc00, asimdmisc
, OP_FCVTN2
, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRHS2
, F_MISC
},
1567 {"fcvtl", 0xe217800, 0xffbffc00, asimdmisc
, OP_FCVTL
, SIMD
, OP2 (Vd
, Vn
), QL_V2LONGHS
, F_MISC
},
1568 {"fcvtl2", 0x4e217800, 0xffbffc00, asimdmisc
, OP_FCVTL2
, SIMD
, OP2 (Vd
, Vn
), QL_V2LONGHS2
, F_MISC
},
1569 {"frintn", 0xe218800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1570 {"frintn", 0xe798800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1571 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1572 {"frintm", 0xe219800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1573 {"frintm", 0xe799800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1574 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1575 {"fcvtns", 0xe21a800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1576 {"fcvtns", 0xe79a800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1577 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1578 {"fcvtms", 0xe21b800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1579 {"fcvtms", 0xe79b800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1580 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1581 {"fcvtas", 0xe21c800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1582 {"fcvtas", 0xe79c800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1583 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1584 {"scvtf", 0xe21d800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1585 {"scvtf", 0xe79d800, 0xbfbffc00, asimdmisc
, 0, SIMD_F16
,
1586 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1587 {"fcmgt", 0xea0c800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMESD
, F_SIZEQ
},
1588 {"fcmgt", 0xef8c800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1589 OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMEH
, F_SIZEQ
},
1590 {"fcmeq", 0xea0d800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMESD
, F_SIZEQ
},
1591 {"fcmeq", 0xef8d800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1592 OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMEH
, F_SIZEQ
},
1593 {"fcmlt", 0xea0e800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMESD
, F_SIZEQ
},
1594 {"fcmlt", 0xef8e800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1595 OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMEH
, F_SIZEQ
},
1596 {"fabs", 0xea0f800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1597 {"fabs", 0xef8f800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1598 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1599 {"frintp", 0xea18800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1600 {"frintp", 0xef98800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1601 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1602 {"frintz", 0xea19800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1603 {"frintz", 0xef99800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1604 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1605 {"fcvtps", 0xea1a800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1606 {"fcvtps", 0xef9a800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1607 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1608 {"fcvtzs", 0xea1b800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1609 {"fcvtzs", 0xef9b800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1610 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1611 {"urecpe", 0xea1c800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMES
, F_SIZEQ
},
1612 {"frecpe", 0xea1d800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1613 {"frecpe", 0xef9d800, 0xbfbffc00, asimdmisc
, 0, SIMD_F16
,
1614 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1615 {"rev32", 0x2e200800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEBH
, F_SIZEQ
},
1616 {"uaddlp", 0x2e202800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2PAIRWISELONGBHS
, F_SIZEQ
},
1617 {"usqadd", 0x2e203800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAME
, F_SIZEQ
},
1618 {"clz", 0x2e204800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEBHS
, F_SIZEQ
},
1619 {"uadalp", 0x2e206800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2PAIRWISELONGBHS
, F_SIZEQ
},
1620 {"sqneg", 0x2e207800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAME
, F_SIZEQ
},
1621 {"cmge", 0x2e208800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, IMM0
), QL_V2SAME
, F_SIZEQ
},
1622 {"cmle", 0x2e209800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, IMM0
), QL_V2SAME
, F_SIZEQ
},
1623 {"neg", 0x2e20b800, 0xbf3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAME
, F_SIZEQ
},
1624 {"sqxtun", 0x2e212800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRBHS
, F_SIZEQ
},
1625 {"sqxtun2", 0x6e212800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRBHS2
, F_SIZEQ
},
1626 {"shll", 0x2e213800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, SHLL_IMM
), QL_V2LONGBHS
, F_SIZEQ
},
1627 {"shll2", 0x6e213800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, SHLL_IMM
), QL_V2LONGBHS2
, F_SIZEQ
},
1628 {"uqxtn", 0x2e214800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRBHS
, F_SIZEQ
},
1629 {"uqxtn2", 0x6e214800, 0xff3ffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRBHS2
, F_SIZEQ
},
1630 {"fcvtxn", 0x2e616800, 0xfffffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRS
, 0},
1631 {"fcvtxn2", 0x6e616800, 0xfffffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2NARRS2
, 0},
1632 {"frinta", 0x2e218800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1633 {"frinta", 0x2e798800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1634 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1635 {"frintx", 0x2e219800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1636 {"frintx", 0x2e799800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1637 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1638 {"fcvtnu", 0x2e21a800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1639 {"fcvtnu", 0x2e79a800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1640 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1641 {"fcvtmu", 0x2e21b800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1642 {"fcvtmu", 0x2e79b800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1643 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1644 {"fcvtau", 0x2e21c800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1645 {"fcvtau", 0x2e79c800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1646 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1647 {"ucvtf", 0x2e21d800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1648 {"ucvtf", 0x2e79d800, 0xbfbffc00, asimdmisc
, 0, SIMD_F16
,
1649 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1650 {"not", 0x2e205800, 0xbffffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEB
, F_SIZEQ
| F_HAS_ALIAS
},
1651 {"mvn", 0x2e205800, 0xbffffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEB
, F_SIZEQ
| F_ALIAS
},
1652 {"rbit", 0x2e605800, 0xbffffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEB
, F_SIZEQ
},
1653 {"fcmge", 0x2ea0c800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMESD
, F_SIZEQ
},
1654 {"fcmge", 0x2ef8c800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1655 OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMEH
, F_SIZEQ
},
1656 {"fcmle", 0x2ea0d800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMESD
, F_SIZEQ
},
1657 {"fcmle", 0x2ef8d800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1658 OP3 (Vd
, Vn
, FPIMM0
), QL_V2SAMEH
, F_SIZEQ
},
1659 {"fneg", 0x2ea0f800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1660 {"fneg", 0x2ef8f800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1661 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1662 {"frinti", 0x2ea19800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1663 {"frinti", 0x2ef99800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1664 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1665 {"fcvtpu", 0x2ea1a800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1666 {"fcvtpu", 0x2ef9a800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1667 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1668 {"fcvtzu", 0x2ea1b800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1669 {"fcvtzu", 0x2ef9b800, 0xbffffc00, asimdmisc
, 0, SIMD_F16
,
1670 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1671 {"ursqrte", 0x2ea1c800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMES
, F_SIZEQ
},
1672 {"frsqrte", 0x2ea1d800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1673 {"frsqrte", 0x2ef9d800, 0xbfbffc00, asimdmisc
, 0, SIMD_F16
,
1674 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1675 {"fsqrt", 0x2ea1f800, 0xbfbffc00, asimdmisc
, 0, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMESD
, F_SIZEQ
},
1676 {"fsqrt", 0x2ef9f800, 0xbfbffc00, asimdmisc
, 0, SIMD_F16
,
1677 OP2 (Vd
, Vn
), QL_V2SAMEH
, F_SIZEQ
},
1678 /* AdvSIMD ZIP/UZP/TRN. */
1679 {"uzp1", 0xe001800, 0xbf20fc00, asimdperm
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1680 {"trn1", 0xe002800, 0xbf20fc00, asimdperm
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1681 {"zip1", 0xe003800, 0xbf20fc00, asimdperm
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1682 {"uzp2", 0xe005800, 0xbf20fc00, asimdperm
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1683 {"trn2", 0xe006800, 0xbf20fc00, asimdperm
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1684 {"zip2", 0xe007800, 0xbf20fc00, asimdperm
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1685 /* AdvSIMD three same. */
1686 {"shadd", 0xe200400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1687 {"sqadd", 0xe200c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1688 {"srhadd", 0xe201400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1689 {"shsub", 0xe202400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1690 {"sqsub", 0xe202c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1691 {"cmgt", 0xe203400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1692 {"cmge", 0xe203c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1693 {"sshl", 0xe204400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1694 {"sqshl", 0xe204c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1695 {"srshl", 0xe205400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1696 {"sqrshl", 0xe205c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1697 {"smax", 0xe206400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1698 {"smin", 0xe206c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1699 {"sabd", 0xe207400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1700 {"saba", 0xe207c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1701 {"add", 0xe208400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1702 {"cmtst", 0xe208c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1703 {"mla", 0xe209400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1704 {"mul", 0xe209c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1705 {"smaxp", 0xe20a400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1706 {"sminp", 0xe20ac00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1707 {"sqdmulh", 0xe20b400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEHS
, F_SIZEQ
},
1708 {"addp", 0xe20bc00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1709 {"fmaxnm", 0xe20c400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1710 {"fmaxnm", 0xe400400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1711 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1712 {"fmla", 0xe20cc00, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1713 {"fmla", 0xe400c00, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1714 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1715 {"fadd", 0xe20d400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1716 {"fadd", 0xe401400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1717 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1718 {"fmulx", 0xe20dc00, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1719 {"fmulx", 0xe401c00, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1720 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1721 {"fcmeq", 0xe20e400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1722 {"fcmeq", 0xe402400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1723 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1724 {"fmax", 0xe20f400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1725 {"fmax", 0xe403400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1726 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1727 {"frecps", 0xe20fc00, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1728 {"frecps", 0xe403c00, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1729 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1730 {"and", 0xe201c00, 0xbfe0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEB
, F_SIZEQ
},
1731 {"bic", 0xe601c00, 0xbfe0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEB
, F_SIZEQ
},
1732 {"fminnm", 0xea0c400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1733 {"fminnm", 0xec00400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1734 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1735 {"fmls", 0xea0cc00, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1736 {"fmls", 0xec00c00, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1737 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1738 {"fsub", 0xea0d400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1739 {"fsub", 0xec01400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1740 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1741 {"fmin", 0xea0f400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1742 {"fmin", 0xec03400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1743 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1744 {"frsqrts", 0xea0fc00, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1745 {"frsqrts", 0xec03c00, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1746 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1747 {"orr", 0xea01c00, 0xbfe0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEB
, F_HAS_ALIAS
| F_SIZEQ
},
1748 {"mov", 0xea01c00, 0xbfe0fc00, asimdsame
, OP_MOV_V
, SIMD
, OP2 (Vd
, Vn
), QL_V2SAMEB
, F_ALIAS
| F_CONV
},
1749 {"orn", 0xee01c00, 0xbfe0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEB
, F_SIZEQ
},
1750 {"uhadd", 0x2e200400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1751 {"uqadd", 0x2e200c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1752 {"urhadd", 0x2e201400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1753 {"uhsub", 0x2e202400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1754 {"uqsub", 0x2e202c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1755 {"cmhi", 0x2e203400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1756 {"cmhs", 0x2e203c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1757 {"ushl", 0x2e204400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1758 {"uqshl", 0x2e204c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1759 {"urshl", 0x2e205400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1760 {"uqrshl", 0x2e205c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1761 {"umax", 0x2e206400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1762 {"umin", 0x2e206c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1763 {"uabd", 0x2e207400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1764 {"uaba", 0x2e207c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1765 {"sub", 0x2e208400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1766 {"cmeq", 0x2e208c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME
, F_SIZEQ
},
1767 {"mls", 0x2e209400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1768 {"pmul", 0x2e209c00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEB
, F_SIZEQ
},
1769 {"umaxp", 0x2e20a400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1770 {"uminp", 0x2e20ac00, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEBHS
, F_SIZEQ
},
1771 {"sqrdmulh", 0x2e20b400, 0xbf20fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEHS
, F_SIZEQ
},
1772 {"fmaxnmp", 0x2e20c400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1773 {"fmaxnmp", 0x2e400400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1774 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1775 {"faddp", 0x2e20d400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1776 {"faddp", 0x2e401400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1777 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1778 {"fmul", 0x2e20dc00, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1779 {"fmul", 0x2e401c00, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1780 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1781 {"fcmge", 0x2e20e400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1782 {"fcmge", 0x2e402400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1783 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1784 {"facge", 0x2e20ec00, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1785 {"facge", 0x2e402c00, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1786 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1787 {"fmaxp", 0x2e20f400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1788 {"fmaxp", 0x2e403400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1789 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1790 {"fdiv", 0x2e20fc00, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1791 {"fdiv", 0x2e403c00, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1792 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1793 {"eor", 0x2e201c00, 0xbfe0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEB
, F_SIZEQ
},
1794 {"bsl", 0x2e601c00, 0xbfe0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEB
, F_SIZEQ
},
1795 {"fminnmp", 0x2ea0c400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1796 {"fminnmp", 0x2ec00400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1797 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1798 {"fabd", 0x2ea0d400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1799 {"fabd", 0x2ec01400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1800 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1801 {"fcmgt", 0x2ea0e400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1802 {"fcmgt", 0x2ec02400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1803 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1804 {"facgt", 0x2ea0ec00, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1805 {"facgt", 0x2ec02c00, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1806 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1807 {"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMESD
, F_SIZEQ
},
1808 {"fminp", 0x2ec03400, 0xbfe0fc00, asimdsame
, 0, SIMD_F16
,
1809 OP3 (Vd
, Vn
, Vm
), QL_V3SAMEH
, F_SIZEQ
},
1810 {"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEB
, F_SIZEQ
},
1811 {"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame
, 0, SIMD
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEB
, F_SIZEQ
},
1812 /* AdvSIMD three same extension. */
1813 {"sqrdmlah", 0x2e008400, 0xbf20fe00, asimdsame
, 0, RDMA
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEHS
, F_SIZEQ
},
1814 {"sqrdmlsh", 0x2e008c00, 0xbf20fe00, asimdsame
, 0, RDMA
, OP3 (Vd
, Vn
, Vm
), QL_V3SAMEHS
, F_SIZEQ
},
1815 /* AdvSIMD shift by immediate. */
1816 {"sshr", 0xf000400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT
, 0},
1817 {"ssra", 0xf001400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT
, 0},
1818 {"srshr", 0xf002400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT
, 0},
1819 {"srsra", 0xf003400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT
, 0},
1820 {"shl", 0xf005400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSL
), QL_VSHIFT
, 0},
1821 {"sqshl", 0xf007400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSL
), QL_VSHIFT
, 0},
1822 {"shrn", 0xf008400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN
, 0},
1823 {"shrn2", 0x4f008400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN2
, 0},
1824 {"rshrn", 0xf008c00, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN
, 0},
1825 {"rshrn2", 0x4f008c00, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN2
, 0},
1826 {"sqshrn", 0xf009400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN
, 0},
1827 {"sqshrn2", 0x4f009400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN2
, 0},
1828 {"sqrshrn", 0xf009c00, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN
, 0},
1829 {"sqrshrn2", 0x4f009c00, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN2
, 0},
1830 {"sshll", 0xf00a400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSL
), QL_VSHIFTL
, F_HAS_ALIAS
},
1831 {"sxtl", 0xf00a400, 0xff87fc00, asimdshf
, OP_SXTL
, SIMD
, OP2 (Vd
, Vn
), QL_V2LONGBHS
, F_ALIAS
| F_CONV
},
1832 {"sshll2", 0x4f00a400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSL
), QL_VSHIFTL2
, F_HAS_ALIAS
},
1833 {"sxtl2", 0x4f00a400, 0xff87fc00, asimdshf
, OP_SXTL2
, SIMD
, OP2 (Vd
, Vn
), QL_V2LONGBHS2
, F_ALIAS
| F_CONV
},
1834 {"scvtf", 0xf00e400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT_SD
, 0},
1835 {"fcvtzs", 0xf00fc00, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT_SD
, 0},
1836 {"ushr", 0x2f000400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT
, 0},
1837 {"usra", 0x2f001400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT
, 0},
1838 {"urshr", 0x2f002400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT
, 0},
1839 {"ursra", 0x2f003400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT
, 0},
1840 {"sri", 0x2f004400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT
, 0},
1841 {"sli", 0x2f005400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSL
), QL_VSHIFT
, 0},
1842 {"sqshlu", 0x2f006400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSL
), QL_VSHIFT
, 0},
1843 {"uqshl", 0x2f007400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSL
), QL_VSHIFT
, 0},
1844 {"sqshrun", 0x2f008400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN
, 0},
1845 {"sqshrun2", 0x6f008400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN2
, 0},
1846 {"sqrshrun", 0x2f008c00, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN
, 0},
1847 {"sqrshrun2", 0x6f008c00, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN2
, 0},
1848 {"uqshrn", 0x2f009400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN
, 0},
1849 {"uqshrn2", 0x6f009400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN2
, 0},
1850 {"uqrshrn", 0x2f009c00, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN
, 0},
1851 {"uqrshrn2", 0x6f009c00, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFTN2
, 0},
1852 {"ushll", 0x2f00a400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSL
), QL_VSHIFTL
, F_HAS_ALIAS
},
1853 {"uxtl", 0x2f00a400, 0xff87fc00, asimdshf
, OP_UXTL
, SIMD
, OP2 (Vd
, Vn
), QL_V2LONGBHS
, F_ALIAS
| F_CONV
},
1854 {"ushll2", 0x6f00a400, 0xff80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSL
), QL_VSHIFTL2
, F_HAS_ALIAS
},
1855 {"uxtl2", 0x6f00a400, 0xff87fc00, asimdshf
, OP_UXTL2
, SIMD
, OP2 (Vd
, Vn
), QL_V2LONGBHS2
, F_ALIAS
| F_CONV
},
1856 {"ucvtf", 0x2f00e400, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT_SD
, 0},
1857 {"fcvtzu", 0x2f00fc00, 0xbf80fc00, asimdshf
, 0, SIMD
, OP3 (Vd
, Vn
, IMM_VLSR
), QL_VSHIFT_SD
, 0},
1858 /* AdvSIMD TBL/TBX. */
1859 {"tbl", 0xe000000, 0xbfe09c00, asimdtbl
, 0, SIMD
, OP3 (Vd
, LVn
, Vm
), QL_TABLE
, F_SIZEQ
},
1860 {"tbx", 0xe001000, 0xbfe09c00, asimdtbl
, 0, SIMD
, OP3 (Vd
, LVn
, Vm
), QL_TABLE
, F_SIZEQ
},
1861 /* AdvSIMD scalar three different. */
1862 {"sqdmlal", 0x5e209000, 0xff20fc00, asisddiff
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_SISDL_HS
, F_SSIZE
},
1863 {"sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_SISDL_HS
, F_SSIZE
},
1864 {"sqdmull", 0x5e20d000, 0xff20fc00, asisddiff
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_SISDL_HS
, F_SSIZE
},
1865 /* AdvSIMD scalar x indexed element. */
1866 {"sqdmlal", 0x5f003000, 0xff00f400, asisdelem
, 0, SIMD
, OP3 (Sd
, Sn
, Em
), QL_SISDL_HS
, F_SSIZE
},
1867 {"sqdmlsl", 0x5f007000, 0xff00f400, asisdelem
, 0, SIMD
, OP3 (Sd
, Sn
, Em
), QL_SISDL_HS
, F_SSIZE
},
1868 {"sqdmull", 0x5f00b000, 0xff00f400, asisdelem
, 0, SIMD
, OP3 (Sd
, Sn
, Em
), QL_SISDL_HS
, F_SSIZE
},
1869 {"sqdmulh", 0x5f00c000, 0xff00f400, asisdelem
, 0, SIMD
, OP3 (Sd
, Sn
, Em
), QL_SISD_HS
, F_SSIZE
},
1870 {"sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem
, 0, SIMD
, OP3 (Sd
, Sn
, Em
), QL_SISD_HS
, F_SSIZE
},
1871 {"fmla", 0x5f801000, 0xff80f400, asisdelem
, 0, SIMD
, OP3 (Sd
, Sn
, Em
), QL_FP3
, F_SSIZE
},
1872 {"fmla", 0x5f001000, 0xffc0f400, asisdelem
, 0, SIMD_F16
,
1873 OP3 (Sd
, Sn
, Em
), QL_FP3_H
, F_SSIZE
},
1874 {"fmls", 0x5f805000, 0xff80f400, asisdelem
, 0, SIMD
, OP3 (Sd
, Sn
, Em
), QL_FP3
, F_SSIZE
},
1875 {"fmls", 0x5f005000, 0xffc0f400, asisdelem
, 0, SIMD_F16
,
1876 OP3 (Sd
, Sn
, Em
), QL_FP3_H
, F_SSIZE
},
1877 {"fmul", 0x5f809000, 0xff80f400, asisdelem
, 0, SIMD
, OP3 (Sd
, Sn
, Em
), QL_FP3
, F_SSIZE
},
1878 {"fmul", 0x5f009000, 0xffc0f400, asisdelem
, 0, SIMD_F16
,
1879 OP3 (Sd
, Sn
, Em
), QL_FP3_H
, F_SSIZE
},
1880 {"fmulx", 0x7f809000, 0xff80f400, asisdelem
, 0, SIMD
, OP3 (Sd
, Sn
, Em
), QL_FP3
, F_SSIZE
},
1881 {"fmulx", 0x7f009000, 0xffc0f400, asisdelem
, 0, SIMD_F16
,
1882 OP3 (Sd
, Sn
, Em
), QL_FP3_H
, F_SSIZE
},
1883 {"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem
, 0, RDMA
, OP3 (Sd
, Sn
, Em
), QL_SISD_HS
, F_SSIZE
},
1884 {"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem
, 0, RDMA
, OP3 (Sd
, Sn
, Em
), QL_SISD_HS
, F_SSIZE
},
1885 /* AdvSIMD load/store multiple structures. */
1886 {"st4", 0xc000000, 0xbfff0000, asisdlse
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(4)},
1887 {"st1", 0xc000000, 0xbfff0000, asisdlse
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(1)},
1888 {"st2", 0xc000000, 0xbfff0000, asisdlse
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(2)},
1889 {"st3", 0xc000000, 0xbfff0000, asisdlse
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(3)},
1890 {"ld4", 0xc400000, 0xbfff0000, asisdlse
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(4)},
1891 {"ld1", 0xc400000, 0xbfff0000, asisdlse
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(1)},
1892 {"ld2", 0xc400000, 0xbfff0000, asisdlse
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(2)},
1893 {"ld3", 0xc400000, 0xbfff0000, asisdlse
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(3)},
1894 /* AdvSIMD load/store multiple structures (post-indexed). */
1895 {"st4", 0xc800000, 0xbfe00000, asisdlsep
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_POST
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(4)},
1896 {"st1", 0xc800000, 0xbfe00000, asisdlsep
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_POST
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(1)},
1897 {"st2", 0xc800000, 0xbfe00000, asisdlsep
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_POST
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(2)},
1898 {"st3", 0xc800000, 0xbfe00000, asisdlsep
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_POST
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(3)},
1899 {"ld4", 0xcc00000, 0xbfe00000, asisdlsep
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_POST
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(4)},
1900 {"ld1", 0xcc00000, 0xbfe00000, asisdlsep
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_POST
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(1)},
1901 {"ld2", 0xcc00000, 0xbfe00000, asisdlsep
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_POST
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(2)},
1902 {"ld3", 0xcc00000, 0xbfe00000, asisdlsep
, 0, SIMD
, OP2 (LVt
, SIMD_ADDR_POST
), QL_SIMD_LDST
, F_SIZEQ
| F_OD(3)},
1903 /* AdvSIMD load/store single structure. */
1904 {"st1", 0xd000000, 0xbfff2000, asisdlso
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDSTONE
, F_OD(1)},
1905 {"st3", 0xd002000, 0xbfff2000, asisdlso
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDSTONE
, F_OD(3)},
1906 {"st2", 0xd200000, 0xbfff2000, asisdlso
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDSTONE
, F_OD(2)},
1907 {"st4", 0xd202000, 0xbfff2000, asisdlso
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDSTONE
, F_OD(4)},
1908 {"ld1", 0xd400000, 0xbfff2000, asisdlso
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDSTONE
, F_OD(1)},
1909 {"ld3", 0xd402000, 0xbfff2000, asisdlso
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDSTONE
, F_OD(3)},
1910 {"ld1r", 0xd40c000, 0xbfffe000, asisdlso
, 0, SIMD
, OP2 (LVt_AL
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(1)},
1911 {"ld3r", 0xd40e000, 0xbfffe000, asisdlso
, 0, SIMD
, OP2 (LVt_AL
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(3)},
1912 {"ld2", 0xd600000, 0xbfff2000, asisdlso
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDSTONE
, F_OD(2)},
1913 {"ld4", 0xd602000, 0xbfff2000, asisdlso
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDSTONE
, F_OD(4)},
1914 {"ld2r", 0xd60c000, 0xbfffe000, asisdlso
, 0, SIMD
, OP2 (LVt_AL
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(2)},
1915 {"ld4r", 0xd60e000, 0xbfffe000, asisdlso
, 0, SIMD
, OP2 (LVt_AL
, SIMD_ADDR_SIMPLE
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(4)},
1916 /* AdvSIMD load/store single structure (post-indexed). */
1917 {"st1", 0xd800000, 0xbfe02000, asisdlsop
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_POST
), QL_SIMD_LDSTONE
, F_OD(1)},
1918 {"st3", 0xd802000, 0xbfe02000, asisdlsop
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_POST
), QL_SIMD_LDSTONE
, F_OD(3)},
1919 {"st2", 0xda00000, 0xbfe02000, asisdlsop
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_POST
), QL_SIMD_LDSTONE
, F_OD(2)},
1920 {"st4", 0xda02000, 0xbfe02000, asisdlsop
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_POST
), QL_SIMD_LDSTONE
, F_OD(4)},
1921 {"ld1", 0xdc00000, 0xbfe02000, asisdlsop
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_POST
), QL_SIMD_LDSTONE
, F_OD(1)},
1922 {"ld3", 0xdc02000, 0xbfe02000, asisdlsop
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_POST
), QL_SIMD_LDSTONE
, F_OD(3)},
1923 {"ld1r", 0xdc0c000, 0xbfe0e000, asisdlsop
, 0, SIMD
, OP2 (LVt_AL
, SIMD_ADDR_POST
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(1)},
1924 {"ld3r", 0xdc0e000, 0xbfe0e000, asisdlsop
, 0, SIMD
, OP2 (LVt_AL
, SIMD_ADDR_POST
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(3)},
1925 {"ld2", 0xde00000, 0xbfe02000, asisdlsop
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_POST
), QL_SIMD_LDSTONE
, F_OD(2)},
1926 {"ld4", 0xde02000, 0xbfe02000, asisdlsop
, 0, SIMD
, OP2 (LEt
, SIMD_ADDR_POST
), QL_SIMD_LDSTONE
, F_OD(4)},
1927 {"ld2r", 0xde0c000, 0xbfe0e000, asisdlsop
, 0, SIMD
, OP2 (LVt_AL
, SIMD_ADDR_POST
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(2)},
1928 {"ld4r", 0xde0e000, 0xbfe0e000, asisdlsop
, 0, SIMD
, OP2 (LVt_AL
, SIMD_ADDR_POST
), QL_SIMD_LDST_ANY
, F_SIZEQ
| F_OD(4)},
1929 /* AdvSIMD scalar two-reg misc. */
1930 {"suqadd", 0x5e203800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAME
, F_SSIZE
},
1931 {"sqabs", 0x5e207800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAME
, F_SSIZE
},
1932 {"cmgt", 0x5e208800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, IMM0
), QL_SISD_CMP_0
, F_SSIZE
},
1933 {"cmeq", 0x5e209800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, IMM0
), QL_SISD_CMP_0
, F_SSIZE
},
1934 {"cmlt", 0x5e20a800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, IMM0
), QL_SISD_CMP_0
, F_SSIZE
},
1935 {"abs", 0x5e20b800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_2SAMED
, F_SSIZE
},
1936 {"sqxtn", 0x5e214800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_SISD_NARROW
, F_SSIZE
},
1937 {"fcvtns", 0x5e21a800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1938 {"fcvtns", 0x5e79a800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1939 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1940 {"fcvtms", 0x5e21b800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1941 {"fcvtms", 0x5e79b800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1942 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1943 {"fcvtas", 0x5e21c800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1944 {"fcvtas", 0x5e79c800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1945 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1946 {"scvtf", 0x5e21d800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1947 {"scvtf", 0x5e79d800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1948 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1949 {"fcmgt", 0x5ea0c800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_0
, F_SSIZE
},
1950 {"fcmgt", 0x5ef8c800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1951 OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_H_0
, F_SSIZE
},
1952 {"fcmeq", 0x5ea0d800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_0
, F_SSIZE
},
1953 {"fcmeq", 0x5ef8d800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1954 OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_H_0
, F_SSIZE
},
1955 {"fcmlt", 0x5ea0e800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_0
, F_SSIZE
},
1956 {"fcmlt", 0x5ef8e800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1957 OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_H_0
, F_SSIZE
},
1958 {"fcvtps", 0x5ea1a800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1959 {"fcvtps", 0x5ef9a800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1960 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1961 {"fcvtzs", 0x5ea1b800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1962 {"fcvtzs", 0x5ef9b800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1963 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1964 {"frecpe", 0x5ea1d800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1965 {"frecpe", 0x5ef9d800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1966 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1967 {"frecpx", 0x5ea1f800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1968 {"frecpx", 0x5ef9f800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1969 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1970 {"usqadd", 0x7e203800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAME
, F_SSIZE
},
1971 {"sqneg", 0x7e207800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAME
, F_SSIZE
},
1972 {"cmge", 0x7e208800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, IMM0
), QL_SISD_CMP_0
, F_SSIZE
},
1973 {"cmle", 0x7e209800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, IMM0
), QL_SISD_CMP_0
, F_SSIZE
},
1974 {"neg", 0x7e20b800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_2SAMED
, F_SSIZE
},
1975 {"sqxtun", 0x7e212800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_SISD_NARROW
, F_SSIZE
},
1976 {"uqxtn", 0x7e214800, 0xff3ffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_SISD_NARROW
, F_SSIZE
},
1977 {"fcvtxn", 0x7e216800, 0xffbffc00, asisdmisc
, OP_FCVTXN_S
, SIMD
, OP2 (Sd
, Sn
), QL_SISD_NARROW_S
, F_MISC
},
1978 {"fcvtnu", 0x7e21a800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1979 {"fcvtnu", 0x7e79a800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1980 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1981 {"fcvtmu", 0x7e21b800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1982 {"fcvtmu", 0x7e79b800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1983 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1984 {"fcvtau", 0x7e21c800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1985 {"fcvtau", 0x7e79c800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1986 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1987 {"ucvtf", 0x7e21d800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1988 {"ucvtf", 0x7e79d800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1989 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
1990 {"fcmge", 0x7ea0c800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_0
, F_SSIZE
},
1991 {"fcmge", 0x7ef8c800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1992 OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_H_0
, F_SSIZE
},
1993 {"fcmle", 0x7ea0d800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_0
, F_SSIZE
},
1994 {"fcmle", 0x7ef8d800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1995 OP3 (Sd
, Sn
, FPIMM0
), QL_SISD_FCMP_H_0
, F_SSIZE
},
1996 {"fcvtpu", 0x7ea1a800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
1997 {"fcvtpu", 0x7ef9a800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
1998 OP2 (Sd
, Sn
), QL_SISD_FCMP_H_0
, F_SSIZE
},
1999 {"fcvtzu", 0x7ea1b800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
2000 {"fcvtzu", 0x7ef9b800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
2001 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
2002 {"frsqrte", 0x7ea1d800, 0xffbffc00, asisdmisc
, 0, SIMD
, OP2 (Sd
, Sn
), QL_S_2SAMESD
, F_SSIZE
},
2003 {"frsqrte", 0x7ef9d800, 0xfffffc00, asisdmisc
, 0, SIMD_F16
,
2004 OP2 (Sd
, Sn
), QL_S_2SAMEH
, F_SSIZE
},
2005 /* AdvSIMD scalar copy. */
2006 {"dup", 0x5e000400, 0xffe0fc00, asisdone
, 0, SIMD
, OP2 (Sd
, En
), QL_S_2SAME
, F_HAS_ALIAS
},
2007 {"mov", 0x5e000400, 0xffe0fc00, asisdone
, 0, SIMD
, OP2 (Sd
, En
), QL_S_2SAME
, F_ALIAS
},
2008 /* AdvSIMD scalar pairwise. */
2009 {"addp", 0x5e31b800, 0xff3ffc00, asisdpair
, 0, SIMD
, OP2 (Sd
, Vn
), QL_SISD_PAIR_D
, F_SIZEQ
},
2010 {"fmaxnmp", 0x7e30c800, 0xffbffc00, asisdpair
, 0, SIMD
, OP2 (Sd
, Vn
), QL_SISD_PAIR
, F_SIZEQ
},
2011 {"faddp", 0x7e30d800, 0xffbffc00, asisdpair
, 0, SIMD
, OP2 (Sd
, Vn
), QL_SISD_PAIR
, F_SIZEQ
},
2012 {"fmaxp", 0x7e30f800, 0xffbffc00, asisdpair
, 0, SIMD
, OP2 (Sd
, Vn
), QL_SISD_PAIR
, F_SIZEQ
},
2013 {"fminnmp", 0x7eb0c800, 0xffbffc00, asisdpair
, 0, SIMD
, OP2 (Sd
, Vn
), QL_SISD_PAIR
, F_SIZEQ
},
2014 {"fminp", 0x7eb0f800, 0xffbffc00, asisdpair
, 0, SIMD
, OP2 (Sd
, Vn
), QL_SISD_PAIR
, F_SIZEQ
},
2015 /* AdvSIMD scalar three same. */
2016 {"sqadd", 0x5e200c00, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAME
, F_SSIZE
},
2017 {"sqsub", 0x5e202c00, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAME
, F_SSIZE
},
2018 {"sqshl", 0x5e204c00, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAME
, F_SSIZE
},
2019 {"sqrshl", 0x5e205c00, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAME
, F_SSIZE
},
2020 {"sqdmulh", 0x5e20b400, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_SISD_HS
, F_SSIZE
},
2021 {"fmulx", 0x5e20dc00, 0xffa0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_FP3
, F_SSIZE
},
2022 {"fmulx", 0x5e401c00, 0xffe0fc00, asisdsame
, 0, SIMD_F16
,
2023 OP3 (Sd
, Sn
, Sm
), QL_FP3_H
, F_SSIZE
},
2024 {"fcmeq", 0x5e20e400, 0xffa0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_FP3
, F_SSIZE
},
2025 {"fcmeq", 0x5e402400, 0xffe0fc00, asisdsame
, 0, SIMD_F16
,
2026 OP3 (Sd
, Sn
, Sm
), QL_FP3_H
, F_SSIZE
},
2027 {"frecps", 0x5e20fc00, 0xffa0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_FP3
, F_SSIZE
},
2028 {"frecps", 0x5e403c00, 0xffe0fc00, asisdsame
, 0, SIMD_F16
,
2029 OP3 (Sd
, Sn
, Sm
), QL_FP3_H
, F_SSIZE
},
2030 {"frsqrts", 0x5ea0fc00, 0xffa0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_FP3
, F_SSIZE
},
2031 {"frsqrts", 0x5ec03c00, 0xffe0fc00, asisdsame
, 0, SIMD_F16
,
2032 OP3 (Sd
, Sn
, Sm
), QL_FP3_H
, F_SSIZE
},
2033 {"cmgt", 0x5ee03400, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2034 {"cmge", 0x5ee03c00, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2035 {"sshl", 0x5ee04400, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2036 {"srshl", 0x5ee05400, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2037 {"add", 0x5ee08400, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2038 {"cmtst", 0x5ee08c00, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2039 {"uqadd", 0x7e200c00, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAME
, F_SSIZE
},
2040 {"uqsub", 0x7e202c00, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAME
, F_SSIZE
},
2041 {"uqshl", 0x7e204c00, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAME
, F_SSIZE
},
2042 {"uqrshl", 0x7e205c00, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAME
, F_SSIZE
},
2043 {"sqrdmulh", 0x7e20b400, 0xff20fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_SISD_HS
, F_SSIZE
},
2044 {"fcmge", 0x7e20e400, 0xffa0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_FP3
, F_SSIZE
},
2045 {"fcmge", 0x7e402400, 0xffe0fc00, asisdsame
, 0, SIMD_F16
,
2046 OP3 (Sd
, Sn
, Sm
), QL_FP3_H
, F_SSIZE
},
2047 {"facge", 0x7e20ec00, 0xffa0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_FP3
, F_SSIZE
},
2048 {"facge", 0x7e402c00, 0xffe0fc00, asisdsame
, 0, SIMD_F16
,
2049 OP3 (Sd
, Sn
, Sm
), QL_FP3_H
, F_SSIZE
},
2050 {"fabd", 0x7ea0d400, 0xffa0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_FP3
, F_SSIZE
},
2051 {"fabd", 0x7ec01400, 0xffe0fc00, asisdsame
, 0, SIMD_F16
,
2052 OP3 (Sd
, Sn
, Sm
), QL_FP3_H
, F_SSIZE
},
2053 {"fcmgt", 0x7ea0e400, 0xffa0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_FP3
, F_SSIZE
},
2054 {"fcmgt", 0x7ec02400, 0xffe0fc00, asisdsame
, 0, SIMD_F16
,
2055 OP3 (Sd
, Sn
, Sm
), QL_FP3_H
, F_SSIZE
},
2056 {"facgt", 0x7ea0ec00, 0xffa0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_FP3
, F_SSIZE
},
2057 {"facgt", 0x7ec02c00, 0xffe0fc00, asisdsame
, 0, SIMD_F16
,
2058 OP3 (Sd
, Sn
, Sm
), QL_FP3_H
, F_SSIZE
},
2059 {"cmhi", 0x7ee03400, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2060 {"cmhs", 0x7ee03c00, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2061 {"ushl", 0x7ee04400, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2062 {"urshl", 0x7ee05400, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2063 {"sub", 0x7ee08400, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2064 {"cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame
, 0, SIMD
, OP3 (Sd
, Sn
, Sm
), QL_S_3SAMED
, F_SSIZE
},
2065 /* AdvSIMDs scalar three same extension. */
2066 {"sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame
, 0, RDMA
, OP3 (Sd
, Sn
, Sm
), QL_SISD_HS
, F_SSIZE
},
2067 {"sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame
, 0, RDMA
, OP3 (Sd
, Sn
, Sm
), QL_SISD_HS
, F_SSIZE
},
2068 /* AdvSIMD scalar shift by immediate. */
2069 {"sshr", 0x5f000400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_D
, 0},
2070 {"ssra", 0x5f001400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_D
, 0},
2071 {"srshr", 0x5f002400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_D
, 0},
2072 {"srsra", 0x5f003400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_D
, 0},
2073 {"shl", 0x5f005400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSL
), QL_SSHIFT_D
, 0},
2074 {"sqshl", 0x5f007400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSL
), QL_SSHIFT
, 0},
2075 {"sqshrn", 0x5f009400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFTN
, 0},
2076 {"sqrshrn", 0x5f009c00, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFTN
, 0},
2077 {"scvtf", 0x5f00e400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_SD
, 0},
2078 {"fcvtzs", 0x5f00fc00, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_SD
, 0},
2079 {"ushr", 0x7f000400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_D
, 0},
2080 {"usra", 0x7f001400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_D
, 0},
2081 {"urshr", 0x7f002400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_D
, 0},
2082 {"ursra", 0x7f003400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_D
, 0},
2083 {"sri", 0x7f004400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_D
, 0},
2084 {"sli", 0x7f005400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSL
), QL_SSHIFT_D
, 0},
2085 {"sqshlu", 0x7f006400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSL
), QL_SSHIFT
, 0},
2086 {"uqshl", 0x7f007400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSL
), QL_SSHIFT
, 0},
2087 {"sqshrun", 0x7f008400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFTN
, 0},
2088 {"sqrshrun", 0x7f008c00, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFTN
, 0},
2089 {"uqshrn", 0x7f009400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFTN
, 0},
2090 {"uqrshrn", 0x7f009c00, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFTN
, 0},
2091 {"ucvtf", 0x7f00e400, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_SD
, 0},
2092 {"fcvtzu", 0x7f00fc00, 0xff80fc00, asisdshf
, 0, SIMD
, OP3 (Sd
, Sn
, IMM_VLSR
), QL_SSHIFT_SD
, 0},
2094 {"sbfm", 0x13000000, 0x7f800000, bitfield
, 0, CORE
, OP4 (Rd
, Rn
, IMMR
, IMMS
), QL_BF
, F_HAS_ALIAS
| F_SF
| F_N
},
2095 {"sbfiz", 0x13000000, 0x7f800000, bitfield
, OP_SBFIZ
, CORE
, OP4 (Rd
, Rn
, IMM
, WIDTH
), QL_BF2
, F_ALIAS
| F_P1
| F_CONV
},
2096 {"sbfx", 0x13000000, 0x7f800000, bitfield
, OP_SBFX
, CORE
, OP4 (Rd
, Rn
, IMM
, WIDTH
), QL_BF2
, F_ALIAS
| F_P1
| F_CONV
},
2097 {"sxtb", 0x13001c00, 0x7fbffc00, bitfield
, 0, CORE
, OP2 (Rd
, Rn
), QL_EXT
, F_ALIAS
| F_P3
| F_SF
| F_N
},
2098 {"sxth", 0x13003c00, 0x7fbffc00, bitfield
, 0, CORE
, OP2 (Rd
, Rn
), QL_EXT
, F_ALIAS
| F_P3
| F_SF
| F_N
},
2099 {"sxtw", 0x93407c00, 0xfffffc00, bitfield
, 0, CORE
, OP2 (Rd
, Rn
), QL_EXT_W
, F_ALIAS
| F_P3
},
2100 {"asr", 0x13000000, 0x7f800000, bitfield
, OP_ASR_IMM
, CORE
, OP3 (Rd
, Rn
, IMM
), QL_SHIFT
, F_ALIAS
| F_P2
| F_CONV
},
2101 {"bfm", 0x33000000, 0x7f800000, bitfield
, 0, CORE
, OP4 (Rd
, Rn
, IMMR
, IMMS
), QL_BF
, F_HAS_ALIAS
| F_SF
| F_N
},
2102 {"bfi", 0x33000000, 0x7f800000, bitfield
, OP_BFI
, CORE
, OP4 (Rd
, Rn
, IMM
, WIDTH
), QL_BF2
, F_ALIAS
| F_P1
| F_CONV
},
2103 {"bfc", 0x330003e0, 0x7f8003e0, bitfield
, OP_BFC
, ARMV8_2
,
2104 OP3 (Rd
, IMM
, WIDTH
), QL_BF1
, F_ALIAS
| F_P2
| F_CONV
},
2105 {"bfxil", 0x33000000, 0x7f800000, bitfield
, OP_BFXIL
, CORE
, OP4 (Rd
, Rn
, IMM
, WIDTH
), QL_BF2
, F_ALIAS
| F_P1
| F_CONV
},
2106 {"ubfm", 0x53000000, 0x7f800000, bitfield
, 0, CORE
, OP4 (Rd
, Rn
, IMMR
, IMMS
), QL_BF
, F_HAS_ALIAS
| F_SF
| F_N
},
2107 {"ubfiz", 0x53000000, 0x7f800000, bitfield
, OP_UBFIZ
, CORE
, OP4 (Rd
, Rn
, IMM
, WIDTH
), QL_BF2
, F_ALIAS
| F_P1
| F_CONV
},
2108 {"ubfx", 0x53000000, 0x7f800000, bitfield
, OP_UBFX
, CORE
, OP4 (Rd
, Rn
, IMM
, WIDTH
), QL_BF2
, F_ALIAS
| F_P1
| F_CONV
},
2109 {"uxtb", 0x53001c00, 0xfffffc00, bitfield
, OP_UXTB
, CORE
, OP2 (Rd
, Rn
), QL_I2SAMEW
, F_ALIAS
| F_P3
},
2110 {"uxth", 0x53003c00, 0xfffffc00, bitfield
, OP_UXTH
, CORE
, OP2 (Rd
, Rn
), QL_I2SAMEW
, F_ALIAS
| F_P3
},
2111 {"lsl", 0x53000000, 0x7f800000, bitfield
, OP_LSL_IMM
, CORE
, OP3 (Rd
, Rn
, IMM
), QL_SHIFT
, F_ALIAS
| F_P2
| F_CONV
},
2112 {"lsr", 0x53000000, 0x7f800000, bitfield
, OP_LSR_IMM
, CORE
, OP3 (Rd
, Rn
, IMM
), QL_SHIFT
, F_ALIAS
| F_P2
| F_CONV
},
2113 /* Unconditional branch (immediate). */
2114 {"b", 0x14000000, 0xfc000000, branch_imm
, OP_B
, CORE
, OP1 (ADDR_PCREL26
), QL_PCREL_26
, 0},
2115 {"bl", 0x94000000, 0xfc000000, branch_imm
, OP_BL
, CORE
, OP1 (ADDR_PCREL26
), QL_PCREL_26
, 0},
2116 /* Unconditional branch (register). */
2117 {"br", 0xd61f0000, 0xfffffc1f, branch_reg
, 0, CORE
, OP1 (Rn
), QL_I1X
, 0},
2118 {"blr", 0xd63f0000, 0xfffffc1f, branch_reg
, 0, CORE
, OP1 (Rn
), QL_I1X
, 0},
2119 {"ret", 0xd65f0000, 0xfffffc1f, branch_reg
, 0, CORE
, OP1 (Rn
), QL_I1X
, F_OPD0_OPT
| F_DEFAULT (30)},
2120 {"eret", 0xd69f03e0, 0xffffffff, branch_reg
, 0, CORE
, OP0 (), {}, 0},
2121 {"drps", 0xd6bf03e0, 0xffffffff, branch_reg
, 0, CORE
, OP0 (), {}, 0},
2122 /* Compare & branch (immediate). */
2123 {"cbz", 0x34000000, 0x7f000000, compbranch
, 0, CORE
, OP2 (Rt
, ADDR_PCREL19
), QL_R_PCREL
, F_SF
},
2124 {"cbnz", 0x35000000, 0x7f000000, compbranch
, 0, CORE
, OP2 (Rt
, ADDR_PCREL19
), QL_R_PCREL
, F_SF
},
2125 /* Conditional branch (immediate). */
2126 {"b.c", 0x54000000, 0xff000010, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_COND
},
2127 /* Conditional compare (immediate). */
2128 {"ccmn", 0x3a400800, 0x7fe00c10, condcmp_imm
, 0, CORE
, OP4 (Rn
, CCMP_IMM
, NZCV
, COND
), QL_CCMP_IMM
, F_SF
},
2129 {"ccmp", 0x7a400800, 0x7fe00c10, condcmp_imm
, 0, CORE
, OP4 (Rn
, CCMP_IMM
, NZCV
, COND
), QL_CCMP_IMM
, F_SF
},
2130 /* Conditional compare (register). */
2131 {"ccmn", 0x3a400000, 0x7fe00c10, condcmp_reg
, 0, CORE
, OP4 (Rn
, Rm
, NZCV
, COND
), QL_CCMP
, F_SF
},
2132 {"ccmp", 0x7a400000, 0x7fe00c10, condcmp_reg
, 0, CORE
, OP4 (Rn
, Rm
, NZCV
, COND
), QL_CCMP
, F_SF
},
2133 /* Conditional select. */
2134 {"csel", 0x1a800000, 0x7fe00c00, condsel
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, COND
), QL_CSEL
, F_SF
},
2135 {"csinc", 0x1a800400, 0x7fe00c00, condsel
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, COND
), QL_CSEL
, F_HAS_ALIAS
| F_SF
},
2136 {"cinc", 0x1a800400, 0x7fe00c00, condsel
, OP_CINC
, CORE
, OP3 (Rd
, Rn
, COND1
), QL_CSEL
, F_ALIAS
| F_SF
| F_CONV
},
2137 {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel
, OP_CSET
, CORE
, OP2 (Rd
, COND1
), QL_DST_R
, F_ALIAS
| F_P1
| F_SF
| F_CONV
},
2138 {"csinv", 0x5a800000, 0x7fe00c00, condsel
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, COND
), QL_CSEL
, F_HAS_ALIAS
| F_SF
},
2139 {"cinv", 0x5a800000, 0x7fe00c00, condsel
, OP_CINV
, CORE
, OP3 (Rd
, Rn
, COND1
), QL_CSEL
, F_ALIAS
| F_SF
| F_CONV
},
2140 {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel
, OP_CSETM
, CORE
, OP2 (Rd
, COND1
), QL_DST_R
, F_ALIAS
| F_P1
| F_SF
| F_CONV
},
2141 {"csneg", 0x5a800400, 0x7fe00c00, condsel
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, COND
), QL_CSEL
, F_HAS_ALIAS
| F_SF
},
2142 {"cneg", 0x5a800400, 0x7fe00c00, condsel
, OP_CNEG
, CORE
, OP3 (Rd
, Rn
, COND1
), QL_CSEL
, F_ALIAS
| F_SF
| F_CONV
},
2144 {"aese", 0x4e284800, 0xfffffc00, cryptoaes
, 0, CRYPTO
, OP2 (Vd
, Vn
), QL_V2SAME16B
, 0},
2145 {"aesd", 0x4e285800, 0xfffffc00, cryptoaes
, 0, CRYPTO
, OP2 (Vd
, Vn
), QL_V2SAME16B
, 0},
2146 {"aesmc", 0x4e286800, 0xfffffc00, cryptoaes
, 0, CRYPTO
, OP2 (Vd
, Vn
), QL_V2SAME16B
, 0},
2147 {"aesimc", 0x4e287800, 0xfffffc00, cryptoaes
, 0, CRYPTO
, OP2 (Vd
, Vn
), QL_V2SAME16B
, 0},
2148 /* Crypto two-reg SHA. */
2149 {"sha1h", 0x5e280800, 0xfffffc00, cryptosha2
, 0, CRYPTO
, OP2 (Fd
, Fn
), QL_2SAMES
, 0},
2150 {"sha1su1", 0x5e281800, 0xfffffc00, cryptosha2
, 0, CRYPTO
, OP2 (Vd
, Vn
), QL_V2SAME4S
, 0},
2151 {"sha256su0", 0x5e282800, 0xfffffc00, cryptosha2
, 0, CRYPTO
, OP2 (Vd
, Vn
), QL_V2SAME4S
, 0},
2152 /* Crypto three-reg SHA. */
2153 {"sha1c", 0x5e000000, 0xffe0fc00, cryptosha3
, 0, CRYPTO
, OP3 (Fd
, Fn
, Vm
), QL_SHAUPT
, 0},
2154 {"sha1p", 0x5e001000, 0xffe0fc00, cryptosha3
, 0, CRYPTO
, OP3 (Fd
, Fn
, Vm
), QL_SHAUPT
, 0},
2155 {"sha1m", 0x5e002000, 0xffe0fc00, cryptosha3
, 0, CRYPTO
, OP3 (Fd
, Fn
, Vm
), QL_SHAUPT
, 0},
2156 {"sha1su0", 0x5e003000, 0xffe0fc00, cryptosha3
, 0, CRYPTO
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME4S
, 0},
2157 {"sha256h", 0x5e004000, 0xffe0fc00, cryptosha3
, 0, CRYPTO
, OP3 (Fd
, Fn
, Vm
), QL_SHA256UPT
, 0},
2158 {"sha256h2", 0x5e005000, 0xffe0fc00, cryptosha3
, 0, CRYPTO
, OP3 (Fd
, Fn
, Vm
), QL_SHA256UPT
, 0},
2159 {"sha256su1", 0x5e006000, 0xffe0fc00, cryptosha3
, 0, CRYPTO
, OP3 (Vd
, Vn
, Vm
), QL_V3SAME4S
, 0},
2160 /* Data-processing (1 source). */
2161 {"rbit", 0x5ac00000, 0x7ffffc00, dp_1src
, 0, CORE
, OP2 (Rd
, Rn
), QL_I2SAME
, F_SF
},
2162 {"rev16", 0x5ac00400, 0x7ffffc00, dp_1src
, 0, CORE
, OP2 (Rd
, Rn
), QL_I2SAME
, F_SF
},
2163 {"rev", 0x5ac00800, 0xfffffc00, dp_1src
, 0, CORE
, OP2 (Rd
, Rn
), QL_I2SAMEW
, 0},
2164 {"rev", 0xdac00c00, 0xfffffc00, dp_1src
, 0, CORE
,
2165 OP2 (Rd
, Rn
), QL_I2SAMEX
, F_SF
| F_HAS_ALIAS
| F_P1
},
2166 {"rev64", 0xdac00c00, 0xfffffc00, dp_1src
, 0, ARMV8_2
,
2167 OP2 (Rd
, Rn
), QL_I2SAMEX
, F_SF
| F_ALIAS
},
2168 {"clz", 0x5ac01000, 0x7ffffc00, dp_1src
, 0, CORE
, OP2 (Rd
, Rn
), QL_I2SAME
, F_SF
},
2169 {"cls", 0x5ac01400, 0x7ffffc00, dp_1src
, 0, CORE
, OP2 (Rd
, Rn
), QL_I2SAME
, F_SF
},
2170 {"rev32", 0xdac00800, 0xfffffc00, dp_1src
, 0, CORE
, OP2 (Rd
, Rn
), QL_I2SAMEX
, 0},
2171 /* Data-processing (2 source). */
2172 {"udiv", 0x1ac00800, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
},
2173 {"sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
},
2174 {"lslv", 0x1ac02000, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
| F_HAS_ALIAS
},
2175 {"lsl", 0x1ac02000, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
| F_ALIAS
},
2176 {"lsrv", 0x1ac02400, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
| F_HAS_ALIAS
},
2177 {"lsr", 0x1ac02400, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
| F_ALIAS
},
2178 {"asrv", 0x1ac02800, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
| F_HAS_ALIAS
},
2179 {"asr", 0x1ac02800, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
| F_ALIAS
},
2180 {"rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
| F_HAS_ALIAS
},
2181 {"ror", 0x1ac02c00, 0x7fe0fc00, dp_2src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_SF
| F_ALIAS
},
2182 /* CRC instructions. */
2183 {"crc32b", 0x1ac04000, 0xffe0fc00, dp_2src
, 0, CRC
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEW
, 0},
2184 {"crc32h", 0x1ac04400, 0xffe0fc00, dp_2src
, 0, CRC
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEW
, 0},
2185 {"crc32w", 0x1ac04800, 0xffe0fc00, dp_2src
, 0, CRC
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEW
, 0},
2186 {"crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src
, 0, CRC
, OP3 (Rd
, Rn
, Rm
), QL_I3WWX
, 0},
2187 {"crc32cb", 0x1ac05000, 0xffe0fc00, dp_2src
, 0, CRC
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEW
, 0},
2188 {"crc32ch", 0x1ac05400, 0xffe0fc00, dp_2src
, 0, CRC
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEW
, 0},
2189 {"crc32cw", 0x1ac05800, 0xffe0fc00, dp_2src
, 0, CRC
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEW
, 0},
2190 {"crc32cx", 0x9ac05c00, 0xffe0fc00, dp_2src
, 0, CRC
, OP3 (Rd
, Rn
, Rm
), QL_I3WWX
, 0},
2191 /* Data-processing (3 source). */
2192 {"madd", 0x1b000000, 0x7fe08000, dp_3src
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, Ra
), QL_I4SAMER
, F_HAS_ALIAS
| F_SF
},
2193 {"mul", 0x1b007c00, 0x7fe0fc00, dp_3src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_ALIAS
| F_SF
},
2194 {"msub", 0x1b008000, 0x7fe08000, dp_3src
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, Ra
), QL_I4SAMER
, F_HAS_ALIAS
| F_SF
},
2195 {"mneg", 0x1b00fc00, 0x7fe0fc00, dp_3src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMER
, F_ALIAS
| F_SF
},
2196 {"smaddl", 0x9b200000, 0xffe08000, dp_3src
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, Ra
), QL_I4SAMEL
, F_HAS_ALIAS
},
2197 {"smull", 0x9b207c00, 0xffe0fc00, dp_3src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEL
, F_ALIAS
},
2198 {"smsubl", 0x9b208000, 0xffe08000, dp_3src
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, Ra
), QL_I4SAMEL
, F_HAS_ALIAS
},
2199 {"smnegl", 0x9b20fc00, 0xffe0fc00, dp_3src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEL
, F_ALIAS
},
2200 {"smulh", 0x9b407c00, 0xffe08000, dp_3src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEX
, 0},
2201 {"umaddl", 0x9ba00000, 0xffe08000, dp_3src
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, Ra
), QL_I4SAMEL
, F_HAS_ALIAS
},
2202 {"umull", 0x9ba07c00, 0xffe0fc00, dp_3src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEL
, F_ALIAS
},
2203 {"umsubl", 0x9ba08000, 0xffe08000, dp_3src
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, Ra
), QL_I4SAMEL
, F_HAS_ALIAS
},
2204 {"umnegl", 0x9ba0fc00, 0xffe0fc00, dp_3src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEL
, F_ALIAS
},
2205 {"umulh", 0x9bc07c00, 0xffe08000, dp_3src
, 0, CORE
, OP3 (Rd
, Rn
, Rm
), QL_I3SAMEX
, 0},
2206 /* Excep'n generation. */
2207 {"svc", 0xd4000001, 0xffe0001f, exception
, 0, CORE
, OP1 (EXCEPTION
), {}, 0},
2208 {"hvc", 0xd4000002, 0xffe0001f, exception
, 0, CORE
, OP1 (EXCEPTION
), {}, 0},
2209 {"smc", 0xd4000003, 0xffe0001f, exception
, 0, CORE
, OP1 (EXCEPTION
), {}, 0},
2210 {"brk", 0xd4200000, 0xffe0001f, exception
, 0, CORE
, OP1 (EXCEPTION
), {}, 0},
2211 {"hlt", 0xd4400000, 0xffe0001f, exception
, 0, CORE
, OP1 (EXCEPTION
), {}, 0},
2212 {"dcps1", 0xd4a00001, 0xffe0001f, exception
, 0, CORE
, OP1 (EXCEPTION
), {}, F_OPD0_OPT
| F_DEFAULT (0)},
2213 {"dcps2", 0xd4a00002, 0xffe0001f, exception
, 0, CORE
, OP1 (EXCEPTION
), {}, F_OPD0_OPT
| F_DEFAULT (0)},
2214 {"dcps3", 0xd4a00003, 0xffe0001f, exception
, 0, CORE
, OP1 (EXCEPTION
), {}, F_OPD0_OPT
| F_DEFAULT (0)},
2216 {"extr", 0x13800000, 0x7fa00000, extract
, 0, CORE
, OP4 (Rd
, Rn
, Rm
, IMMS
), QL_EXTR
, F_HAS_ALIAS
| F_SF
| F_N
},
2217 {"ror", 0x13800000, 0x7fa00000, extract
, OP_ROR_IMM
, CORE
, OP3 (Rd
, Rm
, IMMS
), QL_SHIFT
, F_ALIAS
| F_CONV
},
2218 /* Floating-point<->fixed-point conversions. */
2219 {"scvtf", 0x1e020000, 0x7f3f0000, float2fix
, 0, FP
, OP3 (Fd
, Rn
, FBITS
), QL_FIX2FP
, F_FPTYPE
| F_SF
},
2220 {"scvtf", 0x1ec20000, 0x7f3f0000, float2fix
, 0, FP_F16
,
2221 OP3 (Fd
, Rn
, FBITS
), QL_FIX2FP_H
, F_FPTYPE
| F_SF
},
2222 {"ucvtf", 0x1e030000, 0x7f3f0000, float2fix
, 0, FP
, OP3 (Fd
, Rn
, FBITS
), QL_FIX2FP
, F_FPTYPE
| F_SF
},
2223 {"ucvtf", 0x1ec30000, 0x7f3f0000, float2fix
, 0, FP_F16
,
2224 OP3 (Fd
, Rn
, FBITS
), QL_FIX2FP_H
, F_FPTYPE
| F_SF
},
2225 {"fcvtzs", 0x1e180000, 0x7f3f0000, float2fix
, 0, FP
, OP3 (Rd
, Fn
, FBITS
), QL_FP2FIX
, F_FPTYPE
| F_SF
},
2226 {"fcvtzs", 0x1ed80000, 0x7f3f0000, float2fix
, 0, FP_F16
,
2227 OP3 (Rd
, Fn
, FBITS
), QL_FP2FIX_H
, F_FPTYPE
| F_SF
},
2228 {"fcvtzu", 0x1e190000, 0x7f3f0000, float2fix
, 0, FP
, OP3 (Rd
, Fn
, FBITS
), QL_FP2FIX
, F_FPTYPE
| F_SF
},
2229 {"fcvtzu", 0x1ed90000, 0x7f3f0000, float2fix
, 0, FP_F16
,
2230 OP3 (Rd
, Fn
, FBITS
), QL_FP2FIX_H
, F_FPTYPE
| F_SF
},
2231 /* Floating-point<->integer conversions. */
2232 {"fcvtns", 0x1e200000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2233 {"fcvtns", 0x1ee00000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2234 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2235 {"fcvtnu", 0x1e210000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2236 {"fcvtnu", 0x1ee10000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2237 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2238 {"scvtf", 0x1e220000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Fd
, Rn
), QL_INT2FP
, F_FPTYPE
| F_SF
},
2239 {"scvtf", 0x1ee20000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2240 OP2 (Fd
, Rn
), QL_INT2FP_H
, F_FPTYPE
| F_SF
},
2241 {"ucvtf", 0x1e230000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Fd
, Rn
), QL_INT2FP
, F_FPTYPE
| F_SF
},
2242 {"ucvtf", 0x1ee30000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2243 OP2 (Fd
, Rn
), QL_INT2FP_H
, F_FPTYPE
| F_SF
},
2244 {"fcvtas", 0x1e240000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2245 {"fcvtas", 0x1ee40000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2246 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2247 {"fcvtau", 0x1e250000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2248 {"fcvtau", 0x1ee50000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2249 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2250 {"fmov", 0x1e260000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2251 {"fmov", 0x1ee60000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2252 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2253 {"fmov", 0x1e270000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Fd
, Rn
), QL_INT2FP
, F_FPTYPE
| F_SF
},
2254 {"fmov", 0x1ee70000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2255 OP2 (Fd
, Rn
), QL_INT2FP_H
, F_FPTYPE
| F_SF
},
2256 {"fcvtps", 0x1e280000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2257 {"fcvtps", 0x1ee80000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2258 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2259 {"fcvtpu", 0x1e290000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2260 {"fcvtpu", 0x1ee90000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2261 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2262 {"fcvtms", 0x1e300000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2263 {"fcvtms", 0x1ef00000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2264 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2265 {"fcvtmu", 0x1e310000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2266 {"fcvtmu", 0x1ef10000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2267 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2268 {"fcvtzs", 0x1e380000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2269 {"fcvtzs", 0x1ef80000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2270 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2271 {"fcvtzu", 0x1e390000, 0x7f3ffc00, float2int
, 0, FP
, OP2 (Rd
, Fn
), QL_FP2INT
, F_FPTYPE
| F_SF
},
2272 {"fcvtzu", 0x1ef90000, 0x7f3ffc00, float2int
, 0, FP_F16
,
2273 OP2 (Rd
, Fn
), QL_FP2INT_H
, F_FPTYPE
| F_SF
},
2274 {"fmov", 0x9eae0000, 0xfffffc00, float2int
, 0, FP
, OP2 (Rd
, VnD1
), QL_XVD1
, 0},
2275 {"fmov", 0x9eaf0000, 0xfffffc00, float2int
, 0, FP
, OP2 (VdD1
, Rn
), QL_VD1X
, 0},
2276 /* Floating-point conditional compare. */
2277 {"fccmp", 0x1e200400, 0xff200c10, floatccmp
, 0, FP
, OP4 (Fn
, Fm
, NZCV
, COND
), QL_FCCMP
, F_FPTYPE
},
2278 {"fccmp", 0x1ee00400, 0xff200c10, floatccmp
, 0, FP_F16
,
2279 OP4 (Fn
, Fm
, NZCV
, COND
), QL_FCCMP_H
, F_FPTYPE
},
2280 {"fccmpe", 0x1e200410, 0xff200c10, floatccmp
, 0, FP
, OP4 (Fn
, Fm
, NZCV
, COND
), QL_FCCMP
, F_FPTYPE
},
2281 {"fccmpe", 0x1ee00410, 0xff200c10, floatccmp
, 0, FP_F16
,
2282 OP4 (Fn
, Fm
, NZCV
, COND
), QL_FCCMP_H
, F_FPTYPE
},
2283 /* Floating-point compare. */
2284 {"fcmp", 0x1e202000, 0xff20fc1f, floatcmp
, 0, FP
, OP2 (Fn
, Fm
), QL_FP2
, F_FPTYPE
},
2285 {"fcmp", 0x1ee02000, 0xff20fc1f, floatcmp
, 0, FP_F16
,
2286 OP2 (Fn
, Fm
), QL_FP2_H
, F_FPTYPE
},
2287 {"fcmpe", 0x1e202010, 0xff20fc1f, floatcmp
, 0, FP
, OP2 (Fn
, Fm
), QL_FP2
, F_FPTYPE
},
2288 {"fcmpe", 0x1ee02010, 0xff20fc1f, floatcmp
, 0, FP_F16
,
2289 OP2 (Fn
, Fm
), QL_FP2_H
, F_FPTYPE
},
2290 {"fcmp", 0x1e202008, 0xff20fc1f, floatcmp
, 0, FP
, OP2 (Fn
, FPIMM0
), QL_DST_SD
, F_FPTYPE
},
2291 {"fcmp", 0x1ee02008, 0xff20fc1f, floatcmp
, 0, FP_F16
,
2292 OP2 (Fn
, FPIMM0
), QL_FP2_H
, F_FPTYPE
},
2293 {"fcmpe", 0x1e202018, 0xff20fc1f, floatcmp
, 0, FP
, OP2 (Fn
, FPIMM0
), QL_DST_SD
, F_FPTYPE
},
2294 {"fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp
, 0, FP_F16
,
2295 OP2 (Fn
, FPIMM0
), QL_FP2_H
, F_FPTYPE
},
2296 /* Floating-point data-processing (1 source). */
2297 {"fmov", 0x1e204000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2298 {"fmov", 0x1ee04000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2299 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2300 {"fabs", 0x1e20c000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2301 {"fabs", 0x1ee0c000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2302 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2303 {"fneg", 0x1e214000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2304 {"fneg", 0x1ee14000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2305 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2306 {"fsqrt", 0x1e21c000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2307 {"fsqrt", 0x1ee1c000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2308 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2309 {"fcvt", 0x1e224000, 0xff3e7c00, floatdp1
, OP_FCVT
, FP
, OP2 (Fd
, Fn
), QL_FCVT
, F_FPTYPE
| F_MISC
},
2310 {"frintn", 0x1e244000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2311 {"frintn", 0x1ee44000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2312 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2313 {"frintp", 0x1e24c000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2314 {"frintp", 0x1ee4c000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2315 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2316 {"frintm", 0x1e254000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2317 {"frintm", 0x1ee54000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2318 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2319 {"frintz", 0x1e25c000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2320 {"frintz", 0x1ee5c000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2321 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2322 {"frinta", 0x1e264000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2323 {"frinta", 0x1ee64000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2324 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2325 {"frintx", 0x1e274000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2326 {"frintx", 0x1ee74000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2327 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2328 {"frinti", 0x1e27c000, 0xff3ffc00, floatdp1
, 0, FP
, OP2 (Fd
, Fn
), QL_FP2
, F_FPTYPE
},
2329 {"frinti", 0x1ee7c000, 0xff3ffc00, floatdp1
, 0, FP_F16
,
2330 OP2 (Fd
, Fn
), QL_FP2_H
, F_FPTYPE
},
2331 /* Floating-point data-processing (2 source). */
2332 {"fmul", 0x1e200800, 0xff20fc00, floatdp2
, 0, FP
, OP3 (Fd
, Fn
, Fm
), QL_FP3
, F_FPTYPE
},
2333 {"fmul", 0x1ee00800, 0xff20fc00, floatdp2
, 0, FP_F16
,
2334 OP3 (Fd
, Fn
, Fm
), QL_FP3_H
, F_FPTYPE
},
2335 {"fdiv", 0x1e201800, 0xff20fc00, floatdp2
, 0, FP
, OP3 (Fd
, Fn
, Fm
), QL_FP3
, F_FPTYPE
},
2336 {"fdiv", 0x1ee01800, 0xff20fc00, floatdp2
, 0, FP_F16
,
2337 OP3 (Fd
, Fn
, Fm
), QL_FP3_H
, F_FPTYPE
},
2338 {"fadd", 0x1e202800, 0xff20fc00, floatdp2
, 0, FP
, OP3 (Fd
, Fn
, Fm
), QL_FP3
, F_FPTYPE
},
2339 {"fadd", 0x1ee02800, 0xff20fc00, floatdp2
, 0, FP_F16
,
2340 OP3 (Fd
, Fn
, Fm
), QL_FP3_H
, F_FPTYPE
},
2341 {"fsub", 0x1e203800, 0xff20fc00, floatdp2
, 0, FP
, OP3 (Fd
, Fn
, Fm
), QL_FP3
, F_FPTYPE
},
2342 {"fsub", 0x1ee03800, 0xff20fc00, floatdp2
, 0, FP_F16
,
2343 OP3 (Fd
, Fn
, Fm
), QL_FP3_H
, F_FPTYPE
},
2344 {"fmax", 0x1e204800, 0xff20fc00, floatdp2
, 0, FP
, OP3 (Fd
, Fn
, Fm
), QL_FP3
, F_FPTYPE
},
2345 {"fmax", 0x1ee04800, 0xff20fc00, floatdp2
, 0, FP_F16
,
2346 OP3 (Fd
, Fn
, Fm
), QL_FP3_H
, F_FPTYPE
},
2347 {"fmin", 0x1e205800, 0xff20fc00, floatdp2
, 0, FP
, OP3 (Fd
, Fn
, Fm
), QL_FP3
, F_FPTYPE
},
2348 {"fmin", 0x1ee05800, 0xff20fc00, floatdp2
, 0, FP_F16
,
2349 OP3 (Fd
, Fn
, Fm
), QL_FP3_H
, F_FPTYPE
},
2350 {"fmaxnm", 0x1e206800, 0xff20fc00, floatdp2
, 0, FP
, OP3 (Fd
, Fn
, Fm
), QL_FP3
, F_FPTYPE
},
2351 {"fmaxnm", 0x1ee06800, 0xff20fc00, floatdp2
, 0, FP_F16
,
2352 OP3 (Fd
, Fn
, Fm
), QL_FP3_H
, F_FPTYPE
},
2353 {"fminnm", 0x1e207800, 0xff20fc00, floatdp2
, 0, FP
, OP3 (Fd
, Fn
, Fm
), QL_FP3
, F_FPTYPE
},
2354 {"fminnm", 0x1ee07800, 0xff20fc00, floatdp2
, 0, FP_F16
,
2355 OP3 (Fd
, Fn
, Fm
), QL_FP3_H
, F_FPTYPE
},
2356 {"fnmul", 0x1e208800, 0xff20fc00, floatdp2
, 0, FP
, OP3 (Fd
, Fn
, Fm
), QL_FP3
, F_FPTYPE
},
2357 {"fnmul", 0x1ee08800, 0xff20fc00, floatdp2
, 0, FP_F16
,
2358 OP3 (Fd
, Fn
, Fm
), QL_FP3_H
, F_FPTYPE
},
2359 /* Floating-point data-processing (3 source). */
2360 {"fmadd", 0x1f000000, 0xff208000, floatdp3
, 0, FP
, OP4 (Fd
, Fn
, Fm
, Fa
), QL_FP4
, F_FPTYPE
},
2361 {"fmadd", 0x1fc00000, 0xff208000, floatdp3
, 0, FP_F16
,
2362 OP4 (Fd
, Fn
, Fm
, Fa
), QL_FP4_H
, F_FPTYPE
},
2363 {"fmsub", 0x1f008000, 0xff208000, floatdp3
, 0, FP
, OP4 (Fd
, Fn
, Fm
, Fa
), QL_FP4
, F_FPTYPE
},
2364 {"fmsub", 0x1fc08000, 0xff208000, floatdp3
, 0, FP_F16
,
2365 OP4 (Fd
, Fn
, Fm
, Fa
), QL_FP4_H
, F_FPTYPE
},
2366 {"fnmadd", 0x1f200000, 0xff208000, floatdp3
, 0, FP
, OP4 (Fd
, Fn
, Fm
, Fa
), QL_FP4
, F_FPTYPE
},
2367 {"fnmadd", 0x1fe00000, 0xff208000, floatdp3
, 0, FP_F16
,
2368 OP4 (Fd
, Fn
, Fm
, Fa
), QL_FP4_H
, F_FPTYPE
},
2369 {"fnmsub", 0x1f208000, 0xff208000, floatdp3
, 0, FP
, OP4 (Fd
, Fn
, Fm
, Fa
), QL_FP4
, F_FPTYPE
},
2370 {"fnmsub", 0x1fe08000, 0xff208000, floatdp3
, 0, FP_F16
,
2371 OP4 (Fd
, Fn
, Fm
, Fa
), QL_FP4_H
, F_FPTYPE
},
2372 /* Floating-point immediate. */
2373 {"fmov", 0x1e201000, 0xff201fe0, floatimm
, 0, FP
, OP2 (Fd
, FPIMM
), QL_DST_SD
, F_FPTYPE
},
2374 {"fmov", 0x1ee01000, 0xff201fe0, floatimm
, 0, FP_F16
,
2375 OP2 (Fd
, FPIMM
), QL_DST_H
, F_FPTYPE
},
2376 /* Floating-point conditional select. */
2377 {"fcsel", 0x1e200c00, 0xff200c00, floatsel
, 0, FP
, OP4 (Fd
, Fn
, Fm
, COND
), QL_FP_COND
, F_FPTYPE
},
2378 {"fcsel", 0x1ee00c00, 0xff200c00, floatsel
, 0, FP_F16
,
2379 OP4 (Fd
, Fn
, Fm
, COND
), QL_FP_COND_H
, F_FPTYPE
},
2380 /* Load/store register (immediate indexed). */
2381 {"strb", 0x38000400, 0xffe00400, ldst_imm9
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W8
, 0},
2382 {"ldrb", 0x38400400, 0xffe00400, ldst_imm9
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W8
, 0},
2383 {"ldrsb", 0x38800400, 0xffa00400, ldst_imm9
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R8
, F_LDS_SIZE
},
2384 {"str", 0x3c000400, 0x3f600400, ldst_imm9
, 0, CORE
, OP2 (Ft
, ADDR_SIMM9
), QL_LDST_FP
, 0},
2385 {"ldr", 0x3c400400, 0x3f600400, ldst_imm9
, 0, CORE
, OP2 (Ft
, ADDR_SIMM9
), QL_LDST_FP
, 0},
2386 {"strh", 0x78000400, 0xffe00400, ldst_imm9
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W16
, 0},
2387 {"ldrh", 0x78400400, 0xffe00400, ldst_imm9
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W16
, 0},
2388 {"ldrsh", 0x78800400, 0xffa00400, ldst_imm9
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R16
, F_LDS_SIZE
},
2389 {"str", 0xb8000400, 0xbfe00400, ldst_imm9
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2390 {"ldr", 0xb8400400, 0xbfe00400, ldst_imm9
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2391 {"ldrsw", 0xb8800400, 0xffe00400, ldst_imm9
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_X32
, 0},
2392 /* Load/store register (unsigned immediate). */
2393 {"strb", 0x39000000, 0xffc00000, ldst_pos
, OP_STRB_POS
, CORE
, OP2 (Rt
, ADDR_UIMM12
), QL_LDST_W8
, 0},
2394 {"ldrb", 0x39400000, 0xffc00000, ldst_pos
, OP_LDRB_POS
, CORE
, OP2 (Rt
, ADDR_UIMM12
), QL_LDST_W8
, 0},
2395 {"ldrsb", 0x39800000, 0xff800000, ldst_pos
, OP_LDRSB_POS
, CORE
, OP2 (Rt
, ADDR_UIMM12
), QL_LDST_R8
, F_LDS_SIZE
},
2396 {"str", 0x3d000000, 0x3f400000, ldst_pos
, OP_STRF_POS
, CORE
, OP2 (Ft
, ADDR_UIMM12
), QL_LDST_FP
, 0},
2397 {"ldr", 0x3d400000, 0x3f400000, ldst_pos
, OP_LDRF_POS
, CORE
, OP2 (Ft
, ADDR_UIMM12
), QL_LDST_FP
, 0},
2398 {"strh", 0x79000000, 0xffc00000, ldst_pos
, OP_STRH_POS
, CORE
, OP2 (Rt
, ADDR_UIMM12
), QL_LDST_W16
, 0},
2399 {"ldrh", 0x79400000, 0xffc00000, ldst_pos
, OP_LDRH_POS
, CORE
, OP2 (Rt
, ADDR_UIMM12
), QL_LDST_W16
, 0},
2400 {"ldrsh", 0x79800000, 0xff800000, ldst_pos
, OP_LDRSH_POS
, CORE
, OP2 (Rt
, ADDR_UIMM12
), QL_LDST_R16
, F_LDS_SIZE
},
2401 {"str", 0xb9000000, 0xbfc00000, ldst_pos
, OP_STR_POS
, CORE
, OP2 (Rt
, ADDR_UIMM12
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2402 {"ldr", 0xb9400000, 0xbfc00000, ldst_pos
, OP_LDR_POS
, CORE
, OP2 (Rt
, ADDR_UIMM12
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2403 {"ldrsw", 0xb9800000, 0xffc00000, ldst_pos
, OP_LDRSW_POS
, CORE
, OP2 (Rt
, ADDR_UIMM12
), QL_LDST_X32
, 0},
2404 {"prfm", 0xf9800000, 0xffc00000, ldst_pos
, OP_PRFM_POS
, CORE
, OP2 (PRFOP
, ADDR_UIMM12
), QL_LDST_PRFM
, 0},
2405 /* Load/store register (register offset). */
2406 {"strb", 0x38200800, 0xffe00c00, ldst_regoff
, 0, CORE
, OP2 (Rt
, ADDR_REGOFF
), QL_LDST_W8
, 0},
2407 {"ldrb", 0x38600800, 0xffe00c00, ldst_regoff
, 0, CORE
, OP2 (Rt
, ADDR_REGOFF
), QL_LDST_W8
, 0},
2408 {"ldrsb", 0x38a00800, 0xffa00c00, ldst_regoff
, 0, CORE
, OP2 (Rt
, ADDR_REGOFF
), QL_LDST_R8
, F_LDS_SIZE
},
2409 {"str", 0x3c200800, 0x3f600c00, ldst_regoff
, 0, CORE
, OP2 (Ft
, ADDR_REGOFF
), QL_LDST_FP
, 0},
2410 {"ldr", 0x3c600800, 0x3f600c00, ldst_regoff
, 0, CORE
, OP2 (Ft
, ADDR_REGOFF
), QL_LDST_FP
, 0},
2411 {"strh", 0x78200800, 0xffe00c00, ldst_regoff
, 0, CORE
, OP2 (Rt
, ADDR_REGOFF
), QL_LDST_W16
, 0},
2412 {"ldrh", 0x78600800, 0xffe00c00, ldst_regoff
, 0, CORE
, OP2 (Rt
, ADDR_REGOFF
), QL_LDST_W16
, 0},
2413 {"ldrsh", 0x78a00800, 0xffa00c00, ldst_regoff
, 0, CORE
, OP2 (Rt
, ADDR_REGOFF
), QL_LDST_R16
, F_LDS_SIZE
},
2414 {"str", 0xb8200800, 0xbfe00c00, ldst_regoff
, 0, CORE
, OP2 (Rt
, ADDR_REGOFF
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2415 {"ldr", 0xb8600800, 0xbfe00c00, ldst_regoff
, 0, CORE
, OP2 (Rt
, ADDR_REGOFF
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2416 {"ldrsw", 0xb8a00800, 0xffe00c00, ldst_regoff
, 0, CORE
, OP2 (Rt
, ADDR_REGOFF
), QL_LDST_X32
, 0},
2417 {"prfm", 0xf8a00800, 0xffe00c00, ldst_regoff
, 0, CORE
, OP2 (PRFOP
, ADDR_REGOFF
), QL_LDST_PRFM
, 0},
2418 /* Load/store register (unprivileged). */
2419 {"sttrb", 0x38000800, 0xffe00c00, ldst_unpriv
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W8
, 0},
2420 {"ldtrb", 0x38400800, 0xffe00c00, ldst_unpriv
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W8
, 0},
2421 {"ldtrsb", 0x38800800, 0xffa00c00, ldst_unpriv
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R8
, F_LDS_SIZE
},
2422 {"sttrh", 0x78000800, 0xffe00c00, ldst_unpriv
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W16
, 0},
2423 {"ldtrh", 0x78400800, 0xffe00c00, ldst_unpriv
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W16
, 0},
2424 {"ldtrsh", 0x78800800, 0xffa00c00, ldst_unpriv
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R16
, F_LDS_SIZE
},
2425 {"sttr", 0xb8000800, 0xbfe00c00, ldst_unpriv
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2426 {"ldtr", 0xb8400800, 0xbfe00c00, ldst_unpriv
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2427 {"ldtrsw", 0xb8800800, 0xffe00c00, ldst_unpriv
, 0, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_X32
, 0},
2428 /* Load/store register (unscaled immediate). */
2429 {"sturb", 0x38000000, 0xffe00c00, ldst_unscaled
, OP_STURB
, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W8
, 0},
2430 {"ldurb", 0x38400000, 0xffe00c00, ldst_unscaled
, OP_LDURB
, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W8
, 0},
2431 {"ldursb", 0x38800000, 0xffa00c00, ldst_unscaled
, OP_LDURSB
, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R8
, F_LDS_SIZE
},
2432 {"stur", 0x3c000000, 0x3f600c00, ldst_unscaled
, OP_STURV
, CORE
, OP2 (Ft
, ADDR_SIMM9
), QL_LDST_FP
, 0},
2433 {"ldur", 0x3c400000, 0x3f600c00, ldst_unscaled
, OP_LDURV
, CORE
, OP2 (Ft
, ADDR_SIMM9
), QL_LDST_FP
, 0},
2434 {"sturh", 0x78000000, 0xffe00c00, ldst_unscaled
, OP_STURH
, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W16
, 0},
2435 {"ldurh", 0x78400000, 0xffe00c00, ldst_unscaled
, OP_LDURH
, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_W16
, 0},
2436 {"ldursh", 0x78800000, 0xffa00c00, ldst_unscaled
, OP_LDURSH
, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R16
, F_LDS_SIZE
},
2437 {"stur", 0xb8000000, 0xbfe00c00, ldst_unscaled
, OP_STUR
, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2438 {"ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled
, OP_LDUR
, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_R
, F_GPRSIZE_IN_Q
},
2439 {"ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled
, OP_LDURSW
, CORE
, OP2 (Rt
, ADDR_SIMM9
), QL_LDST_X32
, 0},
2440 {"prfum", 0xf8800000, 0xffe00c00, ldst_unscaled
, OP_PRFUM
, CORE
, OP2 (PRFOP
, ADDR_SIMM9
), QL_LDST_PRFM
, 0},
2441 /* Load/store exclusive. */
2442 {"stxrb", 0x8007c00, 0xffe08000, ldstexcl
, 0, CORE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2443 {"stlxrb", 0x800fc00, 0xffe08000, ldstexcl
, 0, CORE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2444 {"ldxrb", 0x85f7c00, 0xffe08000, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2445 {"ldaxrb", 0x85ffc00, 0xffe08000, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2446 {"stlrb", 0x89ffc00, 0xffe08000, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2447 {"ldarb", 0x8dffc00, 0xffeffc00, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2448 {"stxrh", 0x48007c00, 0xffe08000, ldstexcl
, 0, CORE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2449 {"stlxrh", 0x4800fc00, 0xffe08000, ldstexcl
, 0, CORE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2450 {"ldxrh", 0x485f7c00, 0xffe08000, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2451 {"ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2452 {"stlrh", 0x489ffc00, 0xffe08000, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2453 {"ldarh", 0x48dffc00, 0xffeffc00, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2454 {"stxr", 0x88007c00, 0xbfe08000, ldstexcl
, 0, CORE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2_LDST_EXC
, F_GPRSIZE_IN_Q
},
2455 {"stlxr", 0x8800fc00, 0xbfe08000, ldstexcl
, 0, CORE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2_LDST_EXC
, F_GPRSIZE_IN_Q
},
2456 {"stxp", 0x88200000, 0xbfe08000, ldstexcl
, 0, CORE
, OP4 (Rs
, Rt
, Rt2
, ADDR_SIMPLE
), QL_R3_LDST_EXC
, F_GPRSIZE_IN_Q
},
2457 {"stlxp", 0x88208000, 0xbfe08000, ldstexcl
, 0, CORE
, OP4 (Rs
, Rt
, Rt2
, ADDR_SIMPLE
), QL_R3_LDST_EXC
, F_GPRSIZE_IN_Q
},
2458 {"ldxr", 0x885f7c00, 0xbfe08000, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_R1NIL
, F_GPRSIZE_IN_Q
},
2459 {"ldaxr", 0x885ffc00, 0xbfe08000, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_R1NIL
, F_GPRSIZE_IN_Q
},
2460 {"ldxp", 0x887f0000, 0xbfe08000, ldstexcl
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMPLE
), QL_R2NIL
, F_GPRSIZE_IN_Q
},
2461 {"ldaxp", 0x887f8000, 0xbfe08000, ldstexcl
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMPLE
), QL_R2NIL
, F_GPRSIZE_IN_Q
},
2462 {"stlr", 0x889ffc00, 0xbfe08000, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_R1NIL
, F_GPRSIZE_IN_Q
},
2463 {"ldar", 0x88dffc00, 0xbfeffc00, ldstexcl
, 0, CORE
, OP2 (Rt
, ADDR_SIMPLE
), QL_R1NIL
, F_GPRSIZE_IN_Q
},
2464 /* Limited Ordering Regions load/store instructions. */
2465 {"ldlar", 0x88df7c00, 0xbfe08000, ldstexcl
, 0, LOR
, OP2 (Rt
, ADDR_SIMPLE
), QL_R1NIL
, F_GPRSIZE_IN_Q
},
2466 {"ldlarb", 0x08df7c00, 0xffe08000, ldstexcl
, 0, LOR
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2467 {"ldlarh", 0x48df7c00, 0xffe08000, ldstexcl
, 0, LOR
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2468 {"stllr", 0x889f7c00, 0xbfe08000, ldstexcl
, 0, LOR
, OP2 (Rt
, ADDR_SIMPLE
), QL_R1NIL
, F_GPRSIZE_IN_Q
},
2469 {"stllrb", 0x089f7c00, 0xffe08000, ldstexcl
, 0, LOR
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2470 {"stllrh", 0x489f7c00, 0xbfe08000, ldstexcl
, 0, LOR
, OP2 (Rt
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, 0},
2471 /* Load/store no-allocate pair (offset). */
2472 {"stnp", 0x28000000, 0x7fc00000, ldstnapair_offs
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMM7
), QL_LDST_PAIR_R
, F_SF
},
2473 {"ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMM7
), QL_LDST_PAIR_R
, F_SF
},
2474 {"stnp", 0x2c000000, 0x3fc00000, ldstnapair_offs
, 0, CORE
, OP3 (Ft
, Ft2
, ADDR_SIMM7
), QL_LDST_PAIR_FP
, 0},
2475 {"ldnp", 0x2c400000, 0x3fc00000, ldstnapair_offs
, 0, CORE
, OP3 (Ft
, Ft2
, ADDR_SIMM7
), QL_LDST_PAIR_FP
, 0},
2476 /* Load/store register pair (offset). */
2477 {"stp", 0x29000000, 0x7ec00000, ldstpair_off
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMM7
), QL_LDST_PAIR_R
, F_SF
},
2478 {"ldp", 0x29400000, 0x7ec00000, ldstpair_off
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMM7
), QL_LDST_PAIR_R
, F_SF
},
2479 {"stp", 0x2d000000, 0x3fc00000, ldstpair_off
, 0, CORE
, OP3 (Ft
, Ft2
, ADDR_SIMM7
), QL_LDST_PAIR_FP
, 0},
2480 {"ldp", 0x2d400000, 0x3fc00000, ldstpair_off
, 0, CORE
, OP3 (Ft
, Ft2
, ADDR_SIMM7
), QL_LDST_PAIR_FP
, 0},
2481 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMM7
), QL_LDST_PAIR_X32
, 0},
2482 /* Load/store register pair (indexed). */
2483 {"stp", 0x28800000, 0x7ec00000, ldstpair_indexed
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMM7
), QL_LDST_PAIR_R
, F_SF
},
2484 {"ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMM7
), QL_LDST_PAIR_R
, F_SF
},
2485 {"stp", 0x2c800000, 0x3ec00000, ldstpair_indexed
, 0, CORE
, OP3 (Ft
, Ft2
, ADDR_SIMM7
), QL_LDST_PAIR_FP
, 0},
2486 {"ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed
, 0, CORE
, OP3 (Ft
, Ft2
, ADDR_SIMM7
), QL_LDST_PAIR_FP
, 0},
2487 {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed
, 0, CORE
, OP3 (Rt
, Rt2
, ADDR_SIMM7
), QL_LDST_PAIR_X32
, 0},
2488 /* Load register (literal). */
2489 {"ldr", 0x18000000, 0xbf000000, loadlit
, OP_LDR_LIT
, CORE
, OP2 (Rt
, ADDR_PCREL19
), QL_R_PCREL
, F_GPRSIZE_IN_Q
},
2490 {"ldr", 0x1c000000, 0x3f000000, loadlit
, OP_LDRV_LIT
, CORE
, OP2 (Ft
, ADDR_PCREL19
), QL_FP_PCREL
, 0},
2491 {"ldrsw", 0x98000000, 0xff000000, loadlit
, OP_LDRSW_LIT
, CORE
, OP2 (Rt
, ADDR_PCREL19
), QL_X_PCREL
, 0},
2492 {"prfm", 0xd8000000, 0xff000000, loadlit
, OP_PRFM_LIT
, CORE
, OP2 (PRFOP
, ADDR_PCREL19
), QL_PRFM_PCREL
, 0},
2493 /* Logical (immediate). */
2494 {"and", 0x12000000, 0x7f800000, log_imm
, 0, CORE
, OP3 (Rd_SP
, Rn
, LIMM
), QL_R2NIL
, F_HAS_ALIAS
| F_SF
},
2495 {"bic", 0x12000000, 0x7f800000, log_imm
, OP_BIC
, CORE
, OP3 (Rd_SP
, Rn
, LIMM
), QL_R2NIL
, F_ALIAS
| F_PSEUDO
| F_SF
},
2496 {"orr", 0x32000000, 0x7f800000, log_imm
, 0, CORE
, OP3 (Rd_SP
, Rn
, LIMM
), QL_R2NIL
, F_HAS_ALIAS
| F_SF
},
2497 {"mov", 0x320003e0, 0x7f8003e0, log_imm
, OP_MOV_IMM_LOG
, CORE
, OP2 (Rd_SP
, IMM_MOV
), QL_R1NIL
, F_ALIAS
| F_P1
| F_SF
| F_CONV
},
2498 {"eor", 0x52000000, 0x7f800000, log_imm
, 0, CORE
, OP3 (Rd_SP
, Rn
, LIMM
), QL_R2NIL
, F_SF
},
2499 {"ands", 0x72000000, 0x7f800000, log_imm
, 0, CORE
, OP3 (Rd
, Rn
, LIMM
), QL_R2NIL
, F_HAS_ALIAS
| F_SF
},
2500 {"tst", 0x7200001f, 0x7f80001f, log_imm
, 0, CORE
, OP2 (Rn
, LIMM
), QL_R1NIL
, F_ALIAS
| F_SF
},
2501 /* Logical (shifted register). */
2502 {"and", 0xa000000, 0x7f200000, log_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_SF
},
2503 {"bic", 0xa200000, 0x7f200000, log_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_SF
},
2504 {"orr", 0x2a000000, 0x7f200000, log_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_HAS_ALIAS
| F_SF
},
2505 {"mov", 0x2a0003e0, 0x7f2003e0, log_shift
, 0, CORE
, OP2 (Rd
, Rm
), QL_I2SAMER
, F_ALIAS
| F_SF
},
2506 {"uxtw", 0x2a0003e0, 0x7f2003e0, log_shift
, OP_UXTW
, CORE
, OP2 (Rd
, Rm
), QL_I2SAMEW
, F_ALIAS
| F_PSEUDO
},
2507 {"orn", 0x2a200000, 0x7f200000, log_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_HAS_ALIAS
| F_SF
},
2508 {"mvn", 0x2a2003e0, 0x7f2003e0, log_shift
, 0, CORE
, OP2 (Rd
, Rm_SFT
), QL_I2SAMER
, F_ALIAS
| F_SF
},
2509 {"eor", 0x4a000000, 0x7f200000, log_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_SF
},
2510 {"eon", 0x4a200000, 0x7f200000, log_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_SF
},
2511 {"ands", 0x6a000000, 0x7f200000, log_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_HAS_ALIAS
| F_SF
},
2512 {"tst", 0x6a00001f, 0x7f20001f, log_shift
, 0, CORE
, OP2 (Rn
, Rm_SFT
), QL_I2SAMER
, F_ALIAS
| F_SF
},
2513 {"bics", 0x6a200000, 0x7f200000, log_shift
, 0, CORE
, OP3 (Rd
, Rn
, Rm_SFT
), QL_I3SAMER
, F_SF
},
2514 /* LSE extension (atomic). */
2515 {"casb", 0x8a07c00, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2516 {"cash", 0x48a07c00, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2517 {"cas", 0x88a07c00, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2518 {"casab", 0x8e07c00, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2519 {"caslb", 0x8a0fc00, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2520 {"casalb", 0x8e0fc00, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2521 {"casah", 0x48e07c00, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2522 {"caslh", 0x48a0fc00, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2523 {"casalh", 0x48e0fc00, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2524 {"casa", 0x88e07c00, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2525 {"casl", 0x88a0fc00, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2526 {"casal", 0x88e0fc00, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2527 {"casp", 0x8207c00, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP5 (Rs
, PAIRREG
, Rt
, PAIRREG
, ADDR_SIMPLE
), QL_R4NIL
, F_LSE_SZ
},
2528 {"caspa", 0x8607c00, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP5 (Rs
, PAIRREG
, Rt
, PAIRREG
, ADDR_SIMPLE
), QL_R4NIL
, F_LSE_SZ
},
2529 {"caspl", 0x820fc00, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP5 (Rs
, PAIRREG
, Rt
, PAIRREG
, ADDR_SIMPLE
), QL_R4NIL
, F_LSE_SZ
},
2530 {"caspal", 0x860fc00, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP5 (Rs
, PAIRREG
, Rt
, PAIRREG
, ADDR_SIMPLE
), QL_R4NIL
, F_LSE_SZ
},
2531 {"swpb", 0x38208000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2532 {"swph", 0x78208000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2533 {"swp", 0xb8208000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2534 {"swpab", 0x38a08000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2535 {"swplb", 0x38608000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2536 {"swpalb", 0x38e08000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2537 {"swpah", 0x78a08000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2538 {"swplh", 0x78608000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2539 {"swpalh", 0x78e08000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2540 {"swpa", 0xb8a08000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2541 {"swpl", 0xb8608000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2542 {"swpal", 0xb8e08000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2543 {"ldaddb", 0x38200000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2544 {"ldaddh", 0x78200000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2545 {"ldadd", 0xb8200000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2546 {"ldaddab", 0x38a00000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2547 {"ldaddlb", 0x38600000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2548 {"ldaddalb", 0x38e00000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2549 {"ldaddah", 0x78a00000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2550 {"ldaddlh", 0x78600000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2551 {"ldaddalh", 0x78e00000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2552 {"ldadda", 0xb8a00000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2553 {"ldaddl", 0xb8600000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2554 {"ldaddal", 0xb8e00000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2555 {"ldclrb", 0x38201000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2556 {"ldclrh", 0x78201000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2557 {"ldclr", 0xb8201000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2558 {"ldclrab", 0x38a01000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2559 {"ldclrlb", 0x38601000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2560 {"ldclralb", 0x38e01000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2561 {"ldclrah", 0x78a01000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2562 {"ldclrlh", 0x78601000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2563 {"ldclralh", 0x78e01000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2564 {"ldclra", 0xb8a01000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2565 {"ldclrl", 0xb8601000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2566 {"ldclral", 0xb8e01000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2567 {"ldeorb", 0x38202000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2568 {"ldeorh", 0x78202000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2569 {"ldeor", 0xb8202000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2570 {"ldeorab", 0x38a02000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2571 {"ldeorlb", 0x38602000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2572 {"ldeoralb", 0x38e02000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2573 {"ldeorah", 0x78a02000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2574 {"ldeorlh", 0x78602000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2575 {"ldeoralh", 0x78e02000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2576 {"ldeora", 0xb8a02000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2577 {"ldeorl", 0xb8602000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2578 {"ldeoral", 0xb8e02000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2579 {"ldsetb", 0x38203000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2580 {"ldseth", 0x78203000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2581 {"ldset", 0xb8203000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2582 {"ldsetab", 0x38a03000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2583 {"ldsetlb", 0x38603000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2584 {"ldsetalb", 0x38e03000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2585 {"ldsetah", 0x78a03000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2586 {"ldsetlh", 0x78603000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2587 {"ldsetalh", 0x78e03000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2588 {"ldseta", 0xb8a03000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2589 {"ldsetl", 0xb8603000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2590 {"ldsetal", 0xb8e03000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2591 {"ldsmaxb", 0x38204000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2592 {"ldsmaxh", 0x78204000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2593 {"ldsmax", 0xb8204000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2594 {"ldsmaxab", 0x38a04000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2595 {"ldsmaxlb", 0x38604000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2596 {"ldsmaxalb", 0x38e04000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2597 {"ldsmaxah", 0x78a04000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2598 {"ldsmaxlh", 0x78604000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2599 {"ldsmaxalh", 0x78e04000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2600 {"ldsmaxa", 0xb8a04000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2601 {"ldsmaxl", 0xb8604000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2602 {"ldsmaxal", 0xb8e04000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2603 {"ldsminb", 0x38205000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2604 {"ldsminh", 0x78205000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2605 {"ldsmin", 0xb8205000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2606 {"ldsminab", 0x38a05000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2607 {"ldsminlb", 0x38605000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2608 {"ldsminalb", 0x38e05000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2609 {"ldsminah", 0x78a05000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2610 {"ldsminlh", 0x78605000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2611 {"ldsminalh", 0x78e05000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2612 {"ldsmina", 0xb8a05000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2613 {"ldsminl", 0xb8605000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2614 {"ldsminal", 0xb8e05000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2615 {"ldumaxb", 0x38206000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2616 {"ldumaxh", 0x78206000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2617 {"ldumax", 0xb8206000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2618 {"ldumaxab", 0x38a06000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2619 {"ldumaxlb", 0x38606000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2620 {"ldumaxalb", 0x38e06000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2621 {"ldumaxah", 0x78a06000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2622 {"ldumaxlh", 0x78606000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2623 {"ldumaxalh", 0x78e06000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2624 {"ldumaxa", 0xb8a06000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2625 {"ldumaxl", 0xb8606000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2626 {"ldumaxal", 0xb8e06000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2627 {"lduminb", 0x38207000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2628 {"lduminh", 0x78207000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2629 {"ldumin", 0xb8207000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2630 {"lduminab", 0x38a07000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2631 {"lduminlb", 0x38607000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2632 {"lduminalb", 0x38e07000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2633 {"lduminah", 0x78a07000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2634 {"lduminlh", 0x78607000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, F_HAS_ALIAS
},
2635 {"lduminalh", 0x78e07000, 0xffe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_W2_LDST_EXC
, 0},
2636 {"ldumina", 0xb8a07000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2637 {"lduminl", 0xb8607000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
| F_HAS_ALIAS
},
2638 {"lduminal", 0xb8e07000, 0xbfe0fc00, lse_atomic
, 0, LSE
, OP3 (Rs
, Rt
, ADDR_SIMPLE
), QL_R2NIL
, F_LSE_SZ
},
2639 {"staddb", 0x3820001f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2640 {"staddh", 0x7820001f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2641 {"stadd", 0xb820001f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2642 {"staddlb", 0x3860001f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2643 {"staddlh", 0x7860001f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2644 {"staddl", 0xb860001f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2645 {"stclrb", 0x3820101f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2646 {"stclrh", 0x7820101f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2647 {"stclr", 0xb820101f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2648 {"stclrlb", 0x3860101f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2649 {"stclrlh", 0x7860101f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2650 {"stclrl", 0xb860101f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2651 {"steorb", 0x3820201f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2652 {"steorh", 0x7820201f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2653 {"steor", 0xb820201f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2654 {"steorlb", 0x3860201f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2655 {"steorlh", 0x7860201f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2656 {"steorl", 0xb860201f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2657 {"stsetb", 0x3820301f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2658 {"stseth", 0x7820301f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2659 {"stset", 0xb820301f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2660 {"stsetlb", 0x3860301f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2661 {"stsetlh", 0x7860301f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2662 {"stsetl", 0xb860301f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2663 {"stsmaxb", 0x3820401f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2664 {"stsmaxh", 0x7820401f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2665 {"stsmax", 0xb820401f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2666 {"stsmaxlb", 0x3860401f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2667 {"stsmaxlh", 0x7860401f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2668 {"stsmaxl", 0xb860401f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2669 {"stsminb", 0x3820501f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2670 {"stsminh", 0x7820501f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2671 {"stsmin", 0xb820501f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2672 {"stsminlb", 0x3860501f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2673 {"stsminlh", 0x7860501f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2674 {"stsminl", 0xb860501f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2675 {"stumaxb", 0x3820601f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2676 {"stumaxh", 0x7820601f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2677 {"stumax", 0xb820601f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2678 {"stumaxlb", 0x3860601f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2679 {"stumaxlh", 0x7860601f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2680 {"stumaxl", 0xb860601f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2681 {"stuminb", 0x3820701f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2682 {"stuminh", 0x7820701f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2683 {"stumin", 0xb820701f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2684 {"stuminlb", 0x3860701f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2685 {"stuminlh", 0x7860701f, 0xffe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_W1_LDST_EXC
, F_ALIAS
},
2686 {"stuminl", 0xb860701f, 0xbfe0fc1f, lse_atomic
, 0, LSE
, OP2 (Rs
, ADDR_SIMPLE
), QL_R1NIL
, F_LSE_SZ
| F_ALIAS
},
2687 /* Move wide (immediate). */
2688 {"movn", 0x12800000, 0x7f800000, movewide
, OP_MOVN
, CORE
, OP2 (Rd
, HALF
), QL_DST_R
, F_SF
| F_HAS_ALIAS
},
2689 {"mov", 0x12800000, 0x7f800000, movewide
, OP_MOV_IMM_WIDEN
, CORE
, OP2 (Rd
, IMM_MOV
), QL_DST_R
, F_SF
| F_ALIAS
| F_CONV
},
2690 {"movz", 0x52800000, 0x7f800000, movewide
, OP_MOVZ
, CORE
, OP2 (Rd
, HALF
), QL_DST_R
, F_SF
| F_HAS_ALIAS
},
2691 {"mov", 0x52800000, 0x7f800000, movewide
, OP_MOV_IMM_WIDE
, CORE
, OP2 (Rd
, IMM_MOV
), QL_DST_R
, F_SF
| F_ALIAS
| F_CONV
},
2692 {"movk", 0x72800000, 0x7f800000, movewide
, OP_MOVK
, CORE
, OP2 (Rd
, HALF
), QL_DST_R
, F_SF
},
2693 /* PC-rel. addressing. */
2694 {"adr", 0x10000000, 0x9f000000, pcreladdr
, 0, CORE
, OP2 (Rd
, ADDR_PCREL21
), QL_ADRP
, 0},
2695 {"adrp", 0x90000000, 0x9f000000, pcreladdr
, 0, CORE
, OP2 (Rd
, ADDR_ADRP
), QL_ADRP
, 0},
2697 {"msr", 0xd500401f, 0xfff8f01f, ic_system
, 0, CORE
, OP2 (PSTATEFIELD
, UIMM4
), {}, 0},
2698 {"hint", 0xd503201f, 0xfffff01f, ic_system
, 0, CORE
, OP1 (UIMM7
), {}, F_HAS_ALIAS
},
2699 {"nop", 0xd503201f, 0xffffffff, ic_system
, 0, CORE
, OP0 (), {}, F_ALIAS
},
2700 {"yield", 0xd503203f, 0xffffffff, ic_system
, 0, CORE
, OP0 (), {}, F_ALIAS
},
2701 {"wfe", 0xd503205f, 0xffffffff, ic_system
, 0, CORE
, OP0 (), {}, F_ALIAS
},
2702 {"wfi", 0xd503207f, 0xffffffff, ic_system
, 0, CORE
, OP0 (), {}, F_ALIAS
},
2703 {"sev", 0xd503209f, 0xffffffff, ic_system
, 0, CORE
, OP0 (), {}, F_ALIAS
},
2704 {"sevl", 0xd50320bf, 0xffffffff, ic_system
, 0, CORE
, OP0 (), {}, F_ALIAS
},
2705 {"esb", 0xd503221f, 0xffffffff, ic_system
, 0, RAS
, OP0 (), {}, F_ALIAS
},
2706 {"psb", 0xd503223f, 0xffffffff, ic_system
, 0, STAT_PROFILE
,
2707 OP1 (BARRIER_PSB
), {}, F_ALIAS
},
2708 {"clrex", 0xd503305f, 0xfffff0ff, ic_system
, 0, CORE
, OP1 (UIMM4
), {}, F_OPD0_OPT
| F_DEFAULT (0xF)},
2709 {"dsb", 0xd503309f, 0xfffff0ff, ic_system
, 0, CORE
, OP1 (BARRIER
), {}, 0},
2710 {"dmb", 0xd50330bf, 0xfffff0ff, ic_system
, 0, CORE
, OP1 (BARRIER
), {}, 0},
2711 {"isb", 0xd50330df, 0xfffff0ff, ic_system
, 0, CORE
, OP1 (BARRIER_ISB
), {}, F_OPD0_OPT
| F_DEFAULT (0xF)},
2712 {"sys", 0xd5080000, 0xfff80000, ic_system
, 0, CORE
, OP5 (UIMM3_OP1
, Cn
, Cm
, UIMM3_OP2
, Rt
), QL_SYS
, F_HAS_ALIAS
| F_OPD4_OPT
| F_DEFAULT (0x1F)},
2713 {"at", 0xd5080000, 0xfff80000, ic_system
, 0, CORE
, OP2 (SYSREG_AT
, Rt
), QL_SRC_X
, F_ALIAS
},
2714 {"dc", 0xd5080000, 0xfff80000, ic_system
, 0, CORE
, OP2 (SYSREG_DC
, Rt
), QL_SRC_X
, F_ALIAS
},
2715 {"ic", 0xd5080000, 0xfff80000, ic_system
, 0, CORE
, OP2 (SYSREG_IC
, Rt_SYS
), QL_SRC_X
, F_ALIAS
| F_OPD1_OPT
| F_DEFAULT (0x1F)},
2716 {"tlbi", 0xd5080000, 0xfff80000, ic_system
, 0, CORE
, OP2 (SYSREG_TLBI
, Rt_SYS
), QL_SRC_X
, F_ALIAS
| F_OPD1_OPT
| F_DEFAULT (0x1F)},
2717 {"msr", 0xd5000000, 0xffe00000, ic_system
, 0, CORE
, OP2 (SYSREG
, Rt
), QL_SRC_X
, 0},
2718 {"sysl", 0xd5280000, 0xfff80000, ic_system
, 0, CORE
, OP5 (Rt
, UIMM3_OP1
, Cn
, Cm
, UIMM3_OP2
), QL_SYSL
, 0},
2719 {"mrs", 0xd5200000, 0xffe00000, ic_system
, 0, CORE
, OP2 (Rt
, SYSREG
), QL_DST_X
, 0},
2720 /* Test & branch (immediate). */
2721 {"tbz", 0x36000000, 0x7f000000, testbranch
, 0, CORE
, OP3 (Rt
, BIT_NUM
, ADDR_PCREL14
), QL_PCREL_14
, 0},
2722 {"tbnz", 0x37000000, 0x7f000000, testbranch
, 0, CORE
, OP3 (Rt
, BIT_NUM
, ADDR_PCREL14
), QL_PCREL_14
, 0},
2723 /* The old UAL conditional branch mnemonics (to aid portability). */
2724 {"beq", 0x54000000, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2725 {"bne", 0x54000001, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2726 {"bcs", 0x54000002, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2727 {"bhs", 0x54000002, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2728 {"bcc", 0x54000003, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2729 {"blo", 0x54000003, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2730 {"bmi", 0x54000004, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2731 {"bpl", 0x54000005, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2732 {"bvs", 0x54000006, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2733 {"bvc", 0x54000007, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2734 {"bhi", 0x54000008, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2735 {"bls", 0x54000009, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2736 {"bge", 0x5400000a, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2737 {"blt", 0x5400000b, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2738 {"bgt", 0x5400000c, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2739 {"ble", 0x5400000d, 0xff00001f, condbranch
, 0, CORE
, OP1 (ADDR_PCREL19
), QL_PCREL_NIL
, F_ALIAS
| F_PSEUDO
},
2741 {0, 0, 0, 0, 0, 0, {}, {}, 0},
2744 #ifdef AARCH64_OPERANDS
2745 #undef AARCH64_OPERANDS
2748 /* Macro-based operand decription; this will be fed into aarch64-gen for it
2749 to generate the structure aarch64_operands and the function
2750 aarch64_insert_operand and aarch64_extract_operand.
2752 These inserters and extracters in the description execute the conversion
2753 between the aarch64_opnd_info and value in the operand-related instruction
2756 /* Y expects arguments (left to right) to be operand class, inserter/extractor
2757 name suffix, operand name, flags, related bitfield(s) and description.
2758 X only differs from Y by having the operand inserter and extractor names
2759 listed separately. */
2761 #define AARCH64_OPERANDS \
2762 Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \
2763 Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \
2764 Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
2765 Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \
2766 Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \
2767 Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \
2768 Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
2769 X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \
2770 "an integer register") \
2771 Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \
2772 "an integer or stack pointer register") \
2773 Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \
2774 "an integer or stack pointer register") \
2775 X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \
2776 "the second reg of a pair") \
2777 Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \
2778 "an integer register with optional extension") \
2779 Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \
2780 "an integer register with optional shift") \
2781 Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \
2782 Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \
2783 Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \
2784 Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \
2785 Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \
2786 Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \
2787 Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \
2788 Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \
2789 Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \
2790 Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \
2791 Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \
2792 Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \
2793 Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \
2794 "the top half of a 128-bit FP/SIMD register") \
2795 Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \
2796 "the top half of a 128-bit FP/SIMD register") \
2797 Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \
2798 "a SIMD vector element") \
2799 Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \
2800 "a SIMD vector element") \
2801 Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \
2802 "a SIMD vector element") \
2803 Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \
2804 "a SIMD vector register list") \
2805 Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \
2806 "a SIMD vector register list") \
2807 Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \
2808 "a SIMD vector register list") \
2809 Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \
2810 "a SIMD vector element list") \
2811 Y(CP_REG, regno, "Cn", 0, F(FLD_CRn), \
2812 "a 4-bit opcode field named for historical reasons C0 - C15") \
2813 Y(CP_REG, regno, "Cm", 0, F(FLD_CRm), \
2814 "a 4-bit opcode field named for historical reasons C0 - C15") \
2815 Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4), \
2816 "an immediate as the index of the least significant byte") \
2817 Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \
2818 "a left shift amount for an AdvSIMD register") \
2819 Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSR", 0, F(), \
2820 "a right shift amount for an AdvSIMD register") \
2821 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM", 0, F(), \
2823 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_IMM_SFT", 0, F(), \
2824 "an 8-bit unsigned immediate with optional shift") \
2825 Y(IMMEDIATE, advsimd_imm_modified, "SIMD_FPIMM", 0, F(), \
2826 "an 8-bit floating-point constant") \
2827 X(IMMEDIATE, 0, ext_shll_imm, "SHLL_IMM", 0, F(), \
2828 "an immediate shift amount of 8, 16 or 32") \
2829 X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \
2830 X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \
2831 Y(IMMEDIATE, imm, "FPIMM", 0, F(FLD_imm8), \
2832 "an 8-bit floating-point constant") \
2833 Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \
2834 "the right rotate amount") \
2835 Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6), \
2836 "the leftmost bit number to be moved from the source") \
2837 Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6), \
2838 "the width of the bit-field") \
2839 Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6), "an immediate") \
2840 Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \
2841 "a 3-bit unsigned immediate") \
2842 Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \
2843 "a 3-bit unsigned immediate") \
2844 Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \
2845 "a 4-bit unsigned immediate") \
2846 Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \
2847 "a 7-bit unsigned immediate") \
2848 Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \
2849 "the bit number to be tested") \
2850 Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \
2851 "a 16-bit unsigned immediate") \
2852 Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \
2853 "a 5-bit unsigned immediate") \
2854 Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \
2855 "a flag bit specifier giving an alternative value for each flag") \
2856 Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \
2857 "Logical immediate") \
2858 Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \
2859 "a 12-bit unsigned immediate with optional left shift of 12 bits")\
2860 Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16), \
2861 "a 16-bit immediate with optional left shift") \
2862 Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \
2863 "the number of bits after the binary point in the fixed-point value")\
2864 X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \
2865 Y(COND, cond, "COND", 0, F(), "a condition") \
2866 Y(COND, cond, "COND1", 0, F(), \
2867 "one of the standard conditions, excluding AL and NV.") \
2868 X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\
2869 "21-bit PC-relative address of a 4KB page") \
2870 Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
2871 F(FLD_imm14), "14-bit PC-relative address") \
2872 Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
2873 F(FLD_imm19), "19-bit PC-relative address") \
2874 Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \
2875 "21-bit PC-relative address") \
2876 Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \
2877 F(FLD_imm26), "26-bit PC-relative address") \
2878 Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \
2879 "an address with base register (no offset)") \
2880 Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \
2881 "an address with register offset") \
2882 Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \
2883 "an address with 7-bit signed immediate offset") \
2884 Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \
2885 "an address with 9-bit signed immediate offset") \
2886 Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \
2887 "an address with 9-bit negative or unaligned immediate offset") \
2888 Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \
2889 "an address with scaled, unsigned immediate offset") \
2890 Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \
2891 "an address with base register (no offset)") \
2892 Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \
2893 "a post-indexed address with immediate or register increment") \
2894 Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \
2895 Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \
2896 "a PSTATE field name") \
2897 Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \
2898 "an address translation operation specifier") \
2899 Y(SYSTEM, sysins_op, "SYSREG_DC", 0, F(), \
2900 "a data cache maintenance operation specifier") \
2901 Y(SYSTEM, sysins_op, "SYSREG_IC", 0, F(), \
2902 "an instruction cache maintenance operation specifier") \
2903 Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \
2904 "a TBL invalidation operation specifier") \
2905 Y(SYSTEM, barrier, "BARRIER", 0, F(), \
2906 "a barrier option name") \
2907 Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \
2908 "the ISB option name SY or an optional 4-bit unsigned immediate") \
2909 Y(SYSTEM, prfop, "PRFOP", 0, F(), \
2910 "a prefetch operation specifier") \
2911 Y (SYSTEM, hint, "BARRIER_PSB", 0, F (), \
2912 "the PSB option name CSYNC")