1 /* Instruction printing code for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
27 #include "opcode/arc.h"
32 /* Globals variables. */
34 static const char * const regnames
[64] =
36 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
37 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
38 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
39 "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
41 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
42 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
43 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
44 "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
50 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
52 # define pr_debug(fmt, args...)
55 #define ARRANGE_ENDIAN(info, buf) \
56 (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
59 #define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
60 (s + (sizeof (word) * 8 - 1 - e)))
61 #define OPCODE(word) (BITS ((word), 27, 31))
63 #define OPCODE_AC(word) (BITS ((word), 11, 15))
65 /* Functions implementation. */
68 bfd_getm32 (unsigned int data
)
72 value
= ((data
& 0xff00) | (data
& 0xff)) << 16;
73 value
|= ((data
& 0xff0000) | (data
& 0xff000000)) >> 16;
78 special_flag_p (const char *opname
,
81 const struct arc_flag_special
*flg_spec
;
82 unsigned i
, j
, flgidx
;
84 for (i
= 0; i
< arc_num_flag_special
; i
++)
86 flg_spec
= &arc_flag_special_cases
[i
];
88 if (strcmp (opname
, flg_spec
->name
))
91 /* Found potential special case instruction. */
94 flgidx
= flg_spec
->flags
[j
];
96 break; /* End of the array. */
98 if (strcmp (flgname
, arc_flag_operands
[flgidx
].name
) == 0)
105 /* Disassemble ARC instructions. */
108 print_insn_arc (bfd_vma memaddr
,
109 struct disassemble_info
*info
)
112 unsigned int lowbyte
, highbyte
;
116 unsigned insn
[2] = { 0, 0 };
118 const unsigned char *opidx
;
119 const unsigned char *flgidx
;
120 const struct arc_opcode
*opcode
;
121 const char *instrName
;
123 bfd_boolean need_comma
;
124 bfd_boolean open_braket
;
127 lowbyte
= ((info
->endian
== BFD_ENDIAN_LITTLE
) ? 1 : 0);
128 highbyte
= ((info
->endian
== BFD_ENDIAN_LITTLE
) ? 0 : 1);
132 case bfd_mach_arc_nps400
:
133 isa_mask
= ARC_OPCODE_ARC700
| ARC_OPCODE_NPS400
;
136 case bfd_mach_arc_arc700
:
137 isa_mask
= ARC_OPCODE_ARC700
;
140 case bfd_mach_arc_arc600
:
141 isa_mask
= ARC_OPCODE_ARC600
;
144 case bfd_mach_arc_arcv2
:
146 isa_mask
= ARC_OPCODE_ARCv2HS
| ARC_OPCODE_ARCv2EM
;
150 /* This variable may be set by the instruction decoder. It suggests
151 the number of bytes objdump should display on a single line. If
152 the instruction decoder sets this, it should always set it to
153 the same value in order to get reasonable looking output. */
155 info
->bytes_per_line
= 8;
157 /* In the next lines, we set two info variables control the way
158 objdump displays the raw data. For example, if bytes_per_line is
159 8 and bytes_per_chunk is 4, the output will look like this:
160 00: 00000000 00000000
161 with the chunks displayed according to "display_endian". */
164 && !(info
->section
->flags
& SEC_CODE
))
166 /* This is not a CODE section. */
167 switch (info
->section
->size
)
172 size
= info
->section
->size
;
175 size
= (info
->section
->size
& 0x01) ? 1 : 4;
178 info
->bytes_per_chunk
= 1;
179 info
->display_endian
= info
->endian
;
184 info
->bytes_per_chunk
= 2;
185 info
->display_endian
= info
->endian
;
188 /* Read the insn into a host word. */
189 status
= (*info
->read_memory_func
) (memaddr
, buffer
, size
, info
);
192 (*info
->memory_error_func
) (status
, memaddr
, info
);
197 && !(info
->section
->flags
& SEC_CODE
))
202 data
= bfd_get_bits (buffer
, size
* 8,
203 info
->display_endian
== BFD_ENDIAN_BIG
);
207 (*info
->fprintf_func
) (info
->stream
, ".byte\t0x%02lx", data
);
210 (*info
->fprintf_func
) (info
->stream
, ".short\t0x%04lx", data
);
213 (*info
->fprintf_func
) (info
->stream
, ".word\t0x%08lx", data
);
221 if ( (((buffer
[lowbyte
] & 0xf8) > 0x38)
222 && ((buffer
[lowbyte
] & 0xf8) != 0x48))
223 || ((info
->mach
== bfd_mach_arc_arcv2
)
224 && ((buffer
[lowbyte
] & 0xF8) == 0x48)) /* FIXME! ugly. */
227 /* This is a short instruction. */
229 insn
[0] = (buffer
[lowbyte
] << 8) | buffer
[highbyte
];
235 /* This is a long instruction: Read the remaning 2 bytes. */
236 status
= (*info
->read_memory_func
) (memaddr
+ 2, &buffer
[2], 2, info
);
239 (*info
->memory_error_func
) (status
, memaddr
+ 2, info
);
242 insn
[0] = ARRANGE_ENDIAN (info
, buffer
);
245 /* Set some defaults for the insn info. */
246 info
->insn_info_valid
= 1;
247 info
->branch_delay_insns
= 0;
249 info
->insn_type
= dis_nonbranch
;
253 /* FIXME to be moved in dissasemble_init_for_target. */
254 info
->disassembler_needs_relocs
= TRUE
;
256 /* Find the first match in the opcode table. */
257 for (i
= 0; i
< arc_num_opcodes
; i
++)
259 bfd_boolean invalid
= FALSE
;
261 opcode
= &arc_opcodes
[i
];
263 if (ARC_SHORT (opcode
->mask
) && (insnLen
== 2))
265 if (OPCODE_AC (opcode
->opcode
) != OPCODE_AC (insn
[0]))
268 else if (!ARC_SHORT (opcode
->mask
) && (insnLen
== 4))
270 if (OPCODE (opcode
->opcode
) != OPCODE (insn
[0]))
276 if ((insn
[0] ^ opcode
->opcode
) & opcode
->mask
)
279 if (!(opcode
->cpu
& isa_mask
))
282 /* Possible candidate, check the operands. */
283 for (opidx
= opcode
->operands
; *opidx
; opidx
++)
286 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
288 if (operand
->flags
& ARC_OPERAND_FAKE
)
291 if (operand
->extract
)
292 value
= (*operand
->extract
) (insn
[0], &invalid
);
294 value
= (insn
[0] >> operand
->shift
) & ((1 << operand
->bits
) - 1);
296 /* Check for LIMM indicator. If it is there, then make sure
297 we pick the right format. */
298 if (operand
->flags
& ARC_OPERAND_IR
299 && !(operand
->flags
& ARC_OPERAND_LIMM
))
301 if ((value
== 0x3E && insnLen
== 4)
302 || (value
== 0x1E && insnLen
== 2))
310 /* Check the flags. */
311 for (flgidx
= opcode
->flags
; *flgidx
; flgidx
++)
313 /* Get a valid flag class. */
314 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
315 const unsigned *flgopridx
;
316 int foundA
= 0, foundB
= 0;
318 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
320 const struct arc_flag_operand
*flg_operand
= &arc_flag_operands
[*flgopridx
];
323 value
= (insn
[0] >> flg_operand
->shift
) & ((1 << flg_operand
->bits
) - 1);
324 if (value
== flg_operand
->code
)
329 if (!foundA
&& foundB
)
339 /* The instruction is valid. */
343 /* No instruction found. Try the extenssions. */
344 instrName
= arcExtMap_instName (OPCODE (insn
[0]), insn
[0], &flags
);
347 opcode
= &arc_opcodes
[0];
348 (*info
->fprintf_func
) (info
->stream
, "%s", instrName
);
353 (*info
->fprintf_func
) (info
->stream
, ".long %#04x", insn
[0]);
355 (*info
->fprintf_func
) (info
->stream
, ".long %#08x", insn
[0]);
357 info
->insn_type
= dis_noninsn
;
361 /* Print the mnemonic. */
362 (*info
->fprintf_func
) (info
->stream
, "%s", opcode
->name
);
364 /* Preselect the insn class. */
365 switch (opcode
->class)
369 if (!strncmp (opcode
->name
, "bl", 2)
370 || !strncmp (opcode
->name
, "jl", 2))
371 info
->insn_type
= dis_jsr
;
373 info
->insn_type
= dis_branch
;
376 info
->insn_type
= dis_dref
; /* FIXME! DB indicates mov as memory! */
379 info
->insn_type
= dis_nonbranch
;
383 pr_debug ("%s: 0x%08x\n", opcode
->name
, opcode
->opcode
);
386 /* Now extract and print the flags. */
387 for (flgidx
= opcode
->flags
; *flgidx
; flgidx
++)
389 /* Get a valid flag class. */
390 const struct arc_flag_class
*cl_flags
= &arc_flag_classes
[*flgidx
];
391 const unsigned *flgopridx
;
393 for (flgopridx
= cl_flags
->flags
; *flgopridx
; ++flgopridx
)
395 const struct arc_flag_operand
*flg_operand
= &arc_flag_operands
[*flgopridx
];
398 if (!flg_operand
->favail
)
401 value
= (insn
[0] >> flg_operand
->shift
) & ((1 << flg_operand
->bits
) - 1);
402 if (value
== flg_operand
->code
)
404 /* FIXME!: print correctly nt/t flag. */
405 if (!special_flag_p (opcode
->name
, flg_operand
->name
))
406 (*info
->fprintf_func
) (info
->stream
, ".");
407 else if (info
->insn_type
== dis_dref
)
409 switch (flg_operand
->name
[0])
423 (*info
->fprintf_func
) (info
->stream
, "%s", flg_operand
->name
);
426 if (flg_operand
->name
[0] == 'd'
427 && flg_operand
->name
[1] == 0)
428 info
->branch_delay_insns
= 1;
432 if (opcode
->operands
[0] != 0)
433 (*info
->fprintf_func
) (info
->stream
, "\t");
438 /* Now extract and print the operands. */
439 for (opidx
= opcode
->operands
; *opidx
; opidx
++)
441 const struct arc_operand
*operand
= &arc_operands
[*opidx
];
444 if (open_braket
&& (operand
->flags
& ARC_OPERAND_BRAKET
))
446 (*info
->fprintf_func
) (info
->stream
, "]");
451 /* Only take input from real operands. */
452 if ((operand
->flags
& ARC_OPERAND_FAKE
)
453 && !(operand
->flags
& ARC_OPERAND_BRAKET
))
456 if (operand
->extract
)
457 value
= (*operand
->extract
) (insn
[0], (int *) NULL
);
460 if (operand
->flags
& ARC_OPERAND_ALIGNED32
)
462 value
= (insn
[0] >> operand
->shift
)
463 & ((1 << (operand
->bits
- 2)) - 1);
468 value
= (insn
[0] >> operand
->shift
) & ((1 << operand
->bits
) - 1);
470 if (operand
->flags
& ARC_OPERAND_SIGNED
)
472 int signbit
= 1 << (operand
->bits
- 1);
473 value
= (value
^ signbit
) - signbit
;
477 if (operand
->flags
& ARC_OPERAND_IGNORE
478 && (operand
->flags
& ARC_OPERAND_IR
483 (*info
->fprintf_func
) (info
->stream
, ",");
485 if (!open_braket
&& (operand
->flags
& ARC_OPERAND_BRAKET
))
487 (*info
->fprintf_func
) (info
->stream
, "[");
493 /* Read the limm operand, if required. */
494 if (operand
->flags
& ARC_OPERAND_LIMM
495 && !(operand
->flags
& ARC_OPERAND_DUPLICATE
))
497 status
= (*info
->read_memory_func
) (memaddr
+ insnLen
, buffer
,
501 (*info
->memory_error_func
) (status
, memaddr
+ insnLen
, info
);
504 insn
[1] = ARRANGE_ENDIAN (info
, buffer
);
507 /* Print the operand as directed by the flags. */
508 if (operand
->flags
& ARC_OPERAND_IR
)
510 assert (value
>=0 && value
< 64);
511 (*info
->fprintf_func
) (info
->stream
, "%s", regnames
[value
]);
512 if (operand
->flags
& ARC_OPERAND_TRUNCATE
)
513 (*info
->fprintf_func
) (info
->stream
, "%s", regnames
[value
+1]);
515 else if (operand
->flags
& ARC_OPERAND_LIMM
)
517 (*info
->fprintf_func
) (info
->stream
, "%#x", insn
[1]);
518 if (info
->insn_type
== dis_branch
519 || info
->insn_type
== dis_jsr
)
520 info
->target
= (bfd_vma
) insn
[1];
522 else if (operand
->flags
& ARC_OPERAND_PCREL
)
525 if (info
->flags
& INSN_HAS_RELOC
)
527 (*info
->print_address_func
) ((memaddr
& ~3) + value
, info
);
529 info
->target
= (bfd_vma
) (memaddr
& ~3) + value
;
531 else if (operand
->flags
& ARC_OPERAND_SIGNED
)
532 (*info
->fprintf_func
) (info
->stream
, "%d", value
);
534 if (operand
->flags
& ARC_OPERAND_TRUNCATE
535 && !(operand
->flags
& ARC_OPERAND_ALIGNED32
)
536 && !(operand
->flags
& ARC_OPERAND_ALIGNED16
)
537 && value
> 0 && value
<= 14)
538 (*info
->fprintf_func
) (info
->stream
, "r13-%s",
539 regnames
[13 + value
- 1]);
541 (*info
->fprintf_func
) (info
->stream
, "%#x", value
);
545 /* Adjust insn len. */
546 if (operand
->flags
& ARC_OPERAND_LIMM
547 && !(operand
->flags
& ARC_OPERAND_DUPLICATE
))
556 arc_get_disassembler (bfd
*abfd
)
558 /* Read the extenssion insns and registers, if any. */
559 build_ARC_extmap (abfd
);
562 return print_insn_arc
;
565 /* Disassemble ARC instructions. Used by debugger. */
568 arcAnalyzeInstr (bfd_vma memaddr
,
569 struct disassemble_info
*info
)
571 struct arcDisState ret
;
572 memset (&ret
, 0, sizeof (struct arcDisState
));
574 ret
.instructionLen
= print_insn_arc (memaddr
, info
);
577 ret
.words
[0] = insn
[0];
578 ret
.words
[1] = insn
[1];
580 ret
.coreRegName
= _coreRegName
;
581 ret
.auxRegName
= _auxRegName
;
582 ret
.condCodeName
= _condCodeName
;
583 ret
.instName
= _instName
;
590 eval: (c-set-style "gnu")