opcodes/arc-dis.c

   1 /* Instruction printing code for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <stdio.h>
  25 #include <assert.h>
  26 #include "dis-asm.h"
  27 #include "opcode/arc.h"
  28 #include "arc-dis.h"
  29 #include "arc-ext.h"
  30
  31
  32 /* Globals variables.  */
  33
  34 static const char * const regnames[64] =
  35 {
  36   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  37   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  38   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  39   "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
  40
  41   "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  42   "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  43   "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
  44   "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
  45 };
  46
  47 /* Macros section.  */
  48
  49 #ifdef DEBUG
  50 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
  51 #else
  52 # define pr_debug(fmt, args...)
  53 #endif
  54
  55 #define ARRANGE_ENDIAN(info, buf)                                       \
  56   (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf))    \
  57    : bfd_getb32 (buf))
  58
  59 #define BITS(word,s,e)  (((word) << (sizeof (word) * 8 - 1 - e)) >>     \
  60                          (s + (sizeof (word) * 8 - 1 - e)))
  61 #define OPCODE(word)    (BITS ((word), 27, 31))
  62 #define FIELDA(word)    (BITS ((word), 21, 26))
  63 #define FIELDB(word)    (BITS ((word), 15, 20))
  64 #define FIELDC(word)    (BITS ((word),  9, 14))
  65
  66 #define OPCODE_AC(word)   (BITS ((word), 11, 15))
  67
  68 /* Functions implementation.  */
  69
  70 static bfd_vma
  71 bfd_getm32 (unsigned int data)
  72 {
  73   bfd_vma value = 0;
  74
  75   value = ((data & 0xff00) | (data & 0xff)) << 16;
  76   value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
  77   return value;
  78 }
  79
  80 static int
  81 special_flag_p (const char *opname,
  82                 const char *flgname)
  83 {
  84   const struct arc_flag_special *flg_spec;
  85   unsigned i, j, flgidx;
  86
  87   for (i = 0; i < arc_num_flag_special; i++)
  88     {
  89       flg_spec = &arc_flag_special_cases[i];
  90
  91       if (strcmp (opname, flg_spec->name))
  92         continue;
  93
  94       /* Found potential special case instruction.  */
  95       for (j=0;; ++j)
  96         {
  97           flgidx = flg_spec->flags[j];
  98           if (flgidx == 0)
  99             break; /* End of the array.  */
 100
 101           if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
 102             return 1;
 103         }
 104     }
 105   return 0;
 106 }
 107
 108 /* Disassemble ARC instructions.  */
 109
 110 static int
 111 print_insn_arc (bfd_vma memaddr,
 112                 struct disassemble_info *info)
 113 {
 114   bfd_byte buffer[4];
 115   unsigned int lowbyte, highbyte;
 116   int status;
 117   unsigned int i;
 118   int insnLen = 0;
 119   unsigned insn[2] = { 0, 0 };
 120   unsigned isa_mask;
 121   const unsigned char *opidx;
 122   const unsigned char *flgidx;
 123   const struct arc_opcode *opcode;
 124   const char *instrName;
 125   int flags;
 126   bfd_boolean need_comma;
 127   bfd_boolean open_braket;
 128   int size;
 129
 130   lowbyte  = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
 131   highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
 132
 133   switch (info->mach)
 134     {
 135     case bfd_mach_arc_nps400:
 136       isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
 137       break;
 138
 139     case bfd_mach_arc_arc700:
 140       isa_mask = ARC_OPCODE_ARC700;
 141       break;
 142
 143     case bfd_mach_arc_arc600:
 144       isa_mask = ARC_OPCODE_ARC600;
 145       break;
 146
 147     case bfd_mach_arc_arcv2:
 148     default:
 149       isa_mask = ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARCv2EM;
 150       break;
 151     }
 152
 153   /* This variable may be set by the instruction decoder.  It suggests
 154      the number of bytes objdump should display on a single line.  If
 155      the instruction decoder sets this, it should always set it to
 156      the same value in order to get reasonable looking output.  */
 157
 158   info->bytes_per_line  = 8;
 159
 160   /* In the next lines, we set two info variables control the way
 161      objdump displays the raw data.  For example, if bytes_per_line is
 162      8 and bytes_per_chunk is 4, the output will look like this:
 163      00:   00000000 00000000
 164      with the chunks displayed according to "display_endian".  */
 165
 166   if (info->section
 167       && !(info->section->flags & SEC_CODE))
 168     {
 169       /* This is not a CODE section.  */
 170       switch (info->section->size)
 171         {
 172         case 1:
 173         case 2:
 174         case 4:
 175           size = info->section->size;
 176           break;
 177         default:
 178           size = (info->section->size & 0x01) ? 1 : 4;
 179           break;
 180         }
 181       info->bytes_per_chunk = 1;
 182       info->display_endian = info->endian;
 183     }
 184   else
 185     {
 186       size = 2;
 187       info->bytes_per_chunk = 2;
 188       info->display_endian = info->endian;
 189     }
 190
 191   /* Read the insn into a host word.  */
 192   status = (*info->read_memory_func) (memaddr, buffer, size, info);
 193   if (status != 0)
 194     {
 195       (*info->memory_error_func) (status, memaddr, info);
 196       return -1;
 197     }
 198
 199   if (info->section
 200       && !(info->section->flags & SEC_CODE))
 201     {
 202       /* Data section.  */
 203       unsigned long data;
 204
 205       data = bfd_get_bits (buffer, size * 8,
 206                            info->display_endian == BFD_ENDIAN_BIG);
 207       switch (size)
 208         {
 209         case 1:
 210           (*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
 211           break;
 212         case 2:
 213           (*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
 214           break;
 215         case 4:
 216           (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
 217           break;
 218         default:
 219           abort ();
 220         }
 221       return size;
 222     }
 223
 224   if (   (((buffer[lowbyte] & 0xf8) > 0x38)
 225        && ((buffer[lowbyte] & 0xf8) != 0x48))
 226       || ((info->mach == bfd_mach_arc_arcv2)
 227           && ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly.  */
 228       )
 229     {
 230       /* This is a short instruction.  */
 231       insnLen = 2;
 232       insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
 233     }
 234   else
 235     {
 236       insnLen = 4;
 237
 238       /* This is a long instruction: Read the remaning 2 bytes.  */
 239       status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
 240       if (status != 0)
 241         {
 242           (*info->memory_error_func) (status, memaddr + 2, info);
 243           return -1;
 244         }
 245       insn[0] = ARRANGE_ENDIAN (info, buffer);
 246     }
 247
 248   /* Set some defaults for the insn info.  */
 249   info->insn_info_valid    = 1;
 250   info->branch_delay_insns = 0;
 251   info->data_size          = 0;
 252   info->insn_type          = dis_nonbranch;
 253   info->target             = 0;
 254   info->target2            = 0;
 255
 256   /* FIXME to be moved in dissasemble_init_for_target.  */
 257   info->disassembler_needs_relocs = TRUE;
 258
 259   /* Find the first match in the opcode table.  */
 260   for (i = 0; i < arc_num_opcodes; i++)
 261     {
 262       bfd_boolean invalid = FALSE;
 263
 264       opcode = &arc_opcodes[i];
 265
 266       if (ARC_SHORT (opcode->mask) && (insnLen == 2))
 267         {
 268           if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
 269             continue;
 270         }
 271       else if (!ARC_SHORT (opcode->mask) && (insnLen == 4))
 272         {
 273           if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
 274             continue;
 275         }
 276       else
 277         continue;
 278
 279       if ((insn[0] ^ opcode->opcode) & opcode->mask)
 280         continue;
 281
 282       if (!(opcode->cpu & isa_mask))
 283         continue;
 284
 285       /* Possible candidate, check the operands.  */
 286       for (opidx = opcode->operands; *opidx; opidx++)
 287         {
 288           int value;
 289           const struct arc_operand *operand = &arc_operands[*opidx];
 290
 291           if (operand->flags & ARC_OPERAND_FAKE)
 292             continue;
 293
 294           if (operand->extract)
 295             value = (*operand->extract) (insn[0], &invalid);
 296           else
 297             value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
 298
 299           /* Check for LIMM indicator.  If it is there, then make sure
 300              we pick the right format.  */
 301           if (operand->flags & ARC_OPERAND_IR
 302               && !(operand->flags & ARC_OPERAND_LIMM))
 303             {
 304               if ((value == 0x3E && insnLen == 4)
 305                   || (value == 0x1E && insnLen == 2))
 306                 {
 307                   invalid = TRUE;
 308                   break;
 309                 }
 310             }
 311         }
 312
 313       /* Check the flags.  */
 314       for (flgidx = opcode->flags; *flgidx; flgidx++)
 315         {
 316           /* Get a valid flag class.  */
 317           const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
 318           const unsigned *flgopridx;
 319           int foundA = 0, foundB = 0;
 320
 321           for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
 322             {
 323               const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx];
 324               unsigned int value;
 325
 326               value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1);
 327               if (value == flg_operand->code)
 328                 foundA = 1;
 329               if (value)
 330                 foundB = 1;
 331             }
 332           if (!foundA && foundB)
 333             {
 334               invalid = TRUE;
 335               break;
 336             }
 337         }
 338
 339       if (invalid)
 340         continue;
 341
 342       /* The instruction is valid.  */
 343       goto found;
 344     }
 345
 346   /* No instruction found.  Try the extenssions.  */
 347   instrName = arcExtMap_instName (OPCODE (insn[0]), insn[0], &flags);
 348   if (instrName)
 349     {
 350       opcode = &arc_opcodes[0];
 351       (*info->fprintf_func) (info->stream, "%s", instrName);
 352       goto print_flags;
 353     }
 354
 355   if (insnLen == 2)
 356     (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
 357   else
 358     (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
 359
 360   info->insn_type = dis_noninsn;
 361   return insnLen;
 362
 363  found:
 364   /* Print the mnemonic.  */
 365   (*info->fprintf_func) (info->stream, "%s", opcode->name);
 366
 367   /* Preselect the insn class.  */
 368   switch (opcode->class)
 369     {
 370     case BRANCH:
 371     case JUMP:
 372       if (!strncmp (opcode->name, "bl", 2)
 373           || !strncmp (opcode->name, "jl", 2))
 374         info->insn_type = dis_jsr;
 375       else
 376         info->insn_type = dis_branch;
 377       break;
 378     case MEMORY:
 379       info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
 380       break;
 381     default:
 382       info->insn_type = dis_nonbranch;
 383       break;
 384     }
 385
 386   pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
 387
 388  print_flags:
 389   /* Now extract and print the flags.  */
 390   for (flgidx = opcode->flags; *flgidx; flgidx++)
 391     {
 392       /* Get a valid flag class.  */
 393       const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
 394       const unsigned *flgopridx;
 395
 396       for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
 397         {
 398           const struct arc_flag_operand *flg_operand = &arc_flag_operands[*flgopridx];
 399           unsigned int value;
 400
 401           if (!flg_operand->favail)
 402             continue;
 403
 404           value = (insn[0] >> flg_operand->shift) & ((1 << flg_operand->bits) - 1);
 405           if (value == flg_operand->code)
 406             {
 407                /* FIXME!: print correctly nt/t flag.  */
 408               if (!special_flag_p (opcode->name, flg_operand->name))
 409                 (*info->fprintf_func) (info->stream, ".");
 410               else if (info->insn_type == dis_dref)
 411                 {
 412                   switch (flg_operand->name[0])
 413                     {
 414                     case 'b':
 415                       info->data_size = 1;
 416                       break;
 417                     case 'h':
 418                     case 'w':
 419                       info->data_size = 2;
 420                       break;
 421                     default:
 422                       info->data_size = 4;
 423                       break;
 424                     }
 425                 }
 426               (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
 427             }
 428
 429           if (flg_operand->name[0] == 'd'
 430               && flg_operand->name[1] == 0)
 431             info->branch_delay_insns = 1;
 432         }
 433     }
 434
 435   if (opcode->operands[0] != 0)
 436     (*info->fprintf_func) (info->stream, "\t");
 437
 438   need_comma = FALSE;
 439   open_braket = FALSE;
 440
 441   /* Now extract and print the operands.  */
 442   for (opidx = opcode->operands; *opidx; opidx++)
 443     {
 444       const struct arc_operand *operand = &arc_operands[*opidx];
 445       int value;
 446
 447       if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
 448         {
 449           (*info->fprintf_func) (info->stream, "]");
 450           open_braket = FALSE;
 451           continue;
 452         }
 453
 454       /* Only take input from real operands.  */
 455       if ((operand->flags & ARC_OPERAND_FAKE)
 456           && !(operand->flags & ARC_OPERAND_BRAKET))
 457         continue;
 458
 459       if (operand->extract)
 460         value = (*operand->extract) (insn[0], (int *) NULL);
 461       else
 462         {
 463           if (operand->flags & ARC_OPERAND_ALIGNED32)
 464             {
 465               value = (insn[0] >> operand->shift)
 466                 & ((1 << (operand->bits - 2)) - 1);
 467               value = value << 2;
 468             }
 469           else
 470             {
 471               value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
 472             }
 473           if (operand->flags & ARC_OPERAND_SIGNED)
 474             {
 475               int signbit = 1 << (operand->bits - 1);
 476               value = (value ^ signbit) - signbit;
 477             }
 478         }
 479
 480       if (operand->flags & ARC_OPERAND_IGNORE
 481           && (operand->flags & ARC_OPERAND_IR
 482               && value == -1))
 483         continue;
 484
 485       if (need_comma)
 486         (*info->fprintf_func) (info->stream, ",");
 487
 488       if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
 489         {
 490           (*info->fprintf_func) (info->stream, "[");
 491           open_braket = TRUE;
 492           need_comma = FALSE;
 493           continue;
 494         }
 495
 496       /* Read the limm operand, if required.  */
 497       if (operand->flags & ARC_OPERAND_LIMM
 498           && !(operand->flags & ARC_OPERAND_DUPLICATE))
 499         {
 500           status = (*info->read_memory_func) (memaddr + insnLen, buffer,
 501                                               4, info);
 502           if (status != 0)
 503             {
 504               (*info->memory_error_func) (status, memaddr + insnLen, info);
 505               return -1;
 506             }
 507           insn[1] = ARRANGE_ENDIAN (info, buffer);
 508         }
 509
 510       /* Print the operand as directed by the flags.  */
 511       if (operand->flags & ARC_OPERAND_IR)
 512         {
 513           assert (value >=0 && value < 64);
 514           (*info->fprintf_func) (info->stream, "%s", regnames[value]);
 515           if (operand->flags & ARC_OPERAND_TRUNCATE)
 516             (*info->fprintf_func) (info->stream, "%s", regnames[value+1]);
 517         }
 518       else if (operand->flags & ARC_OPERAND_LIMM)
 519         {
 520           (*info->fprintf_func) (info->stream, "%#x", insn[1]);
 521           if (info->insn_type == dis_branch
 522               || info->insn_type == dis_jsr)
 523             info->target = (bfd_vma) insn[1];
 524         }
 525       else if (operand->flags & ARC_OPERAND_PCREL)
 526         {
 527            /* PCL relative.  */
 528           if (info->flags & INSN_HAS_RELOC)
 529             memaddr = 0;
 530           (*info->print_address_func) ((memaddr & ~3) + value, info);
 531
 532           info->target = (bfd_vma) (memaddr & ~3) + value;
 533         }
 534       else if (operand->flags & ARC_OPERAND_SIGNED)
 535         (*info->fprintf_func) (info->stream, "%d", value);
 536       else
 537         if (operand->flags & ARC_OPERAND_TRUNCATE
 538             && !(operand->flags & ARC_OPERAND_ALIGNED32)
 539             && !(operand->flags & ARC_OPERAND_ALIGNED16)
 540             && value > 0 && value <= 14)
 541           (*info->fprintf_func) (info->stream, "r13-%s",
 542                                  regnames[13 + value - 1]);
 543         else
 544           (*info->fprintf_func) (info->stream, "%#x", value);
 545
 546       need_comma = TRUE;
 547
 548       /* Adjust insn len.  */
 549       if (operand->flags & ARC_OPERAND_LIMM
 550           && !(operand->flags & ARC_OPERAND_DUPLICATE))
 551         insnLen += 4;
 552     }
 553
 554   return insnLen;
 555 }
 556
 557
 558 disassembler_ftype
 559 arc_get_disassembler (bfd *abfd)
 560 {
 561   /* Read the extenssion insns and registers, if any.  */
 562   build_ARC_extmap (abfd);
 563   dump_ARC_extmap ();
 564
 565   return print_insn_arc;
 566 }
 567
 568 /* Disassemble ARC instructions.  Used by debugger.  */
 569
 570 struct arcDisState
 571 arcAnalyzeInstr (bfd_vma memaddr,
 572                  struct disassemble_info *info)
 573 {
 574   struct arcDisState ret;
 575   memset (&ret, 0, sizeof (struct arcDisState));
 576
 577   ret.instructionLen = print_insn_arc (memaddr, info);
 578
 579 #if 0
 580   ret.words[0] = insn[0];
 581   ret.words[1] = insn[1];
 582   ret._this = &ret;
 583   ret.coreRegName = _coreRegName;
 584   ret.auxRegName = _auxRegName;
 585   ret.condCodeName = _condCodeName;
 586   ret.instName = _instName;
 587 #endif
 588
 589   return ret;
 590 }
 591
 592 /* Local variables:
 593    eval: (c-set-style "gnu")
 594    indent-tabs-mode: t
 595    End:  */