1 /* Instruction printing code for the ARC.
2 Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2007, 2009,
3 2010, 2012 Free Software Foundation, Inc.
4 Contributed by Doug Evans (dje@cygnus.com).
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 #include "libiberty.h"
26 #include "opcode/arc.h"
39 /* Classification of the opcodes for the decoder to print
47 /* All branches other than JC. */
50 /* All loads other than immediate
56 /* All single operand instructions. */
57 CLASS_A4_OP3_SUBOPC3F
,
61 #define BIT(word,n) ((word) & (1 << n))
62 #define BITS(word,s,e) (((word) >> s) & ((1 << (e + 1 - s)) - 1))
63 #define OPCODE(word) (BITS ((word), 27, 31))
64 #define FIELDA(word) (BITS ((word), 21, 26))
65 #define FIELDB(word) (BITS ((word), 15, 20))
66 #define FIELDC(word) (BITS ((word), 9, 14))
68 /* FIELD D is signed. */
69 #define FIELDD(word) ((BITS ((word), 0, 8) ^ 0x100) - 0x100)
71 #define PUT_NEXT_WORD_IN(a) \
74 if (is_limm == 1 && !NEXT_WORD (1)) \
75 mwerror (state, _("Illegal limm reference in last instruction!\n")); \
76 a = state->words[1]; \
80 #define CHECK_FLAG_COND_NULLIFY() \
85 flag = BIT (state->words[0], 8); \
86 state->nullifyMode = BITS (state->words[0], 5, 6); \
87 cond = BITS (state->words[0], 0, 4); \
92 #define CHECK_COND() \
96 cond = BITS (state->words[0], 0, 4); \
100 #define CHECK_FIELD(field) \
107 PUT_NEXT_WORD_IN (field); \
108 limm_value = field; \
110 else if (field > 60) \
114 flag = (field == 61); \
115 field = FIELDD (state->words[0]); \
120 #define CHECK_FIELD_A() \
123 fieldA = FIELDA (state->words[0]); \
132 #define CHECK_FIELD_B() \
135 fieldB = FIELDB (state->words[0]); \
136 CHECK_FIELD (fieldB); \
140 #define CHECK_FIELD_C() \
143 fieldC = FIELDC (state->words[0]); \
144 CHECK_FIELD (fieldC); \
148 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
149 #define IS_REG(x) (field##x##isReg)
150 #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","")
151 #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[")
152 #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]")
153 #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]")
154 #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","")
155 #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",")
156 #define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","")
157 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
158 (IS_REG (x) ? cb1"%r"ca1 : \
159 usesAuxReg ? cb"%a"ca : \
160 IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
161 #define WRITE_FORMAT_RB() strcat (formatString, "]")
162 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
163 #define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
165 #define NEXT_WORD(x) (offset += 4, state->words[x])
167 #define add_target(x) (state->targets[state->tcnt++] = (x))
169 static char comment_prefix
[] = "\t; ";
172 core_reg_name (struct arcDisState
* state
, int val
)
174 if (state
->coreRegName
)
175 return (*state
->coreRegName
)(state
->_this
, val
);
180 aux_reg_name (struct arcDisState
* state
, int val
)
182 if (state
->auxRegName
)
183 return (*state
->auxRegName
)(state
->_this
, val
);
188 cond_code_name (struct arcDisState
* state
, int val
)
190 if (state
->condCodeName
)
191 return (*state
->condCodeName
)(state
->_this
, val
);
196 instruction_name (struct arcDisState
* state
,
202 return (*state
->instName
)(state
->_this
, op1
, op2
, flags
);
207 mwerror (struct arcDisState
* state
, const char * msg
)
210 (*state
->err
)(state
->_this
, (msg
));
214 post_address (struct arcDisState
* state
, int addr
)
216 static char id
[3 * ARRAY_SIZE (state
->addresses
)];
217 int j
, i
= state
->acnt
;
219 if (i
< ((int) ARRAY_SIZE (state
->addresses
)))
221 state
->addresses
[i
] = addr
;
234 arc_sprintf (struct arcDisState
*state
, char *buf
, const char *format
, ...)
238 int size
, leading_zero
, regMap
[2];
241 va_start (ap
, format
);
253 goto DOCOMM
; /* (return) */
277 leading_zero
= 1; /* e.g. %08x */
278 while (*p
>= '0' && *p
<= '9')
280 size
= size
* 10 + *p
- '0';
285 #define inc_bp() bp = bp + strlen (bp)
289 unsigned u
= va_arg (ap
, int);
291 /* Hex. We can change the format to 0x%08x in
292 one place, here, if we wish.
293 We add underscores for easy reading. */
295 sprintf (bp
, "0x%x_%04x", u
>> 16, u
& 0xffff);
297 sprintf (bp
, "0x%x", u
);
303 int val
= va_arg (ap
, int);
307 sprintf (bp
, "%0*x", size
, val
);
309 sprintf (bp
, "%*x", size
, val
);
311 sprintf (bp
, "%x", val
);
317 int val
= va_arg (ap
, int);
320 sprintf (bp
, "%*d", size
, val
);
322 sprintf (bp
, "%d", val
);
329 int val
= va_arg (ap
, int);
331 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
332 regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
339 REG2NAME (29, "ilink1");
340 REG2NAME (30, "ilink2");
341 REG2NAME (31, "blink");
342 REG2NAME (60, "lp_count");
347 ext
= core_reg_name (state
, val
);
349 sprintf (bp
, "%s", ext
);
351 sprintf (bp
,"r%d",val
);
361 int val
= va_arg (ap
, int);
363 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
367 AUXREG2NAME (0x0, "status");
368 AUXREG2NAME (0x1, "semaphore");
369 AUXREG2NAME (0x2, "lp_start");
370 AUXREG2NAME (0x3, "lp_end");
371 AUXREG2NAME (0x4, "identity");
372 AUXREG2NAME (0x5, "debug");
377 ext
= aux_reg_name (state
, val
);
379 sprintf (bp
, "%s", ext
);
381 arc_sprintf (state
, bp
, "%h", val
);
391 sprintf (bp
, "%s", va_arg (ap
, char *));
397 fprintf (stderr
, "?? format %c\n", p
[-1]);
407 write_comments_(struct arcDisState
* state
,
412 if (state
->commentBuffer
!= 0)
418 const char *name
= post_address (state
, limm_value
+ shimm
);
421 WRITE_COMMENT (name
);
423 for (i
= 0; i
< state
->commNum
; i
++)
426 strcpy (state
->commentBuffer
, comment_prefix
);
428 strcat (state
->commentBuffer
, ", ");
429 strcat (state
->commentBuffer
, state
->comm
[i
]);
434 #define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
435 #define write_comments() write_comments2 (0)
437 static const char *condName
[] =
440 "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
441 "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
445 write_instr_name_(struct arcDisState
* state
,
446 const char * instrName
,
448 int condCodeIsPartOfName
,
454 strcpy (state
->instrBuffer
, instrName
);
460 if (!condCodeIsPartOfName
)
461 strcat (state
->instrBuffer
, ".");
466 cc
= cond_code_name (state
, cond
);
471 strcat (state
->instrBuffer
, cc
);
475 strcat (state
->instrBuffer
, ".f");
477 switch (state
->nullifyMode
)
480 strcat (state
->instrBuffer
, ".d");
482 case BR_exec_when_jump
:
483 strcat (state
->instrBuffer
, ".jd");
488 strcat (state
->instrBuffer
, ".x");
491 strcat (state
->instrBuffer
, ".a");
494 strcat (state
->instrBuffer
, ".di");
497 #define write_instr_name() \
500 write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
501 flag, signExtend, addrWriteBack, directMem); \
502 formatString[0] = '\0'; \
508 op_LD0
= 0, op_LD1
= 1, op_ST
= 2, op_3
= 3,
509 op_BC
= 4, op_BLC
= 5, op_LPC
= 6, op_JC
= 7,
510 op_ADD
= 8, op_ADC
= 9, op_SUB
= 10, op_SBC
= 11,
511 op_AND
= 12, op_OR
= 13, op_BIC
= 14, op_XOR
= 15
514 extern disassemble_info tm_print_insn_info
;
517 dsmOneArcInst (bfd_vma addr
, struct arcDisState
* state
)
519 int condCodeIsPartOfName
= 0;
520 a4_decoding_class decodingClass
;
521 const char * instrName
;
535 int addrWriteBack
= 0;
542 char formatString
[60];
544 state
->instructionLen
= 4;
545 state
->nullifyMode
= BR_exec_when_no_jump
;
549 state
->_mem_load
= 0;
550 state
->_ea_present
= 0;
551 state
->_load_len
= 0;
552 state
->ea_reg1
= no_reg
;
553 state
->ea_reg2
= no_reg
;
559 state
->_opcode
= OPCODE (state
->words
[0]);
561 decodingClass
= CLASS_A4_ARITH
; /* default! */
563 condCodeIsPartOfName
=0;
567 state
->flow
= noflow
;
570 if (state
->commentBuffer
)
571 state
->commentBuffer
[0] = '\0';
573 switch (state
->_opcode
)
576 switch (BITS (state
->words
[0],1,2))
580 state
->_load_len
= 4;
584 state
->_load_len
= 1;
588 state
->_load_len
= 2;
591 instrName
= "??? (0[3])";
592 state
->flow
= invalid_instr
;
595 decodingClass
= CLASS_A4_LD0
;
599 if (BIT (state
->words
[0],13))
602 decodingClass
= CLASS_A4_LR
;
606 switch (BITS (state
->words
[0], 10, 11))
610 state
->_load_len
= 4;
614 state
->_load_len
= 1;
618 state
->_load_len
= 2;
621 instrName
= "??? (1[3])";
622 state
->flow
= invalid_instr
;
625 decodingClass
= CLASS_A4_LD1
;
630 if (BIT (state
->words
[0], 25))
633 decodingClass
= CLASS_A4_SR
;
637 switch (BITS (state
->words
[0], 22, 23))
649 instrName
= "??? (2[3])";
650 state
->flow
= invalid_instr
;
653 decodingClass
= CLASS_A4_ST
;
658 decodingClass
= CLASS_A4_OP3_GENERAL
; /* default for opcode 3... */
659 switch (FIELDC (state
->words
[0]))
663 decodingClass
= CLASS_A4_FLAG
;
691 decodingClass
= CLASS_A4_OP3_SUBOPC3F
;
692 switch (FIELDD (state
->words
[0]))
705 state
->flow
=invalid_instr
;
711 /* ARC Extension Library Instructions
712 NOTE: We assume that extension codes are these instrs. */
714 instrName
= instruction_name (state
,
716 FIELDC (state
->words
[0]),
721 state
->flow
= invalid_instr
;
723 if (flags
& IGNORE_FIRST_OPD
)
740 if (BITS (state
->words
[0],9,9))
751 condCodeIsPartOfName
= 1;
752 decodingClass
= ((state
->_opcode
== op_JC
) ? CLASS_A4_JC
: CLASS_A4_BRANCH
);
759 repeatsOp
= (FIELDC (state
->words
[0]) == FIELDB (state
->words
[0]));
761 switch (state
->_opcode
)
764 instrName
= (repeatsOp
? "asl" : "add");
767 instrName
= (repeatsOp
? "rlc" : "adc");
770 instrName
= (repeatsOp
? "mov" : "and");
775 case op_SUB
: instrName
= "sub";
777 case op_SBC
: instrName
= "sbc";
779 case op_OR
: instrName
= "or";
781 case op_BIC
: instrName
= "bic";
785 if (state
->words
[0] == 0x7fffffff)
787 /* NOP encoded as xor -1, -1, -1. */
789 decodingClass
= CLASS_A4_OP3_SUBOPC3F
;
796 instrName
= instruction_name (state
,state
->_opcode
,0,&flags
);
797 /* if (instrName) printf("FLAGS=0x%x\n", flags); */
801 state
->flow
=invalid_instr
;
803 if (flags
& IGNORE_FIRST_OPD
)
808 fieldAisReg
= fieldBisReg
= fieldCisReg
= 1; /* Assume regs for now. */
809 flag
= cond
= is_shimm
= is_limm
= 0;
810 state
->nullifyMode
= BR_exec_when_no_jump
; /* 0 */
811 signExtend
= addrWriteBack
= directMem
= 0;
814 switch (decodingClass
)
821 CHECK_FLAG_COND_NULLIFY ();
827 WRITE_FORMAT_COMMA_x (B
);
829 WRITE_FORMAT_COMMA_x (C
);
830 WRITE_NOP_COMMENT ();
831 arc_sprintf (state
, state
->operandBuffer
, formatString
,
832 fieldA
, fieldB
, fieldC
);
838 WRITE_FORMAT_COMMA_x (C
);
839 arc_sprintf (state
, state
->operandBuffer
, formatString
,
845 case CLASS_A4_OP3_GENERAL
:
848 CHECK_FLAG_COND_NULLIFY ();
854 WRITE_FORMAT_COMMA_x (B
);
855 WRITE_NOP_COMMENT ();
856 arc_sprintf (state
, state
->operandBuffer
, formatString
,
862 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
);
869 CHECK_FLAG_COND_NULLIFY ();
870 flag
= 0; /* This is the FLAG instruction -- it's redundant. */
874 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
);
878 case CLASS_A4_BRANCH
:
879 fieldA
= BITS (state
->words
[0],7,26) << 2;
880 fieldA
= (fieldA
<< 10) >> 10; /* Make it signed. */
882 CHECK_FLAG_COND_NULLIFY ();
886 /* This address could be a label we know. Convert it. */
887 if (state
->_opcode
!= op_LPC
/* LP */)
889 add_target (fieldA
); /* For debugger. */
890 state
->flow
= state
->_opcode
== op_BLC
/* BL */
893 /* indirect calls are achieved by "lr blink,[status];
894 lr dest<- func addr; j [dest]" */
897 strcat (formatString
, "%s"); /* Address/label name. */
898 arc_sprintf (state
, state
->operandBuffer
, formatString
,
899 post_address (state
, fieldA
));
904 /* For op_JC -- jump to address specified.
905 Also covers jump and link--bit 9 of the instr. word
906 selects whether linked, thus "is_linked" is set above. */
909 CHECK_FLAG_COND_NULLIFY ();
914 fieldA
= (fieldB
>> 25) & 0x7F; /* Flags. */
915 fieldB
= (fieldB
& 0xFFFFFF) << 2;
916 state
->flow
= is_linked
? direct_call
: direct_jump
;
918 /* Screwy JLcc requires .jd mode to execute correctly
919 but we pretend it is .nd (no delay slot). */
920 if (is_linked
&& state
->nullifyMode
== BR_exec_when_jump
)
921 state
->nullifyMode
= BR_exec_when_no_jump
;
925 state
->flow
= is_linked
? indirect_call
: indirect_jump
;
926 /* We should also treat this as indirect call if NOT linked
927 but the preceding instruction was a "lr blink,[status]"
928 and we have a delay slot with "add blink,blink,2".
929 For now we can't detect such. */
930 state
->register_for_indirect_jump
= fieldB
;
934 strcat (formatString
,
935 IS_REG (B
) ? "[%r]" : "%s"); /* Address/label name. */
939 WRITE_FORMAT_COMMA_x (A
);
942 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
, fieldA
);
944 arc_sprintf (state
, state
->operandBuffer
, formatString
,
945 post_address (state
, fieldB
), fieldA
);
951 B and C can be regs, or one (both?) can be limm. */
956 printf ("5:b reg %d %d c reg %d %d \n",
957 fieldBisReg
,fieldB
,fieldCisReg
,fieldC
);
959 state
->_ea_present
= 1;
961 state
->ea_reg1
= fieldB
;
963 state
->_offset
+= fieldB
;
965 state
->ea_reg2
= fieldC
;
967 state
->_offset
+= fieldC
;
968 state
->_mem_load
= 1;
970 directMem
= BIT (state
->words
[0], 5);
971 addrWriteBack
= BIT (state
->words
[0], 3);
972 signExtend
= BIT (state
->words
[0], 0);
975 WRITE_FORMAT_x_COMMA_LB(A
);
976 if (fieldBisReg
|| fieldB
!= 0)
977 WRITE_FORMAT_x_COMMA (B
);
981 WRITE_FORMAT_x_RB (C
);
982 arc_sprintf (state
, state
->operandBuffer
, formatString
,
983 fieldA
, fieldB
, fieldC
);
988 /* LD instruction. */
991 fieldC
= FIELDD (state
->words
[0]);
994 printf ("6:b reg %d %d c 0x%x \n",
995 fieldBisReg
, fieldB
, fieldC
);
996 state
->_ea_present
= 1;
997 state
->_offset
= fieldC
;
998 state
->_mem_load
= 1;
1000 state
->ea_reg1
= fieldB
;
1001 /* Field B is either a shimm (same as fieldC) or limm (different!)
1002 Say ea is not present, so only one of us will do the name lookup. */
1004 state
->_offset
+= fieldB
, state
->_ea_present
= 0;
1006 directMem
= BIT (state
->words
[0],14);
1007 addrWriteBack
= BIT (state
->words
[0],12);
1008 signExtend
= BIT (state
->words
[0],9);
1010 write_instr_name ();
1011 WRITE_FORMAT_x_COMMA_LB (A
);
1014 fieldB
= state
->_offset
;
1015 WRITE_FORMAT_x_RB (B
);
1020 if (fieldC
!= 0 && !BIT (state
->words
[0],13))
1023 WRITE_FORMAT_COMMA_x_RB (C
);
1028 arc_sprintf (state
, state
->operandBuffer
, formatString
,
1029 fieldA
, fieldB
, fieldC
);
1034 /* ST instruction. */
1037 fieldA
= FIELDD(state
->words
[0]); /* shimm */
1040 if (dbg
) printf("7:b reg %d %x off %x\n",
1041 fieldBisReg
,fieldB
,fieldA
);
1042 state
->_ea_present
= 1;
1043 state
->_offset
= fieldA
;
1045 state
->ea_reg1
= fieldB
;
1046 /* Field B is either a shimm (same as fieldA) or limm (different!)
1047 Say ea is not present, so only one of us will do the name lookup.
1048 (for is_limm we do the name translation here). */
1050 state
->_offset
+= fieldB
, state
->_ea_present
= 0;
1052 directMem
= BIT (state
->words
[0], 26);
1053 addrWriteBack
= BIT (state
->words
[0], 24);
1055 write_instr_name ();
1056 WRITE_FORMAT_x_COMMA_LB(C
);
1060 fieldB
= state
->_offset
;
1061 WRITE_FORMAT_x_RB (B
);
1066 if (fieldBisReg
&& fieldA
!= 0)
1069 WRITE_FORMAT_COMMA_x_RB(A
);
1074 arc_sprintf (state
, state
->operandBuffer
, formatString
,
1075 fieldC
, fieldB
, fieldA
);
1076 write_comments2 (fieldA
);
1080 /* SR instruction */
1084 write_instr_name ();
1085 WRITE_FORMAT_x_COMMA_LB(C
);
1086 /* Try to print B as an aux reg if it is not a core reg. */
1090 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldC
, fieldB
);
1094 case CLASS_A4_OP3_SUBOPC3F
:
1095 write_instr_name ();
1096 state
->operandBuffer
[0] = '\0';
1100 /* LR instruction */
1104 write_instr_name ();
1105 WRITE_FORMAT_x_COMMA_LB (A
);
1106 /* Try to print B as an aux reg if it is not a core reg. */
1110 arc_sprintf (state
, state
->operandBuffer
, formatString
, fieldA
, fieldB
);
1115 mwerror (state
, "Bad decoding class in ARC disassembler");
1119 state
->_cond
= cond
;
1120 return state
->instructionLen
= offset
;
1124 /* Returns the name the user specified core extension register. */
1127 _coreRegName(void * arg ATTRIBUTE_UNUSED
, int regval
)
1129 return arcExtMap_coreRegName (regval
);
1132 /* Returns the name the user specified AUX extension register. */
1135 _auxRegName(void *_this ATTRIBUTE_UNUSED
, int regval
)
1137 return arcExtMap_auxRegName(regval
);
1140 /* Returns the name the user specified condition code name. */
1143 _condCodeName(void *_this ATTRIBUTE_UNUSED
, int regval
)
1145 return arcExtMap_condCodeName(regval
);
1148 /* Returns the name the user specified extension instruction. */
1151 _instName (void *_this ATTRIBUTE_UNUSED
, int majop
, int minop
, int *flags
)
1153 return arcExtMap_instName(majop
, minop
, flags
);
1156 /* Decode an instruction returning the size of the instruction
1157 in bytes or zero if unrecognized. */
1160 decodeInstr (bfd_vma address
, /* Address of this instruction. */
1161 disassemble_info
* info
)
1165 struct arcDisState s
; /* ARC Disassembler state. */
1166 void *stream
= info
->stream
; /* Output stream. */
1167 fprintf_ftype func
= info
->fprintf_func
;
1169 memset (&s
, 0, sizeof(struct arcDisState
));
1171 /* read first instruction */
1172 status
= (*info
->read_memory_func
) (address
, buffer
, 4, info
);
1175 (*info
->memory_error_func
) (status
, address
, info
);
1178 if (info
->endian
== BFD_ENDIAN_LITTLE
)
1179 s
.words
[0] = bfd_getl32(buffer
);
1181 s
.words
[0] = bfd_getb32(buffer
);
1182 /* Always read second word in case of limm. */
1184 /* We ignore the result since last insn may not have a limm. */
1185 status
= (*info
->read_memory_func
) (address
+ 4, buffer
, 4, info
);
1186 if (info
->endian
== BFD_ENDIAN_LITTLE
)
1187 s
.words
[1] = bfd_getl32(buffer
);
1189 s
.words
[1] = bfd_getb32(buffer
);
1192 s
.coreRegName
= _coreRegName
;
1193 s
.auxRegName
= _auxRegName
;
1194 s
.condCodeName
= _condCodeName
;
1195 s
.instName
= _instName
;
1198 dsmOneArcInst (address
, & s
);
1200 /* Display the disassembly instruction. */
1201 (*func
) (stream
, "%08lx ", s
.words
[0]);
1202 (*func
) (stream
, " ");
1203 (*func
) (stream
, "%-10s ", s
.instrBuffer
);
1205 if (__TRANSLATION_REQUIRED (s
))
1207 bfd_vma addr
= s
.addresses
[s
.operandBuffer
[1] - '0'];
1209 (*info
->print_address_func
) ((bfd_vma
) addr
, info
);
1210 (*func
) (stream
, "\n");
1213 (*func
) (stream
, "%s",s
.operandBuffer
);
1215 return s
.instructionLen
;
1218 /* Return the print_insn function to use.
1219 Side effect: load (possibly empty) extension section */
1222 arc_get_disassembler (void *ptr
)
1225 build_ARC_extmap ((struct bfd
*) ptr
);