1 /* Instruction printing code for the ARC.
2 Copyright 1994, 1995, 1997, 1998, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Doug Evans (dje@cygnus.com).
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #include <libiberty.h>
23 #include "opcode/arc.h"
38 #define BIT(word,n) ((word) & (1 << n))
39 #define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
40 #define OPCODE(word) (BITS ((word), 27, 31))
41 #define FIELDA(word) (BITS ((word), 21, 26))
42 #define FIELDB(word) (BITS ((word), 15, 20))
43 #define FIELDC(word) (BITS ((word), 9, 14))
45 /* FIELD D is signed in all of its uses, so we make sure argument is
46 treated as signed for bit shifting purposes: */
47 #define FIELDD(word) (BITS (((signed int)word), 0, 8))
49 #define PUT_NEXT_WORD_IN(a) \
52 if (is_limm == 1 && !NEXT_WORD (1)) \
53 mwerror (state, _("Illegal limm reference in last instruction!\n")); \
54 a = state->words[1]; \
58 #define CHECK_FLAG_COND_NULLIFY() \
63 flag = BIT (state->words[0], 8); \
64 state->nullifyMode = BITS (state->words[0], 5, 6); \
65 cond = BITS (state->words[0], 0, 4); \
70 #define CHECK_COND() \
74 cond = BITS (state->words[0], 0, 4); \
78 #define CHECK_FIELD(field) \
85 PUT_NEXT_WORD_IN (field); \
88 else if (field > 60) \
92 flag = (field == 61); \
93 field = FIELDD (state->words[0]); \
98 #define CHECK_FIELD_A() \
101 fieldA = FIELDA(state->words[0]); \
110 #define CHECK_FIELD_B() \
113 fieldB = FIELDB (state->words[0]); \
114 CHECK_FIELD (fieldB); \
118 #define CHECK_FIELD_C() \
121 fieldC = FIELDC (state->words[0]); \
122 CHECK_FIELD (fieldC); \
126 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
127 #define IS_REG(x) (field##x##isReg)
128 #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x,"[","]","","")
129 #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x,"",",[","",",[")
130 #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x,",","]",",","]")
131 #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x,"","]","","]")
132 #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x,",","",",","")
133 #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x,"",",","",",")
134 #define WRITE_FORMAT_x(x) WRITE_FORMAT(x,"","","","")
135 #define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
136 (IS_REG (x) ? cb1"%r"ca1 : \
137 usesAuxReg ? cb"%a"ca : \
138 IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
139 #define WRITE_FORMAT_RB() strcat (formatString, "]")
140 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
141 #define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
143 #define NEXT_WORD(x) (offset += 4, state->words[x])
145 #define add_target(x) (state->targets[state->tcnt++] = (x))
147 static char comment_prefix
[] = "\t; ";
149 static const char *core_reg_name
PARAMS ((struct arcDisState
*, int));
150 static const char *aux_reg_name
PARAMS ((struct arcDisState
*, int));
151 static const char *cond_code_name
PARAMS ((struct arcDisState
*, int));
152 static const char *instruction_name
153 PARAMS ((struct arcDisState
*, int, int, int *));
154 static void mwerror
PARAMS ((struct arcDisState
*, const char *));
155 static const char *post_address
PARAMS ((struct arcDisState
*, int));
156 static void write_comments_
157 PARAMS ((struct arcDisState
*, int, int, long int));
158 static void write_instr_name_
159 PARAMS ((struct arcDisState
*, const char *, int, int, int, int, int, int));
160 static int dsmOneArcInst
PARAMS ((bfd_vma
, struct arcDisState
*));
161 static const char *_coreRegName
PARAMS ((void *, int));
162 static int decodeInstr
PARAMS ((bfd_vma
, disassemble_info
*));
165 core_reg_name (state
, val
)
166 struct arcDisState
* state
;
169 if (state
->coreRegName
)
170 return (*state
->coreRegName
)(state
->_this
, val
);
175 aux_reg_name (state
, val
)
176 struct arcDisState
* state
;
179 if (state
->auxRegName
)
180 return (*state
->auxRegName
)(state
->_this
, val
);
185 cond_code_name (state
, val
)
186 struct arcDisState
* state
;
189 if (state
->condCodeName
)
190 return (*state
->condCodeName
)(state
->_this
, val
);
195 instruction_name (state
, op1
, op2
, flags
)
196 struct arcDisState
* state
;
202 return (*state
->instName
)(state
->_this
, op1
, op2
, flags
);
208 struct arcDisState
* state
;
212 (*state
->err
)(state
->_this
, (msg
));
216 post_address (state
, addr
)
217 struct arcDisState
* state
;
220 static char id
[3 * ARRAY_SIZE (state
->addresses
)];
221 int j
, i
= state
->acnt
;
223 if (i
< ((int) ARRAY_SIZE (state
->addresses
)))
225 state
->addresses
[i
] = addr
;
239 struct arcDisState
* state
,
246 int size
, leading_zero
, regMap
[2];
250 va_start (ap
, format
);
263 goto DOCOMM
; /* (return) */
287 leading_zero
= 1; /* e.g. %08x */
288 while (*p
>= '0' && *p
<= '9')
290 size
= size
* 10 + *p
- '0';
295 #define inc_bp() bp = bp + strlen (bp)
299 unsigned u
= va_arg (ap
, int);
301 /* Hex. We can change the format to 0x%08x in
302 one place, here, if we wish.
303 We add underscores for easy reading. */
305 sprintf (bp
, "0x%x_%04x", u
>> 16, u
& 0xffff);
307 sprintf (bp
, "0x%x", u
);
313 int val
= va_arg (ap
, int);
317 sprintf (bp
, "%0*x", size
, val
);
319 sprintf (bp
, "%*x", size
, val
);
321 sprintf (bp
, "%x", val
);
327 int val
= va_arg (ap
, int);
330 sprintf (bp
, "%*d", size
, val
);
332 sprintf (bp
, "%d", val
);
339 int val
= va_arg (ap
, int);
341 #define REG2NAME(num, name) case num: sprintf (bp, ""name); \
342 regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
349 REG2NAME (29, "ilink1");
350 REG2NAME (30, "ilink2");
351 REG2NAME (31, "blink");
352 REG2NAME (60, "lp_count");
357 ext
= core_reg_name (state
, val
);
359 sprintf (bp
, "%s", ext
);
361 sprintf (bp
,"r%d",val
);
371 int val
= va_arg (ap
, int);
373 #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
377 AUXREG2NAME (0x0, "status");
378 AUXREG2NAME (0x1, "semaphore");
379 AUXREG2NAME (0x2, "lp_start");
380 AUXREG2NAME (0x3, "lp_end");
381 AUXREG2NAME (0x4, "identity");
382 AUXREG2NAME (0x5, "debug");
387 ext
= aux_reg_name (state
, val
);
389 sprintf (bp
, "%s", ext
);
391 my_sprintf (state
, bp
, "%h", val
);
401 sprintf (bp
, "%s", va_arg (ap
, char *));
407 fprintf (stderr
, "?? format %c\n", p
[-1]);
416 write_comments_(state
, shimm
, is_limm
, limm_value
)
417 struct arcDisState
* state
;
422 if (state
->commentBuffer
!= 0)
428 const char *name
= post_address (state
, limm_value
+ shimm
);
431 WRITE_COMMENT (name
);
433 for (i
= 0; i
< state
->commNum
; i
++)
436 strcpy (state
->commentBuffer
, comment_prefix
);
438 strcat (state
->commentBuffer
, ", ");
439 strncat (state
->commentBuffer
, state
->comm
[i
], sizeof (state
->commentBuffer
));
444 #define write_comments2(x) write_comments_(state, x, is_limm, limm_value)
445 #define write_comments() write_comments2(0)
447 static const char *condName
[] = {
449 "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
450 "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
454 write_instr_name_(state
, instrName
, cond
, condCodeIsPartOfName
, flag
, signExtend
, addrWriteBack
, directMem
)
455 struct arcDisState
* state
;
456 const char * instrName
;
458 int condCodeIsPartOfName
;
464 strcpy (state
->instrBuffer
, instrName
);
470 if (!condCodeIsPartOfName
)
471 strcat (state
->instrBuffer
, ".");
476 cc
= cond_code_name (state
, cond
);
481 strcat (state
->instrBuffer
, cc
);
485 strcat (state
->instrBuffer
, ".f");
487 switch (state
->nullifyMode
)
490 strcat (state
->instrBuffer
, ".d");
492 case BR_exec_when_jump
:
493 strcat (state
->instrBuffer
, ".jd");
498 strcat (state
->instrBuffer
, ".x");
501 strcat (state
->instrBuffer
, ".a");
504 strcat (state
->instrBuffer
, ".di");
507 #define write_instr_name() \
510 write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
511 flag, signExtend, addrWriteBack, directMem); \
512 formatString[0] = '\0'; \
517 op_LD0
= 0, op_LD1
= 1, op_ST
= 2, op_3
= 3,
518 op_BC
= 4, op_BLC
= 5, op_LPC
= 6, op_JC
= 7,
519 op_ADD
= 8, op_ADC
= 9, op_SUB
= 10, op_SBC
= 11,
520 op_AND
= 12, op_OR
= 13, op_BIC
= 14, op_XOR
= 15
523 extern disassemble_info tm_print_insn_info
;
526 dsmOneArcInst (addr
, state
)
528 struct arcDisState
* state
;
530 int condCodeIsPartOfName
= 0;
532 const char * instrName
;
546 int addrWriteBack
= 0;
553 char formatString
[60];
555 state
->instructionLen
= 4;
556 state
->nullifyMode
= BR_exec_when_no_jump
;
560 state
->_mem_load
= 0;
561 state
->_ea_present
= 0;
562 state
->_load_len
= 0;
563 state
->ea_reg1
= no_reg
;
564 state
->ea_reg2
= no_reg
;
570 state
->_opcode
= OPCODE (state
->words
[0]);
572 decodingClass
= 0; /* default! */
574 condCodeIsPartOfName
=0;
578 state
->flow
= noflow
;
581 if (state
->commentBuffer
)
582 state
->commentBuffer
[0] = '\0';
584 switch (state
->_opcode
)
587 switch (BITS (state
->words
[0],1,2))
591 state
->_load_len
= 4;
595 state
->_load_len
= 1;
599 state
->_load_len
= 2;
602 instrName
= "??? (0[3])";
603 state
->flow
= invalid_instr
;
610 if (BIT (state
->words
[0],13))
617 switch (BITS (state
->words
[0],10,11))
621 state
->_load_len
= 4;
625 state
->_load_len
= 1;
629 state
->_load_len
= 2;
632 instrName
= "??? (1[3])";
633 state
->flow
= invalid_instr
;
641 if (BIT (state
->words
[0],25))
648 switch (BITS (state
->words
[0],22,23))
660 instrName
= "??? (2[3])";
661 state
->flow
= invalid_instr
;
669 decodingClass
= 1; /* default for opcode 3... */
670 switch (FIELDC (state
->words
[0]))
703 switch( FIELDD (state
->words
[0]) )
716 state
->flow
=invalid_instr
;
722 /* ARC Extension Library Instructions
723 NOTE: We assume that extension codes are these instrs. */
725 instrName
= instruction_name (state
,
727 FIELDC (state
->words
[0]),
732 state
->flow
= invalid_instr
;
734 if (flags
& IGNORE_FIRST_OPD
)
751 if (BITS (state
->words
[0],9,9))
762 condCodeIsPartOfName
= 1;
763 decodingClass
= ((state
->_opcode
== op_JC
) ? 4 : 3);
770 repeatsOp
= (FIELDC (state
->words
[0]) == FIELDB (state
->words
[0]));
773 switch (state
->_opcode
)
776 instrName
= (repeatsOp
? "asl" : "add");
779 instrName
= (repeatsOp
? "rlc" : "adc");
782 instrName
= (repeatsOp
? "mov" : "and");
787 case op_SUB
: instrName
= "sub";
789 case op_SBC
: instrName
= "sbc";
791 case op_OR
: instrName
= "or";
793 case op_BIC
: instrName
= "bic";
797 if (state
->words
[0] == 0x7fffffff)
799 /* nop encoded as xor -1, -1, -1 */
808 instrName
= instruction_name (state
,state
->_opcode
,0,&flags
);
809 /* if (instrName) printf("FLAGS=0x%x\n", flags); */
813 state
->flow
=invalid_instr
;
815 if (flags
& IGNORE_FIRST_OPD
)
820 fieldAisReg
= fieldBisReg
= fieldCisReg
= 1; /* Assume regs for now. */
821 flag
= cond
= is_shimm
= is_limm
= 0;
822 state
->nullifyMode
= BR_exec_when_no_jump
; /* 0 */
823 signExtend
= addrWriteBack
= directMem
= 0;
826 switch (decodingClass
)
833 CHECK_FLAG_COND_NULLIFY ();
839 WRITE_FORMAT_COMMA_x (B
);
841 WRITE_FORMAT_COMMA_x (C
);
842 WRITE_NOP_COMMENT ();
843 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldA
, fieldB
, fieldC
);
849 WRITE_FORMAT_COMMA_x (C
);
850 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
, fieldC
);
858 CHECK_FLAG_COND_NULLIFY ();
864 WRITE_FORMAT_COMMA_x (B
);
865 WRITE_NOP_COMMENT ();
866 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldA
, fieldB
);
871 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
);
878 CHECK_FLAG_COND_NULLIFY ();
879 flag
= 0; /* this is the FLAG instruction -- it's redundant */
883 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
);
888 fieldA
= BITS (state
->words
[0],7,26) << 2;
889 fieldA
= (fieldA
<< 10) >> 10; /* make it signed */
891 CHECK_FLAG_COND_NULLIFY ();
895 /* This address could be a label we know. Convert it. */
896 if (state
->_opcode
!= op_LPC
/* LP */)
898 add_target (fieldA
); /* For debugger. */
899 state
->flow
= state
->_opcode
== op_BLC
/* BL */
902 /* indirect calls are achieved by "lr blink,[status];
903 lr dest<- func addr; j [dest]" */
906 strcat (formatString
, "%s"); /* address/label name */
907 my_sprintf (state
, state
->operandBuffer
, formatString
, post_address (state
, fieldA
));
912 /* For op_JC -- jump to address specified.
913 Also covers jump and link--bit 9 of the instr. word
914 selects whether linked, thus "is_linked" is set above. */
917 CHECK_FLAG_COND_NULLIFY ();
922 fieldA
= (fieldB
>> 25) & 0x7F; /* flags */
923 fieldB
= (fieldB
& 0xFFFFFF) << 2;
924 state
->flow
= is_linked
? direct_call
: direct_jump
;
926 /* screwy JLcc requires .jd mode to execute correctly
927 * but we pretend it is .nd (no delay slot). */
928 if (is_linked
&& state
->nullifyMode
== BR_exec_when_jump
)
929 state
->nullifyMode
= BR_exec_when_no_jump
;
933 state
->flow
= is_linked
? indirect_call
: indirect_jump
;
934 /* We should also treat this as indirect call if NOT linked
935 * but the preceding instruction was a "lr blink,[status]"
936 * and we have a delay slot with "add blink,blink,2".
937 * For now we can't detect such. */
938 state
->register_for_indirect_jump
= fieldB
;
942 strcat (formatString
,
943 IS_REG (B
) ? "[%r]" : "%s"); /* address/label name */
947 WRITE_FORMAT_COMMA_x (A
);
950 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldB
, fieldA
);
952 my_sprintf (state
, state
->operandBuffer
, formatString
,
953 post_address (state
, fieldB
), fieldA
);
959 B and C can be regs, or one (both?) can be limm. */
964 printf ("5:b reg %d %d c reg %d %d \n",
965 fieldBisReg
,fieldB
,fieldCisReg
,fieldC
);
967 state
->_ea_present
= 1;
969 state
->ea_reg1
= fieldB
;
971 state
->_offset
+= fieldB
;
973 state
->ea_reg2
= fieldC
;
975 state
->_offset
+= fieldC
;
976 state
->_mem_load
= 1;
978 directMem
= BIT (state
->words
[0],5);
979 addrWriteBack
= BIT (state
->words
[0],3);
980 signExtend
= BIT (state
->words
[0],0);
983 WRITE_FORMAT_x_COMMA_LB(A
);
984 if (fieldBisReg
|| fieldB
!= 0)
985 WRITE_FORMAT_x_COMMA (B
);
989 WRITE_FORMAT_x_RB (C
);
990 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldA
, fieldB
, fieldC
);
995 /* LD instruction. */
998 fieldC
= FIELDD (state
->words
[0]);
1001 printf ("6:b reg %d %d c 0x%x \n",
1002 fieldBisReg
, fieldB
, fieldC
);
1003 state
->_ea_present
= 1;
1004 state
->_offset
= fieldC
;
1005 state
->_mem_load
= 1;
1007 state
->ea_reg1
= fieldB
;
1008 /* field B is either a shimm (same as fieldC) or limm (different!)
1009 Say ea is not present, so only one of us will do the name lookup. */
1011 state
->_offset
+= fieldB
, state
->_ea_present
= 0;
1013 directMem
= BIT (state
->words
[0],14);
1014 addrWriteBack
= BIT (state
->words
[0],12);
1015 signExtend
= BIT (state
->words
[0],9);
1017 write_instr_name ();
1018 WRITE_FORMAT_x_COMMA_LB (A
);
1021 fieldB
= state
->_offset
;
1022 WRITE_FORMAT_x_RB (B
);
1027 if (fieldC
!= 0 && !BIT (state
->words
[0],13))
1030 WRITE_FORMAT_COMMA_x_RB (C
);
1035 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldA
, fieldB
, fieldC
);
1040 /* ST instruction. */
1043 fieldA
= FIELDD(state
->words
[0]); /* shimm */
1046 if (dbg
) printf("7:b reg %d %x off %x\n",
1047 fieldBisReg
,fieldB
,fieldA
);
1048 state
->_ea_present
= 1;
1049 state
->_offset
= fieldA
;
1051 state
->ea_reg1
= fieldB
;
1052 /* field B is either a shimm (same as fieldA) or limm (different!)
1053 Say ea is not present, so only one of us will do the name lookup.
1054 (for is_limm we do the name translation here). */
1056 state
->_offset
+= fieldB
, state
->_ea_present
= 0;
1058 directMem
= BIT(state
->words
[0],26);
1059 addrWriteBack
= BIT(state
->words
[0],24);
1062 WRITE_FORMAT_x_COMMA_LB(C
);
1066 fieldB
= state
->_offset
;
1067 WRITE_FORMAT_x_RB(B
);
1072 if (fieldBisReg
&& fieldA
!= 0)
1075 WRITE_FORMAT_COMMA_x_RB(A
);
1080 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldC
, fieldB
, fieldA
);
1081 write_comments2(fieldA
);
1084 /* SR instruction */
1089 WRITE_FORMAT_x_COMMA_LB(C
);
1090 /* Try to print B as an aux reg if it is not a core reg. */
1094 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldC
, fieldB
);
1100 state
->operandBuffer
[0] = '\0';
1104 /* LR instruction */
1109 WRITE_FORMAT_x_COMMA_LB(A
);
1110 /* Try to print B as an aux reg if it is not a core reg. */
1114 my_sprintf (state
, state
->operandBuffer
, formatString
, fieldA
, fieldB
);
1121 state
->operandBuffer
[0] = '\0';
1125 mwerror (state
, "Bad decoding class in ARC disassembler");
1129 state
->_cond
= cond
;
1130 return state
->instructionLen
= offset
;
1134 /* Returns the name the user specified core extension register. */
1136 _coreRegName(arg
, regval
)
1137 void * arg ATTRIBUTE_UNUSED
;
1140 return arcExtMap_coreRegName (regval
);
1143 /* Returns the name the user specified AUX extension register. */
1145 _auxRegName(void *_this ATTRIBUTE_UNUSED
, int regval
)
1147 return arcExtMap_auxRegName(regval
);
1151 /* Returns the name the user specified condition code name. */
1153 _condCodeName(void *_this ATTRIBUTE_UNUSED
, int regval
)
1155 return arcExtMap_condCodeName(regval
);
1158 /* Returns the name the user specified extension instruction. */
1160 _instName (void *_this ATTRIBUTE_UNUSED
, int majop
, int minop
, int *flags
)
1162 return arcExtMap_instName(majop
, minop
, flags
);
1165 /* Decode an instruction returning the size of the instruction
1166 in bytes or zero if unrecognized. */
1168 decodeInstr (address
, info
)
1169 bfd_vma address
; /* Address of this instruction. */
1170 disassemble_info
* info
;
1174 struct arcDisState s
; /* ARC Disassembler state */
1175 void *stream
= info
->stream
; /* output stream */
1176 fprintf_ftype func
= info
->fprintf_func
;
1179 memset (&s
, 0, sizeof(struct arcDisState
));
1181 /* read first instruction */
1182 status
= (*info
->read_memory_func
) (address
, buffer
, 4, info
);
1185 (*info
->memory_error_func
) (status
, address
, info
);
1188 if (info
->endian
== BFD_ENDIAN_LITTLE
)
1189 s
.words
[0] = bfd_getl32(buffer
);
1191 s
.words
[0] = bfd_getb32(buffer
);
1192 /* always read second word in case of limm */
1194 /* we ignore the result since last insn may not have a limm */
1195 status
= (*info
->read_memory_func
) (address
+ 4, buffer
, 4, info
);
1196 if (info
->endian
== BFD_ENDIAN_LITTLE
)
1197 s
.words
[1] = bfd_getl32(buffer
);
1199 s
.words
[1] = bfd_getb32(buffer
);
1202 s
.coreRegName
= _coreRegName
;
1203 s
.auxRegName
= _auxRegName
;
1204 s
.condCodeName
= _condCodeName
;
1205 s
.instName
= _instName
;
1208 bytes
= dsmOneArcInst(address
, (void *)&s
);
1210 /* display the disassembly instruction */
1211 (*func
) (stream
, "%08x ", s
.words
[0]);
1212 (*func
) (stream
, " ");
1214 (*func
) (stream
, "%-10s ", s
.instrBuffer
);
1216 if (__TRANSLATION_REQUIRED(s
))
1218 bfd_vma addr
= s
.addresses
[s
.operandBuffer
[1] - '0'];
1219 (*info
->print_address_func
) ((bfd_vma
) addr
, info
);
1220 (*func
) (stream
, "\n");
1223 (*func
) (stream
, "%s",s
.operandBuffer
);
1224 return s
.instructionLen
;
1227 /* Return the print_insn function to use.
1228 Side effect: load (possibly empty) extension section */
1231 arc_get_disassembler (void *ptr
)
1234 build_ARC_extmap (ptr
);