opcodes/arc-dis.c

   1 /* Instruction printing code for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24 #include <stdio.h>
  25 #include <assert.h>
  26 #include "dis-asm.h"
  27 #include "opcode/arc.h"
  28 #include "arc-dis.h"
  29 #include "arc-ext.h"
  30
  31
  32 /* Globals variables.  */
  33
  34 static const char * const regnames[64] =
  35 {
  36   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  37   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  38   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  39   "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
  40
  41   "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  42   "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  43   "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
  44   "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
  45 };
  46
  47 /* Macros section.  */
  48
  49 #ifdef DEBUG
  50 # define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
  51 #else
  52 # define pr_debug(fmt, args...)
  53 #endif
  54
  55 #define ARRANGE_ENDIAN(info, buf)                                       \
  56   (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf))    \
  57    : bfd_getb32 (buf))
  58
  59 #define BITS(word,s,e)  (((word) << (sizeof (word) * 8 - 1 - e)) >>     \
  60                          (s + (sizeof (word) * 8 - 1 - e)))
  61 #define OPCODE(word)    (BITS ((word), 27, 31))
  62
  63 #define OPCODE_AC(word)   (BITS ((word), 11, 15))
  64
  65 /* Functions implementation.  */
  66
  67 static bfd_vma
  68 bfd_getm32 (unsigned int data)
  69 {
  70   bfd_vma value = 0;
  71
  72   value = ((data & 0xff00) | (data & 0xff)) << 16;
  73   value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
  74   return value;
  75 }
  76
  77 static int
  78 special_flag_p (const char *opname,
  79                 const char *flgname)
  80 {
  81   const struct arc_flag_special *flg_spec;
  82   unsigned i, j, flgidx;
  83
  84   for (i = 0; i < arc_num_flag_special; i++)
  85     {
  86       flg_spec = &arc_flag_special_cases[i];
  87
  88       if (strcmp (opname, flg_spec->name))
  89         continue;
  90
  91       /* Found potential special case instruction.  */
  92       for (j=0;; ++j)
  93         {
  94           flgidx = flg_spec->flags[j];
  95           if (flgidx == 0)
  96             break; /* End of the array.  */
  97
  98           if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
  99             return 1;
 100         }
 101     }
 102   return 0;
 103 }
 104
 105 /* Find proper format for the given opcode.  */
 106 static const struct arc_opcode *
 107 find_format (const struct arc_opcode *arc_table,
 108              unsigned *insn, int insnLen,
 109              unsigned isa_mask)
 110 {
 111   unsigned int i = 0;
 112   const struct arc_opcode *opcode = NULL;
 113   const unsigned char *opidx;
 114   const unsigned char *flgidx;
 115
 116   do {
 117     bfd_boolean invalid = FALSE;
 118
 119     opcode = &arc_table[i++];
 120
 121     if (ARC_SHORT (opcode->mask) && (insnLen == 2))
 122       {
 123         if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
 124           continue;
 125       }
 126     else if (!ARC_SHORT (opcode->mask) && (insnLen == 4))
 127       {
 128         if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
 129           continue;
 130       }
 131     else
 132       continue;
 133
 134     if ((insn[0] ^ opcode->opcode) & opcode->mask)
 135       continue;
 136
 137     if (!(opcode->cpu & isa_mask))
 138       continue;
 139
 140     /* Possible candidate, check the operands.  */
 141     for (opidx = opcode->operands; *opidx; opidx++)
 142       {
 143         int value;
 144         const struct arc_operand *operand = &arc_operands[*opidx];
 145
 146         if (operand->flags & ARC_OPERAND_FAKE)
 147           continue;
 148
 149         if (operand->extract)
 150           value = (*operand->extract) (insn[0], &invalid);
 151         else
 152           value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
 153
 154         /* Check for LIMM indicator.  If it is there, then make sure
 155            we pick the right format.  */
 156         if (operand->flags & ARC_OPERAND_IR
 157             && !(operand->flags & ARC_OPERAND_LIMM))
 158           {
 159             if ((value == 0x3E && insnLen == 4)
 160                 || (value == 0x1E && insnLen == 2))
 161               {
 162                 invalid = TRUE;
 163                 break;
 164               }
 165           }
 166       }
 167
 168     /* Check the flags.  */
 169     for (flgidx = opcode->flags; *flgidx; flgidx++)
 170       {
 171         /* Get a valid flag class.  */
 172         const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
 173         const unsigned *flgopridx;
 174         int foundA = 0, foundB = 0;
 175         unsigned int value;
 176
 177         /* Check first the extensions.  */
 178         if (cl_flags->class & F_CLASS_EXTEND)
 179           {
 180             value = (insn[0] & 0x1F);
 181             if (arcExtMap_condCodeName (value))
 182               continue;
 183           }
 184         for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
 185           {
 186             const struct arc_flag_operand *flg_operand =
 187               &arc_flag_operands[*flgopridx];
 188
 189             value = (insn[0] >> flg_operand->shift)
 190               & ((1 << flg_operand->bits) - 1);
 191             if (value == flg_operand->code)
 192               foundA = 1;
 193             if (value)
 194               foundB = 1;
 195           }
 196         if (!foundA && foundB)
 197           {
 198             invalid = TRUE;
 199             break;
 200           }
 201       }
 202
 203     if (invalid)
 204       continue;
 205
 206     /* The instruction is valid.  */
 207     return opcode;
 208   } while (opcode->mask);
 209
 210   return NULL;
 211 }
 212
 213 static void
 214 print_flags (const struct arc_opcode *opcode,
 215              unsigned *insn,
 216              struct disassemble_info *info)
 217 {
 218   const unsigned char *flgidx;
 219   unsigned int value;
 220
 221   /* Now extract and print the flags.  */
 222   for (flgidx = opcode->flags; *flgidx; flgidx++)
 223     {
 224       /* Get a valid flag class.  */
 225       const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
 226       const unsigned *flgopridx;
 227
 228       /* Check first the extensions.  */
 229       if (cl_flags->class & F_CLASS_EXTEND)
 230         {
 231           const char *name;
 232           value = (insn[0] & 0x1F);
 233
 234           name = arcExtMap_condCodeName (value);
 235           if (name)
 236             {
 237               (*info->fprintf_func) (info->stream, ".%s", name);
 238               continue;
 239             }
 240         }
 241
 242       for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
 243         {
 244           const struct arc_flag_operand *flg_operand =
 245             &arc_flag_operands[*flgopridx];
 246
 247           if (!flg_operand->favail)
 248             continue;
 249
 250           value = (insn[0] >> flg_operand->shift)
 251             & ((1 << flg_operand->bits) - 1);
 252           if (value == flg_operand->code)
 253             {
 254                /* FIXME!: print correctly nt/t flag.  */
 255               if (!special_flag_p (opcode->name, flg_operand->name))
 256                 (*info->fprintf_func) (info->stream, ".");
 257               else if (info->insn_type == dis_dref)
 258                 {
 259                   switch (flg_operand->name[0])
 260                     {
 261                     case 'b':
 262                       info->data_size = 1;
 263                       break;
 264                     case 'h':
 265                     case 'w':
 266                       info->data_size = 2;
 267                       break;
 268                     default:
 269                       info->data_size = 4;
 270                       break;
 271                     }
 272                 }
 273               (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
 274             }
 275
 276           if (flg_operand->name[0] == 'd'
 277               && flg_operand->name[1] == 0)
 278             info->branch_delay_insns = 1;
 279         }
 280     }
 281 }
 282
 283 static const char *
 284 get_auxreg (const struct arc_opcode *opcode,
 285             int value,
 286             unsigned isa_mask)
 287 {
 288   const char *name;
 289   unsigned int i;
 290   const struct arc_aux_reg *auxr = &arc_aux_regs[0];
 291
 292   if (opcode->class != AUXREG)
 293     return NULL;
 294
 295   name = arcExtMap_auxRegName (value);
 296   if (name)
 297     return name;
 298
 299   for (i = 0; i < arc_num_aux_regs; i++, auxr++)
 300     {
 301       if (!(auxr->cpu & isa_mask))
 302         continue;
 303
 304       if (auxr->subclass != NONE)
 305         return NULL;
 306
 307       if (auxr->address == value)
 308         return auxr->name;
 309     }
 310   return NULL;
 311 }
 312 /* Disassemble ARC instructions.  */
 313
 314 static int
 315 print_insn_arc (bfd_vma memaddr,
 316                 struct disassemble_info *info)
 317 {
 318   bfd_byte buffer[4];
 319   unsigned int lowbyte, highbyte;
 320   int status;
 321   int insnLen = 0;
 322   unsigned insn[2] = { 0, 0 };
 323   unsigned isa_mask;
 324   const unsigned char *opidx;
 325   const struct arc_opcode *opcode;
 326   const extInstruction_t *einsn;
 327   bfd_boolean need_comma;
 328   bfd_boolean open_braket;
 329   int size;
 330
 331   lowbyte  = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
 332   highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
 333
 334   switch (info->mach)
 335     {
 336     case bfd_mach_arc_nps400:
 337       isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
 338       break;
 339
 340     case bfd_mach_arc_arc700:
 341       isa_mask = ARC_OPCODE_ARC700;
 342       break;
 343
 344     case bfd_mach_arc_arc600:
 345       isa_mask = ARC_OPCODE_ARC600;
 346       break;
 347
 348     case bfd_mach_arc_arcv2:
 349     default:
 350       isa_mask = ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARCv2EM;
 351       break;
 352     }
 353
 354   /* This variable may be set by the instruction decoder.  It suggests
 355      the number of bytes objdump should display on a single line.  If
 356      the instruction decoder sets this, it should always set it to
 357      the same value in order to get reasonable looking output.  */
 358
 359   info->bytes_per_line  = 8;
 360
 361   /* In the next lines, we set two info variables control the way
 362      objdump displays the raw data.  For example, if bytes_per_line is
 363      8 and bytes_per_chunk is 4, the output will look like this:
 364      00:   00000000 00000000
 365      with the chunks displayed according to "display_endian".  */
 366
 367   if (info->section
 368       && !(info->section->flags & SEC_CODE))
 369     {
 370       /* This is not a CODE section.  */
 371       switch (info->section->size)
 372         {
 373         case 1:
 374         case 2:
 375         case 4:
 376           size = info->section->size;
 377           break;
 378         default:
 379           size = (info->section->size & 0x01) ? 1 : 4;
 380           break;
 381         }
 382       info->bytes_per_chunk = 1;
 383       info->display_endian = info->endian;
 384     }
 385   else
 386     {
 387       size = 2;
 388       info->bytes_per_chunk = 2;
 389       info->display_endian = info->endian;
 390     }
 391
 392   /* Read the insn into a host word.  */
 393   status = (*info->read_memory_func) (memaddr, buffer, size, info);
 394   if (status != 0)
 395     {
 396       (*info->memory_error_func) (status, memaddr, info);
 397       return -1;
 398     }
 399
 400   if (info->section
 401       && !(info->section->flags & SEC_CODE))
 402     {
 403       /* Data section.  */
 404       unsigned long data;
 405
 406       data = bfd_get_bits (buffer, size * 8,
 407                            info->display_endian == BFD_ENDIAN_BIG);
 408       switch (size)
 409         {
 410         case 1:
 411           (*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
 412           break;
 413         case 2:
 414           (*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
 415           break;
 416         case 4:
 417           (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
 418           break;
 419         default:
 420           abort ();
 421         }
 422       return size;
 423     }
 424
 425   if ((((buffer[lowbyte] & 0xf8) > 0x38)
 426        && ((buffer[lowbyte] & 0xf8) != 0x48))
 427       || ((info->mach == bfd_mach_arc_arcv2)
 428           && ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly.  */
 429       )
 430     {
 431       /* This is a short instruction.  */
 432       insnLen = 2;
 433       insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
 434     }
 435   else
 436     {
 437       insnLen = 4;
 438
 439       /* This is a long instruction: Read the remaning 2 bytes.  */
 440       status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
 441       if (status != 0)
 442         {
 443           (*info->memory_error_func) (status, memaddr + 2, info);
 444           return -1;
 445         }
 446       insn[0] = ARRANGE_ENDIAN (info, buffer);
 447     }
 448
 449   /* Set some defaults for the insn info.  */
 450   info->insn_info_valid    = 1;
 451   info->branch_delay_insns = 0;
 452   info->data_size          = 0;
 453   info->insn_type          = dis_nonbranch;
 454   info->target             = 0;
 455   info->target2            = 0;
 456
 457   /* FIXME to be moved in dissasemble_init_for_target.  */
 458   info->disassembler_needs_relocs = TRUE;
 459
 460   /* Find the first match in the opcode table.  */
 461   opcode = find_format (arc_opcodes, insn, insnLen, isa_mask);
 462
 463   if (!opcode)
 464     {
 465       /* No instruction found.  Try the extensions.  */
 466       einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]);
 467       if (einsn)
 468         {
 469           const char *errmsg = NULL;
 470           opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg);
 471           if (opcode == NULL)
 472             {
 473               (*info->fprintf_func) (info->stream,
 474                                      "An error occured while "
 475                                      "generating the extension instruction "
 476                                      "operations");
 477               return -1;
 478             }
 479
 480           opcode = find_format (opcode, insn, insnLen, isa_mask);
 481           assert (opcode != NULL);
 482         }
 483       else
 484         {
 485           if (insnLen == 2)
 486             (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
 487           else
 488             (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
 489
 490           info->insn_type = dis_noninsn;
 491           return insnLen;
 492         }
 493     }
 494
 495   /* Print the mnemonic.  */
 496   (*info->fprintf_func) (info->stream, "%s", opcode->name);
 497
 498   /* Preselect the insn class.  */
 499   switch (opcode->class)
 500     {
 501     case BRANCH:
 502     case JUMP:
 503       if (!strncmp (opcode->name, "bl", 2)
 504           || !strncmp (opcode->name, "jl", 2))
 505         info->insn_type = dis_jsr;
 506       else
 507         info->insn_type = dis_branch;
 508       break;
 509     case MEMORY:
 510       info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
 511       break;
 512     default:
 513       info->insn_type = dis_nonbranch;
 514       break;
 515     }
 516
 517   pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
 518
 519   print_flags (opcode, insn, info);
 520
 521   if (opcode->operands[0] != 0)
 522     (*info->fprintf_func) (info->stream, "\t");
 523
 524   need_comma = FALSE;
 525   open_braket = FALSE;
 526
 527   /* Now extract and print the operands.  */
 528   for (opidx = opcode->operands; *opidx; opidx++)
 529     {
 530       const struct arc_operand *operand = &arc_operands[*opidx];
 531       int value;
 532
 533       if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
 534         {
 535           (*info->fprintf_func) (info->stream, "]");
 536           open_braket = FALSE;
 537           continue;
 538         }
 539
 540       /* Only take input from real operands.  */
 541       if ((operand->flags & ARC_OPERAND_FAKE)
 542           && !(operand->flags & ARC_OPERAND_BRAKET))
 543         continue;
 544
 545       if (operand->extract)
 546         value = (*operand->extract) (insn[0], (int *) NULL);
 547       else
 548         {
 549           if (operand->flags & ARC_OPERAND_ALIGNED32)
 550             {
 551               value = (insn[0] >> operand->shift)
 552                 & ((1 << (operand->bits - 2)) - 1);
 553               value = value << 2;
 554             }
 555           else
 556             {
 557               value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
 558             }
 559           if (operand->flags & ARC_OPERAND_SIGNED)
 560             {
 561               int signbit = 1 << (operand->bits - 1);
 562               value = (value ^ signbit) - signbit;
 563             }
 564         }
 565
 566       if (operand->flags & ARC_OPERAND_IGNORE
 567           && (operand->flags & ARC_OPERAND_IR
 568               && value == -1))
 569         continue;
 570
 571       if (need_comma)
 572         (*info->fprintf_func) (info->stream, ",");
 573
 574       if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
 575         {
 576           (*info->fprintf_func) (info->stream, "[");
 577           open_braket = TRUE;
 578           need_comma = FALSE;
 579           continue;
 580         }
 581
 582       /* Read the limm operand, if required.  */
 583       if (operand->flags & ARC_OPERAND_LIMM
 584           && !(operand->flags & ARC_OPERAND_DUPLICATE))
 585         {
 586           status = (*info->read_memory_func) (memaddr + insnLen, buffer,
 587                                               4, info);
 588           if (status != 0)
 589             {
 590               (*info->memory_error_func) (status, memaddr + insnLen, info);
 591               return -1;
 592             }
 593           insn[1] = ARRANGE_ENDIAN (info, buffer);
 594         }
 595
 596       /* Print the operand as directed by the flags.  */
 597       if (operand->flags & ARC_OPERAND_IR)
 598         {
 599           const char *rname;
 600
 601           assert (value >=0 && value < 64);
 602           rname = arcExtMap_coreRegName (value);
 603           if (!rname)
 604             rname = regnames[value];
 605           (*info->fprintf_func) (info->stream, "%s", rname);
 606           if (operand->flags & ARC_OPERAND_TRUNCATE)
 607             {
 608               rname = arcExtMap_coreRegName (value + 1);
 609               if (!rname)
 610                 rname = regnames[value + 1];
 611               (*info->fprintf_func) (info->stream, "%s", rname);
 612             }
 613         }
 614       else if (operand->flags & ARC_OPERAND_LIMM)
 615         {
 616           const char *rname = get_auxreg (opcode, insn[1], isa_mask);
 617           if (rname && open_braket)
 618             (*info->fprintf_func) (info->stream, "%s", rname);
 619           else
 620             {
 621               (*info->fprintf_func) (info->stream, "%#x", insn[1]);
 622               if (info->insn_type == dis_branch
 623                   || info->insn_type == dis_jsr)
 624                 info->target = (bfd_vma) insn[1];
 625             }
 626         }
 627       else if (operand->flags & ARC_OPERAND_PCREL)
 628         {
 629            /* PCL relative.  */
 630           if (info->flags & INSN_HAS_RELOC)
 631             memaddr = 0;
 632           (*info->print_address_func) ((memaddr & ~3) + value, info);
 633
 634           info->target = (bfd_vma) (memaddr & ~3) + value;
 635         }
 636       else if (operand->flags & ARC_OPERAND_SIGNED)
 637         {
 638           const char *rname = get_auxreg (opcode, value, isa_mask);
 639           if (rname && open_braket)
 640             (*info->fprintf_func) (info->stream, "%s", rname);
 641           else
 642             (*info->fprintf_func) (info->stream, "%d", value);
 643         }
 644       else
 645         {
 646           if (operand->flags & ARC_OPERAND_TRUNCATE
 647               && !(operand->flags & ARC_OPERAND_ALIGNED32)
 648               && !(operand->flags & ARC_OPERAND_ALIGNED16)
 649               && value > 0 && value <= 14)
 650             (*info->fprintf_func) (info->stream, "r13-%s",
 651                                    regnames[13 + value - 1]);
 652           else
 653             {
 654               const char *rname = get_auxreg (opcode, value, isa_mask);
 655               if (rname && open_braket)
 656                 (*info->fprintf_func) (info->stream, "%s", rname);
 657               else
 658                 (*info->fprintf_func) (info->stream, "%#x", value);
 659             }
 660         }
 661
 662       need_comma = TRUE;
 663
 664       /* Adjust insn len.  */
 665       if (operand->flags & ARC_OPERAND_LIMM
 666           && !(operand->flags & ARC_OPERAND_DUPLICATE))
 667         insnLen += 4;
 668     }
 669
 670   return insnLen;
 671 }
 672
 673
 674 disassembler_ftype
 675 arc_get_disassembler (bfd *abfd)
 676 {
 677   /* Read the extenssion insns and registers, if any.  */
 678   build_ARC_extmap (abfd);
 679 #ifdef DEBUG
 680   dump_ARC_extmap ();
 681 #endif
 682
 683   return print_insn_arc;
 684 }
 685
 686 /* Disassemble ARC instructions.  Used by debugger.  */
 687
 688 struct arcDisState
 689 arcAnalyzeInstr (bfd_vma memaddr,
 690                  struct disassemble_info *info)
 691 {
 692   struct arcDisState ret;
 693   memset (&ret, 0, sizeof (struct arcDisState));
 694
 695   ret.instructionLen = print_insn_arc (memaddr, info);
 696
 697 #if 0
 698   ret.words[0] = insn[0];
 699   ret.words[1] = insn[1];
 700   ret._this = &ret;
 701   ret.coreRegName = _coreRegName;
 702   ret.auxRegName = _auxRegName;
 703   ret.condCodeName = _condCodeName;
 704   ret.instName = _instName;
 705 #endif
 706
 707   return ret;
 708 }
 709
 710 /* Local variables:
 711    eval: (c-set-style "gnu")
 712    indent-tabs-mode: t
 713    End:  */