1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 #include "opcode/arc.h"
27 #include "libiberty.h"
29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. All NPS400 features are built into all ARC target builds as
31 this reduces the chances that regressions might creep in. */
33 /* Insert RB register into a 32-bit opcode. */
34 static unsigned long long
35 insert_rb (unsigned long long insn
,
37 const char **errmsg ATTRIBUTE_UNUSED
)
39 return insn
| ((value
& 0x07) << 24) | (((value
>> 3) & 0x07) << 12);
43 extract_rb (unsigned long long insn ATTRIBUTE_UNUSED
,
44 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
46 int value
= (((insn
>> 12) & 0x07) << 3) | ((insn
>> 24) & 0x07);
48 if (value
== 0x3e && invalid
)
49 *invalid
= TRUE
; /* A limm operand, it should be extracted in a
55 static unsigned long long
56 insert_rad (unsigned long long insn
,
58 const char **errmsg ATTRIBUTE_UNUSED
)
61 *errmsg
= _("Improper register value.");
63 return insn
| (value
& 0x3F);
66 static unsigned long long
67 insert_rcd (unsigned long long insn
,
69 const char **errmsg ATTRIBUTE_UNUSED
)
72 *errmsg
= _("Improper register value.");
74 return insn
| ((value
& 0x3F) << 6);
77 /* Dummy insert ZERO operand function. */
79 static unsigned long long
80 insert_za (unsigned long long insn
,
85 *errmsg
= _("operand is not zero");
89 /* Insert Y-bit in bbit/br instructions. This function is called only
90 when solving fixups. */
92 static unsigned long long
93 insert_Ybit (unsigned long long insn
,
95 const char **errmsg ATTRIBUTE_UNUSED
)
103 /* Insert Y-bit in bbit/br instructions. This function is called only
104 when solving fixups. */
106 static unsigned long long
107 insert_NYbit (unsigned long long insn
,
109 const char **errmsg ATTRIBUTE_UNUSED
)
117 /* Insert H register into a 16-bit opcode. */
119 static unsigned long long
120 insert_rhv1 (unsigned long long insn
,
122 const char **errmsg ATTRIBUTE_UNUSED
)
124 return insn
|= ((value
& 0x07) << 5) | ((value
>> 3) & 0x07);
128 extract_rhv1 (unsigned long long insn ATTRIBUTE_UNUSED
,
129 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
131 int value
= ((insn
& 0x7) << 3) | ((insn
>> 5) & 0x7);
136 /* Insert H register into a 16-bit opcode. */
138 static unsigned long long
139 insert_rhv2 (unsigned long long insn
,
145 _("Register R30 is a limm indicator for this type of instruction.");
146 return insn
|= ((value
& 0x07) << 5) | ((value
>> 3) & 0x03);
150 extract_rhv2 (unsigned long long insn ATTRIBUTE_UNUSED
,
151 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
153 int value
= ((insn
>> 5) & 0x07) | ((insn
& 0x03) << 3);
158 static unsigned long long
159 insert_r0 (unsigned long long insn
,
161 const char **errmsg ATTRIBUTE_UNUSED
)
164 *errmsg
= _("Register must be R0.");
169 extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED
,
170 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
176 static unsigned long long
177 insert_r1 (unsigned long long insn
,
179 const char **errmsg ATTRIBUTE_UNUSED
)
182 *errmsg
= _("Register must be R1.");
187 extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED
,
188 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
193 static unsigned long long
194 insert_r2 (unsigned long long insn
,
196 const char **errmsg ATTRIBUTE_UNUSED
)
199 *errmsg
= _("Register must be R2.");
204 extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED
,
205 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
210 static unsigned long long
211 insert_r3 (unsigned long long insn
,
213 const char **errmsg ATTRIBUTE_UNUSED
)
216 *errmsg
= _("Register must be R3.");
221 extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED
,
222 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
227 static unsigned long long
228 insert_sp (unsigned long long insn
,
230 const char **errmsg ATTRIBUTE_UNUSED
)
233 *errmsg
= _("Register must be SP.");
238 extract_sp (unsigned long long insn ATTRIBUTE_UNUSED
,
239 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
244 static unsigned long long
245 insert_gp (unsigned long long insn
,
247 const char **errmsg ATTRIBUTE_UNUSED
)
250 *errmsg
= _("Register must be GP.");
255 extract_gp (unsigned long long insn ATTRIBUTE_UNUSED
,
256 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
261 static unsigned long long
262 insert_pcl (unsigned long long insn
,
264 const char **errmsg ATTRIBUTE_UNUSED
)
267 *errmsg
= _("Register must be PCL.");
272 extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED
,
273 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
278 static unsigned long long
279 insert_blink (unsigned long long insn
,
281 const char **errmsg ATTRIBUTE_UNUSED
)
284 *errmsg
= _("Register must be BLINK.");
289 extract_blink (unsigned long long insn ATTRIBUTE_UNUSED
,
290 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
295 static unsigned long long
296 insert_ilink1 (unsigned long long insn
,
298 const char **errmsg ATTRIBUTE_UNUSED
)
301 *errmsg
= _("Register must be ILINK1.");
306 extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED
,
307 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
312 static unsigned long long
313 insert_ilink2 (unsigned long long insn
,
315 const char **errmsg ATTRIBUTE_UNUSED
)
318 *errmsg
= _("Register must be ILINK2.");
323 extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED
,
324 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
329 static unsigned long long
330 insert_ras (unsigned long long insn
,
332 const char **errmsg ATTRIBUTE_UNUSED
)
349 *errmsg
= _("Register must be either r0-r3 or r12-r15.");
356 extract_ras (unsigned long long insn ATTRIBUTE_UNUSED
,
357 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
359 int value
= insn
& 0x07;
366 static unsigned long long
367 insert_rbs (unsigned long long insn
,
369 const char **errmsg ATTRIBUTE_UNUSED
)
383 insn
|= ((value
- 8)) << 8;
386 *errmsg
= _("Register must be either r0-r3 or r12-r15.");
393 extract_rbs (unsigned long long insn ATTRIBUTE_UNUSED
,
394 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
396 int value
= (insn
>> 8) & 0x07;
403 static unsigned long long
404 insert_rcs (unsigned long long insn
,
406 const char **errmsg ATTRIBUTE_UNUSED
)
420 insn
|= ((value
- 8)) << 5;
423 *errmsg
= _("Register must be either r0-r3 or r12-r15.");
430 extract_rcs (unsigned long long insn ATTRIBUTE_UNUSED
,
431 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
433 int value
= (insn
>> 5) & 0x07;
440 static unsigned long long
441 insert_simm3s (unsigned long long insn
,
443 const char **errmsg ATTRIBUTE_UNUSED
)
473 *errmsg
= _("Accepted values are from -1 to 6.");
482 extract_simm3s (unsigned long long insn ATTRIBUTE_UNUSED
,
483 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
485 int value
= (insn
>> 8) & 0x07;
492 static unsigned long long
493 insert_rrange (unsigned long long insn
,
495 const char **errmsg ATTRIBUTE_UNUSED
)
497 int reg1
= (value
>> 16) & 0xFFFF;
498 int reg2
= value
& 0xFFFF;
501 *errmsg
= _("First register of the range should be r13.");
504 if (reg2
< 13 || reg2
> 26)
506 *errmsg
= _("Last register of the range doesn't fit.");
509 insn
|= ((reg2
- 12) & 0x0F) << 1;
514 extract_rrange (unsigned long long insn ATTRIBUTE_UNUSED
,
515 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
517 return (insn
>> 1) & 0x0F;
520 static unsigned long long
521 insert_fpel (unsigned long long insn
,
523 const char **errmsg ATTRIBUTE_UNUSED
)
527 *errmsg
= _("Invalid register number, should be fp.");
536 extract_fpel (unsigned long long insn ATTRIBUTE_UNUSED
,
537 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
539 return (insn
& 0x0100) ? 27 : -1;
542 static unsigned long long
543 insert_blinkel (unsigned long long insn
,
545 const char **errmsg ATTRIBUTE_UNUSED
)
549 *errmsg
= _("Invalid register number, should be blink.");
558 extract_blinkel (unsigned long long insn ATTRIBUTE_UNUSED
,
559 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
561 return (insn
& 0x0200) ? 31 : -1;
564 static unsigned long long
565 insert_pclel (unsigned long long insn
,
567 const char **errmsg ATTRIBUTE_UNUSED
)
571 *errmsg
= _("Invalid register number, should be pcl.");
580 extract_pclel (unsigned long long insn ATTRIBUTE_UNUSED
,
581 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
583 return (insn
& 0x0400) ? 63 : -1;
587 /* mask = 00000000000000000000111111000000
588 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
589 static unsigned long long
590 insert_w6 (unsigned long long insn ATTRIBUTE_UNUSED
,
591 long long int value ATTRIBUTE_UNUSED
,
592 const char **errmsg ATTRIBUTE_UNUSED
)
594 insn
|= ((value
>> 0) & 0x003f) << 6;
600 /* mask = 00000000000000000000111111000000. */
602 extract_w6 (unsigned long long insn ATTRIBUTE_UNUSED
,
603 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
607 value
|= ((insn
>> 6) & 0x003f) << 0;
613 /* mask = 0000011100022000
614 insn = 01000ggghhhGG0HH. */
615 static unsigned long long
616 insert_g_s (unsigned long long insn ATTRIBUTE_UNUSED
,
617 long long int value ATTRIBUTE_UNUSED
,
618 const char **errmsg ATTRIBUTE_UNUSED
)
620 insn
|= ((value
>> 0) & 0x0007) << 8;
621 insn
|= ((value
>> 3) & 0x0003) << 3;
627 /* mask = 0000011100022000. */
629 extract_g_s (unsigned long long insn ATTRIBUTE_UNUSED
,
630 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
634 value
|= ((insn
>> 8) & 0x0007) << 0;
635 value
|= ((insn
>> 3) & 0x0003) << 3;
637 /* Extend the sign. */
638 int signbit
= 1 << (6 - 1);
639 value
= (value
^ signbit
) - signbit
;
644 /* ARC NPS400 Support: See comment near head of file. */
645 #define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
646 static unsigned long long \
647 insert_nps_3bit_reg_at_##OFFSET##_##NAME \
648 (unsigned long long insn ATTRIBUTE_UNUSED, \
649 long long int value ATTRIBUTE_UNUSED, \
650 const char **errmsg ATTRIBUTE_UNUSED) \
658 insn |= value << (OFFSET); \
664 insn |= (value - 8) << (OFFSET); \
667 *errmsg = _("Register must be either r0-r3 or r12-r15."); \
673 static long long int \
674 extract_nps_3bit_reg_at_##OFFSET##_##NAME \
675 (unsigned long long insn ATTRIBUTE_UNUSED, \
676 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
678 int value = (insn >> (OFFSET)) & 0x07; \
684 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
685 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst
,24)
686 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst
,40)
687 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst
,56)
689 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2
,5)
690 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2
,21)
691 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2
,37)
692 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2
,53)
694 static unsigned long long
695 insert_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED
,
696 long long int value ATTRIBUTE_UNUSED
,
697 const char **errmsg ATTRIBUTE_UNUSED
)
715 *errmsg
= _("Invalid size, should be 1, 2, 4, or 8.");
724 extract_nps_bitop_size_2b (unsigned long long insn ATTRIBUTE_UNUSED
,
725 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
727 return 1 << ((insn
>> 10) & 0x3);
730 static unsigned long long
731 insert_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED
,
732 long long int value ATTRIBUTE_UNUSED
,
733 const char **errmsg ATTRIBUTE_UNUSED
)
735 insn
|= ((value
>> 5) & 7) << 12;
736 insn
|= (value
& 0x1f);
741 extract_nps_bitop_uimm8 (unsigned long long insn ATTRIBUTE_UNUSED
,
742 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
744 return (((insn
>> 12) & 0x7) << 5) | (insn
& 0x1f);
747 static unsigned long long
748 insert_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED
,
749 long long int value ATTRIBUTE_UNUSED
,
750 const char **errmsg ATTRIBUTE_UNUSED
)
760 *errmsg
= _("invalid immediate, must be 1, 2, or 4");
764 insn
|= (value
<< 6);
769 extract_nps_rflt_uimm6 (unsigned long long insn ATTRIBUTE_UNUSED
,
770 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
772 return (insn
>> 6) & 0x3f;
775 static unsigned long long
776 insert_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED
,
777 long long int value ATTRIBUTE_UNUSED
,
778 const char **errmsg ATTRIBUTE_UNUSED
)
780 insn
|= ((value
& 0x1f) | (((32 - value
- 1) & 0x1f) << 10));
785 extract_nps_dst_pos_and_size (unsigned long long insn ATTRIBUTE_UNUSED
,
786 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
788 return (insn
& 0x1f);
791 static unsigned long long
792 insert_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED
,
793 long long int value ATTRIBUTE_UNUSED
,
794 const char **errmsg ATTRIBUTE_UNUSED
)
796 int top
= (value
>> 16) & 0xffff;
797 if (top
!= 0x0 && top
!= NPS_CMEM_HIGH_VALUE
)
798 *errmsg
= _("invalid value for CMEM ld/st immediate");
799 insn
|= (value
& 0xffff);
804 extract_nps_cmem_uimm16 (unsigned long long insn ATTRIBUTE_UNUSED
,
805 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
807 return (NPS_CMEM_HIGH_VALUE
<< 16) | (insn
& 0xffff);
810 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
811 static unsigned long long \
812 insert_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
813 long long int value ATTRIBUTE_UNUSED, \
814 const char **errmsg ATTRIBUTE_UNUSED) \
825 *errmsg = _("Invalid position, should be 0, 8, 16, or 24."); \
828 insn |= (value << SHIFT); \
832 static long long int \
833 extract_nps_##NAME##_pos (unsigned long long insn ATTRIBUTE_UNUSED, \
834 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
836 return ((insn >> SHIFT) & 0x3) * 8; \
839 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2
, 12)
840 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1
, 10)
842 #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT)\
843 static unsigned long long \
844 insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
845 long long int value ATTRIBUTE_UNUSED, \
846 const char **errmsg ATTRIBUTE_UNUSED) \
848 if (value < LOWER || value > UPPER) \
850 *errmsg = _("Invalid size, value must be " \
851 #LOWER " to " #UPPER "."); \
855 insn |= (value << SHIFT); \
859 static long long int \
860 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
861 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
863 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
866 MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size
,2,32,5,1,5)
867 MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size
,1,32,5,1,5)
868 MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size
,8,32,5,8,5)
869 MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size
,16,32,5,16,5)
870 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size
,1,32,5,1,10)
871 MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size
,1,8,3,1,9)
872 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size
,1,32,5,1,20)
873 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size
,1,32,5,1,25)
874 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width
,1,32,5,1,6)
875 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len
,1,8,3,1,2)
876 MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3
,4,7,2,4,0)
879 extract_nps_qcmp_m3 (unsigned long long insn ATTRIBUTE_UNUSED
,
880 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
882 int m3
= (insn
>> 5) & 0xf;
889 extract_nps_qcmp_m2 (unsigned long long insn ATTRIBUTE_UNUSED
,
890 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
892 bfd_boolean tmp_invalid
= FALSE
;
893 int m2
= (insn
>> 15) & 0x1;
894 int m3
= extract_nps_qcmp_m3 (insn
, &tmp_invalid
);
896 if (m2
== 0 && m3
== 0xf)
902 extract_nps_qcmp_m1 (unsigned long long insn ATTRIBUTE_UNUSED
,
903 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
905 bfd_boolean tmp_invalid
= FALSE
;
906 int m1
= (insn
>> 14) & 0x1;
907 int m2
= extract_nps_qcmp_m2 (insn
, &tmp_invalid
);
908 int m3
= extract_nps_qcmp_m3 (insn
, &tmp_invalid
);
910 if (m1
== 0 && m2
== 0 && m3
== 0xf)
915 static unsigned long long
916 insert_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED
,
917 long long int value ATTRIBUTE_UNUSED
,
918 const char **errmsg ATTRIBUTE_UNUSED
)
922 if (value
< 1 || value
> 256)
924 *errmsg
= _("value out of range 1 - 256");
928 for (pwr
= 0; (value
& 1) == 0; value
>>= 1)
933 *errmsg
= _("value must be power of 2");
937 return insn
| (pwr
<< 8);
941 extract_nps_calc_entry_size (unsigned long long insn ATTRIBUTE_UNUSED
,
942 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
944 unsigned entry_size
= (insn
>> 8) & 0xf;
945 return 1 << entry_size
;
948 static unsigned long long
949 insert_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED
,
950 long long int value ATTRIBUTE_UNUSED
,
951 const char **errmsg ATTRIBUTE_UNUSED
)
953 return insn
| ((value
& 0x2) << 30) | ((value
& 0x1) << 47);
957 extract_nps_bitop_mod4 (unsigned long long insn ATTRIBUTE_UNUSED
,
958 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
960 return ((insn
>> 30) & 0x2) | ((insn
>> 47) & 0x1);
963 static unsigned long long
964 insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED
,
965 long long int value ATTRIBUTE_UNUSED
,
966 const char **errmsg ATTRIBUTE_UNUSED
)
968 return insn
| (value
<< 42) | (value
<< 37);
972 extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn ATTRIBUTE_UNUSED
,
973 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
975 if (((insn
>> 42) & 0x1f) != ((insn
>> 37) & 0x1f))
977 return ((insn
>> 37) & 0x1f);
980 static unsigned long long
981 insert_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED
,
982 long long int value ATTRIBUTE_UNUSED
,
983 const char **errmsg ATTRIBUTE_UNUSED
)
985 if (value
< 0 || value
> 28)
986 *errmsg
= _("Value must be in the range 0 to 28");
987 return insn
| (value
<< 20);
991 extract_nps_bitop_ins_ext (unsigned long long insn ATTRIBUTE_UNUSED
,
992 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
994 int value
= (insn
>> 20) & 0x1f;
1000 #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
1001 static unsigned long long \
1002 insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1003 long long int value ATTRIBUTE_UNUSED, \
1004 const char **errmsg ATTRIBUTE_UNUSED) \
1006 if (value < 1 || value > UPPER) \
1007 *errmsg = _("Value must be in the range 1 to " #UPPER); \
1008 if (value == UPPER) \
1010 return insn | (value << SHIFT); \
1013 static long long int \
1014 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1015 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1017 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1023 MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size
, 6, 8, 3)
1024 MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor
, 9, 8, 3)
1025 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble
, 12, 8, 3)
1026 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len
, 5, 256, 8)
1027 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff
, 6, 8, 3)
1028 MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job
, 6, 4, 2)
1029 MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size
, 16, 64, 6)
1031 static unsigned long long
1032 insert_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED
,
1033 long long int value ATTRIBUTE_UNUSED
,
1034 const char **errmsg ATTRIBUTE_UNUSED
)
1036 if (value
< 0 || value
> 240)
1037 *errmsg
= _("Value must be in the range 0 to 240");
1038 if ((value
% 16) != 0)
1039 *errmsg
= _("Value must be a multiple of 16");
1041 return insn
| (value
<< 6);
1044 static long long int
1045 extract_nps_min_hofs (unsigned long long insn ATTRIBUTE_UNUSED
,
1046 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
1048 int value
= (insn
>> 6) & 0xF;
1052 #define MAKE_INSERT_NPS_ADDRTYPE(NAME,VALUE) \
1053 static unsigned long long \
1054 insert_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1055 long long int value ATTRIBUTE_UNUSED, \
1056 const char **errmsg ATTRIBUTE_UNUSED) \
1058 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
1059 *errmsg = _("Invalid address type for operand"); \
1063 static long long int \
1064 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1065 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1067 return ARC_NPS400_ADDRTYPE_##VALUE; \
1070 MAKE_INSERT_NPS_ADDRTYPE (bd
, BD
)
1071 MAKE_INSERT_NPS_ADDRTYPE (jid
, JID
)
1072 MAKE_INSERT_NPS_ADDRTYPE (lbd
, LBD
)
1073 MAKE_INSERT_NPS_ADDRTYPE (mbd
, MBD
)
1074 MAKE_INSERT_NPS_ADDRTYPE (sd
, SD
)
1075 MAKE_INSERT_NPS_ADDRTYPE (sm
, SM
)
1076 MAKE_INSERT_NPS_ADDRTYPE (xa
, XA
)
1077 MAKE_INSERT_NPS_ADDRTYPE (xd
, XD
)
1078 MAKE_INSERT_NPS_ADDRTYPE (cd
, CD
)
1079 MAKE_INSERT_NPS_ADDRTYPE (cbd
, CBD
)
1080 MAKE_INSERT_NPS_ADDRTYPE (cjid
, CJID
)
1081 MAKE_INSERT_NPS_ADDRTYPE (clbd
, CLBD
)
1082 MAKE_INSERT_NPS_ADDRTYPE (cm
, CM
)
1083 MAKE_INSERT_NPS_ADDRTYPE (csd
, CSD
)
1084 MAKE_INSERT_NPS_ADDRTYPE (cxa
, CXA
)
1085 MAKE_INSERT_NPS_ADDRTYPE (cxd
, CXD
)
1087 static unsigned long long
1088 insert_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED
,
1089 long long int value ATTRIBUTE_UNUSED
,
1090 const char **errmsg ATTRIBUTE_UNUSED
)
1092 if (value
< 0 || value
> 31)
1093 *errmsg
= _("Value must be in the range 0 to 31");
1094 return insn
| (value
<< 43) | (value
<< 48);
1098 static long long int
1099 extract_nps_rbdouble_64 (unsigned long long insn ATTRIBUTE_UNUSED
,
1100 bfd_boolean
* invalid ATTRIBUTE_UNUSED
)
1102 int value1
= (insn
>> 43) & 0x1F;
1103 int value2
= (insn
>> 48) & 0x1F;
1105 if (value1
!= value2
)
1111 /* Include the generic extract/insert functions. Order is important
1112 as some of the functions present in the .h may be disabled via
1114 #include "arc-fxi.h"
1116 /* The flag operands table.
1118 The format of the table is
1119 NAME CODE BITS SHIFT FAVAIL. */
1120 const struct arc_flag_operand arc_flag_operands
[] =
1124 #define F_ALWAYS (F_NULL + 1)
1125 { "al", 0, 0, 0, 0 },
1126 #define F_RA (F_ALWAYS + 1)
1127 { "ra", 0, 0, 0, 0 },
1128 #define F_EQUAL (F_RA + 1)
1129 { "eq", 1, 5, 0, 1 },
1130 #define F_ZERO (F_EQUAL + 1)
1131 { "z", 1, 5, 0, 0 },
1132 #define F_NOTEQUAL (F_ZERO + 1)
1133 { "ne", 2, 5, 0, 1 },
1134 #define F_NOTZERO (F_NOTEQUAL + 1)
1135 { "nz", 2, 5, 0, 0 },
1136 #define F_POZITIVE (F_NOTZERO + 1)
1137 { "p", 3, 5, 0, 1 },
1138 #define F_PL (F_POZITIVE + 1)
1139 { "pl", 3, 5, 0, 0 },
1140 #define F_NEGATIVE (F_PL + 1)
1141 { "n", 4, 5, 0, 1 },
1142 #define F_MINUS (F_NEGATIVE + 1)
1143 { "mi", 4, 5, 0, 0 },
1144 #define F_CARRY (F_MINUS + 1)
1145 { "c", 5, 5, 0, 1 },
1146 #define F_CARRYSET (F_CARRY + 1)
1147 { "cs", 5, 5, 0, 0 },
1148 #define F_LOWER (F_CARRYSET + 1)
1149 { "lo", 5, 5, 0, 0 },
1150 #define F_CARRYCLR (F_LOWER + 1)
1151 { "cc", 6, 5, 0, 0 },
1152 #define F_NOTCARRY (F_CARRYCLR + 1)
1153 { "nc", 6, 5, 0, 1 },
1154 #define F_HIGHER (F_NOTCARRY + 1)
1155 { "hs", 6, 5, 0, 0 },
1156 #define F_OVERFLOWSET (F_HIGHER + 1)
1157 { "vs", 7, 5, 0, 0 },
1158 #define F_OVERFLOW (F_OVERFLOWSET + 1)
1159 { "v", 7, 5, 0, 1 },
1160 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
1161 { "nv", 8, 5, 0, 1 },
1162 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1163 { "vc", 8, 5, 0, 0 },
1164 #define F_GT (F_OVERFLOWCLR + 1)
1165 { "gt", 9, 5, 0, 1 },
1166 #define F_GE (F_GT + 1)
1167 { "ge", 10, 5, 0, 1 },
1168 #define F_LT (F_GE + 1)
1169 { "lt", 11, 5, 0, 1 },
1170 #define F_LE (F_LT + 1)
1171 { "le", 12, 5, 0, 1 },
1172 #define F_HI (F_LE + 1)
1173 { "hi", 13, 5, 0, 1 },
1174 #define F_LS (F_HI + 1)
1175 { "ls", 14, 5, 0, 1 },
1176 #define F_PNZ (F_LS + 1)
1177 { "pnz", 15, 5, 0, 1 },
1180 #define F_FLAG (F_PNZ + 1)
1181 { "f", 1, 1, 15, 1 },
1182 #define F_FFAKE (F_FLAG + 1)
1183 { "f", 0, 0, 0, 1 },
1186 #define F_ND (F_FFAKE + 1)
1187 { "nd", 0, 1, 5, 0 },
1188 #define F_D (F_ND + 1)
1189 { "d", 1, 1, 5, 1 },
1190 #define F_DFAKE (F_D + 1)
1191 { "d", 0, 0, 0, 1 },
1192 #define F_DNZ_ND (F_DFAKE + 1)
1193 { "nd", 0, 1, 16, 0 },
1194 #define F_DNZ_D (F_DNZ_ND + 1)
1195 { "d", 1, 1, 16, 1 },
1198 #define F_SIZEB1 (F_DNZ_D + 1)
1199 { "b", 1, 2, 1, 1 },
1200 #define F_SIZEB7 (F_SIZEB1 + 1)
1201 { "b", 1, 2, 7, 1 },
1202 #define F_SIZEB17 (F_SIZEB7 + 1)
1203 { "b", 1, 2, 17, 1 },
1204 #define F_SIZEW1 (F_SIZEB17 + 1)
1205 { "w", 2, 2, 1, 0 },
1206 #define F_SIZEW7 (F_SIZEW1 + 1)
1207 { "w", 2, 2, 7, 0 },
1208 #define F_SIZEW17 (F_SIZEW7 + 1)
1209 { "w", 2, 2, 17, 0 },
1211 /* Sign extension. */
1212 #define F_SIGN6 (F_SIZEW17 + 1)
1213 { "x", 1, 1, 6, 1 },
1214 #define F_SIGN16 (F_SIGN6 + 1)
1215 { "x", 1, 1, 16, 1 },
1216 #define F_SIGNX (F_SIGN16 + 1)
1217 { "x", 0, 0, 0, 1 },
1219 /* Address write-back modes. */
1220 #define F_A3 (F_SIGNX + 1)
1221 { "a", 1, 2, 3, 0 },
1222 #define F_A9 (F_A3 + 1)
1223 { "a", 1, 2, 9, 0 },
1224 #define F_A22 (F_A9 + 1)
1225 { "a", 1, 2, 22, 0 },
1226 #define F_AW3 (F_A22 + 1)
1227 { "aw", 1, 2, 3, 1 },
1228 #define F_AW9 (F_AW3 + 1)
1229 { "aw", 1, 2, 9, 1 },
1230 #define F_AW22 (F_AW9 + 1)
1231 { "aw", 1, 2, 22, 1 },
1232 #define F_AB3 (F_AW22 + 1)
1233 { "ab", 2, 2, 3, 1 },
1234 #define F_AB9 (F_AB3 + 1)
1235 { "ab", 2, 2, 9, 1 },
1236 #define F_AB22 (F_AB9 + 1)
1237 { "ab", 2, 2, 22, 1 },
1238 #define F_AS3 (F_AB22 + 1)
1239 { "as", 3, 2, 3, 1 },
1240 #define F_AS9 (F_AS3 + 1)
1241 { "as", 3, 2, 9, 1 },
1242 #define F_AS22 (F_AS9 + 1)
1243 { "as", 3, 2, 22, 1 },
1244 #define F_ASFAKE (F_AS22 + 1)
1245 { "as", 0, 0, 0, 1 },
1248 #define F_DI5 (F_ASFAKE + 1)
1249 { "di", 1, 1, 5, 1 },
1250 #define F_DI11 (F_DI5 + 1)
1251 { "di", 1, 1, 11, 1 },
1252 #define F_DI14 (F_DI11 + 1)
1253 { "di", 1, 1, 14, 1 },
1254 #define F_DI15 (F_DI14 + 1)
1255 { "di", 1, 1, 15, 1 },
1257 /* ARCv2 specific. */
1258 #define F_NT (F_DI15 + 1)
1259 { "nt", 0, 1, 3, 1},
1260 #define F_T (F_NT + 1)
1262 #define F_H1 (F_T + 1)
1263 { "h", 2, 2, 1, 1 },
1264 #define F_H7 (F_H1 + 1)
1265 { "h", 2, 2, 7, 1 },
1266 #define F_H17 (F_H7 + 1)
1267 { "h", 2, 2, 17, 1 },
1270 #define F_NE (F_H17 + 1)
1271 { "ne", 0, 0, 0, 1 },
1273 /* ARC NPS400 Support: See comment near head of file. */
1274 #define F_NPS_CL (F_NE + 1)
1275 { "cl", 0, 0, 0, 1 },
1277 #define F_NPS_FLAG (F_NPS_CL + 1)
1278 { "f", 1, 1, 20, 1 },
1280 #define F_NPS_R (F_NPS_FLAG + 1)
1281 { "r", 1, 1, 15, 1 },
1283 #define F_NPS_RW (F_NPS_R + 1)
1284 { "rw", 0, 1, 7, 1 },
1286 #define F_NPS_RD (F_NPS_RW + 1)
1287 { "rd", 1, 1, 7, 1 },
1289 #define F_NPS_WFT (F_NPS_RD + 1)
1290 { "wft", 0, 0, 0, 1 },
1292 #define F_NPS_IE1 (F_NPS_WFT + 1)
1293 { "ie1", 1, 2, 8, 1 },
1295 #define F_NPS_IE2 (F_NPS_IE1 + 1)
1296 { "ie2", 2, 2, 8, 1 },
1298 #define F_NPS_IE12 (F_NPS_IE2 + 1)
1299 { "ie12", 3, 2, 8, 1 },
1301 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1302 { "rd", 0, 1, 6, 1 },
1304 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1305 { "wr", 1, 1, 6, 1 },
1307 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1308 { "off", 0, 0, 0, 1 },
1310 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1311 { "restore", 0, 0, 0, 1 },
1313 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1314 { "sx", 1, 1, 14, 1 },
1316 #define F_NPS_AR (F_NPS_SX + 1)
1317 { "ar", 0, 1, 0, 1 },
1319 #define F_NPS_AL (F_NPS_AR + 1)
1320 { "al", 1, 1, 0, 1 },
1322 #define F_NPS_S (F_NPS_AL + 1)
1323 { "s", 0, 0, 0, 1 },
1325 #define F_NPS_ZNCV_RD (F_NPS_S + 1)
1326 { "rd", 0, 1, 15, 1 },
1328 #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1329 { "wr", 1, 1, 15, 1 },
1331 #define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1332 { "p0", 0, 0, 0, 1 },
1334 #define F_NPS_P1 (F_NPS_P0 + 1)
1335 { "p1", 0, 0, 0, 1 },
1337 #define F_NPS_P2 (F_NPS_P1 + 1)
1338 { "p2", 0, 0, 0, 1 },
1340 #define F_NPS_P3 (F_NPS_P2 + 1)
1341 { "p3", 0, 0, 0, 1 },
1343 #define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1344 { "di", 0, 0, 0, 1 },
1346 #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1347 { "cl", 1, 1, 6, 1 },
1349 #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1350 { "cl", 1, 1, 16, 1 },
1352 #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1353 { "x2", 1, 2, 9, 1 },
1355 #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1356 { "x2", 1, 2, 22, 1 },
1358 #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1359 { "x4", 2, 2, 9, 1 },
1361 #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1362 { "x4", 2, 2, 22, 1 },
1365 const unsigned arc_num_flag_operands
= ARRAY_SIZE (arc_flag_operands
);
1367 /* Table of the flag classes.
1369 The format of the table is
1370 CLASS {FLAG_CODE}. */
1371 const struct arc_flag_class arc_flag_classes
[] =
1374 { F_CLASS_NONE
, { F_NULL
} },
1376 #define C_CC (C_EMPTY + 1)
1377 { F_CLASS_OPTIONAL
| F_CLASS_EXTEND
| F_CLASS_COND
,
1378 { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
,
1379 F_NOTZERO
, F_POZITIVE
, F_PL
, F_NEGATIVE
, F_MINUS
,
1380 F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
1381 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
,
1382 F_NOTOVERFLOW
, F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
,
1383 F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
1385 #define C_AA_ADDR3 (C_CC + 1)
1386 #define C_AA27 (C_CC + 1)
1387 { F_CLASS_OPTIONAL
, { F_A3
, F_AW3
, F_AB3
, F_AS3
, F_NULL
} },
1388 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1389 #define C_AA21 (C_AA_ADDR3 + 1)
1390 { F_CLASS_OPTIONAL
, { F_A9
, F_AW9
, F_AB9
, F_AS9
, F_NULL
} },
1391 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1392 #define C_AA8 (C_AA_ADDR9 + 1)
1393 { F_CLASS_OPTIONAL
, { F_A22
, F_AW22
, F_AB22
, F_AS22
, F_NULL
} },
1395 #define C_F (C_AA_ADDR22 + 1)
1396 { F_CLASS_OPTIONAL
, { F_FLAG
, F_NULL
} },
1397 #define C_FHARD (C_F + 1)
1398 { F_CLASS_OPTIONAL
, { F_FFAKE
, F_NULL
} },
1400 #define C_T (C_FHARD + 1)
1401 { F_CLASS_OPTIONAL
, { F_NT
, F_T
, F_NULL
} },
1402 #define C_D (C_T + 1)
1403 { F_CLASS_OPTIONAL
, { F_ND
, F_D
, F_NULL
} },
1404 #define C_DNZ_D (C_D + 1)
1405 { F_CLASS_OPTIONAL
, { F_DNZ_ND
, F_DNZ_D
, F_NULL
} },
1407 #define C_DHARD (C_DNZ_D + 1)
1408 { F_CLASS_OPTIONAL
, { F_DFAKE
, F_NULL
} },
1410 #define C_DI20 (C_DHARD + 1)
1411 { F_CLASS_OPTIONAL
, { F_DI11
, F_NULL
}},
1412 #define C_DI14 (C_DI20 + 1)
1413 { F_CLASS_OPTIONAL
, { F_DI14
, F_NULL
}},
1414 #define C_DI16 (C_DI14 + 1)
1415 { F_CLASS_OPTIONAL
, { F_DI15
, F_NULL
}},
1416 #define C_DI26 (C_DI16 + 1)
1417 { F_CLASS_OPTIONAL
, { F_DI5
, F_NULL
}},
1419 #define C_X25 (C_DI26 + 1)
1420 { F_CLASS_OPTIONAL
, { F_SIGN6
, F_NULL
}},
1421 #define C_X15 (C_X25 + 1)
1422 { F_CLASS_OPTIONAL
, { F_SIGN16
, F_NULL
}},
1423 #define C_XHARD (C_X15 + 1)
1424 #define C_X (C_X15 + 1)
1425 { F_CLASS_OPTIONAL
, { F_SIGNX
, F_NULL
}},
1427 #define C_ZZ13 (C_X + 1)
1428 { F_CLASS_OPTIONAL
, { F_SIZEB17
, F_SIZEW17
, F_H17
, F_NULL
}},
1429 #define C_ZZ23 (C_ZZ13 + 1)
1430 { F_CLASS_OPTIONAL
, { F_SIZEB7
, F_SIZEW7
, F_H7
, F_NULL
}},
1431 #define C_ZZ29 (C_ZZ23 + 1)
1432 { F_CLASS_OPTIONAL
, { F_SIZEB1
, F_SIZEW1
, F_H1
, F_NULL
}},
1434 #define C_AS (C_ZZ29 + 1)
1435 { F_CLASS_OPTIONAL
, { F_ASFAKE
, F_NULL
}},
1437 #define C_NE (C_AS + 1)
1438 { F_CLASS_OPTIONAL
, { F_NE
, F_NULL
}},
1440 /* ARC NPS400 Support: See comment near head of file. */
1441 #define C_NPS_CL (C_NE + 1)
1442 { F_CLASS_REQUIRED
, { F_NPS_CL
, F_NULL
}},
1444 #define C_NPS_F (C_NPS_CL + 1)
1445 { F_CLASS_OPTIONAL
, { F_NPS_FLAG
, F_NULL
}},
1447 #define C_NPS_R (C_NPS_F + 1)
1448 { F_CLASS_OPTIONAL
, { F_NPS_R
, F_NULL
}},
1450 #define C_NPS_SCHD_RW (C_NPS_R + 1)
1451 { F_CLASS_REQUIRED
, { F_NPS_RW
, F_NPS_RD
, F_NULL
}},
1453 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1454 { F_CLASS_REQUIRED
, { F_NPS_WFT
, F_NULL
}},
1456 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1457 { F_CLASS_OPTIONAL
, { F_NPS_IE1
, F_NPS_IE2
, F_NPS_IE12
, F_NULL
}},
1459 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1460 { F_CLASS_REQUIRED
, { F_NPS_SYNC_RD
, F_NPS_SYNC_WR
, F_NULL
}},
1462 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1463 { F_CLASS_REQUIRED
, { F_NPS_HWS_OFF
, F_NULL
}},
1465 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1466 { F_CLASS_REQUIRED
, { F_NPS_HWS_RESTORE
, F_NULL
}},
1468 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1469 { F_CLASS_OPTIONAL
, { F_NPS_SX
, F_NULL
}},
1471 #define C_NPS_AR_AL (C_NPS_SX + 1)
1472 { F_CLASS_REQUIRED
, { F_NPS_AR
, F_NPS_AL
, F_NULL
}},
1474 #define C_NPS_S (C_NPS_AR_AL + 1)
1475 { F_CLASS_REQUIRED
, { F_NPS_S
, F_NULL
}},
1477 #define C_NPS_ZNCV (C_NPS_S + 1)
1478 { F_CLASS_REQUIRED
, { F_NPS_ZNCV_RD
, F_NPS_ZNCV_WR
, F_NULL
}},
1480 #define C_NPS_P0 (C_NPS_ZNCV + 1)
1481 { F_CLASS_REQUIRED
, { F_NPS_P0
, F_NULL
}},
1483 #define C_NPS_P1 (C_NPS_P0 + 1)
1484 { F_CLASS_REQUIRED
, { F_NPS_P1
, F_NULL
}},
1486 #define C_NPS_P2 (C_NPS_P1 + 1)
1487 { F_CLASS_REQUIRED
, { F_NPS_P2
, F_NULL
}},
1489 #define C_NPS_P3 (C_NPS_P2 + 1)
1490 { F_CLASS_REQUIRED
, { F_NPS_P3
, F_NULL
}},
1492 #define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1493 { F_CLASS_REQUIRED
, { F_NPS_LDBIT_DI
, F_NULL
}},
1495 #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1496 { F_CLASS_OPTIONAL
, { F_NPS_LDBIT_CL1
, F_NULL
}},
1498 #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1499 { F_CLASS_OPTIONAL
, { F_NPS_LDBIT_CL2
, F_NULL
}},
1501 #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1502 { F_CLASS_OPTIONAL
, { F_NPS_LDBIT_X2_1
, F_NPS_LDBIT_X4_1
, F_NULL
}},
1504 #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1505 { F_CLASS_OPTIONAL
, { F_NPS_LDBIT_X2_2
, F_NPS_LDBIT_X4_2
, F_NULL
}},
1508 const unsigned char flags_none
[] = { 0 };
1509 const unsigned char flags_f
[] = { C_F
};
1510 const unsigned char flags_cc
[] = { C_CC
};
1511 const unsigned char flags_ccf
[] = { C_CC
, C_F
};
1513 /* The operands table.
1515 The format of the operands table is:
1517 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1518 const struct arc_operand arc_operands
[] =
1520 /* The fields are bits, shift, insert, extract, flags. The zero
1521 index is used to indicate end-of-list. */
1523 { 0, 0, 0, 0, 0, 0 },
1525 #define IGNORED (UNUSED + 1)
1526 { 0, 0, 0, ARC_OPERAND_IGNORE
| ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, 0, 0 },
1528 /* The plain integer register fields. Used by 32 bit
1530 #define RA (IGNORED + 1)
1531 { 6, 0, 0, ARC_OPERAND_IR
, 0, 0 },
1533 { 6, 12, 0, ARC_OPERAND_IR
, insert_rb
, extract_rb
},
1535 { 6, 6, 0, ARC_OPERAND_IR
, 0, 0 },
1536 #define RBdup (RC + 1)
1537 { 6, 12, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
, insert_rb
, extract_rb
},
1539 #define RAD (RBdup + 1)
1540 { 6, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_TRUNCATE
, insert_rad
, 0 },
1541 #define RCD (RAD + 1)
1542 { 6, 6, 0, ARC_OPERAND_IR
| ARC_OPERAND_TRUNCATE
, insert_rcd
, 0 },
1544 /* The plain integer register fields. Used by short
1546 #define RA16 (RCD + 1)
1547 #define RA_S (RCD + 1)
1548 { 4, 0, 0, ARC_OPERAND_IR
, insert_ras
, extract_ras
},
1549 #define RB16 (RA16 + 1)
1550 #define RB_S (RA16 + 1)
1551 { 4, 8, 0, ARC_OPERAND_IR
, insert_rbs
, extract_rbs
},
1552 #define RB16dup (RB16 + 1)
1553 #define RB_Sdup (RB16 + 1)
1554 { 4, 8, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
, insert_rbs
, extract_rbs
},
1555 #define RC16 (RB16dup + 1)
1556 #define RC_S (RB16dup + 1)
1557 { 4, 5, 0, ARC_OPERAND_IR
, insert_rcs
, extract_rcs
},
1558 #define R6H (RC16 + 1) /* 6bit register field 'h' used
1560 { 6, 5, 0, ARC_OPERAND_IR
, insert_rhv1
, extract_rhv1
},
1561 #define R5H (R6H + 1) /* 5bit register field 'h' used
1563 #define RH_S (R6H + 1) /* 5bit register field 'h' used
1565 { 5, 5, 0, ARC_OPERAND_IR
, insert_rhv2
, extract_rhv2
},
1566 #define R5Hdup (R5H + 1)
1567 #define RH_Sdup (R5H + 1)
1568 { 5, 5, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
,
1569 insert_rhv2
, extract_rhv2
},
1571 #define RG (R5Hdup + 1)
1572 #define G_S (R5Hdup + 1)
1573 { 5, 5, 0, ARC_OPERAND_IR
, insert_g_s
, extract_g_s
},
1575 /* Fix registers. */
1577 #define R0_S (RG + 1)
1578 { 0, 0, 0, ARC_OPERAND_IR
, insert_r0
, extract_r0
},
1580 #define R1_S (R0 + 1)
1581 { 1, 0, 0, ARC_OPERAND_IR
, insert_r1
, extract_r1
},
1583 #define R2_S (R1 + 1)
1584 { 2, 0, 0, ARC_OPERAND_IR
, insert_r2
, extract_r2
},
1586 #define R3_S (R2 + 1)
1587 { 2, 0, 0, ARC_OPERAND_IR
, insert_r3
, extract_r3
},
1588 #define RSP (R3 + 1)
1589 #define SP_S (R3 + 1)
1590 { 5, 0, 0, ARC_OPERAND_IR
, insert_sp
, extract_sp
},
1591 #define SPdup (RSP + 1)
1592 #define SP_Sdup (RSP + 1)
1593 { 5, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
, insert_sp
, extract_sp
},
1594 #define GP (SPdup + 1)
1595 #define GP_S (SPdup + 1)
1596 { 5, 0, 0, ARC_OPERAND_IR
, insert_gp
, extract_gp
},
1598 #define PCL_S (GP + 1)
1599 { 1, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_pcl
, extract_pcl
},
1601 #define BLINK (PCL_S + 1)
1602 #define BLINK_S (PCL_S + 1)
1603 { 5, 0, 0, ARC_OPERAND_IR
, insert_blink
, extract_blink
},
1605 #define ILINK1 (BLINK + 1)
1606 { 5, 0, 0, ARC_OPERAND_IR
, insert_ilink1
, extract_ilink1
},
1607 #define ILINK2 (ILINK1 + 1)
1608 { 5, 0, 0, ARC_OPERAND_IR
, insert_ilink2
, extract_ilink2
},
1610 /* Long immediate. */
1611 #define LIMM (ILINK2 + 1)
1612 #define LIMM_S (ILINK2 + 1)
1613 { 32, 0, BFD_RELOC_ARC_32_ME
, ARC_OPERAND_LIMM
, insert_limm
, 0 },
1614 #define LIMMdup (LIMM + 1)
1615 { 32, 0, 0, ARC_OPERAND_LIMM
| ARC_OPERAND_DUPLICATE
, insert_limm
, 0 },
1617 /* Special operands. */
1618 #define ZA (LIMMdup + 1)
1619 #define ZB (LIMMdup + 1)
1620 #define ZA_S (LIMMdup + 1)
1621 #define ZB_S (LIMMdup + 1)
1622 #define ZC_S (LIMMdup + 1)
1623 { 0, 0, 0, ARC_OPERAND_UNSIGNED
, insert_za
, 0 },
1625 #define RRANGE_EL (ZA + 1)
1626 { 4, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
| ARC_OPERAND_TRUNCATE
,
1627 insert_rrange
, extract_rrange
},
1628 #define FP_EL (RRANGE_EL + 1)
1629 { 1, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_IGNORE
| ARC_OPERAND_NCHK
,
1630 insert_fpel
, extract_fpel
},
1631 #define BLINK_EL (FP_EL + 1)
1632 { 1, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_IGNORE
| ARC_OPERAND_NCHK
,
1633 insert_blinkel
, extract_blinkel
},
1634 #define PCL_EL (BLINK_EL + 1)
1635 { 1, 0, 0, ARC_OPERAND_IR
| ARC_OPERAND_IGNORE
| ARC_OPERAND_NCHK
,
1636 insert_pclel
, extract_pclel
},
1638 /* Fake operand to handle the T flag. */
1639 #define BRAKET (PCL_EL + 1)
1640 #define BRAKETdup (PCL_EL + 1)
1641 { 0, 0, 0, ARC_OPERAND_FAKE
| ARC_OPERAND_BRAKET
, 0, 0 },
1643 /* Fake operand to handle the T flag. */
1644 #define FKT_T (BRAKET + 1)
1645 { 1, 3, 0, ARC_OPERAND_FAKE
, insert_Ybit
, 0 },
1646 /* Fake operand to handle the T flag. */
1647 #define FKT_NT (FKT_T + 1)
1648 { 1, 3, 0, ARC_OPERAND_FAKE
, insert_NYbit
, 0 },
1650 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1651 #define UIMM6_20 (FKT_NT + 1)
1652 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_20
, extract_uimm6_20
},
1654 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1655 #define SIMM12_20 (UIMM6_20 + 1)
1656 {12, 0, 0, ARC_OPERAND_SIGNED
, insert_simm12_20
, extract_simm12_20
},
1658 /* SIMM3_5_S mask = 0000011100000000. */
1659 #define SIMM3_5_S (SIMM12_20 + 1)
1660 {3, 0, 0, ARC_OPERAND_SIGNED
| ARC_OPERAND_NCHK
,
1661 insert_simm3s
, extract_simm3s
},
1663 /* UIMM7_A32_11_S mask = 0000000000011111. */
1664 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1665 {7, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED32
1666 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_IGNORE
, insert_uimm7_a32_11_s
,
1667 extract_uimm7_a32_11_s
},
1669 /* UIMM7_9_S mask = 0000000001111111. */
1670 #define UIMM7_9_S (UIMM7_A32_11_S + 1)
1671 {7, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm7_9_s
, extract_uimm7_9_s
},
1673 /* UIMM3_13_S mask = 0000000000000111. */
1674 #define UIMM3_13_S (UIMM7_9_S + 1)
1675 {3, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm3_13_s
, extract_uimm3_13_s
},
1677 /* SIMM11_A32_7_S mask = 0000000111111111. */
1678 #define SIMM11_A32_7_S (UIMM3_13_S + 1)
1679 {11, 0, BFD_RELOC_ARC_SDA16_LD2
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1680 | ARC_OPERAND_TRUNCATE
, insert_simm11_a32_7_s
, extract_simm11_a32_7_s
},
1682 /* UIMM6_13_S mask = 0000000002220111. */
1683 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1684 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_13_s
, extract_uimm6_13_s
},
1685 /* UIMM5_11_S mask = 0000000000011111. */
1686 #define UIMM5_11_S (UIMM6_13_S + 1)
1687 {5, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_IGNORE
, insert_uimm5_11_s
,
1688 extract_uimm5_11_s
},
1690 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1691 #define SIMM9_A16_8 (UIMM5_11_S + 1)
1692 {9, 0, -SIMM9_A16_8
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1693 | ARC_OPERAND_PCREL
| ARC_OPERAND_TRUNCATE
, insert_simm9_a16_8
,
1694 extract_simm9_a16_8
},
1696 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1697 #define UIMM6_8 (SIMM9_A16_8 + 1)
1698 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_8
, extract_uimm6_8
},
1700 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1701 #define SIMM21_A16_5 (UIMM6_8 + 1)
1702 {21, 0, BFD_RELOC_ARC_S21H_PCREL
, ARC_OPERAND_SIGNED
1703 | ARC_OPERAND_ALIGNED16
| ARC_OPERAND_TRUNCATE
,
1704 insert_simm21_a16_5
, extract_simm21_a16_5
},
1706 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1707 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1708 {25, 0, BFD_RELOC_ARC_S25H_PCREL
, ARC_OPERAND_SIGNED
1709 | ARC_OPERAND_ALIGNED16
| ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
,
1710 insert_simm25_a16_5
, extract_simm25_a16_5
},
1712 /* SIMM10_A16_7_S mask = 0000000111111111. */
1713 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
1714 {10, 0, -SIMM10_A16_7_S
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1715 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm10_a16_7_s
,
1716 extract_simm10_a16_7_s
},
1718 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
1719 {10, 0, -SIMM10_A16_7_Sbis
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1720 | ARC_OPERAND_TRUNCATE
, insert_simm10_a16_7_s
, extract_simm10_a16_7_s
},
1722 /* SIMM7_A16_10_S mask = 0000000000111111. */
1723 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
1724 {7, 0, -SIMM7_A16_10_S
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1725 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm7_a16_10_s
,
1726 extract_simm7_a16_10_s
},
1728 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
1729 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
1730 {21, 0, BFD_RELOC_ARC_S21W_PCREL
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1731 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm21_a32_5
,
1732 extract_simm21_a32_5
},
1734 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
1735 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
1736 {25, 0, BFD_RELOC_ARC_S25W_PCREL
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1737 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm25_a32_5
,
1738 extract_simm25_a32_5
},
1740 /* SIMM13_A32_5_S mask = 0000011111111111. */
1741 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
1742 {13, 0, BFD_RELOC_ARC_S13_PCREL
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1743 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm13_a32_5_s
,
1744 extract_simm13_a32_5_s
},
1746 /* SIMM8_A16_9_S mask = 0000000001111111. */
1747 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
1748 {8, 0, -SIMM8_A16_9_S
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1749 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm8_a16_9_s
,
1750 extract_simm8_a16_9_s
},
1752 /* UIMM3_23 mask = 00000000000000000000000111000000. */
1753 #define UIMM3_23 (SIMM8_A16_9_S + 1)
1754 {3, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm3_23
, extract_uimm3_23
},
1756 /* UIMM10_6_S mask = 0000001111111111. */
1757 #define UIMM10_6_S (UIMM3_23 + 1)
1758 {10, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm10_6_s
, extract_uimm10_6_s
},
1760 /* UIMM6_11_S mask = 0000002200011110. */
1761 #define UIMM6_11_S (UIMM10_6_S + 1)
1762 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_11_s
, extract_uimm6_11_s
},
1764 /* SIMM9_8 mask = 00000000111111112000000000000000. */
1765 #define SIMM9_8 (UIMM6_11_S + 1)
1766 {9, 0, BFD_RELOC_ARC_SDA_LDST
, ARC_OPERAND_SIGNED
| ARC_OPERAND_IGNORE
,
1767 insert_simm9_8
, extract_simm9_8
},
1769 /* UIMM10_A32_8_S mask = 0000000011111111. */
1770 #define UIMM10_A32_8_S (SIMM9_8 + 1)
1771 {10, 0, -UIMM10_A32_8_S
, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED32
1772 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_uimm10_a32_8_s
,
1773 extract_uimm10_a32_8_s
},
1775 /* SIMM9_7_S mask = 0000000111111111. */
1776 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
1777 {9, 0, BFD_RELOC_ARC_SDA16_LD
, ARC_OPERAND_SIGNED
, insert_simm9_7_s
,
1780 /* UIMM6_A16_11_S mask = 0000000000011111. */
1781 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
1782 {6, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED16
1783 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_IGNORE
, insert_uimm6_a16_11_s
,
1784 extract_uimm6_a16_11_s
},
1786 /* UIMM5_A32_11_S mask = 0000020000011000. */
1787 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
1788 {5, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED32
1789 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_IGNORE
, insert_uimm5_a32_11_s
,
1790 extract_uimm5_a32_11_s
},
1792 /* SIMM11_A32_13_S mask = 0000022222200111. */
1793 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
1794 {11, 0, BFD_RELOC_ARC_SDA16_ST2
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED32
1795 | ARC_OPERAND_TRUNCATE
, insert_simm11_a32_13_s
, extract_simm11_a32_13_s
},
1797 /* UIMM7_13_S mask = 0000000022220111. */
1798 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
1799 {7, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm7_13_s
, extract_uimm7_13_s
},
1801 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
1802 #define UIMM6_A16_21 (UIMM7_13_S + 1)
1803 {6, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED16
1804 | ARC_OPERAND_TRUNCATE
, insert_uimm6_a16_21
, extract_uimm6_a16_21
},
1806 /* UIMM7_11_S mask = 0000022200011110. */
1807 #define UIMM7_11_S (UIMM6_A16_21 + 1)
1808 {7, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm7_11_s
, extract_uimm7_11_s
},
1810 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
1811 #define UIMM7_A16_20 (UIMM7_11_S + 1)
1812 {7, 0, -UIMM7_A16_20
, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_ALIGNED16
1813 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_uimm7_a16_20
,
1814 extract_uimm7_a16_20
},
1816 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
1817 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
1818 {13, 0, -SIMM13_A16_20
, ARC_OPERAND_SIGNED
| ARC_OPERAND_ALIGNED16
1819 | ARC_OPERAND_TRUNCATE
| ARC_OPERAND_PCREL
, insert_simm13_a16_20
,
1820 extract_simm13_a16_20
},
1822 /* UIMM8_8_S mask = 0000000011111111. */
1823 #define UIMM8_8_S (SIMM13_A16_20 + 1)
1824 {8, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm8_8_s
, extract_uimm8_8_s
},
1826 /* W6 mask = 00000000000000000000111111000000. */
1827 #define W6 (UIMM8_8_S + 1)
1828 {6, 0, 0, ARC_OPERAND_SIGNED
, insert_w6
, extract_w6
},
1830 /* UIMM6_5_S mask = 0000011111100000. */
1831 #define UIMM6_5_S (W6 + 1)
1832 {6, 0, 0, ARC_OPERAND_UNSIGNED
, insert_uimm6_5_s
, extract_uimm6_5_s
},
1834 /* ARC NPS400 Support: See comment near head of file. */
1835 #define NPS_R_DST_3B (UIMM6_5_S + 1)
1836 { 3, 24, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_24_dst
, extract_nps_3bit_reg_at_24_dst
},
1838 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
1839 { 3, 24, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_24_dst
, extract_nps_3bit_reg_at_24_dst
},
1841 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
1842 { 3, 21, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_21_src2
, extract_nps_3bit_reg_at_21_src2
},
1844 #define NPS_R_DST (NPS_R_SRC2_3B + 1)
1845 { 6, 21, 0, ARC_OPERAND_IR
, NULL
, NULL
},
1847 #define NPS_R_SRC1 (NPS_R_DST + 1)
1848 { 6, 21, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
, NULL
, NULL
},
1850 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
1851 { 5, 5, 0, ARC_OPERAND_UNSIGNED
, 0, 0 },
1853 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
1854 { 5, 0, 0, ARC_OPERAND_UNSIGNED
, 0, 0 },
1856 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
1857 { 5, 10, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_bitop_size
, extract_nps_bitop_size
},
1859 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
1860 { 5, 0, 0, ARC_OPERAND_UNSIGNED
, insert_nps_dst_pos_and_size
, extract_nps_dst_pos_and_size
},
1862 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
1863 { 0, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_bitop_size_2b
, extract_nps_bitop_size_2b
},
1865 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
1866 { 8, 0, 0, ARC_OPERAND_UNSIGNED
, insert_nps_bitop_uimm8
, extract_nps_bitop_uimm8
},
1868 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
1869 { 16, 0, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1871 #define NPS_SIMM16 (NPS_UIMM16 + 1)
1872 { 16, 0, 0, ARC_OPERAND_SIGNED
, NULL
, NULL
},
1874 #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
1875 { 6, 6, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_rflt_uimm6
, extract_nps_rflt_uimm6
},
1877 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
1878 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16
, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_cmem_uimm16
, extract_nps_cmem_uimm16
},
1880 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
1881 { 0, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_src2_pos
, extract_nps_src2_pos
},
1883 #define NPS_SRC1_POS (NPS_SRC2_POS + 1)
1884 { 0, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_src1_pos
, extract_nps_src1_pos
},
1886 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
1887 { 0, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_addb_size
, extract_nps_addb_size
},
1889 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
1890 { 0, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_andb_size
, extract_nps_andb_size
},
1892 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
1893 { 0, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_fxorb_size
, extract_nps_fxorb_size
},
1895 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
1896 { 0, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_wxorb_size
, extract_nps_wxorb_size
},
1898 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
1899 { 6, 5, 0, ARC_OPERAND_IR
, NULL
, NULL
},
1901 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
1902 { 4, 5, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1904 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
1905 { 0, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_qcmp_size
, extract_nps_qcmp_size
},
1907 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
1908 { 1, 14, 0, ARC_OPERAND_UNSIGNED
, NULL
, extract_nps_qcmp_m1
},
1910 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
1911 { 1, 15, 0, ARC_OPERAND_UNSIGNED
, NULL
, extract_nps_qcmp_m2
},
1913 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
1914 { 4, 5, 0, ARC_OPERAND_UNSIGNED
, NULL
, extract_nps_qcmp_m3
},
1916 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
1917 { 0, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_calc_entry_size
, extract_nps_calc_entry_size
},
1919 #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
1920 { 3, 8, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_8_dst
, extract_nps_3bit_reg_at_8_dst
},
1922 #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
1923 { 3, 8, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_8_dst
, extract_nps_3bit_reg_at_8_dst
},
1925 #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
1926 { 3, 5, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_5_src2
, extract_nps_3bit_reg_at_5_src2
},
1928 #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
1929 { 5, 25, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_bitop2_size
, extract_nps_bitop2_size
},
1931 #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
1932 { 5, 20, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_bitop1_size
, extract_nps_bitop1_size
},
1934 #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
1935 { 5, 0, 0, ARC_OPERAND_UNSIGNED
, insert_nps_bitop_dst_pos3_pos4
, extract_nps_bitop_dst_pos3_pos4
},
1937 #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
1938 { 5, 42, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1940 #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
1941 { 5, 37, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1943 #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
1944 { 5, 15, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1946 #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
1947 { 5, 10, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1949 #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
1950 { 5, 32, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1952 #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
1953 { 5, 20, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1955 #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
1956 { 5, 5, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1958 #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
1959 { 5, 0, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1961 #define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
1962 { 2, 0, 0, ARC_OPERAND_UNSIGNED
, insert_nps_bitop_mod4
, extract_nps_bitop_mod4
},
1964 #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
1965 { 2, 29, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1967 #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
1968 { 2, 27, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1970 #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
1971 { 2, 25, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1973 #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
1974 { 5, 20, 0, ARC_OPERAND_UNSIGNED
, insert_nps_bitop_ins_ext
, extract_nps_bitop_ins_ext
},
1976 #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
1977 { 3, 3, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1979 #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
1980 { 3, 6, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_field_size
, extract_nps_field_size
},
1982 #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
1983 { 3, 9, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_shift_factor
, extract_nps_shift_factor
},
1985 #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
1986 { 3, 12, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_bits_to_scramble
, extract_nps_bits_to_scramble
},
1988 #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
1989 { 5, 5, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
1991 #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
1992 { 8, 5, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_bdlen_max_len
, extract_nps_bdlen_max_len
},
1994 #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
1995 { 4, 6, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_min_hofs
, extract_nps_min_hofs
},
1997 #define NPS_PSBC (NPS_MIN_HOFS + 1)
1998 { 1, 11, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2000 #define NPS_DPI_DST (NPS_PSBC + 1)
2001 { 5, 11, 0, ARC_OPERAND_IR
, NULL
, NULL
},
2003 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B but doesn't duplicate an operand */
2004 #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
2005 { 3, 24, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_24_dst
, extract_nps_3bit_reg_at_24_dst
},
2007 #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
2008 { 5, 6, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_hash_width
, extract_nps_hash_width
},
2010 #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2011 { 3, 2, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2013 #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2014 { 1, 5, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2016 #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2017 { 2, 0, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2019 #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
2020 { 3, 2, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_hash_len
, extract_nps_hash_len
},
2022 #define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2023 { 2, 0, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2025 #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2026 { 1, 5, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2028 #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2029 { 3, 8, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2031 #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2032 { 3, 5, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2034 #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2035 { 3, 2, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2037 #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2038 { 2, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_index3
, extract_nps_index3
},
2040 #define COLON (NPS_E4BY_INDEX3 + 1)
2041 { 0, 0, 0, ARC_OPERAND_COLON
| ARC_OPERAND_FAKE
, NULL
, NULL
},
2043 #define NPS_BD (COLON + 1)
2044 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_bd
, extract_nps_bd
},
2046 #define NPS_JID (NPS_BD + 1)
2047 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_jid
, extract_nps_jid
},
2049 #define NPS_LBD (NPS_JID + 1)
2050 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_lbd
, extract_nps_lbd
},
2052 #define NPS_MBD (NPS_LBD + 1)
2053 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_mbd
, extract_nps_mbd
},
2055 #define NPS_SD (NPS_MBD + 1)
2056 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_sd
, extract_nps_sd
},
2058 #define NPS_SM (NPS_SD + 1)
2059 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_sm
, extract_nps_sm
},
2061 #define NPS_XA (NPS_SM + 1)
2062 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_xa
, extract_nps_xa
},
2064 #define NPS_XD (NPS_XA + 1)
2065 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_xd
, extract_nps_xd
},
2067 #define NPS_CD (NPS_XD + 1)
2068 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_cd
, extract_nps_cd
},
2070 #define NPS_CBD (NPS_CD + 1)
2071 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_cbd
, extract_nps_cbd
},
2073 #define NPS_CJID (NPS_CBD + 1)
2074 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_cjid
, extract_nps_cjid
},
2076 #define NPS_CLBD (NPS_CJID + 1)
2077 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_clbd
, extract_nps_clbd
},
2079 #define NPS_CM (NPS_CLBD + 1)
2080 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_cm
, extract_nps_cm
},
2082 #define NPS_CSD (NPS_CM + 1)
2083 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_csd
, extract_nps_csd
},
2085 #define NPS_CXA (NPS_CSD + 1)
2086 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_cxa
, extract_nps_cxa
},
2088 #define NPS_CXD (NPS_CXA + 1)
2089 { 0, 0, 0, ARC_OPERAND_ADDRTYPE
| ARC_OPERAND_NCHK
, insert_nps_cxd
, extract_nps_cxd
},
2091 #define NPS_BD_TYPE (NPS_CXD + 1)
2092 { 1, 10, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2094 #define NPS_BMU_NUM (NPS_BD_TYPE + 1)
2095 { 3, 0, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_bd_num_buff
, extract_nps_bd_num_buff
},
2097 #define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2098 { 4, 6, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2100 #define NPS_PMU_NUM_JOB (NPS_PMU_NXT_DST + 1)
2101 { 2, 6, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_pmu_num_job
, extract_nps_pmu_num_job
},
2103 #define NPS_R_DST_3B_48 (NPS_PMU_NUM_JOB + 1)
2104 { 3, 40, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_40_dst
, extract_nps_3bit_reg_at_40_dst
},
2106 #define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
2107 { 3, 40, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_40_dst
, extract_nps_3bit_reg_at_40_dst
},
2109 #define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
2110 { 3, 37, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_37_src2
, extract_nps_3bit_reg_at_37_src2
},
2112 #define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
2113 { 3, 56, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_56_dst
, extract_nps_3bit_reg_at_56_dst
},
2115 #define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
2116 { 3, 56, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_56_dst
, extract_nps_3bit_reg_at_56_dst
},
2118 #define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
2119 { 3, 53, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_3bit_reg_at_53_src2
, extract_nps_3bit_reg_at_53_src2
},
2121 #define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
2122 { 6, 53, 0, ARC_OPERAND_IR
, NULL
, NULL
},
2124 #define NPS_RB_64 (NPS_RA_64 + 1)
2125 { 5, 48, 0, ARC_OPERAND_IR
, NULL
, NULL
},
2127 #define NPS_RBdup_64 (NPS_RB_64 + 1)
2128 { 5, 43, 0, ARC_OPERAND_IR
| ARC_OPERAND_DUPLICATE
, NULL
, NULL
},
2130 #define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
2131 { 10, 43, 0, ARC_OPERAND_IR
| ARC_OPERAND_NCHK
, insert_nps_rbdouble_64
, extract_nps_rbdouble_64
},
2133 #define NPS_RC_64 (NPS_RBdouble_64 + 1)
2134 { 5, 43, 0, ARC_OPERAND_IR
, NULL
, NULL
},
2136 #define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
2137 { 16, 0, 0, ARC_OPERAND_UNSIGNED
, NULL
, NULL
},
2139 #define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
2140 { 6, 16, 0, ARC_OPERAND_UNSIGNED
| ARC_OPERAND_NCHK
, insert_nps_proto_size
, extract_nps_proto_size
}
2142 const unsigned arc_num_operands
= ARRAY_SIZE (arc_operands
);
2144 const unsigned arc_Toperand
= FKT_T
;
2145 const unsigned arc_NToperand
= FKT_NT
;
2147 const unsigned char arg_none
[] = { 0 };
2148 const unsigned char arg_32bit_rarbrc
[] = { RA
, RB
, RC
};
2149 const unsigned char arg_32bit_zarbrc
[] = { ZA
, RB
, RC
};
2150 const unsigned char arg_32bit_rbrbrc
[] = { RB
, RBdup
, RC
};
2151 const unsigned char arg_32bit_rarbu6
[] = { RA
, RB
, UIMM6_20
};
2152 const unsigned char arg_32bit_zarbu6
[] = { ZA
, RB
, UIMM6_20
};
2153 const unsigned char arg_32bit_rbrbu6
[] = { RB
, RBdup
, UIMM6_20
};
2154 const unsigned char arg_32bit_rbrbs12
[] = { RB
, RBdup
, SIMM12_20
};
2155 const unsigned char arg_32bit_ralimmrc
[] = { RA
, LIMM
, RC
};
2156 const unsigned char arg_32bit_rarblimm
[] = { RA
, RB
, LIMM
};
2157 const unsigned char arg_32bit_zalimmrc
[] = { ZA
, LIMM
, RC
};
2158 const unsigned char arg_32bit_zarblimm
[] = { ZA
, RB
, LIMM
};
2160 const unsigned char arg_32bit_rbrblimm
[] = { RB
, RBdup
, LIMM
};
2161 const unsigned char arg_32bit_ralimmu6
[] = { RA
, LIMM
, UIMM6_20
};
2162 const unsigned char arg_32bit_zalimmu6
[] = { ZA
, LIMM
, UIMM6_20
};
2164 const unsigned char arg_32bit_zalimms12
[] = { ZA
, LIMM
, SIMM12_20
};
2165 const unsigned char arg_32bit_ralimmlimm
[] = { RA
, LIMM
, LIMMdup
};
2166 const unsigned char arg_32bit_zalimmlimm
[] = { ZA
, LIMM
, LIMMdup
};
2168 const unsigned char arg_32bit_rbrc
[] = { RB
, RC
};
2169 const unsigned char arg_32bit_zarc
[] = { ZA
, RC
};
2170 const unsigned char arg_32bit_rbu6
[] = { RB
, UIMM6_20
};
2171 const unsigned char arg_32bit_zau6
[] = { ZA
, UIMM6_20
};
2172 const unsigned char arg_32bit_rblimm
[] = { RB
, LIMM
};
2173 const unsigned char arg_32bit_zalimm
[] = { ZA
, LIMM
};
2175 const unsigned char arg_32bit_limmrc
[] = { LIMM
, RC
};
2176 const unsigned char arg_32bit_limmu6
[] = { LIMM
, UIMM6_20
};
2177 const unsigned char arg_32bit_limms12
[] = { LIMM
, SIMM12_20
};
2178 const unsigned char arg_32bit_limmlimm
[] = { LIMM
, LIMMdup
};
2180 const unsigned char arg_32bit_rc
[] = { RC
};
2181 const unsigned char arg_32bit_u6
[] = { UIMM6_20
};
2182 const unsigned char arg_32bit_limm
[] = { LIMM
};
2184 /* The opcode table.
2186 The format of the opcode table is:
2188 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2190 The table is organised such that, where possible, all instructions with
2191 the same mnemonic are together in a block. When the assembler searches
2192 for a suitable instruction the entries are checked in table order, so
2193 more specific, or specialised cases should appear earlier in the table.
2195 As an example, consider two instructions 'add a,b,u6' and 'add
2196 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2197 32-bit instruction, while the second takes a 32-bit immediate that is
2198 encoded in a follow-on 32-bit, making the total instruction length
2199 64-bits. In this case the u6 variant must appear first in the table, as
2200 all u6 immediates could also be encoded using the 'limm' extension,
2201 however, we want to use the shorter instruction wherever possible.
2203 It is possible though to split instructions with the same mnemonic into
2204 multiple groups. However, the instructions are still checked in table
2205 order, even across groups. The only time that instructions with the
2206 same mnemonic should be split into different groups is when different
2207 variants of the instruction appear in different architectures, in which
2208 case, grouping all instructions from a particular architecture together
2209 might be preferable to merging the instruction into the main instruction
2212 An example of this split instruction groups can be found with the 'sync'
2213 instruction. The core arc architecture provides a 'sync' instruction,
2214 while the nps instruction set extension provides 'sync.rd' and
2215 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2216 mnemonic, so we end up with two groups for the sync instruction, the
2217 first within the core arc instruction table, and the second within the
2218 nps extension instructions. */
2219 const struct arc_opcode arc_opcodes
[] =
2221 #include "arc-tbl.h"
2222 #include "arc-nps400-tbl.h"
2223 #include "arc-ext-tbl.h"
2225 { NULL
, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2228 /* List with special cases instructions and the applicable flags. */
2229 const struct arc_flag_special arc_flag_special_cases
[] =
2231 { "b", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
2232 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
2233 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
2234 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
2235 { "bl", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
2236 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
2237 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
2238 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
2239 { "br", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
2240 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
2241 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
2242 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
2243 { "j", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
2244 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
2245 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
2246 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
2247 { "jl", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
2248 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
2249 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
2250 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
2251 { "lp", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
2252 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
2253 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
2254 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
2255 { "set", { F_ALWAYS
, F_RA
, F_EQUAL
, F_ZERO
, F_NOTEQUAL
, F_NOTZERO
, F_POZITIVE
,
2256 F_PL
, F_NEGATIVE
, F_MINUS
, F_CARRY
, F_CARRYSET
, F_LOWER
, F_CARRYCLR
,
2257 F_NOTCARRY
, F_HIGHER
, F_OVERFLOWSET
, F_OVERFLOW
, F_NOTOVERFLOW
,
2258 F_OVERFLOWCLR
, F_GT
, F_GE
, F_LT
, F_LE
, F_HI
, F_LS
, F_PNZ
, F_NULL
} },
2259 { "ld", { F_SIZEB17
, F_SIZEW17
, F_H17
, F_NULL
} },
2260 { "st", { F_SIZEB1
, F_SIZEW1
, F_H1
, F_NULL
} }
2263 const unsigned arc_num_flag_special
= ARRAY_SIZE (arc_flag_special_cases
);
2266 const struct arc_reloc_equiv_tab arc_reloc_equiv
[] =
2268 { "sda", "ld", { F_ASFAKE
, F_H1
, F_NULL
},
2269 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST1
},
2270 { "sda", "st", { F_ASFAKE
, F_H1
, F_NULL
},
2271 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST1
},
2272 { "sda", "ld", { F_ASFAKE
, F_SIZEW7
, F_NULL
},
2273 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST1
},
2274 { "sda", "st", { F_ASFAKE
, F_SIZEW7
, F_NULL
},
2275 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST1
},
2277 /* Next two entries will cover the undefined behavior ldb/stb with
2279 { "sda", "ld", { F_ASFAKE
, F_SIZEB7
, F_NULL
},
2280 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST
},
2281 { "sda", "st", { F_ASFAKE
, F_SIZEB7
, F_NULL
},
2282 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST
},
2284 { "sda", "ld", { F_ASFAKE
, F_NULL
},
2285 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST2
},
2286 { "sda", "st", { F_ASFAKE
, F_NULL
},
2287 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST2
},
2288 { "sda", "ldd", { F_ASFAKE
, F_NULL
},
2289 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST2
},
2290 { "sda", "std", { F_ASFAKE
, F_NULL
},
2291 BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST2
},
2293 /* Short instructions. */
2294 { "sda", 0, { F_NULL
}, BFD_RELOC_ARC_SDA16_LD
, BFD_RELOC_ARC_SDA16_LD
},
2295 { "sda", 0, { F_NULL
}, -SIMM10_A16_7_Sbis
, BFD_RELOC_ARC_SDA16_LD1
},
2296 { "sda", 0, { F_NULL
}, BFD_RELOC_ARC_SDA16_LD2
, BFD_RELOC_ARC_SDA16_LD2
},
2297 { "sda", 0, { F_NULL
}, BFD_RELOC_ARC_SDA16_ST2
, BFD_RELOC_ARC_SDA16_ST2
},
2299 { "sda", 0, { F_NULL
}, BFD_RELOC_ARC_32_ME
, BFD_RELOC_ARC_SDA32_ME
},
2300 { "sda", 0, { F_NULL
}, BFD_RELOC_ARC_SDA_LDST
, BFD_RELOC_ARC_SDA_LDST
},
2302 { "plt", 0, { F_NULL
}, BFD_RELOC_ARC_S25H_PCREL
,
2303 BFD_RELOC_ARC_S25H_PCREL_PLT
},
2304 { "plt", 0, { F_NULL
}, BFD_RELOC_ARC_S21H_PCREL
,
2305 BFD_RELOC_ARC_S21H_PCREL_PLT
},
2306 { "plt", 0, { F_NULL
}, BFD_RELOC_ARC_S25W_PCREL
,
2307 BFD_RELOC_ARC_S25W_PCREL_PLT
},
2308 { "plt", 0, { F_NULL
}, BFD_RELOC_ARC_S21W_PCREL
,
2309 BFD_RELOC_ARC_S21W_PCREL_PLT
},
2311 { "plt", 0, { F_NULL
}, BFD_RELOC_ARC_32_ME
, BFD_RELOC_ARC_PLT32
}
2314 const unsigned arc_num_equiv_tab
= ARRAY_SIZE (arc_reloc_equiv
);
2316 const struct arc_pseudo_insn arc_pseudo_insns
[] =
2318 { "push", "st", ".aw", 5, { { RC
, 0, 0, 0 }, { BRAKET
, 1, 0, 1 },
2319 { RB
, 1, 28, 2 }, { SIMM9_8
, 1, -4, 3 },
2320 { BRAKETdup
, 1, 0, 4} } },
2321 { "pop", "ld", ".ab", 5, { { RA
, 0, 0, 0 }, { BRAKET
, 1, 0, 1 },
2322 { RB
, 1, 28, 2 }, { SIMM9_8
, 1, 4, 3 },
2323 { BRAKETdup
, 1, 0, 4} } },
2325 { "brgt", "brlt", NULL
, 3, { { RB
, 0, 0, 1 }, { RC
, 0, 0, 0 },
2326 { SIMM9_A16_8
, 0, 0, 2 } } },
2327 { "brgt", "brge", NULL
, 3, { { RB
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
2328 { SIMM9_A16_8
, 0, 0, 2 } } },
2329 { "brgt", "brlt", NULL
, 3, { { RB
, 0, 0, 1 }, { LIMM
, 0, 0, 0 },
2330 { SIMM9_A16_8
, 0, 0, 2 } } },
2331 { "brgt", "brlt", NULL
, 3, { { LIMM
, 0, 0, 1 }, { RC
, 0, 0, 0 },
2332 { SIMM9_A16_8
, 0, 0, 2 } } },
2333 { "brgt", "brge", NULL
, 3, { { LIMM
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
2334 { SIMM9_A16_8
, 0, 0, 2 } } },
2336 { "brhi", "brlo", NULL
, 3, { { RB
, 0, 0, 1 }, { RC
, 0, 0, 0 },
2337 { SIMM9_A16_8
, 0, 0, 2 } } },
2338 { "brhi", "brhs", NULL
, 3, { { RB
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
2339 { SIMM9_A16_8
, 0, 0, 2 } } },
2340 { "brhi", "brlo", NULL
, 3, { { RB
, 0, 0, 1 }, { LIMM
, 0, 0, 0 },
2341 { SIMM9_A16_8
, 0, 0, 2 } } },
2342 { "brhi", "brlo", NULL
, 3, { { LIMM
, 0, 0, 1 }, { RC
, 0, 0, 0 },
2343 { SIMM9_A16_8
, 0, 0, 2 } } },
2344 { "brhi", "brhs", NULL
, 3, { { LIMM
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
2345 { SIMM9_A16_8
, 0, 0, 2 } } },
2347 { "brle", "brge", NULL
, 3, { { RB
, 0, 0, 1 }, { RC
, 0, 0, 0 },
2348 { SIMM9_A16_8
, 0, 0, 2 } } },
2349 { "brle", "brlt", NULL
, 3, { { RB
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
2350 { SIMM9_A16_8
, 0, 0, 2 } } },
2351 { "brle", "brge", NULL
, 3, { { RB
, 0, 0, 1 }, { LIMM
, 0, 0, 0 },
2352 { SIMM9_A16_8
, 0, 0, 2 } } },
2353 { "brle", "brge", NULL
, 3, { { LIMM
, 0, 0, 1 }, { RC
, 0, 0, 0 },
2354 { SIMM9_A16_8
, 0, 0, 2 } } },
2355 { "brle", "brlt", NULL
, 3, { { LIMM
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
2356 { SIMM9_A16_8
, 0, 0, 2 } } },
2358 { "brls", "brhs", NULL
, 3, { { RB
, 0, 0, 1 }, { RC
, 0, 0, 0 },
2359 { SIMM9_A16_8
, 0, 0, 2 } } },
2360 { "brls", "brlo", NULL
, 3, { { RB
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
2361 { SIMM9_A16_8
, 0, 0, 2 } } },
2362 { "brls", "brhs", NULL
, 3, { { RB
, 0, 0, 1 }, { LIMM
, 0, 0, 0 },
2363 { SIMM9_A16_8
, 0, 0, 2 } } },
2364 { "brls", "brhs", NULL
, 3, { { LIMM
, 0, 0, 1 }, { RC
, 0, 0, 0 },
2365 { SIMM9_A16_8
, 0, 0, 2 } } },
2366 { "brls", "brlo", NULL
, 3, { { LIMM
, 0, 0, 0 }, { UIMM6_8
, 0, 1, 1 },
2367 { SIMM9_A16_8
, 0, 0, 2 } } },
2370 const unsigned arc_num_pseudo_insn
=
2371 sizeof (arc_pseudo_insns
) / sizeof (*arc_pseudo_insns
);
2373 const struct arc_aux_reg arc_aux_regs
[] =
2376 #define DEF(ADDR, CPU, SUBCLASS, NAME) \
2377 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
2379 #include "arc-regs.h"
2384 const unsigned arc_num_aux_regs
= ARRAY_SIZE (arc_aux_regs
);
2386 /* NOTE: The order of this array MUST be consistent with 'enum
2387 arc_rlx_types' located in tc-arc.h! */
2388 const struct arc_opcode arc_relax_opcodes
[] =
2390 { NULL
, 0x0, 0x0, 0x0, ARITH
, NONE
, { UNUSED
}, { 0 } },
2392 /* bl_s s13 11111sssssssssss. */
2393 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2394 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, BRANCH
, NONE
,
2395 { SIMM13_A32_5_S
}, { 0 }},
2397 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2398 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2399 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, BRANCH
, NONE
,
2400 { SIMM25_A32_5
}, { C_D
}},
2402 /* b_s s10 1111000sssssssss. */
2403 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2404 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, BRANCH
, NONE
,
2405 { SIMM10_A16_7_S
}, { 0 }},
2407 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2408 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2409 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, BRANCH
, NONE
,
2410 { SIMM25_A16_5
}, { C_D
}},
2412 /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
2413 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2414 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, ARITH
, NONE
,
2415 { RC_S
, RB_S
, UIMM3_13_S
}, { 0 }},
2417 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
2419 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2420 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, ARITH
, NONE
,
2421 { RA
, RB
, UIMM6_20
}, { C_F
}},
2423 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2424 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2425 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, ARITH
, NONE
,
2426 { RA
, RB
, LIMM
}, { C_F
}},
2428 /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
2429 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2430 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, MEMORY
, NONE
,
2431 { RC_S
, BRAKET
, RB_S
, UIMM7_A32_11_S
, BRAKETdup
}, { 0 }},
2433 /* ld<.di><.aa><.x><zz> a,b,s9
2434 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
2435 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2436 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, MEMORY
, NONE
,
2437 { RA
, BRAKET
, RB
, SIMM9_8
, BRAKETdup
},
2438 { C_ZZ23
, C_DI20
, C_AA21
, C_X25
}},
2440 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2441 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2442 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, MEMORY
, NONE
,
2443 { RA
, BRAKET
, RB
, LIMM
, BRAKETdup
},
2444 { C_ZZ13
, C_DI16
, C_AA8
, C_X15
}},
2446 /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
2447 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2448 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, MEMORY
, NONE
,
2449 { RB_S
, UIMM8_8_S
}, { 0 }},
2451 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
2453 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2454 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, MEMORY
, NONE
,
2455 { RB
, SIMM12_20
}, { C_F
}},
2457 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2458 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2459 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, MEMORY
, NONE
,
2460 { RB
, LIMM
}, { C_F
}},
2462 /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
2463 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2464 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, ARITH
, NONE
,
2465 { RC_S
, RB_S
, UIMM3_13_S
}, { 0 }},
2467 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
2469 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2470 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, ARITH
, NONE
,
2471 { RA
, RB
, UIMM6_20
}, { C_F
}},
2473 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2474 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2475 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, ARITH
, NONE
,
2476 { RA
, RB
, LIMM
}, { C_F
}},
2478 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
2480 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM
2481 | ARC_OPCODE_ARCv2HS
, ARITH
, MPY6E
, { RA
, RB
, UIMM6_20
}, { C_F
}},
2483 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2484 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM
2485 | ARC_OPCODE_ARCv2HS
, ARITH
, MPY6E
, { RA
, RB
, LIMM
}, { C_F
}},
2487 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
2489 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2490 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, MEMORY
, NONE
,
2491 { RB
, UIMM6_20
}, { C_F
, C_CC
}},
2493 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2494 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2495 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, MEMORY
, NONE
,
2496 { RB
, LIMM
}, { C_F
, C_CC
}},
2498 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
2500 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2501 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, ARITH
, NONE
,
2502 { RB
, RBdup
, UIMM6_20
}, { C_F
, C_CC
}},
2504 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2505 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600
| ARC_OPCODE_ARC700
2506 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS
, ARITH
, NONE
,
2507 { RB
, RBdup
, LIMM
}, { C_F
, C_CC
}}
2510 const unsigned arc_num_relax_opcodes
= ARRAY_SIZE (arc_relax_opcodes
);
2512 /* Return length of an opcode in bytes. */
2515 arc_opcode_len (const struct arc_opcode
*opcode
)
2517 if (opcode
->mask
< 0x10000ull
)
2520 if (opcode
->mask
< 0x100000000ull
)
2523 if (opcode
->mask
< 0x1000000000000ull
)