opcodes/arc-opc.c

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software Foundation,
  20    Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  21
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "bfd.h"
  25 #include "opcode/arc.h"
  26 #include "opintl.h"
  27 #include "libiberty.h"
  28
  29 /* Insert RB register into a 32-bit opcode.  */
  30 static unsigned
  31 insert_rb (unsigned insn,
  32            int value,
  33            const char **errmsg ATTRIBUTE_UNUSED)
  34 {
  35   return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
  36 }
  37
  38 static int
  39 extract_rb (unsigned insn ATTRIBUTE_UNUSED,
  40             bfd_boolean * invalid ATTRIBUTE_UNUSED)
  41 {
  42   int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
  43
  44   if (value == 0x3e && invalid)
  45     *invalid = TRUE; /* A limm operand, it should be extracted in a
  46                         different way.  */
  47
  48   return value;
  49 }
  50
  51 static unsigned
  52 insert_rad (unsigned insn,
  53             int value,
  54             const char **errmsg ATTRIBUTE_UNUSED)
  55 {
  56   if (value & 0x01)
  57     *errmsg = _("Improper register value.");
  58
  59   return insn | (value & 0x3F);
  60 }
  61
  62 static unsigned
  63 insert_rcd (unsigned insn,
  64             int value,
  65             const char **errmsg ATTRIBUTE_UNUSED)
  66 {
  67   if (value & 0x01)
  68     *errmsg = _("Improper register value.");
  69
  70   return insn | ((value & 0x3F) << 6);
  71 }
  72
  73 /* Dummy insert ZERO operand function.  */
  74
  75 static unsigned
  76 insert_za (unsigned insn,
  77            int value,
  78            const char **errmsg)
  79 {
  80   if (value)
  81     *errmsg = _("operand is not zero");
  82   return insn;
  83 }
  84
  85 /* Insert Y-bit in bbit/br instructions.  This function is called only
  86    when solving fixups.  */
  87
  88 static unsigned
  89 insert_Ybit (unsigned insn,
  90              int value,
  91              const char **errmsg ATTRIBUTE_UNUSED)
  92 {
  93   if (value > 0)
  94     insn |= 0x08;
  95
  96   return insn;
  97 }
  98
  99 /* Insert Y-bit in bbit/br instructions.  This function is called only
 100    when solving fixups.  */
 101
 102 static unsigned
 103 insert_NYbit (unsigned insn,
 104               int value,
 105               const char **errmsg ATTRIBUTE_UNUSED)
 106 {
 107   if (value < 0)
 108     insn |= 0x08;
 109
 110   return insn;
 111 }
 112
 113 /* Insert H register into a 16-bit opcode.  */
 114
 115 static unsigned
 116 insert_rhv1 (unsigned insn,
 117              int value,
 118              const char **errmsg ATTRIBUTE_UNUSED)
 119 {
 120   return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
 121 }
 122
 123 static int
 124 extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
 125               bfd_boolean * invalid ATTRIBUTE_UNUSED)
 126 {
 127   int value = 0;
 128
 129   return value;
 130 }
 131
 132 /* Insert H register into a 16-bit opcode.  */
 133
 134 static unsigned
 135 insert_rhv2 (unsigned insn,
 136              int value,
 137              const char **errmsg)
 138 {
 139   if (value == 0x1E)
 140     *errmsg =
 141       _("Register R30 is a limm indicator for this type of instruction.");
 142   return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
 143 }
 144
 145 static int
 146 extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
 147               bfd_boolean * invalid ATTRIBUTE_UNUSED)
 148 {
 149   int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
 150
 151   return value;
 152 }
 153
 154 static unsigned
 155 insert_r0 (unsigned insn,
 156            int value,
 157            const char **errmsg ATTRIBUTE_UNUSED)
 158 {
 159   if (value != 0)
 160     *errmsg = _("Register must be R0.");
 161   return insn;
 162 }
 163
 164 static int
 165 extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
 166             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 167 {
 168   return 0;
 169 }
 170
 171
 172 static unsigned
 173 insert_r1 (unsigned insn,
 174            int value,
 175            const char **errmsg ATTRIBUTE_UNUSED)
 176 {
 177   if (value != 1)
 178     *errmsg = _("Register must be R1.");
 179   return insn;
 180 }
 181
 182 static int
 183 extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
 184             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 185 {
 186   return 1;
 187 }
 188
 189 static unsigned
 190 insert_r2 (unsigned insn,
 191            int value,
 192            const char **errmsg ATTRIBUTE_UNUSED)
 193 {
 194   if (value != 2)
 195     *errmsg = _("Register must be R2.");
 196   return insn;
 197 }
 198
 199 static int
 200 extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
 201             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 202 {
 203   return 2;
 204 }
 205
 206 static unsigned
 207 insert_r3 (unsigned insn,
 208            int value,
 209            const char **errmsg ATTRIBUTE_UNUSED)
 210 {
 211   if (value != 3)
 212     *errmsg = _("Register must be R3.");
 213   return insn;
 214 }
 215
 216 static int
 217 extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
 218             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 219 {
 220   return 3;
 221 }
 222
 223 static unsigned
 224 insert_sp (unsigned insn,
 225            int value,
 226            const char **errmsg ATTRIBUTE_UNUSED)
 227 {
 228   if (value != 28)
 229     *errmsg = _("Register must be SP.");
 230   return insn;
 231 }
 232
 233 static int
 234 extract_sp (unsigned insn ATTRIBUTE_UNUSED,
 235             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 236 {
 237   return 28;
 238 }
 239
 240 static unsigned
 241 insert_gp (unsigned insn,
 242            int value,
 243            const char **errmsg ATTRIBUTE_UNUSED)
 244 {
 245   if (value != 26)
 246     *errmsg = _("Register must be GP.");
 247   return insn;
 248 }
 249
 250 static int
 251 extract_gp (unsigned insn ATTRIBUTE_UNUSED,
 252             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 253 {
 254   return 26;
 255 }
 256
 257 static unsigned
 258 insert_pcl (unsigned insn,
 259             int value,
 260             const char **errmsg ATTRIBUTE_UNUSED)
 261 {
 262   if (value != 63)
 263     *errmsg = _("Register must be PCL.");
 264   return insn;
 265 }
 266
 267 static int
 268 extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
 269              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 270 {
 271   return 63;
 272 }
 273
 274 static unsigned
 275 insert_blink (unsigned insn,
 276               int value,
 277               const char **errmsg ATTRIBUTE_UNUSED)
 278 {
 279   if (value != 31)
 280     *errmsg = _("Register must be BLINK.");
 281   return insn;
 282 }
 283
 284 static int
 285 extract_blink (unsigned insn ATTRIBUTE_UNUSED,
 286                bfd_boolean * invalid ATTRIBUTE_UNUSED)
 287 {
 288   return 31;
 289 }
 290
 291 static unsigned
 292 insert_ilink1 (unsigned insn,
 293                int value,
 294                const char **errmsg ATTRIBUTE_UNUSED)
 295 {
 296   if (value != 29)
 297     *errmsg = _("Register must be ILINK1.");
 298   return insn;
 299 }
 300
 301 static int
 302 extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
 303                 bfd_boolean * invalid ATTRIBUTE_UNUSED)
 304 {
 305   return 29;
 306 }
 307
 308 static unsigned
 309 insert_ilink2 (unsigned insn,
 310                int value,
 311                const char **errmsg ATTRIBUTE_UNUSED)
 312 {
 313   if (value != 30)
 314     *errmsg = _("Register must be ILINK2.");
 315   return insn;
 316 }
 317
 318 static int
 319 extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
 320                 bfd_boolean * invalid ATTRIBUTE_UNUSED)
 321 {
 322   return 30;
 323 }
 324
 325 static unsigned
 326 insert_ras (unsigned insn,
 327             int value,
 328             const char **errmsg ATTRIBUTE_UNUSED)
 329 {
 330   switch (value)
 331     {
 332     case 0:
 333     case 1:
 334     case 2:
 335     case 3:
 336       insn |= value;
 337       break;
 338     case 12:
 339     case 13:
 340     case 14:
 341     case 15:
 342       insn |= (value - 8);
 343       break;
 344     default:
 345       *errmsg = _("Register must be either r0-r3 or r12-r15.");
 346       break;
 347     }
 348   return insn;
 349 }
 350
 351 static int
 352 extract_ras (unsigned insn ATTRIBUTE_UNUSED,
 353              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 354 {
 355   int value = insn & 0x07;
 356   if (value > 3)
 357     return (value + 8);
 358   else
 359     return value;
 360 }
 361
 362 static unsigned
 363 insert_rbs (unsigned insn,
 364             int value,
 365             const char **errmsg ATTRIBUTE_UNUSED)
 366 {
 367   switch (value)
 368     {
 369     case 0:
 370     case 1:
 371     case 2:
 372     case 3:
 373       insn |= value << 8;
 374       break;
 375     case 12:
 376     case 13:
 377     case 14:
 378     case 15:
 379       insn |= ((value - 8)) << 8;
 380       break;
 381     default:
 382       *errmsg = _("Register must be either r0-r3 or r12-r15.");
 383       break;
 384     }
 385   return insn;
 386 }
 387
 388 static int
 389 extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
 390              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 391 {
 392   int value = (insn >> 8) & 0x07;
 393   if (value > 3)
 394     return (value + 8);
 395   else
 396     return value;
 397 }
 398
 399 static unsigned
 400 insert_rcs (unsigned insn,
 401             int value,
 402             const char **errmsg ATTRIBUTE_UNUSED)
 403 {
 404   switch (value)
 405     {
 406     case 0:
 407     case 1:
 408     case 2:
 409     case 3:
 410       insn |= value << 5;
 411       break;
 412     case 12:
 413     case 13:
 414     case 14:
 415     case 15:
 416       insn |= ((value - 8)) << 5;
 417       break;
 418     default:
 419       *errmsg = _("Register must be either r0-r3 or r12-r15.");
 420       break;
 421     }
 422   return insn;
 423 }
 424
 425 static int
 426 extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
 427              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 428 {
 429   int value = (insn >> 5) & 0x07;
 430   if (value > 3)
 431     return (value + 8);
 432   else
 433     return value;
 434 }
 435
 436 static unsigned
 437 insert_simm3s (unsigned insn,
 438                int value,
 439                const char **errmsg ATTRIBUTE_UNUSED)
 440 {
 441   int tmp = 0;
 442   switch (value)
 443     {
 444     case -1:
 445       tmp = 0x07;
 446       break;
 447     case 0:
 448       tmp = 0x00;
 449       break;
 450     case 1:
 451       tmp = 0x01;
 452       break;
 453     case 2:
 454       tmp = 0x02;
 455       break;
 456     case 3:
 457       tmp = 0x03;
 458       break;
 459     case 4:
 460       tmp = 0x04;
 461       break;
 462     case 5:
 463       tmp = 0x05;
 464       break;
 465     case 6:
 466       tmp = 0x06;
 467       break;
 468     default:
 469       *errmsg = _("Accepted values are from -1 to 6.");
 470       break;
 471     }
 472
 473   insn |= tmp << 8;
 474   return insn;
 475 }
 476
 477 static int
 478 extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
 479                 bfd_boolean * invalid ATTRIBUTE_UNUSED)
 480 {
 481   int value = (insn >> 8) & 0x07;
 482   if (value == 7)
 483     return -1;
 484   else
 485     return value;
 486 }
 487
 488 static unsigned
 489 insert_rrange (unsigned insn,
 490                int value,
 491                const char **errmsg ATTRIBUTE_UNUSED)
 492 {
 493   int reg1 = (value >> 16) & 0xFFFF;
 494   int reg2 = value & 0xFFFF;
 495   if (reg1 != 13)
 496     {
 497       *errmsg = _("First register of the range should be r13.");
 498       return insn;
 499     }
 500   if (reg2 < 13 || reg2 > 26)
 501     {
 502       *errmsg = _("Last register of the range doesn't fit.");
 503       return insn;
 504     }
 505   insn |= ((reg2 - 12) & 0x0F) << 1;
 506   return insn;
 507 }
 508
 509 static int
 510 extract_rrange (unsigned insn  ATTRIBUTE_UNUSED,
 511                 bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 512 {
 513   return (insn >> 1) & 0x0F;
 514 }
 515
 516 static unsigned
 517 insert_fpel (unsigned insn,
 518              int value,
 519              const char **errmsg ATTRIBUTE_UNUSED)
 520 {
 521   if (value != 27)
 522     {
 523       *errmsg = _("Invalid register number, should be fp.");
 524       return insn;
 525     }
 526
 527   insn |= 0x0100;
 528   return insn;
 529 }
 530
 531 static int
 532 extract_fpel (unsigned insn  ATTRIBUTE_UNUSED,
 533               bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 534 {
 535   return (insn & 0x0100) ? 27 : -1;
 536 }
 537
 538 static unsigned
 539 insert_blinkel (unsigned insn,
 540                 int value,
 541                 const char **errmsg ATTRIBUTE_UNUSED)
 542 {
 543   if (value != 31)
 544     {
 545       *errmsg = _("Invalid register number, should be blink.");
 546       return insn;
 547     }
 548
 549   insn |= 0x0200;
 550   return insn;
 551 }
 552
 553 static int
 554 extract_blinkel (unsigned insn  ATTRIBUTE_UNUSED,
 555                  bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 556 {
 557   return (insn & 0x0200) ? 31 : -1;
 558 }
 559
 560 static unsigned
 561 insert_pclel (unsigned insn,
 562               int value,
 563               const char **errmsg ATTRIBUTE_UNUSED)
 564 {
 565   if (value != 63)
 566     {
 567       *errmsg = _("Invalid register number, should be pcl.");
 568       return insn;
 569     }
 570
 571   insn |= 0x0400;
 572   return insn;
 573 }
 574
 575 static int
 576 extract_pclel (unsigned insn  ATTRIBUTE_UNUSED,
 577                bfd_boolean * invalid  ATTRIBUTE_UNUSED)
 578 {
 579   return (insn & 0x0400) ? 63 : -1;
 580 }
 581
 582 #define INSERT_W6
 583 /* mask = 00000000000000000000111111000000
 584    insn = 00011bbb000000000BBBwwwwwwDaaZZ1.  */
 585 static unsigned
 586 insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
 587            int value ATTRIBUTE_UNUSED,
 588            const char **errmsg ATTRIBUTE_UNUSED)
 589 {
 590   insn |= ((value >> 0) & 0x003f) << 6;
 591
 592   return insn;
 593 }
 594
 595 #define EXTRACT_W6
 596 /* mask = 00000000000000000000111111000000.  */
 597 static int
 598 extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
 599             bfd_boolean * invalid ATTRIBUTE_UNUSED)
 600 {
 601   unsigned value = 0;
 602
 603   value |= ((insn >> 6) & 0x003f) << 0;
 604
 605   return value;
 606 }
 607
 608 #define INSERT_G_S
 609 /* mask = 0000011100022000
 610    insn = 01000ggghhhGG0HH.  */
 611 static unsigned
 612 insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
 613             int value ATTRIBUTE_UNUSED,
 614             const char **errmsg ATTRIBUTE_UNUSED)
 615 {
 616   insn |= ((value >> 0) & 0x0007) << 8;
 617   insn |= ((value >> 3) & 0x0003) << 3;
 618
 619   return insn;
 620 }
 621
 622 #define EXTRACT_G_S
 623 /* mask = 0000011100022000.  */
 624 static int
 625 extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
 626              bfd_boolean * invalid ATTRIBUTE_UNUSED)
 627 {
 628   int value = 0;
 629
 630   value |= ((insn >> 8) & 0x0007) << 0;
 631   value |= ((insn >> 3) & 0x0003) << 3;
 632
 633   /* Extend the sign.  */
 634   int signbit = 1 << (6 - 1);
 635   value = (value ^ signbit) - signbit;
 636
 637   return value;
 638 }
 639
 640 /* Include the generic extract/insert functions.  Order is important
 641    as some of the functions present in the .h may be disabled via
 642    defines.  */
 643 #include "arc-fxi.h"
 644
 645 /* The flag operands table.
 646
 647    The format of the table is
 648    NAME CODE BITS SHIFT FAVAIL.  */
 649 const struct arc_flag_operand arc_flag_operands[] =
 650 {
 651 #define F_NULL  0
 652   { 0, 0, 0, 0, 0},
 653 #define F_ALWAYS    (F_NULL + 1)
 654   { "al", 0, 0, 0, 0 },
 655 #define F_RA        (F_ALWAYS + 1)
 656   { "ra", 0, 0, 0, 0 },
 657 #define F_EQUAL     (F_RA + 1)
 658   { "eq", 1, 5, 0, 1 },
 659 #define F_ZERO      (F_EQUAL + 1)
 660   { "z",  1, 5, 0, 0 },
 661 #define F_NOTEQUAL  (F_ZERO + 1)
 662   { "ne", 2, 5, 0, 1 },
 663 #define F_NOTZERO   (F_NOTEQUAL + 1)
 664   { "nz", 2, 5, 0, 0 },
 665 #define F_POZITIVE  (F_NOTZERO + 1)
 666   { "p",  3, 5, 0, 1 },
 667 #define F_PL        (F_POZITIVE + 1)
 668   { "pl", 3, 5, 0, 0 },
 669 #define F_NEGATIVE  (F_PL + 1)
 670   { "n",  4, 5, 0, 1 },
 671 #define F_MINUS     (F_NEGATIVE + 1)
 672   { "mi", 4, 5, 0, 0 },
 673 #define F_CARRY     (F_MINUS + 1)
 674   { "c",  5, 5, 0, 1 },
 675 #define F_CARRYSET  (F_CARRY + 1)
 676   { "cs", 5, 5, 0, 0 },
 677 #define F_LOWER     (F_CARRYSET + 1)
 678   { "lo", 5, 5, 0, 0 },
 679 #define F_CARRYCLR  (F_LOWER + 1)
 680   { "cc", 6, 5, 0, 0 },
 681 #define F_NOTCARRY (F_CARRYCLR + 1)
 682   { "nc", 6, 5, 0, 1 },
 683 #define F_HIGHER   (F_NOTCARRY + 1)
 684   { "hs", 6, 5, 0, 0 },
 685 #define F_OVERFLOWSET (F_HIGHER + 1)
 686   { "vs", 7, 5, 0, 0 },
 687 #define F_OVERFLOW (F_OVERFLOWSET + 1)
 688   { "v",  7, 5, 0, 1 },
 689 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
 690   { "nv", 8, 5, 0, 1 },
 691 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
 692   { "vc", 8, 5, 0, 0 },
 693 #define F_GT       (F_OVERFLOWCLR + 1)
 694   { "gt", 9, 5, 0, 1 },
 695 #define F_GE       (F_GT + 1)
 696   { "ge", 10, 5, 0, 1 },
 697 #define F_LT       (F_GE + 1)
 698   { "lt", 11, 5, 0, 1 },
 699 #define F_LE       (F_LT + 1)
 700   { "le", 12, 5, 0, 1 },
 701 #define F_HI       (F_LE + 1)
 702   { "hi", 13, 5, 0, 1 },
 703 #define F_LS       (F_HI + 1)
 704   { "ls", 14, 5, 0, 1 },
 705 #define F_PNZ      (F_LS + 1)
 706   { "pnz", 15, 5, 0, 1 },
 707
 708   /* FLAG.  */
 709 #define F_FLAG     (F_PNZ + 1)
 710   { "f",  1, 1, 15, 1 },
 711 #define F_FFAKE     (F_FLAG + 1)
 712   { "f",  0, 0, 0, 1 },
 713
 714   /* Delay slot.  */
 715 #define F_ND       (F_FFAKE + 1)
 716   { "nd", 0, 1, 5, 0 },
 717 #define F_D        (F_ND + 1)
 718   { "d",  1, 1, 5, 1 },
 719 #define F_DFAKE    (F_D + 1)
 720   { "d",  0, 0, 0, 1 },
 721
 722   /* Data size.  */
 723 #define F_SIZEB1   (F_DFAKE + 1)
 724   { "b", 1, 2, 1, 1 },
 725 #define F_SIZEB7   (F_SIZEB1 + 1)
 726   { "b", 1, 2, 7, 1 },
 727 #define F_SIZEB17  (F_SIZEB7 + 1)
 728   { "b", 1, 2, 17, 1 },
 729 #define F_SIZEW1   (F_SIZEB17 + 1)
 730   { "w", 2, 2, 1, 0 },
 731 #define F_SIZEW7   (F_SIZEW1 + 1)
 732   { "w", 2, 2, 7, 0 },
 733 #define F_SIZEW17  (F_SIZEW7 + 1)
 734   { "w", 2, 2, 17, 0 },
 735
 736   /* Sign extension.  */
 737 #define F_SIGN6   (F_SIZEW17 + 1)
 738   { "x", 1, 1, 6, 1 },
 739 #define F_SIGN16  (F_SIGN6 + 1)
 740   { "x", 1, 1, 16, 1 },
 741 #define F_SIGNX   (F_SIGN16 + 1)
 742   { "x", 0, 0, 0, 1 },
 743
 744   /* Address write-back modes.  */
 745 #define F_A3       (F_SIGNX + 1)
 746   { "a", 1, 2, 3, 0 },
 747 #define F_A9       (F_A3 + 1)
 748   { "a", 1, 2, 9, 0 },
 749 #define F_A22      (F_A9 + 1)
 750   { "a", 1, 2, 22, 0 },
 751 #define F_AW3      (F_A22 + 1)
 752   { "aw", 1, 2, 3, 1 },
 753 #define F_AW9      (F_AW3 + 1)
 754   { "aw", 1, 2, 9, 1 },
 755 #define F_AW22     (F_AW9 + 1)
 756   { "aw", 1, 2, 22, 1 },
 757 #define F_AB3      (F_AW22 + 1)
 758   { "ab", 2, 2, 3, 1 },
 759 #define F_AB9      (F_AB3 + 1)
 760   { "ab", 2, 2, 9, 1 },
 761 #define F_AB22     (F_AB9 + 1)
 762   { "ab", 2, 2, 22, 1 },
 763 #define F_AS3      (F_AB22 + 1)
 764   { "as", 3, 2, 3, 1 },
 765 #define F_AS9      (F_AS3 + 1)
 766   { "as", 3, 2, 9, 1 },
 767 #define F_AS22     (F_AS9 + 1)
 768   { "as", 3, 2, 22, 1 },
 769 #define F_ASFAKE   (F_AS22 + 1)
 770   { "as", 0, 0, 0, 1 },
 771
 772   /* Cache bypass.  */
 773 #define F_DI5     (F_ASFAKE + 1)
 774   { "di", 1, 1, 5, 1 },
 775 #define F_DI11    (F_DI5 + 1)
 776   { "di", 1, 1, 11, 1 },
 777 #define F_DI15    (F_DI11 + 1)
 778   { "di", 1, 1, 15, 1 },
 779
 780   /* ARCv2 specific.  */
 781 #define F_NT     (F_DI15 + 1)
 782   { "nt", 0, 1, 3, 1},
 783 #define F_T      (F_NT + 1)
 784   { "t", 1, 1, 3, 1},
 785 #define F_H1     (F_T + 1)
 786   { "h", 2, 2, 1, 1 },
 787 #define F_H7     (F_H1 + 1)
 788   { "h", 2, 2, 7, 1 },
 789 #define F_H17    (F_H7 + 1)
 790   { "h", 2, 2, 17, 1 },
 791
 792   /* Fake Flags.  */
 793 #define F_NE   (F_H17 + 1)
 794   { "ne", 0, 0, 0, 1 },
 795 };
 796
 797 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
 798
 799 /* Table of the flag classes.
 800
 801    The format of the table is
 802    CLASS {FLAG_CODE}.  */
 803 const struct arc_flag_class arc_flag_classes[] =
 804 {
 805 #define C_EMPTY     0
 806   { FNONE, { F_NULL } },
 807
 808 #define C_CC        (C_EMPTY + 1)
 809   { CND, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO,
 810            F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET,
 811            F_LOWER, F_CARRYCLR, F_NOTCARRY, F_HIGHER, F_OVERFLOWSET,
 812            F_OVERFLOW, F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
 813            F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
 814
 815 #define C_AA_ADDR3  (C_CC + 1)
 816 #define C_AA27      (C_CC + 1)
 817   { WBM, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
 818 #define C_AA_ADDR9  (C_AA_ADDR3 + 1)
 819 #define C_AA21       (C_AA_ADDR3 + 1)
 820   { WBM, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
 821 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
 822 #define C_AA8      (C_AA_ADDR9 + 1)
 823   { WBM, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
 824
 825 #define C_F         (C_AA_ADDR22 + 1)
 826   { FLG, { F_FLAG, F_NULL } },
 827 #define C_FHARD     (C_F + 1)
 828   { FLG, { F_FFAKE, F_NULL } },
 829
 830 #define C_T         (C_FHARD + 1)
 831   { SBP, { F_NT, F_T, F_NULL } },
 832 #define C_D         (C_T + 1)
 833   { DLY, { F_ND, F_D, F_NULL } },
 834
 835 #define C_DHARD     (C_D + 1)
 836   { DLY, { F_DFAKE, F_NULL } },
 837
 838 #define C_DI20      (C_DHARD + 1)
 839   { DIF, { F_DI11, F_NULL }},
 840 #define C_DI16      (C_DI20 + 1)
 841   { DIF, { F_DI15, F_NULL }},
 842 #define C_DI26      (C_DI16 + 1)
 843   { DIF, { F_DI5, F_NULL }},
 844
 845 #define C_X25       (C_DI26 + 1)
 846   { SGX, { F_SIGN6, F_NULL }},
 847 #define C_X15      (C_X25 + 1)
 848   { SGX, { F_SIGN16, F_NULL }},
 849 #define C_XHARD    (C_X15 + 1)
 850 #define C_X        (C_X15 + 1)
 851   { SGX, { F_SIGNX, F_NULL }},
 852
 853 #define C_ZZ13        (C_X + 1)
 854   { SZM, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
 855 #define C_ZZ23        (C_ZZ13 + 1)
 856   { SZM, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
 857 #define C_ZZ29        (C_ZZ23 + 1)
 858   { SZM, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
 859
 860 #define C_AS        (C_ZZ29 + 1)
 861   { SZM, { F_ASFAKE, F_NULL}},
 862
 863 #define C_NE        (C_AS + 1)
 864   { CND, { F_NE, F_NULL}},
 865 };
 866
 867 /* The operands table.
 868
 869    The format of the operands table is:
 870
 871    BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN.  */
 872 const struct arc_operand arc_operands[] =
 873 {
 874   /* The fields are bits, shift, insert, extract, flags.  The zero
 875      index is used to indicate end-of-list.  */
 876 #define UNUSED          0
 877   { 0, 0, 0, 0, 0, 0 },
 878   /* The plain integer register fields.  Used by 32 bit
 879      instructions.  */
 880 #define RA              (UNUSED + 1)
 881   { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
 882 #define RB              (RA + 1)
 883   { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
 884 #define RC              (RB + 1)
 885   { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
 886 #define RBdup           (RC + 1)
 887   { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
 888
 889 #define RAD             (RBdup + 1)
 890   { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
 891 #define RCD             (RAD + 1)
 892   { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
 893
 894   /* The plain integer register fields.  Used by short
 895      instructions.  */
 896 #define RA16            (RCD + 1)
 897 #define RA_S            (RCD + 1)
 898   { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
 899 #define RB16            (RA16 + 1)
 900 #define RB_S            (RA16 + 1)
 901   { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
 902 #define RB16dup         (RB16 + 1)
 903 #define RB_Sdup         (RB16 + 1)
 904   { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
 905 #define RC16            (RB16dup + 1)
 906 #define RC_S            (RB16dup + 1)
 907   { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
 908 #define R6H             (RC16 + 1)   /* 6bit register field 'h' used
 909                                         by V1 cpus.  */
 910   { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
 911 #define R5H             (R6H + 1)    /* 5bit register field 'h' used
 912                                         by V2 cpus.  */
 913 #define RH_S            (R6H + 1)    /* 5bit register field 'h' used
 914                                         by V2 cpus.  */
 915   { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
 916 #define R5Hdup          (R5H + 1)
 917 #define RH_Sdup         (R5H + 1)
 918   { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
 919     insert_rhv2, extract_rhv2 },
 920
 921 #define RG              (R5Hdup + 1)
 922 #define G_S             (R5Hdup + 1)
 923   { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
 924
 925   /* Fix registers.  */
 926 #define R0              (RG + 1)
 927 #define R0_S            (RG + 1)
 928   { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
 929 #define R1              (R0 + 1)
 930 #define R1_S            (R0 + 1)
 931   { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
 932 #define R2              (R1 + 1)
 933 #define R2_S            (R1 + 1)
 934   { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
 935 #define R3              (R2 + 1)
 936 #define R3_S            (R2 + 1)
 937   { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
 938 #define SP              (R3 + 1)
 939 #define SP_S            (R3 + 1)
 940   { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
 941 #define SPdup           (SP + 1)
 942 #define SP_Sdup         (SP + 1)
 943   { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
 944 #define GP              (SPdup + 1)
 945 #define GP_S            (SPdup + 1)
 946   { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
 947
 948 #define PCL_S           (GP + 1)
 949   { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
 950
 951 #define BLINK           (PCL_S + 1)
 952 #define BLINK_S         (PCL_S + 1)
 953   { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
 954
 955 #define ILINK1          (BLINK + 1)
 956   { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
 957 #define ILINK2          (ILINK1 + 1)
 958   { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
 959
 960   /* Long immediate.  */
 961 #define LIMM            (ILINK2 + 1)
 962 #define LIMM_S          (ILINK2 + 1)
 963   { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
 964 #define LIMMdup         (LIMM + 1)
 965   { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
 966
 967   /* Special operands.  */
 968 #define ZA              (LIMMdup + 1)
 969 #define ZB              (LIMMdup + 1)
 970 #define ZA_S            (LIMMdup + 1)
 971 #define ZB_S            (LIMMdup + 1)
 972 #define ZC_S            (LIMMdup + 1)
 973   { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
 974
 975 #define RRANGE_EL       (ZA + 1)
 976   { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
 977     insert_rrange, extract_rrange},
 978 #define FP_EL           (RRANGE_EL + 1)
 979   { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
 980     insert_fpel, extract_fpel },
 981 #define BLINK_EL        (FP_EL + 1)
 982   { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
 983     insert_blinkel, extract_blinkel },
 984 #define PCL_EL          (BLINK_EL + 1)
 985   { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
 986     insert_pclel, extract_pclel },
 987
 988   /* Fake operand to handle the T flag.  */
 989 #define BRAKET          (PCL_EL + 1)
 990 #define BRAKETdup       (PCL_EL + 1)
 991   { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
 992
 993   /* Fake operand to handle the T flag.  */
 994 #define FKT_T           (BRAKET + 1)
 995   { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
 996   /* Fake operand to handle the T flag.  */
 997 #define FKT_NT          (FKT_T + 1)
 998   { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
 999
1000   /* UIMM6_20 mask = 00000000000000000000111111000000.  */
1001 #define UIMM6_20       (FKT_NT + 1)
1002   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1003
1004   /* SIMM12_20 mask = 00000000000000000000111111222222.  */
1005 #define SIMM12_20       (UIMM6_20 + 1)
1006   {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1007
1008   /* SIMM3_5_S mask = 0000011100000000.  */
1009 #define SIMM3_5_S       (SIMM12_20 + 1)
1010   {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1011    insert_simm3s, extract_simm3s},
1012
1013   /* UIMM7_A32_11_S mask = 0000000000011111.  */
1014 #define UIMM7_A32_11_S       (SIMM3_5_S + 1)
1015   {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1016    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1017    extract_uimm7_a32_11_s},
1018
1019   /* UIMM7_9_S mask = 0000000001111111.  */
1020 #define UIMM7_9_S       (UIMM7_A32_11_S + 1)
1021   {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1022
1023   /* UIMM3_13_S mask = 0000000000000111.  */
1024 #define UIMM3_13_S       (UIMM7_9_S + 1)
1025   {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1026
1027   /* SIMM11_A32_7_S mask = 0000000111111111.  */
1028 #define SIMM11_A32_7_S       (UIMM3_13_S + 1)
1029   {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1030    | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1031
1032   /* UIMM6_13_S mask = 0000000002220111.  */
1033 #define UIMM6_13_S       (SIMM11_A32_7_S + 1)
1034   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1035   /* UIMM5_11_S mask = 0000000000011111.  */
1036 #define UIMM5_11_S       (UIMM6_13_S + 1)
1037   {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1038    extract_uimm5_11_s},
1039
1040   /* SIMM9_A16_8 mask = 00000000111111102000000000000000.  */
1041 #define SIMM9_A16_8       (UIMM5_11_S + 1)
1042   {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1043    | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1044    extract_simm9_a16_8},
1045
1046   /* UIMM6_8 mask = 00000000000000000000111111000000.    */
1047 #define UIMM6_8       (SIMM9_A16_8 + 1)
1048   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1049
1050   /* SIMM21_A16_5 mask = 00000111111111102222222222000000.  */
1051 #define SIMM21_A16_5       (UIMM6_8 + 1)
1052   {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1053    | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1054    insert_simm21_a16_5, extract_simm21_a16_5},
1055
1056   /* SIMM25_A16_5 mask = 00000111111111102222222222003333.  */
1057 #define SIMM25_A16_5       (SIMM21_A16_5 + 1)
1058   {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1059    | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
1060    insert_simm25_a16_5, extract_simm25_a16_5},
1061
1062   /* SIMM10_A16_7_S mask = 0000000111111111.  */
1063 #define SIMM10_A16_7_S       (SIMM25_A16_5 + 1)
1064   {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1065    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
1066    extract_simm10_a16_7_s},
1067
1068 #define SIMM10_A16_7_Sbis    (SIMM10_A16_7_S + 1)
1069   {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1070    | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
1071
1072   /* SIMM7_A16_10_S mask = 0000000000111111.  */
1073 #define SIMM7_A16_10_S       (SIMM10_A16_7_Sbis + 1)
1074   {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1075    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
1076    extract_simm7_a16_10_s},
1077
1078   /* SIMM21_A32_5 mask = 00000111111111002222222222000000.  */
1079 #define SIMM21_A32_5       (SIMM7_A16_10_S + 1)
1080   {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1081    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
1082    extract_simm21_a32_5},
1083
1084   /* SIMM25_A32_5 mask = 00000111111111002222222222003333.  */
1085 #define SIMM25_A32_5       (SIMM21_A32_5 + 1)
1086   {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1087    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
1088    extract_simm25_a32_5},
1089
1090   /* SIMM13_A32_5_S mask = 0000011111111111.  */
1091 #define SIMM13_A32_5_S       (SIMM25_A32_5 + 1)
1092   {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1093    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
1094    extract_simm13_a32_5_s},
1095
1096   /* SIMM8_A16_9_S mask = 0000000001111111.  */
1097 #define SIMM8_A16_9_S       (SIMM13_A32_5_S + 1)
1098   {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1099    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
1100    extract_simm8_a16_9_s},
1101
1102   /* UIMM3_23 mask = 00000000000000000000000111000000.  */
1103 #define UIMM3_23       (SIMM8_A16_9_S + 1)
1104   {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
1105
1106   /* UIMM10_6_S mask = 0000001111111111.  */
1107 #define UIMM10_6_S       (UIMM3_23 + 1)
1108   {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
1109
1110   /* UIMM6_11_S mask = 0000002200011110.  */
1111 #define UIMM6_11_S       (UIMM10_6_S + 1)
1112   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
1113
1114   /* SIMM9_8 mask = 00000000111111112000000000000000.    */
1115 #define SIMM9_8       (UIMM6_11_S + 1)
1116   {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
1117    insert_simm9_8, extract_simm9_8},
1118
1119   /* UIMM10_A32_8_S mask = 0000000011111111.  */
1120 #define UIMM10_A32_8_S       (SIMM9_8 + 1)
1121   {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1122    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
1123    extract_uimm10_a32_8_s},
1124
1125   /* SIMM9_7_S mask = 0000000111111111.  */
1126 #define SIMM9_7_S       (UIMM10_A32_8_S + 1)
1127   {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
1128    extract_simm9_7_s},
1129
1130   /* UIMM6_A16_11_S mask = 0000000000011111.  */
1131 #define UIMM6_A16_11_S       (SIMM9_7_S + 1)
1132   {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1133    | ARC_OPERAND_TRUNCATE  | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
1134    extract_uimm6_a16_11_s},
1135
1136   /* UIMM5_A32_11_S mask = 0000020000011000.  */
1137 #define UIMM5_A32_11_S       (UIMM6_A16_11_S + 1)
1138   {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1139    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
1140    extract_uimm5_a32_11_s},
1141
1142   /* SIMM11_A32_13_S mask = 0000022222200111.    */
1143 #define SIMM11_A32_13_S       (UIMM5_A32_11_S + 1)
1144   {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1145    | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
1146
1147   /* UIMM7_13_S mask = 0000000022220111.  */
1148 #define UIMM7_13_S       (SIMM11_A32_13_S + 1)
1149   {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
1150
1151   /* UIMM6_A16_21 mask = 00000000000000000000011111000000.  */
1152 #define UIMM6_A16_21       (UIMM7_13_S + 1)
1153   {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1154    | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
1155
1156   /* UIMM7_11_S mask = 0000022200011110.  */
1157 #define UIMM7_11_S       (UIMM6_A16_21 + 1)
1158   {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
1159
1160   /* UIMM7_A16_20 mask = 00000000000000000000111111000000.  */
1161 #define UIMM7_A16_20       (UIMM7_11_S + 1)
1162   {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
1163    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
1164    extract_uimm7_a16_20},
1165
1166   /* SIMM13_A16_20 mask = 00000000000000000000111111222222.  */
1167 #define SIMM13_A16_20       (UIMM7_A16_20 + 1)
1168   {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1169    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
1170    extract_simm13_a16_20},
1171
1172   /* UIMM8_8_S mask = 0000000011111111.  */
1173 #define UIMM8_8_S       (SIMM13_A16_20 + 1)
1174   {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
1175
1176   /* W6 mask = 00000000000000000000111111000000.  */
1177 #define W6       (UIMM8_8_S + 1)
1178   {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
1179
1180   /* UIMM6_5_S mask = 0000011111100000.  */
1181 #define UIMM6_5_S       (W6 + 1)
1182   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
1183 };
1184
1185 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
1186
1187 const unsigned arc_Toperand = FKT_T;
1188 const unsigned arc_NToperand = FKT_NT;
1189
1190 /* The opcode table.
1191
1192    The format of the opcode table is:
1193
1194    NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.  */
1195 const struct arc_opcode arc_opcodes[] =
1196 {
1197 #include "arc-tbl.h"
1198 };
1199
1200 const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
1201
1202 /* List with special cases instructions and the applicable flags.  */
1203 const struct arc_flag_special arc_flag_special_cases[] =
1204 {
1205   { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1206            F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1207            F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1208            F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1209   { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1210             F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1211             F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1212             F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1213   { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1214             F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1215             F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1216             F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1217   { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1218            F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1219            F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1220            F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1221   { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1222             F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1223             F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1224             F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1225   { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1226             F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1227             F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1228             F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1229   { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
1230              F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1231              F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
1232              F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
1233   { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
1234   { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
1235 };
1236
1237 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
1238
1239 /* Relocations.  */
1240 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
1241 {
1242   { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
1243     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1244   { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
1245     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1246   { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
1247     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1248   { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
1249     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
1250
1251   /* Next two entries will cover the undefined behavior ldb/stb with
1252      address scaling.  */
1253   { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
1254     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1255   { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
1256     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
1257
1258   { "sda", "ld", { F_ASFAKE, F_NULL },
1259     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1260   { "sda", "st", { F_ASFAKE, F_NULL },
1261     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1262   { "sda", "ldd", { F_ASFAKE, F_NULL },
1263     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
1264   { "sda", "std", { F_ASFAKE, F_NULL },
1265     BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
1266
1267   /* Short instructions.  */
1268   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
1269   { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
1270   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
1271   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
1272
1273   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
1274   { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
1275
1276   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
1277     BFD_RELOC_ARC_S25H_PCREL_PLT },
1278   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
1279     BFD_RELOC_ARC_S21H_PCREL_PLT },
1280   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
1281     BFD_RELOC_ARC_S25W_PCREL_PLT },
1282   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
1283     BFD_RELOC_ARC_S21W_PCREL_PLT },
1284
1285   { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
1286 };
1287
1288 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
1289
1290 const struct arc_pseudo_insn arc_pseudo_insns[] =
1291 {
1292   { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1293                               { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
1294                               { BRAKETdup, 1, 0, 4} } },
1295   { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
1296                              { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
1297                              { BRAKETdup, 1, 0, 4} } },
1298
1299   { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1300                                { SIMM9_A16_8, 0, 0, 2 } } },
1301   { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1302                                { SIMM9_A16_8, 0, 0, 2 } } },
1303   { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1304                                { SIMM9_A16_8, 0, 0, 2 } } },
1305   { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1306                                { SIMM9_A16_8, 0, 0, 2 } } },
1307   { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1308                                { SIMM9_A16_8, 0, 0, 2 } } },
1309
1310   { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1311                                { SIMM9_A16_8, 0, 0, 2 } } },
1312   { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1313                                { SIMM9_A16_8, 0, 0, 2 } } },
1314   { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1315                                { SIMM9_A16_8, 0, 0, 2 } } },
1316   { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1317                                { SIMM9_A16_8, 0, 0, 2 } } },
1318   { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1319                                { SIMM9_A16_8, 0, 0, 2 } } },
1320
1321   { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1322                                { SIMM9_A16_8, 0, 0, 2 } } },
1323   { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1324                                { SIMM9_A16_8, 0, 0, 2 } } },
1325   { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1326                                { SIMM9_A16_8, 0, 0, 2 } } },
1327   { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1328                                { SIMM9_A16_8, 0, 0, 2 } } },
1329   { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1330                                { SIMM9_A16_8, 0, 0, 2 } } },
1331
1332   { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
1333                                { SIMM9_A16_8, 0, 0, 2 } } },
1334   { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1335                                { SIMM9_A16_8, 0, 0, 2 } } },
1336   { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
1337                                { SIMM9_A16_8, 0, 0, 2 } } },
1338   { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
1339                                { SIMM9_A16_8, 0, 0, 2 } } },
1340   { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
1341                                { SIMM9_A16_8, 0, 0, 2 } } },
1342 };
1343
1344 const unsigned arc_num_pseudo_insn =
1345   sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
1346
1347 const struct arc_aux_reg arc_aux_regs[] =
1348 {
1349 #undef DEF
1350 #define DEF(ADDR, NAME)                         \
1351   { ADDR, #NAME, sizeof (#NAME)-1 },
1352
1353 #include "arc-regs.h"
1354
1355 #undef DEF
1356 };
1357
1358 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
1359
1360 /* NOTE: The order of this array MUST be consistent with 'enum
1361    arc_rlx_types' located in tc-arc.h!  */
1362 const struct arc_opcode arc_relax_opcodes[] =
1363 {
1364   { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
1365
1366   /* bl_s s13 11111sssssssssss.  */
1367   { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1368     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1369     { SIMM13_A32_5_S }, { 0 }},
1370
1371   /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt.  */
1372   { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1373     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1374     { SIMM25_A32_5 }, { C_D }},
1375
1376   /* b_s s10 1111000sssssssss.  */
1377   { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1378     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1379     { SIMM10_A16_7_S }, { 0 }},
1380
1381   /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt.  */
1382   { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1383     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
1384     { SIMM25_A16_5 }, { C_D }},
1385
1386   /* add_s c,b,u3 01101bbbccc00uuu.  Wants UIMM3_13_S_PCREL.  */
1387   { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1388     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1389     { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1390
1391   /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA.  Wants
1392      UIMM6_20_PCREL.  */
1393   { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1394     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1395     { RA, RB, UIMM6_20 }, { C_F }},
1396
1397   /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA.  */
1398   { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1399     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1400     { RA, RB, LIMM }, { C_F }},
1401
1402   /* ld_s c,b,u7 10000bbbcccuuuuu.  Wants UIMM7_A32_11_S_PCREL.  */
1403   { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1404     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1405     { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
1406
1407   /* ld<.di><.aa><.x><zz> a,b,s9
1408      00010bbbssssssssSBBBDaaZZXAAAAAA.  Wants SIMM9_8_PCREL.  */
1409   { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1410     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1411     { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
1412     { C_ZZ23, C_DI20, C_AA21, C_X25 }},
1413
1414   /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA.  */
1415   { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1416     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1417     { RA, BRAKET, RB, LIMM, BRAKETdup },
1418     { C_ZZ13, C_DI16, C_AA8, C_X15 }},
1419
1420   /* mov_s b,u8 11011bbbuuuuuuuu.  Wants UIMM8_8_S_PCREL.  */
1421   { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1422     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1423     { RB_S, UIMM8_8_S }, { 0 }},
1424
1425   /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS.  Wants
1426      SIMM12_20_PCREL.  */
1427   { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1428     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1429     { RB, SIMM12_20 }, { C_F }},
1430
1431   /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR.  */
1432   { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1433     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1434     { RB, LIMM }, { C_F }},
1435
1436   /* sub_s c,b,u3 01101bbbccc01uuu.  UIMM3_13_S_PCREL.  */
1437   { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1438     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1439     { RC_S, RB_S, UIMM3_13_S }, { 0 }},
1440
1441   /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
1442      UIMM6_20_PCREL.  */
1443   { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1444     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1445     { RA, RB, UIMM6_20 }, { C_F }},
1446
1447   /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA.  */
1448   { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1449     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1450     { RA, RB, LIMM }, { C_F }},
1451
1452   /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
1453      UIMM6_20_PCREL.  */
1454   { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1455     | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
1456
1457   /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA.  */
1458   { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
1459     | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
1460
1461   /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
1462      UIMM6_20_PCREL.  */
1463   { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1464     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1465     { RB, UIMM6_20 }, { C_F, C_CC }},
1466
1467   /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ.  */
1468   { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1469     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
1470     { RB, LIMM }, { C_F, C_CC }},
1471
1472   /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
1473      UIMM6_20_PCREL.  */
1474   { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1475     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1476     { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
1477
1478   /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ.  */
1479   { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
1480     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
1481     { RB, RBdup, LIMM }, { C_F, C_CC }}
1482 };
1483
1484 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);