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[ARC] Add JLI support.
[deliverable/binutils-gdb.git] / opcodes / arc-opc.c
1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
5
6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software Foundation,
20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
21
22 #include "sysdep.h"
23 #include <stdio.h>
24 #include "bfd.h"
25 #include "opcode/arc.h"
26 #include "opintl.h"
27 #include "libiberty.h"
28
29 /* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
30 instructions. All NPS400 features are built into all ARC target builds as
31 this reduces the chances that regressions might creep in. */
32
33 /* Insert RA register into a 32-bit opcode, with checks. */
34
35 static unsigned long long
36 insert_ra_chk (unsigned long long insn,
37 long long value,
38 const char ** errmsg)
39 {
40 if (value == 60)
41 *errmsg = _("LP_COUNT register cannot be used as destination register");
42
43 return insn | (value & 0x3F);
44 }
45
46 /* Insert RB register into a 32-bit opcode. */
47
48 static unsigned long long
49 insert_rb (unsigned long long insn,
50 long long value,
51 const char ** errmsg ATTRIBUTE_UNUSED)
52 {
53 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
54 }
55
56 /* Insert RB register with checks. */
57
58 static unsigned long long
59 insert_rb_chk (unsigned long long insn,
60 long long value,
61 const char ** errmsg)
62 {
63 if (value == 60)
64 *errmsg = _("LP_COUNT register cannot be used as destination register");
65
66 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
67 }
68
69 static long long
70 extract_rb (unsigned long long insn,
71 bfd_boolean * invalid)
72 {
73 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
74
75 if (value == 0x3e && invalid)
76 *invalid = TRUE; /* A limm operand, it should be extracted in a
77 different way. */
78
79 return value;
80 }
81
82 static unsigned long long
83 insert_rad (unsigned long long insn,
84 long long value,
85 const char ** errmsg)
86 {
87 if (value & 0x01)
88 *errmsg = _("cannot use odd number destination register");
89 if (value == 60)
90 *errmsg = _("LP_COUNT register cannot be used as destination register");
91
92 return insn | (value & 0x3F);
93 }
94
95 static unsigned long long
96 insert_rcd (unsigned long long insn,
97 long long value,
98 const char ** errmsg)
99 {
100 if (value & 0x01)
101 *errmsg = _("cannot use odd number source register");
102
103 return insn | ((value & 0x3F) << 6);
104 }
105
106 /* Dummy insert ZERO operand function. */
107
108 static unsigned long long
109 insert_za (unsigned long long insn,
110 long long value,
111 const char ** errmsg)
112 {
113 if (value)
114 *errmsg = _("operand is not zero");
115 return insn;
116 }
117
118 /* Insert Y-bit in bbit/br instructions. This function is called only
119 when solving fixups. */
120
121 static unsigned long long
122 insert_Ybit (unsigned long long insn,
123 long long value,
124 const char ** errmsg ATTRIBUTE_UNUSED)
125 {
126 if (value > 0)
127 insn |= 0x08;
128
129 return insn;
130 }
131
132 /* Insert Y-bit in bbit/br instructions. This function is called only
133 when solving fixups. */
134
135 static unsigned long long
136 insert_NYbit (unsigned long long insn,
137 long long value,
138 const char ** errmsg ATTRIBUTE_UNUSED)
139 {
140 if (value < 0)
141 insn |= 0x08;
142
143 return insn;
144 }
145
146 /* Insert H register into a 16-bit opcode. */
147
148 static unsigned long long
149 insert_rhv1 (unsigned long long insn,
150 long long value,
151 const char ** errmsg ATTRIBUTE_UNUSED)
152 {
153 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
154 }
155
156 static long long
157 extract_rhv1 (unsigned long long insn,
158 bfd_boolean * invalid ATTRIBUTE_UNUSED)
159 {
160 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
161
162 return value;
163 }
164
165 /* Insert H register into a 16-bit opcode. */
166
167 static unsigned long long
168 insert_rhv2 (unsigned long long insn,
169 long long value,
170 const char ** errmsg)
171 {
172 if (value == 0x1E)
173 *errmsg = _("Register R30 is a limm indicator");
174 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
175 }
176
177 static long long
178 extract_rhv2 (unsigned long long insn,
179 bfd_boolean * invalid ATTRIBUTE_UNUSED)
180 {
181 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
182
183 return value;
184 }
185
186 static unsigned long long
187 insert_r0 (unsigned long long insn,
188 long long value,
189 const char ** errmsg)
190 {
191 if (value != 0)
192 *errmsg = _("Register must be R0");
193 return insn;
194 }
195
196 static long long
197 extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
198 bfd_boolean * invalid ATTRIBUTE_UNUSED)
199 {
200 return 0;
201 }
202
203
204 static unsigned long long
205 insert_r1 (unsigned long long insn,
206 long long value,
207 const char ** errmsg)
208 {
209 if (value != 1)
210 *errmsg = _("Register must be R1");
211 return insn;
212 }
213
214 static long long
215 extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
216 bfd_boolean * invalid ATTRIBUTE_UNUSED)
217 {
218 return 1;
219 }
220
221 static unsigned long long
222 insert_r2 (unsigned long long insn,
223 long long value,
224 const char ** errmsg)
225 {
226 if (value != 2)
227 *errmsg = _("Register must be R2");
228 return insn;
229 }
230
231 static long long
232 extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
233 bfd_boolean * invalid ATTRIBUTE_UNUSED)
234 {
235 return 2;
236 }
237
238 static unsigned long long
239 insert_r3 (unsigned long long insn,
240 long long value,
241 const char ** errmsg)
242 {
243 if (value != 3)
244 *errmsg = _("Register must be R3");
245 return insn;
246 }
247
248 static long long
249 extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
250 bfd_boolean * invalid ATTRIBUTE_UNUSED)
251 {
252 return 3;
253 }
254
255 static unsigned long long
256 insert_sp (unsigned long long insn,
257 long long value,
258 const char ** errmsg)
259 {
260 if (value != 28)
261 *errmsg = _("Register must be SP");
262 return insn;
263 }
264
265 static long long
266 extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
267 bfd_boolean * invalid ATTRIBUTE_UNUSED)
268 {
269 return 28;
270 }
271
272 static unsigned long long
273 insert_gp (unsigned long long insn,
274 long long value,
275 const char ** errmsg)
276 {
277 if (value != 26)
278 *errmsg = _("Register must be GP");
279 return insn;
280 }
281
282 static long long
283 extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
284 bfd_boolean * invalid ATTRIBUTE_UNUSED)
285 {
286 return 26;
287 }
288
289 static unsigned long long
290 insert_pcl (unsigned long long insn,
291 long long value,
292 const char ** errmsg)
293 {
294 if (value != 63)
295 *errmsg = _("Register must be PCL");
296 return insn;
297 }
298
299 static long long
300 extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
301 bfd_boolean * invalid ATTRIBUTE_UNUSED)
302 {
303 return 63;
304 }
305
306 static unsigned long long
307 insert_blink (unsigned long long insn,
308 long long value,
309 const char ** errmsg)
310 {
311 if (value != 31)
312 *errmsg = _("Register must be BLINK");
313 return insn;
314 }
315
316 static long long
317 extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
318 bfd_boolean * invalid ATTRIBUTE_UNUSED)
319 {
320 return 31;
321 }
322
323 static unsigned long long
324 insert_ilink1 (unsigned long long insn,
325 long long value,
326 const char ** errmsg)
327 {
328 if (value != 29)
329 *errmsg = _("Register must be ILINK1");
330 return insn;
331 }
332
333 static long long
334 extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
335 bfd_boolean * invalid ATTRIBUTE_UNUSED)
336 {
337 return 29;
338 }
339
340 static unsigned long long
341 insert_ilink2 (unsigned long long insn,
342 long long value,
343 const char ** errmsg)
344 {
345 if (value != 30)
346 *errmsg = _("Register must be ILINK2");
347 return insn;
348 }
349
350 static long long
351 extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
352 bfd_boolean * invalid ATTRIBUTE_UNUSED)
353 {
354 return 30;
355 }
356
357 static unsigned long long
358 insert_ras (unsigned long long insn,
359 long long value,
360 const char ** errmsg)
361 {
362 switch (value)
363 {
364 case 0:
365 case 1:
366 case 2:
367 case 3:
368 insn |= value;
369 break;
370 case 12:
371 case 13:
372 case 14:
373 case 15:
374 insn |= (value - 8);
375 break;
376 default:
377 *errmsg = _("Register must be either r0-r3 or r12-r15");
378 break;
379 }
380 return insn;
381 }
382
383 static long long
384 extract_ras (unsigned long long insn,
385 bfd_boolean * invalid ATTRIBUTE_UNUSED)
386 {
387 int value = insn & 0x07;
388
389 if (value > 3)
390 return (value + 8);
391 else
392 return value;
393 }
394
395 static unsigned long long
396 insert_rbs (unsigned long long insn,
397 long long value,
398 const char ** errmsg)
399 {
400 switch (value)
401 {
402 case 0:
403 case 1:
404 case 2:
405 case 3:
406 insn |= value << 8;
407 break;
408 case 12:
409 case 13:
410 case 14:
411 case 15:
412 insn |= ((value - 8)) << 8;
413 break;
414 default:
415 *errmsg = _("Register must be either r0-r3 or r12-r15");
416 break;
417 }
418 return insn;
419 }
420
421 static long long
422 extract_rbs (unsigned long long insn,
423 bfd_boolean * invalid ATTRIBUTE_UNUSED)
424 {
425 int value = (insn >> 8) & 0x07;
426
427 if (value > 3)
428 return (value + 8);
429 else
430 return value;
431 }
432
433 static unsigned long long
434 insert_rcs (unsigned long long insn,
435 long long value,
436 const char ** errmsg)
437 {
438 switch (value)
439 {
440 case 0:
441 case 1:
442 case 2:
443 case 3:
444 insn |= value << 5;
445 break;
446 case 12:
447 case 13:
448 case 14:
449 case 15:
450 insn |= ((value - 8)) << 5;
451 break;
452 default:
453 *errmsg = _("Register must be either r0-r3 or r12-r15");
454 break;
455 }
456 return insn;
457 }
458
459 static long long
460 extract_rcs (unsigned long long insn,
461 bfd_boolean * invalid ATTRIBUTE_UNUSED)
462 {
463 int value = (insn >> 5) & 0x07;
464
465 if (value > 3)
466 return (value + 8);
467 else
468 return value;
469 }
470
471 static unsigned long long
472 insert_simm3s (unsigned long long insn,
473 long long value,
474 const char ** errmsg)
475 {
476 int tmp = 0;
477 switch (value)
478 {
479 case -1:
480 tmp = 0x07;
481 break;
482 case 0:
483 tmp = 0x00;
484 break;
485 case 1:
486 tmp = 0x01;
487 break;
488 case 2:
489 tmp = 0x02;
490 break;
491 case 3:
492 tmp = 0x03;
493 break;
494 case 4:
495 tmp = 0x04;
496 break;
497 case 5:
498 tmp = 0x05;
499 break;
500 case 6:
501 tmp = 0x06;
502 break;
503 default:
504 *errmsg = _("Accepted values are from -1 to 6");
505 break;
506 }
507
508 insn |= tmp << 8;
509 return insn;
510 }
511
512 static long long
513 extract_simm3s (unsigned long long insn,
514 bfd_boolean * invalid ATTRIBUTE_UNUSED)
515 {
516 int value = (insn >> 8) & 0x07;
517
518 if (value == 7)
519 return -1;
520 else
521 return value;
522 }
523
524 static unsigned long long
525 insert_rrange (unsigned long long insn,
526 long long value,
527 const char ** errmsg)
528 {
529 int reg1 = (value >> 16) & 0xFFFF;
530 int reg2 = value & 0xFFFF;
531
532 if (reg1 != 13)
533 *errmsg = _("First register of the range should be r13");
534 else if (reg2 < 13 || reg2 > 26)
535 *errmsg = _("Last register of the range doesn't fit");
536 else
537 insn |= ((reg2 - 12) & 0x0F) << 1;
538 return insn;
539 }
540
541 static long long
542 extract_rrange (unsigned long long insn,
543 bfd_boolean * invalid ATTRIBUTE_UNUSED)
544 {
545 return (insn >> 1) & 0x0F;
546 }
547
548 static unsigned long long
549 insert_r13el (unsigned long long insn,
550 long long int value,
551 const char **errmsg)
552 {
553 if (value != 13)
554 {
555 *errmsg = _("Invalid register number, should be fp");
556 return insn;
557 }
558
559 insn |= 0x02;
560 return insn;
561 }
562
563 static unsigned long long
564 insert_fpel (unsigned long long insn,
565 long long value,
566 const char ** errmsg)
567 {
568 if (value != 27)
569 {
570 *errmsg = _("Invalid register number, should be fp");
571 return insn;
572 }
573
574 insn |= 0x0100;
575 return insn;
576 }
577
578 static long long
579 extract_fpel (unsigned long long insn,
580 bfd_boolean * invalid ATTRIBUTE_UNUSED)
581 {
582 return (insn & 0x0100) ? 27 : -1;
583 }
584
585 static unsigned long long
586 insert_blinkel (unsigned long long insn,
587 long long value,
588 const char ** errmsg)
589 {
590 if (value != 31)
591 {
592 *errmsg = _("Invalid register number, should be blink");
593 return insn;
594 }
595
596 insn |= 0x0200;
597 return insn;
598 }
599
600 static long long
601 extract_blinkel (unsigned long long insn,
602 bfd_boolean * invalid ATTRIBUTE_UNUSED)
603 {
604 return (insn & 0x0200) ? 31 : -1;
605 }
606
607 static unsigned long long
608 insert_pclel (unsigned long long insn,
609 long long value,
610 const char ** errmsg)
611 {
612 if (value != 63)
613 {
614 *errmsg = _("Invalid register number, should be pcl");
615 return insn;
616 }
617
618 insn |= 0x0400;
619 return insn;
620 }
621
622 static long long
623 extract_pclel (unsigned long long insn,
624 bfd_boolean * invalid ATTRIBUTE_UNUSED)
625 {
626 return (insn & 0x0400) ? 63 : -1;
627 }
628
629 #define INSERT_W6
630
631 /* mask = 00000000000000000000111111000000
632 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
633
634 static unsigned long long
635 insert_w6 (unsigned long long insn,
636 long long value,
637 const char ** errmsg ATTRIBUTE_UNUSED)
638 {
639 insn |= ((value >> 0) & 0x003f) << 6;
640
641 return insn;
642 }
643
644 #define EXTRACT_W6
645
646 /* mask = 00000000000000000000111111000000. */
647
648 static long long
649 extract_w6 (unsigned long long insn,
650 bfd_boolean * invalid ATTRIBUTE_UNUSED)
651 {
652 unsigned value = 0;
653
654 value |= ((insn >> 6) & 0x003f) << 0;
655
656 return value;
657 }
658
659 #define INSERT_G_S
660
661 /* mask = 0000011100022000
662 insn = 01000ggghhhGG0HH. */
663
664 static unsigned long long
665 insert_g_s (unsigned long long insn,
666 long long value,
667 const char ** errmsg ATTRIBUTE_UNUSED)
668 {
669 insn |= ((value >> 0) & 0x0007) << 8;
670 insn |= ((value >> 3) & 0x0003) << 3;
671
672 return insn;
673 }
674
675 #define EXTRACT_G_S
676
677 /* mask = 0000011100022000. */
678
679 static long long
680 extract_g_s (unsigned long long insn,
681 bfd_boolean * invalid ATTRIBUTE_UNUSED)
682 {
683 int value = 0;
684 int signbit = 1 << (6 - 1);
685
686 value |= ((insn >> 8) & 0x0007) << 0;
687 value |= ((insn >> 3) & 0x0003) << 3;
688
689 /* Extend the sign. */
690 value = (value ^ signbit) - signbit;
691
692 return value;
693 }
694
695 /* ARC NPS400 Support: See comment near head of file. */
696 #define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
697 static unsigned long long \
698 insert_nps_3bit_reg_at_##OFFSET##_##NAME \
699 (unsigned long long insn, \
700 long long value, \
701 const char ** errmsg) \
702 { \
703 switch (value) \
704 { \
705 case 0: \
706 case 1: \
707 case 2: \
708 case 3: \
709 insn |= value << (OFFSET); \
710 break; \
711 case 12: \
712 case 13: \
713 case 14: \
714 case 15: \
715 insn |= (value - 8) << (OFFSET); \
716 break; \
717 default: \
718 *errmsg = _("Register must be either r0-r3 or r12-r15"); \
719 break; \
720 } \
721 return insn; \
722 } \
723 \
724 static long long \
725 extract_nps_3bit_reg_at_##OFFSET##_##NAME \
726 (unsigned long long insn, \
727 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
728 { \
729 int value = (insn >> (OFFSET)) & 0x07; \
730 if (value > 3) \
731 value += 8; \
732 return value; \
733 } \
734
735 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
736 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
737 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
738 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
739
740 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
741 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
742 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
743 MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
744
745 static unsigned long long
746 insert_nps_bitop_size_2b (unsigned long long insn,
747 long long value,
748 const char ** errmsg)
749 {
750 switch (value)
751 {
752 case 1:
753 value = 0;
754 break;
755 case 2:
756 value = 1;
757 break;
758 case 4:
759 value = 2;
760 break;
761 case 8:
762 value = 3;
763 break;
764 default:
765 value = 0;
766 *errmsg = _("Invalid size, should be 1, 2, 4, or 8");
767 break;
768 }
769
770 insn |= value << 10;
771 return insn;
772 }
773
774 static long long
775 extract_nps_bitop_size_2b (unsigned long long insn,
776 bfd_boolean * invalid ATTRIBUTE_UNUSED)
777 {
778 return 1 << ((insn >> 10) & 0x3);
779 }
780
781 static unsigned long long
782 insert_nps_bitop_uimm8 (unsigned long long insn,
783 long long value,
784 const char ** errmsg ATTRIBUTE_UNUSED)
785 {
786 insn |= ((value >> 5) & 7) << 12;
787 insn |= (value & 0x1f);
788 return insn;
789 }
790
791 static long long
792 extract_nps_bitop_uimm8 (unsigned long long insn,
793 bfd_boolean * invalid ATTRIBUTE_UNUSED)
794 {
795 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
796 }
797
798 static unsigned long long
799 insert_nps_rflt_uimm6 (unsigned long long insn,
800 long long value,
801 const char ** errmsg)
802 {
803 switch (value)
804 {
805 case 1:
806 case 2:
807 case 4:
808 break;
809
810 default:
811 *errmsg = _("invalid immediate, must be 1, 2, or 4");
812 value = 0;
813 }
814
815 insn |= (value << 6);
816 return insn;
817 }
818
819 static long long
820 extract_nps_rflt_uimm6 (unsigned long long insn,
821 bfd_boolean * invalid ATTRIBUTE_UNUSED)
822 {
823 return (insn >> 6) & 0x3f;
824 }
825
826 static unsigned long long
827 insert_nps_dst_pos_and_size (unsigned long long insn,
828 long long value,
829 const char ** errmsg ATTRIBUTE_UNUSED)
830 {
831 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
832 return insn;
833 }
834
835 static long long
836 extract_nps_dst_pos_and_size (unsigned long long insn,
837 bfd_boolean * invalid ATTRIBUTE_UNUSED)
838 {
839 return (insn & 0x1f);
840 }
841
842 static unsigned long long
843 insert_nps_cmem_uimm16 (unsigned long long insn,
844 long long value,
845 const char ** errmsg)
846 {
847 int top = (value >> 16) & 0xffff;
848
849 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
850 *errmsg = _("invalid value for CMEM ld/st immediate");
851 insn |= (value & 0xffff);
852 return insn;
853 }
854
855 static long long
856 extract_nps_cmem_uimm16 (unsigned long long insn,
857 bfd_boolean * invalid ATTRIBUTE_UNUSED)
858 {
859 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
860 }
861
862 static unsigned long long
863 insert_nps_imm_offset (unsigned long long insn,
864 long long value,
865 const char ** errmsg)
866 {
867 switch (value)
868 {
869 case 0:
870 case 16:
871 case 32:
872 case 48:
873 case 64:
874 value = value >> 4;
875 break;
876 default:
877 *errmsg = _("Invalid position, should be 0, 16, 32, 48 or 64.");
878 value = 0;
879 }
880 insn |= (value << 10);
881 return insn;
882 }
883
884 static long long
885 extract_nps_imm_offset (unsigned long long insn,
886 bfd_boolean * invalid ATTRIBUTE_UNUSED)
887 {
888 return ((insn >> 10) & 0x7) * 16;
889 }
890
891 static unsigned long long
892 insert_nps_imm_entry (unsigned long long insn,
893 long long value,
894 const char ** errmsg)
895 {
896 switch (value)
897 {
898 case 16:
899 value = 0;
900 break;
901 case 32:
902 value = 1;
903 break;
904 case 64:
905 value = 2;
906 break;
907 case 128:
908 value = 3;
909 break;
910 default:
911 *errmsg = _("Invalid position, should be 16, 32, 64 or 128.");
912 value = 0;
913 }
914 insn |= (value << 2);
915 return insn;
916 }
917
918 static long long
919 extract_nps_imm_entry (unsigned long long insn,
920 bfd_boolean * invalid ATTRIBUTE_UNUSED)
921 {
922 int imm_entry = ((insn >> 2) & 0x7);
923 return (1 << (imm_entry + 4));
924 }
925
926 static unsigned long long
927 insert_nps_size_16bit (unsigned long long insn,
928 long long value,
929 const char ** errmsg)
930 {
931 if ((value < 1) || (value > 64))
932 {
933 *errmsg = _("Invalid size value must be on range 1-64.");
934 value = 0;
935 }
936 value = value & 0x3f;
937 insn |= (value << 6);
938 return insn;
939 }
940
941 static long long
942 extract_nps_size_16bit (unsigned long long insn,
943 bfd_boolean * invalid ATTRIBUTE_UNUSED)
944 {
945 return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
946 }
947
948
949 #define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
950 static unsigned long long \
951 insert_nps_##NAME##_pos (unsigned long long insn, \
952 long long value, \
953 const char ** errmsg) \
954 { \
955 switch (value) \
956 { \
957 case 0: \
958 case 8: \
959 case 16: \
960 case 24: \
961 value = value / 8; \
962 break; \
963 default: \
964 *errmsg = _("Invalid position, should be 0, 8, 16, or 24"); \
965 value = 0; \
966 } \
967 insn |= (value << SHIFT); \
968 return insn; \
969 } \
970 \
971 static long long \
972 extract_nps_##NAME##_pos (unsigned long long insn, \
973 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
974 { \
975 return ((insn >> SHIFT) & 0x3) * 8; \
976 }
977
978 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
979 MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
980
981 #define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
982 static unsigned long long \
983 insert_nps_##NAME (unsigned long long insn, \
984 long long value, \
985 const char ** errmsg) \
986 { \
987 if (value < LOWER || value > UPPER) \
988 { \
989 *errmsg = _("Invalid size, value must be " \
990 #LOWER " to " #UPPER "."); \
991 return insn; \
992 } \
993 value -= BIAS; \
994 insn |= (value << SHIFT); \
995 return insn; \
996 } \
997 \
998 static long long \
999 extract_nps_##NAME (unsigned long long insn, \
1000 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1001 { \
1002 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
1003 }
1004
1005 MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
1006 MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
1007 MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
1008 MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
1009 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
1010 MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
1011 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
1012 MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
1013 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
1014 MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
1015 MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
1016
1017 static long long
1018 extract_nps_qcmp_m3 (unsigned long long insn,
1019 bfd_boolean * invalid)
1020 {
1021 int m3 = (insn >> 5) & 0xf;
1022 if (m3 == 0xf)
1023 *invalid = TRUE;
1024 return m3;
1025 }
1026
1027 static long long
1028 extract_nps_qcmp_m2 (unsigned long long insn,
1029 bfd_boolean * invalid)
1030 {
1031 bfd_boolean tmp_invalid = FALSE;
1032 int m2 = (insn >> 15) & 0x1;
1033 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1034
1035 if (m2 == 0 && m3 == 0xf)
1036 *invalid = TRUE;
1037 return m2;
1038 }
1039
1040 static long long
1041 extract_nps_qcmp_m1 (unsigned long long insn,
1042 bfd_boolean * invalid)
1043 {
1044 bfd_boolean tmp_invalid = FALSE;
1045 int m1 = (insn >> 14) & 0x1;
1046 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
1047 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1048
1049 if (m1 == 0 && m2 == 0 && m3 == 0xf)
1050 *invalid = TRUE;
1051 return m1;
1052 }
1053
1054 static unsigned long long
1055 insert_nps_calc_entry_size (unsigned long long insn,
1056 long long value,
1057 const char ** errmsg)
1058 {
1059 unsigned pwr;
1060
1061 if (value < 1 || value > 256)
1062 {
1063 *errmsg = _("value out of range 1 - 256");
1064 return 0;
1065 }
1066
1067 for (pwr = 0; (value & 1) == 0; value >>= 1)
1068 ++pwr;
1069
1070 if (value != 1)
1071 {
1072 *errmsg = _("value must be power of 2");
1073 return 0;
1074 }
1075
1076 return insn | (pwr << 8);
1077 }
1078
1079 static long long
1080 extract_nps_calc_entry_size (unsigned long long insn,
1081 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1082 {
1083 unsigned entry_size = (insn >> 8) & 0xf;
1084 return 1 << entry_size;
1085 }
1086
1087 static unsigned long long
1088 insert_nps_bitop_mod4 (unsigned long long insn,
1089 long long value,
1090 const char ** errmsg ATTRIBUTE_UNUSED)
1091 {
1092 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
1093 }
1094
1095 static long long
1096 extract_nps_bitop_mod4 (unsigned long long insn,
1097 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1098 {
1099 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
1100 }
1101
1102 static unsigned long long
1103 insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1104 long long value,
1105 const char ** errmsg ATTRIBUTE_UNUSED)
1106 {
1107 return insn | (value << 42) | (value << 37);
1108 }
1109
1110 static long long
1111 extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1112 bfd_boolean * invalid)
1113 {
1114 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
1115 *invalid = TRUE;
1116 return ((insn >> 37) & 0x1f);
1117 }
1118
1119 static unsigned long long
1120 insert_nps_bitop_ins_ext (unsigned long long insn,
1121 long long value,
1122 const char ** errmsg)
1123 {
1124 if (value < 0 || value > 28)
1125 *errmsg = _("Value must be in the range 0 to 28");
1126 return insn | (value << 20);
1127 }
1128
1129 static long long
1130 extract_nps_bitop_ins_ext (unsigned long long insn,
1131 bfd_boolean * invalid)
1132 {
1133 int value = (insn >> 20) & 0x1f;
1134
1135 if (value > 28)
1136 *invalid = TRUE;
1137 return value;
1138 }
1139
1140 #define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
1141 static unsigned long long \
1142 insert_nps_##NAME (unsigned long long insn, \
1143 long long value, \
1144 const char ** errmsg) \
1145 { \
1146 if (value < 1 || value > UPPER) \
1147 *errmsg = _("Value must be in the range 1 to " #UPPER); \
1148 if (value == UPPER) \
1149 value = 0; \
1150 return insn | (value << SHIFT); \
1151 } \
1152 \
1153 static long long \
1154 extract_nps_##NAME (unsigned long long insn, \
1155 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1156 { \
1157 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1158 if (value == 0) \
1159 value = UPPER; \
1160 return value; \
1161 }
1162
1163 MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1164 MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1165 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1166 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1167 MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1168 MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
1169 MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
1170
1171 static unsigned long long
1172 insert_nps_min_hofs (unsigned long long insn,
1173 long long value,
1174 const char ** errmsg)
1175 {
1176 if (value < 0 || value > 240)
1177 *errmsg = _("Value must be in the range 0 to 240");
1178 if ((value % 16) != 0)
1179 *errmsg = _("Value must be a multiple of 16");
1180 value = value / 16;
1181 return insn | (value << 6);
1182 }
1183
1184 static long long
1185 extract_nps_min_hofs (unsigned long long insn,
1186 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1187 {
1188 int value = (insn >> 6) & 0xF;
1189 return value * 16;
1190 }
1191
1192 #define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
1193 static unsigned long long \
1194 insert_nps_##NAME (unsigned long long insn, \
1195 long long value, \
1196 const char ** errmsg) \
1197 { \
1198 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
1199 *errmsg = _("Invalid address type for operand"); \
1200 return insn; \
1201 } \
1202 \
1203 static long long \
1204 extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1205 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
1206 { \
1207 return ARC_NPS400_ADDRTYPE_##VALUE; \
1208 }
1209
1210 MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1211 MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1212 MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1213 MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1214 MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1215 MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1216 MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1217 MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1218 MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1219 MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1220 MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1221 MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1222 MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1223 MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1224 MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1225 MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1226
1227 static unsigned long long
1228 insert_nps_rbdouble_64 (unsigned long long insn,
1229 long long value,
1230 const char ** errmsg)
1231 {
1232 if (value < 0 || value > 31)
1233 *errmsg = _("Value must be in the range 0 to 31");
1234 return insn | (value << 43) | (value << 48);
1235 }
1236
1237
1238 static long long
1239 extract_nps_rbdouble_64 (unsigned long long insn,
1240 bfd_boolean * invalid)
1241 {
1242 int value1 = (insn >> 43) & 0x1F;
1243 int value2 = (insn >> 48) & 0x1F;
1244
1245 if (value1 != value2)
1246 *invalid = TRUE;
1247
1248 return value1;
1249 }
1250
1251 static unsigned long long
1252 insert_nps_misc_imm_offset (unsigned long long insn,
1253 long long value,
1254 const char ** errmsg)
1255 {
1256 if (value & 0x3)
1257 {
1258 *errmsg = _("Invalid position, should be 0,4, 8,...124.");
1259 value = 0;
1260 }
1261 insn |= (value << 6);
1262 return insn;
1263 }
1264
1265 static long long int
1266 extract_nps_misc_imm_offset (unsigned long long insn,
1267 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1268 {
1269 return ((insn >> 8) & 0x1f) * 4;
1270 }
1271
1272 /* Include the generic extract/insert functions. Order is important
1273 as some of the functions present in the .h may be disabled via
1274 defines. */
1275 #include "arc-fxi.h"
1276
1277 /* The flag operands table.
1278
1279 The format of the table is
1280 NAME CODE BITS SHIFT FAVAIL. */
1281 const struct arc_flag_operand arc_flag_operands[] =
1282 {
1283 #define F_NULL 0
1284 { 0, 0, 0, 0, 0},
1285 #define F_ALWAYS (F_NULL + 1)
1286 { "al", 0, 0, 0, 0 },
1287 #define F_RA (F_ALWAYS + 1)
1288 { "ra", 0, 0, 0, 0 },
1289 #define F_EQUAL (F_RA + 1)
1290 { "eq", 1, 5, 0, 1 },
1291 #define F_ZERO (F_EQUAL + 1)
1292 { "z", 1, 5, 0, 0 },
1293 #define F_NOTEQUAL (F_ZERO + 1)
1294 { "ne", 2, 5, 0, 1 },
1295 #define F_NOTZERO (F_NOTEQUAL + 1)
1296 { "nz", 2, 5, 0, 0 },
1297 #define F_POZITIVE (F_NOTZERO + 1)
1298 { "p", 3, 5, 0, 1 },
1299 #define F_PL (F_POZITIVE + 1)
1300 { "pl", 3, 5, 0, 0 },
1301 #define F_NEGATIVE (F_PL + 1)
1302 { "n", 4, 5, 0, 1 },
1303 #define F_MINUS (F_NEGATIVE + 1)
1304 { "mi", 4, 5, 0, 0 },
1305 #define F_CARRY (F_MINUS + 1)
1306 { "c", 5, 5, 0, 1 },
1307 #define F_CARRYSET (F_CARRY + 1)
1308 { "cs", 5, 5, 0, 0 },
1309 #define F_LOWER (F_CARRYSET + 1)
1310 { "lo", 5, 5, 0, 0 },
1311 #define F_CARRYCLR (F_LOWER + 1)
1312 { "cc", 6, 5, 0, 0 },
1313 #define F_NOTCARRY (F_CARRYCLR + 1)
1314 { "nc", 6, 5, 0, 1 },
1315 #define F_HIGHER (F_NOTCARRY + 1)
1316 { "hs", 6, 5, 0, 0 },
1317 #define F_OVERFLOWSET (F_HIGHER + 1)
1318 { "vs", 7, 5, 0, 0 },
1319 #define F_OVERFLOW (F_OVERFLOWSET + 1)
1320 { "v", 7, 5, 0, 1 },
1321 #define F_NOTOVERFLOW (F_OVERFLOW + 1)
1322 { "nv", 8, 5, 0, 1 },
1323 #define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1324 { "vc", 8, 5, 0, 0 },
1325 #define F_GT (F_OVERFLOWCLR + 1)
1326 { "gt", 9, 5, 0, 1 },
1327 #define F_GE (F_GT + 1)
1328 { "ge", 10, 5, 0, 1 },
1329 #define F_LT (F_GE + 1)
1330 { "lt", 11, 5, 0, 1 },
1331 #define F_LE (F_LT + 1)
1332 { "le", 12, 5, 0, 1 },
1333 #define F_HI (F_LE + 1)
1334 { "hi", 13, 5, 0, 1 },
1335 #define F_LS (F_HI + 1)
1336 { "ls", 14, 5, 0, 1 },
1337 #define F_PNZ (F_LS + 1)
1338 { "pnz", 15, 5, 0, 1 },
1339 #define F_NJ (F_PNZ + 1)
1340 { "nj", 21, 5, 0, 1 },
1341 #define F_NM (F_NJ + 1)
1342 { "nm", 23, 5, 0, 1 },
1343 #define F_NO_T (F_NM + 1)
1344 { "nt", 24, 5, 0, 1 },
1345
1346 /* FLAG. */
1347 #define F_FLAG (F_NO_T + 1)
1348 { "f", 1, 1, 15, 1 },
1349 #define F_FFAKE (F_FLAG + 1)
1350 { "f", 0, 0, 0, 1 },
1351
1352 /* Delay slot. */
1353 #define F_ND (F_FFAKE + 1)
1354 { "nd", 0, 1, 5, 0 },
1355 #define F_D (F_ND + 1)
1356 { "d", 1, 1, 5, 1 },
1357 #define F_DFAKE (F_D + 1)
1358 { "d", 0, 0, 0, 1 },
1359 #define F_DNZ_ND (F_DFAKE + 1)
1360 { "nd", 0, 1, 16, 0 },
1361 #define F_DNZ_D (F_DNZ_ND + 1)
1362 { "d", 1, 1, 16, 1 },
1363
1364 /* Data size. */
1365 #define F_SIZEB1 (F_DNZ_D + 1)
1366 { "b", 1, 2, 1, 1 },
1367 #define F_SIZEB7 (F_SIZEB1 + 1)
1368 { "b", 1, 2, 7, 1 },
1369 #define F_SIZEB17 (F_SIZEB7 + 1)
1370 { "b", 1, 2, 17, 1 },
1371 #define F_SIZEW1 (F_SIZEB17 + 1)
1372 { "w", 2, 2, 1, 0 },
1373 #define F_SIZEW7 (F_SIZEW1 + 1)
1374 { "w", 2, 2, 7, 0 },
1375 #define F_SIZEW17 (F_SIZEW7 + 1)
1376 { "w", 2, 2, 17, 0 },
1377
1378 /* Sign extension. */
1379 #define F_SIGN6 (F_SIZEW17 + 1)
1380 { "x", 1, 1, 6, 1 },
1381 #define F_SIGN16 (F_SIGN6 + 1)
1382 { "x", 1, 1, 16, 1 },
1383 #define F_SIGNX (F_SIGN16 + 1)
1384 { "x", 0, 0, 0, 1 },
1385
1386 /* Address write-back modes. */
1387 #define F_A3 (F_SIGNX + 1)
1388 { "a", 1, 2, 3, 0 },
1389 #define F_A9 (F_A3 + 1)
1390 { "a", 1, 2, 9, 0 },
1391 #define F_A22 (F_A9 + 1)
1392 { "a", 1, 2, 22, 0 },
1393 #define F_AW3 (F_A22 + 1)
1394 { "aw", 1, 2, 3, 1 },
1395 #define F_AW9 (F_AW3 + 1)
1396 { "aw", 1, 2, 9, 1 },
1397 #define F_AW22 (F_AW9 + 1)
1398 { "aw", 1, 2, 22, 1 },
1399 #define F_AB3 (F_AW22 + 1)
1400 { "ab", 2, 2, 3, 1 },
1401 #define F_AB9 (F_AB3 + 1)
1402 { "ab", 2, 2, 9, 1 },
1403 #define F_AB22 (F_AB9 + 1)
1404 { "ab", 2, 2, 22, 1 },
1405 #define F_AS3 (F_AB22 + 1)
1406 { "as", 3, 2, 3, 1 },
1407 #define F_AS9 (F_AS3 + 1)
1408 { "as", 3, 2, 9, 1 },
1409 #define F_AS22 (F_AS9 + 1)
1410 { "as", 3, 2, 22, 1 },
1411 #define F_ASFAKE (F_AS22 + 1)
1412 { "as", 0, 0, 0, 1 },
1413
1414 /* Cache bypass. */
1415 #define F_DI5 (F_ASFAKE + 1)
1416 { "di", 1, 1, 5, 1 },
1417 #define F_DI11 (F_DI5 + 1)
1418 { "di", 1, 1, 11, 1 },
1419 #define F_DI14 (F_DI11 + 1)
1420 { "di", 1, 1, 14, 1 },
1421 #define F_DI15 (F_DI14 + 1)
1422 { "di", 1, 1, 15, 1 },
1423
1424 /* ARCv2 specific. */
1425 #define F_NT (F_DI15 + 1)
1426 { "nt", 0, 1, 3, 1},
1427 #define F_T (F_NT + 1)
1428 { "t", 1, 1, 3, 1},
1429 #define F_H1 (F_T + 1)
1430 { "h", 2, 2, 1, 1 },
1431 #define F_H7 (F_H1 + 1)
1432 { "h", 2, 2, 7, 1 },
1433 #define F_H17 (F_H7 + 1)
1434 { "h", 2, 2, 17, 1 },
1435 #define F_SIZED (F_H17 + 1)
1436 { "dd", 8, 0, 0, 0 }, /* Fake. */
1437
1438 /* Fake Flags. */
1439 #define F_NE (F_SIZED + 1)
1440 { "ne", 0, 0, 0, 1 },
1441
1442 /* ARC NPS400 Support: See comment near head of file. */
1443 #define F_NPS_CL (F_NE + 1)
1444 { "cl", 0, 0, 0, 1 },
1445
1446 #define F_NPS_NA (F_NPS_CL + 1)
1447 { "na", 1, 1, 9, 1 },
1448
1449 #define F_NPS_SR (F_NPS_NA + 1)
1450 { "s", 1, 1, 13, 1 },
1451
1452 #define F_NPS_M (F_NPS_SR + 1)
1453 { "m", 1, 1, 7, 1 },
1454
1455 #define F_NPS_FLAG (F_NPS_M + 1)
1456 { "f", 1, 1, 20, 1 },
1457
1458 #define F_NPS_R (F_NPS_FLAG + 1)
1459 { "r", 1, 1, 15, 1 },
1460
1461 #define F_NPS_RW (F_NPS_R + 1)
1462 { "rw", 0, 1, 7, 1 },
1463
1464 #define F_NPS_RD (F_NPS_RW + 1)
1465 { "rd", 1, 1, 7, 1 },
1466
1467 #define F_NPS_WFT (F_NPS_RD + 1)
1468 { "wft", 0, 0, 0, 1 },
1469
1470 #define F_NPS_IE1 (F_NPS_WFT + 1)
1471 { "ie1", 1, 2, 8, 1 },
1472
1473 #define F_NPS_IE2 (F_NPS_IE1 + 1)
1474 { "ie2", 2, 2, 8, 1 },
1475
1476 #define F_NPS_IE12 (F_NPS_IE2 + 1)
1477 { "ie12", 3, 2, 8, 1 },
1478
1479 #define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1480 { "rd", 0, 1, 6, 1 },
1481
1482 #define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1483 { "wr", 1, 1, 6, 1 },
1484
1485 #define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1486 { "off", 0, 0, 0, 1 },
1487
1488 #define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1489 { "restore", 0, 0, 0, 1 },
1490
1491 #define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1492 { "sx", 1, 1, 14, 1 },
1493
1494 #define F_NPS_AR (F_NPS_SX + 1)
1495 { "ar", 0, 1, 0, 1 },
1496
1497 #define F_NPS_AL (F_NPS_AR + 1)
1498 { "al", 1, 1, 0, 1 },
1499
1500 #define F_NPS_S (F_NPS_AL + 1)
1501 { "s", 0, 0, 0, 1 },
1502
1503 #define F_NPS_ZNCV_RD (F_NPS_S + 1)
1504 { "rd", 0, 1, 15, 1 },
1505
1506 #define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1507 { "wr", 1, 1, 15, 1 },
1508
1509 #define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1510 { "p0", 0, 0, 0, 1 },
1511
1512 #define F_NPS_P1 (F_NPS_P0 + 1)
1513 { "p1", 0, 0, 0, 1 },
1514
1515 #define F_NPS_P2 (F_NPS_P1 + 1)
1516 { "p2", 0, 0, 0, 1 },
1517
1518 #define F_NPS_P3 (F_NPS_P2 + 1)
1519 { "p3", 0, 0, 0, 1 },
1520
1521 #define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1522 { "di", 0, 0, 0, 1 },
1523
1524 #define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1525 { "cl", 1, 1, 6, 1 },
1526
1527 #define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1528 { "cl", 1, 1, 16, 1 },
1529
1530 #define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1531 { "x2", 1, 2, 9, 1 },
1532
1533 #define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1534 { "x2", 1, 2, 22, 1 },
1535
1536 #define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1537 { "x4", 2, 2, 9, 1 },
1538
1539 #define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1540 { "x4", 2, 2, 22, 1 },
1541
1542 #define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1)
1543 { "core", 1, 3, 6, 1 },
1544
1545 #define F_NPS_CLSR (F_NPS_CORE + 1)
1546 { "clsr", 2, 3, 6, 1 },
1547
1548 #define F_NPS_ALL (F_NPS_CLSR + 1)
1549 { "all", 3, 3, 6, 1 },
1550
1551 #define F_NPS_GIC (F_NPS_ALL + 1)
1552 { "gic", 4, 3, 6, 1 },
1553
1554 #define F_NPS_RSPI_GIC (F_NPS_GIC + 1)
1555 { "gic", 5, 3, 6, 1 },
1556 };
1557
1558 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
1559
1560 /* Table of the flag classes.
1561
1562 The format of the table is
1563 CLASS {FLAG_CODE}. */
1564 const struct arc_flag_class arc_flag_classes[] =
1565 {
1566 #define C_EMPTY 0
1567 { F_CLASS_NONE, { F_NULL } },
1568
1569 #define C_CC_EQ (C_EMPTY + 1)
1570 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
1571
1572 #define C_CC_GE (C_CC_EQ + 1)
1573 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
1574
1575 #define C_CC_GT (C_CC_GE + 1)
1576 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
1577
1578 #define C_CC_HI (C_CC_GT + 1)
1579 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
1580
1581 #define C_CC_HS (C_CC_HI + 1)
1582 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
1583
1584 #define C_CC_LE (C_CC_HS + 1)
1585 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
1586
1587 #define C_CC_LO (C_CC_LE + 1)
1588 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
1589
1590 #define C_CC_LS (C_CC_LO + 1)
1591 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
1592
1593 #define C_CC_LT (C_CC_LS + 1)
1594 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
1595
1596 #define C_CC_NE (C_CC_LT + 1)
1597 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
1598
1599 #define C_AA_AB (C_CC_NE + 1)
1600 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
1601
1602 #define C_AA_AW (C_AA_AB + 1)
1603 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
1604
1605 #define C_ZZ_D (C_AA_AW + 1)
1606 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
1607
1608 #define C_ZZ_H (C_ZZ_D + 1)
1609 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
1610
1611 #define C_ZZ_B (C_ZZ_H + 1)
1612 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
1613
1614 #define C_CC (C_ZZ_B + 1)
1615 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
1616 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1617 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1618 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1619 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1620 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
1621 F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
1622
1623 #define C_AA_ADDR3 (C_CC + 1)
1624 #define C_AA27 (C_CC + 1)
1625 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
1626 #define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1627 #define C_AA21 (C_AA_ADDR3 + 1)
1628 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
1629 #define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1630 #define C_AA8 (C_AA_ADDR9 + 1)
1631 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
1632
1633 #define C_F (C_AA_ADDR22 + 1)
1634 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
1635 #define C_FHARD (C_F + 1)
1636 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
1637
1638 #define C_T (C_FHARD + 1)
1639 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
1640 #define C_D (C_T + 1)
1641 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
1642 #define C_DNZ_D (C_D + 1)
1643 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
1644
1645 #define C_DHARD (C_DNZ_D + 1)
1646 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
1647
1648 #define C_DI20 (C_DHARD + 1)
1649 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
1650 #define C_DI14 (C_DI20 + 1)
1651 { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
1652 #define C_DI16 (C_DI14 + 1)
1653 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
1654 #define C_DI26 (C_DI16 + 1)
1655 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
1656
1657 #define C_X25 (C_DI26 + 1)
1658 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
1659 #define C_X15 (C_X25 + 1)
1660 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
1661 #define C_XHARD (C_X15 + 1)
1662 #define C_X (C_X15 + 1)
1663 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
1664
1665 #define C_ZZ13 (C_X + 1)
1666 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
1667 #define C_ZZ23 (C_ZZ13 + 1)
1668 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
1669 #define C_ZZ29 (C_ZZ23 + 1)
1670 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
1671
1672 #define C_AS (C_ZZ29 + 1)
1673 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
1674
1675 #define C_NE (C_AS + 1)
1676 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
1677
1678 /* ARC NPS400 Support: See comment near head of file. */
1679 #define C_NPS_CL (C_NE + 1)
1680 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1681
1682 #define C_NPS_NA (C_NPS_CL + 1)
1683 { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
1684
1685 #define C_NPS_SR (C_NPS_NA + 1)
1686 { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
1687
1688 #define C_NPS_M (C_NPS_SR + 1)
1689 { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
1690
1691 #define C_NPS_F (C_NPS_M + 1)
1692 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
1693
1694 #define C_NPS_R (C_NPS_F + 1)
1695 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
1696
1697 #define C_NPS_SCHD_RW (C_NPS_R + 1)
1698 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1699
1700 #define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1701 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1702
1703 #define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1704 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1705
1706 #define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1707 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1708
1709 #define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1710 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1711
1712 #define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1713 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1714
1715 #define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1716 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1717
1718 #define C_NPS_AR_AL (C_NPS_SX + 1)
1719 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
1720
1721 #define C_NPS_S (C_NPS_AR_AL + 1)
1722 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1723
1724 #define C_NPS_ZNCV (C_NPS_S + 1)
1725 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
1726
1727 #define C_NPS_P0 (C_NPS_ZNCV + 1)
1728 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1729
1730 #define C_NPS_P1 (C_NPS_P0 + 1)
1731 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1732
1733 #define C_NPS_P2 (C_NPS_P1 + 1)
1734 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1735
1736 #define C_NPS_P3 (C_NPS_P2 + 1)
1737 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
1738
1739 #define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1740 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1741
1742 #define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1743 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1744
1745 #define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1746 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1747
1748 #define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1749 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1750
1751 #define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1752 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
1753
1754 #define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
1755 { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
1756
1757 #define C_NPS_CLSR (C_NPS_CORE + 1)
1758 { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
1759
1760 #define C_NPS_ALL (C_NPS_CLSR + 1)
1761 { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
1762
1763 #define C_NPS_GIC (C_NPS_ALL + 1)
1764 { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
1765
1766 #define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
1767 { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
1768 };
1769
1770 const unsigned char flags_none[] = { 0 };
1771 const unsigned char flags_f[] = { C_F };
1772 const unsigned char flags_cc[] = { C_CC };
1773 const unsigned char flags_ccf[] = { C_CC, C_F };
1774
1775 /* The operands table.
1776
1777 The format of the operands table is:
1778
1779 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1780 const struct arc_operand arc_operands[] =
1781 {
1782 /* The fields are bits, shift, insert, extract, flags. The zero
1783 index is used to indicate end-of-list. */
1784 #define UNUSED 0
1785 { 0, 0, 0, 0, 0, 0 },
1786
1787 #define IGNORED (UNUSED + 1)
1788 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1789
1790 /* The plain integer register fields. Used by 32 bit
1791 instructions. */
1792 #define RA (IGNORED + 1)
1793 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
1794 #define RA_CHK (RA + 1)
1795 { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
1796 #define RB (RA_CHK + 1)
1797 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
1798 #define RB_CHK (RB + 1)
1799 { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
1800 #define RC (RB_CHK + 1)
1801 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1802 #define RBdup (RC + 1)
1803 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1804
1805 #define RAD (RBdup + 1)
1806 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1807 #define RCD (RAD + 1)
1808 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1809
1810 /* The plain integer register fields. Used by short
1811 instructions. */
1812 #define RA16 (RCD + 1)
1813 #define RA_S (RCD + 1)
1814 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1815 #define RB16 (RA16 + 1)
1816 #define RB_S (RA16 + 1)
1817 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1818 #define RB16dup (RB16 + 1)
1819 #define RB_Sdup (RB16 + 1)
1820 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1821 #define RC16 (RB16dup + 1)
1822 #define RC_S (RB16dup + 1)
1823 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1824 #define R6H (RC16 + 1) /* 6bit register field 'h' used
1825 by V1 cpus. */
1826 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1827 #define R5H (R6H + 1) /* 5bit register field 'h' used
1828 by V2 cpus. */
1829 #define RH_S (R6H + 1) /* 5bit register field 'h' used
1830 by V2 cpus. */
1831 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1832 #define R5Hdup (R5H + 1)
1833 #define RH_Sdup (R5H + 1)
1834 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1835 insert_rhv2, extract_rhv2 },
1836
1837 #define RG (R5Hdup + 1)
1838 #define G_S (R5Hdup + 1)
1839 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1840
1841 /* Fix registers. */
1842 #define R0 (RG + 1)
1843 #define R0_S (RG + 1)
1844 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1845 #define R1 (R0 + 1)
1846 #define R1_S (R0 + 1)
1847 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1848 #define R2 (R1 + 1)
1849 #define R2_S (R1 + 1)
1850 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1851 #define R3 (R2 + 1)
1852 #define R3_S (R2 + 1)
1853 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
1854 #define RSP (R3 + 1)
1855 #define SP_S (R3 + 1)
1856 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
1857 #define SPdup (RSP + 1)
1858 #define SP_Sdup (RSP + 1)
1859 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1860 #define GP (SPdup + 1)
1861 #define GP_S (SPdup + 1)
1862 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1863
1864 #define PCL_S (GP + 1)
1865 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1866
1867 #define BLINK (PCL_S + 1)
1868 #define BLINK_S (PCL_S + 1)
1869 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1870
1871 #define ILINK1 (BLINK + 1)
1872 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1873 #define ILINK2 (ILINK1 + 1)
1874 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1875
1876 /* Long immediate. */
1877 #define LIMM (ILINK2 + 1)
1878 #define LIMM_S (ILINK2 + 1)
1879 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1880 #define LIMMdup (LIMM + 1)
1881 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1882
1883 /* Special operands. */
1884 #define ZA (LIMMdup + 1)
1885 #define ZB (LIMMdup + 1)
1886 #define ZA_S (LIMMdup + 1)
1887 #define ZB_S (LIMMdup + 1)
1888 #define ZC_S (LIMMdup + 1)
1889 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1890
1891 #define RRANGE_EL (ZA + 1)
1892 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1893 insert_rrange, extract_rrange},
1894 #define R13_EL (RRANGE_EL + 1)
1895 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1896 insert_r13el, extract_rrange },
1897 #define FP_EL (R13_EL + 1)
1898 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1899 insert_fpel, extract_fpel },
1900 #define BLINK_EL (FP_EL + 1)
1901 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1902 insert_blinkel, extract_blinkel },
1903 #define PCL_EL (BLINK_EL + 1)
1904 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1905 insert_pclel, extract_pclel },
1906
1907 /* Fake operand to handle the T flag. */
1908 #define BRAKET (PCL_EL + 1)
1909 #define BRAKETdup (PCL_EL + 1)
1910 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1911
1912 /* Fake operand to handle the T flag. */
1913 #define FKT_T (BRAKET + 1)
1914 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1915 /* Fake operand to handle the T flag. */
1916 #define FKT_NT (FKT_T + 1)
1917 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1918
1919 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1920 #define UIMM6_20 (FKT_NT + 1)
1921 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1922
1923 /* Exactly like the above but used by relaxation. */
1924 #define UIMM6_20R (UIMM6_20 + 1)
1925 {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1926 insert_uimm6_20, extract_uimm6_20},
1927
1928 /* SIMM12_20 mask = 00000000000000000000111111222222. */
1929 #define SIMM12_20 (UIMM6_20R + 1)
1930 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1931
1932 /* Exactly like the above but used by relaxation. */
1933 #define SIMM12_20R (SIMM12_20 + 1)
1934 {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
1935 insert_simm12_20, extract_simm12_20},
1936
1937 /* SIMM3_5_S mask = 0000011100000000. */
1938 #define SIMM3_5_S (SIMM12_20R + 1)
1939 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1940 insert_simm3s, extract_simm3s},
1941
1942 /* UIMM7_A32_11_S mask = 0000000000011111. */
1943 #define UIMM7_A32_11_S (SIMM3_5_S + 1)
1944 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1945 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1946 extract_uimm7_a32_11_s},
1947
1948 /* The same as above but used by relaxation. */
1949 #define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
1950 {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1951 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
1952 insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
1953
1954 /* UIMM7_9_S mask = 0000000001111111. */
1955 #define UIMM7_9_S (UIMM7_A32_11R_S + 1)
1956 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1957
1958 /* UIMM3_13_S mask = 0000000000000111. */
1959 #define UIMM3_13_S (UIMM7_9_S + 1)
1960 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1961
1962 /* Exactly like the above but used for relaxation. */
1963 #define UIMM3_13R_S (UIMM3_13_S + 1)
1964 {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1965 insert_uimm3_13_s, extract_uimm3_13_s},
1966
1967 /* SIMM11_A32_7_S mask = 0000000111111111. */
1968 #define SIMM11_A32_7_S (UIMM3_13R_S + 1)
1969 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1970 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1971
1972 /* UIMM6_13_S mask = 0000000002220111. */
1973 #define UIMM6_13_S (SIMM11_A32_7_S + 1)
1974 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1975 /* UIMM5_11_S mask = 0000000000011111. */
1976 #define UIMM5_11_S (UIMM6_13_S + 1)
1977 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1978 extract_uimm5_11_s},
1979
1980 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1981 #define SIMM9_A16_8 (UIMM5_11_S + 1)
1982 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
1983 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
1984 extract_simm9_a16_8},
1985
1986 /* UIMM6_8 mask = 00000000000000000000111111000000. */
1987 #define UIMM6_8 (SIMM9_A16_8 + 1)
1988 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
1989
1990 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
1991 #define SIMM21_A16_5 (UIMM6_8 + 1)
1992 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
1993 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
1994 insert_simm21_a16_5, extract_simm21_a16_5},
1995
1996 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
1997 #define SIMM25_A16_5 (SIMM21_A16_5 + 1)
1998 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
1999 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
2000 insert_simm25_a16_5, extract_simm25_a16_5},
2001
2002 /* SIMM10_A16_7_S mask = 0000000111111111. */
2003 #define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
2004 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2005 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
2006 extract_simm10_a16_7_s},
2007
2008 #define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
2009 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2010 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
2011
2012 /* SIMM7_A16_10_S mask = 0000000000111111. */
2013 #define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
2014 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2015 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
2016 extract_simm7_a16_10_s},
2017
2018 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
2019 #define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
2020 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2021 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
2022 extract_simm21_a32_5},
2023
2024 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
2025 #define SIMM25_A32_5 (SIMM21_A32_5 + 1)
2026 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2027 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
2028 extract_simm25_a32_5},
2029
2030 /* SIMM13_A32_5_S mask = 0000011111111111. */
2031 #define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
2032 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2033 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
2034 extract_simm13_a32_5_s},
2035
2036 /* SIMM8_A16_9_S mask = 0000000001111111. */
2037 #define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
2038 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2039 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
2040 extract_simm8_a16_9_s},
2041
2042 /* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
2043 #define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1)
2044 {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED
2045 | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s,
2046 extract_uimm10_6_s},
2047
2048 /* UIMM3_23 mask = 00000000000000000000000111000000. */
2049 #define UIMM3_23 (UIMM10_6_S_JLIOFF + 1)
2050 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
2051
2052 /* UIMM10_6_S mask = 0000001111111111. */
2053 #define UIMM10_6_S (UIMM3_23 + 1)
2054 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
2055
2056 /* UIMM6_11_S mask = 0000002200011110. */
2057 #define UIMM6_11_S (UIMM10_6_S + 1)
2058 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
2059
2060 /* SIMM9_8 mask = 00000000111111112000000000000000. */
2061 #define SIMM9_8 (UIMM6_11_S + 1)
2062 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
2063 insert_simm9_8, extract_simm9_8},
2064
2065 /* The same as above but used by relaxation. */
2066 #define SIMM9_8R (SIMM9_8 + 1)
2067 {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
2068 | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
2069
2070 /* UIMM10_A32_8_S mask = 0000000011111111. */
2071 #define UIMM10_A32_8_S (SIMM9_8R + 1)
2072 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2073 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
2074 extract_uimm10_a32_8_s},
2075
2076 /* SIMM9_7_S mask = 0000000111111111. */
2077 #define SIMM9_7_S (UIMM10_A32_8_S + 1)
2078 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
2079 extract_simm9_7_s},
2080
2081 /* UIMM6_A16_11_S mask = 0000000000011111. */
2082 #define UIMM6_A16_11_S (SIMM9_7_S + 1)
2083 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2084 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
2085 extract_uimm6_a16_11_s},
2086
2087 /* UIMM5_A32_11_S mask = 0000020000011000. */
2088 #define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
2089 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2090 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
2091 extract_uimm5_a32_11_s},
2092
2093 /* SIMM11_A32_13_S mask = 0000022222200111. */
2094 #define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
2095 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2096 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
2097
2098 /* UIMM7_13_S mask = 0000000022220111. */
2099 #define UIMM7_13_S (SIMM11_A32_13_S + 1)
2100 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
2101
2102 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
2103 #define UIMM6_A16_21 (UIMM7_13_S + 1)
2104 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2105 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
2106
2107 /* UIMM7_11_S mask = 0000022200011110. */
2108 #define UIMM7_11_S (UIMM6_A16_21 + 1)
2109 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
2110
2111 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
2112 #define UIMM7_A16_20 (UIMM7_11_S + 1)
2113 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2114 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
2115 extract_uimm7_a16_20},
2116
2117 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
2118 #define SIMM13_A16_20 (UIMM7_A16_20 + 1)
2119 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2120 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
2121 extract_simm13_a16_20},
2122
2123 /* UIMM8_8_S mask = 0000000011111111. */
2124 #define UIMM8_8_S (SIMM13_A16_20 + 1)
2125 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
2126
2127 /* The same as above but used for relaxation. */
2128 #define UIMM8_8R_S (UIMM8_8_S + 1)
2129 {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
2130 insert_uimm8_8_s, extract_uimm8_8_s},
2131
2132 /* W6 mask = 00000000000000000000111111000000. */
2133 #define W6 (UIMM8_8R_S + 1)
2134 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
2135
2136 /* UIMM6_5_S mask = 0000011111100000. */
2137 #define UIMM6_5_S (W6 + 1)
2138 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
2139
2140 /* ARC NPS400 Support: See comment near head of file. */
2141 #define NPS_R_DST_3B (UIMM6_5_S + 1)
2142 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2143 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2144
2145 #define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
2146 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2147 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2148
2149 #define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
2150 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2151 insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
2152
2153 #define NPS_R_DST (NPS_R_SRC2_3B + 1)
2154 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
2155
2156 #define NPS_R_SRC1 (NPS_R_DST + 1)
2157 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2158
2159 #define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
2160 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2161
2162 #define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
2163 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2164
2165 #define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
2166 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2167 insert_nps_bitop_size, extract_nps_bitop_size },
2168
2169 #define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
2170 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2171 insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
2172
2173 #define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
2174 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2175 insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
2176
2177 #define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
2178 { 8, 0, 0, ARC_OPERAND_UNSIGNED,
2179 insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
2180
2181 #define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
2182 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2183
2184 #define NPS_SIMM16 (NPS_UIMM16 + 1)
2185 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
2186
2187 #define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
2188 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2189 insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
2190
2191 #define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
2192 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2193 insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
2194
2195 #define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
2196 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2197 insert_nps_src2_pos, extract_nps_src2_pos },
2198
2199 #define NPS_SRC1_POS (NPS_SRC2_POS + 1)
2200 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2201 insert_nps_src1_pos, extract_nps_src1_pos },
2202
2203 #define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
2204 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2205 insert_nps_addb_size, extract_nps_addb_size },
2206
2207 #define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
2208 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2209 insert_nps_andb_size, extract_nps_andb_size },
2210
2211 #define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
2212 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2213 insert_nps_fxorb_size, extract_nps_fxorb_size },
2214
2215 #define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
2216 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2217 insert_nps_wxorb_size, extract_nps_wxorb_size },
2218
2219 #define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
2220 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
2221
2222 #define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
2223 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2224
2225 #define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
2226 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2227 insert_nps_qcmp_size, extract_nps_qcmp_size },
2228
2229 #define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
2230 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
2231
2232 #define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
2233 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
2234
2235 #define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
2236 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
2237
2238 #define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
2239 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2240 insert_nps_calc_entry_size, extract_nps_calc_entry_size },
2241
2242 #define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
2243 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2244 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
2245
2246 #define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
2247 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2248 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
2249
2250 #define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
2251 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2252 insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
2253
2254 #define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
2255 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2256 insert_nps_bitop2_size, extract_nps_bitop2_size },
2257
2258 #define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
2259 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2260 insert_nps_bitop1_size, extract_nps_bitop1_size },
2261
2262 #define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
2263 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2264 insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
2265
2266 #define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
2267 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2268
2269 #define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
2270 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2271
2272 #define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
2273 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2274
2275 #define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
2276 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2277
2278 #define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
2279 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2280
2281 #define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
2282 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2283
2284 #define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
2285 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2286
2287 #define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
2288 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2289
2290 #define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
2291 { 2, 0, 0, ARC_OPERAND_UNSIGNED,
2292 insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
2293
2294 #define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
2295 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2296
2297 #define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
2298 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2299
2300 #define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2301 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2302
2303 #define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
2304 { 5, 20, 0, ARC_OPERAND_UNSIGNED,
2305 insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
2306
2307 #define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2308 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2309
2310 #define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
2311 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2312 insert_nps_field_size, extract_nps_field_size },
2313
2314 #define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
2315 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2316 insert_nps_shift_factor, extract_nps_shift_factor },
2317
2318 #define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
2319 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2320 insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
2321
2322 #define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2323 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2324
2325 #define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
2326 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2327 insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
2328
2329 #define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
2330 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2331 insert_nps_min_hofs, extract_nps_min_hofs },
2332
2333 #define NPS_PSBC (NPS_MIN_HOFS + 1)
2334 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2335
2336 #define NPS_DPI_DST (NPS_PSBC + 1)
2337 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2338
2339 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
2340 but doesn't duplicate an operand. */
2341 #define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
2342 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2343 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
2344
2345 #define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
2346 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2347 insert_nps_hash_width, extract_nps_hash_width },
2348
2349 #define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2350 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2351
2352 #define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2353 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2354
2355 #define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2356 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2357
2358 #define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
2359 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2360 insert_nps_hash_len, extract_nps_hash_len },
2361
2362 #define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2363 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2364
2365 #define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2366 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2367
2368 #define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2369 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2370
2371 #define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2372 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2373
2374 #define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2375 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2376
2377 #define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
2378 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2379 insert_nps_index3, extract_nps_index3 },
2380
2381 #define COLON (NPS_E4BY_INDEX3 + 1)
2382 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2383
2384 #define NPS_BD (COLON + 1)
2385 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2386 insert_nps_bd, extract_nps_bd },
2387
2388 #define NPS_JID (NPS_BD + 1)
2389 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2390 insert_nps_jid, extract_nps_jid },
2391
2392 #define NPS_LBD (NPS_JID + 1)
2393 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2394 insert_nps_lbd, extract_nps_lbd },
2395
2396 #define NPS_MBD (NPS_LBD + 1)
2397 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2398 insert_nps_mbd, extract_nps_mbd },
2399
2400 #define NPS_SD (NPS_MBD + 1)
2401 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2402 insert_nps_sd, extract_nps_sd },
2403
2404 #define NPS_SM (NPS_SD + 1)
2405 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2406 insert_nps_sm, extract_nps_sm },
2407
2408 #define NPS_XA (NPS_SM + 1)
2409 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2410 insert_nps_xa, extract_nps_xa },
2411
2412 #define NPS_XD (NPS_XA + 1)
2413 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2414 insert_nps_xd, extract_nps_xd },
2415
2416 #define NPS_CD (NPS_XD + 1)
2417 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2418 insert_nps_cd, extract_nps_cd },
2419
2420 #define NPS_CBD (NPS_CD + 1)
2421 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2422 insert_nps_cbd, extract_nps_cbd },
2423
2424 #define NPS_CJID (NPS_CBD + 1)
2425 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2426 insert_nps_cjid, extract_nps_cjid },
2427
2428 #define NPS_CLBD (NPS_CJID + 1)
2429 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2430 insert_nps_clbd, extract_nps_clbd },
2431
2432 #define NPS_CM (NPS_CLBD + 1)
2433 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2434 insert_nps_cm, extract_nps_cm },
2435
2436 #define NPS_CSD (NPS_CM + 1)
2437 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2438 insert_nps_csd, extract_nps_csd },
2439
2440 #define NPS_CXA (NPS_CSD + 1)
2441 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2442 insert_nps_cxa, extract_nps_cxa },
2443
2444 #define NPS_CXD (NPS_CXA + 1)
2445 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2446 insert_nps_cxd, extract_nps_cxd },
2447
2448 #define NPS_BD_TYPE (NPS_CXD + 1)
2449 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2450
2451 #define NPS_BMU_NUM (NPS_BD_TYPE + 1)
2452 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2453 insert_nps_bd_num_buff, extract_nps_bd_num_buff },
2454
2455 #define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2456 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2457
2458 #define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1)
2459 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2460 insert_nps_size_16bit, extract_nps_size_16bit },
2461
2462 #define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1)
2463 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2464 insert_nps_pmu_num_job, extract_nps_pmu_num_job },
2465
2466 #define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1)
2467 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2468 insert_nps_imm_entry, extract_nps_imm_entry },
2469
2470 #define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
2471 { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2472 insert_nps_imm_offset, extract_nps_imm_offset },
2473
2474 #define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1)
2475 { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL },
2476
2477 #define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1)
2478 { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2479 insert_nps_misc_imm_offset, extract_nps_misc_imm_offset },
2480
2481 #define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1)
2482 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2483 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2484
2485 #define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
2486 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2487 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
2488
2489 #define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
2490 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2491 insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
2492
2493 #define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
2494 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2495 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2496
2497 #define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
2498 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2499 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
2500
2501 #define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
2502 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2503 insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
2504
2505 #define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
2506 { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
2507
2508 #define NPS_RB_64 (NPS_RA_64 + 1)
2509 { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
2510
2511 #define NPS_RBdup_64 (NPS_RB_64 + 1)
2512 { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2513
2514 #define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
2515 { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2516 insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
2517
2518 #define NPS_RC_64 (NPS_RBdouble_64 + 1)
2519 { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
2520
2521 #define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
2522 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2523
2524 #define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
2525 { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2526 insert_nps_proto_size, extract_nps_proto_size }
2527 };
2528 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
2529
2530 const unsigned arc_Toperand = FKT_T;
2531 const unsigned arc_NToperand = FKT_NT;
2532
2533 const unsigned char arg_none[] = { 0 };
2534 const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2535 const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2536 const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2537 const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2538 const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2539 const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2540 const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2541 const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2542 const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2543 const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2544 const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2545
2546 const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2547 const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2548 const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2549
2550 const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2551 const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2552 const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2553
2554 const unsigned char arg_32bit_rbrc[] = { RB, RC };
2555 const unsigned char arg_32bit_zarc[] = { ZA, RC };
2556 const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2557 const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2558 const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2559 const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2560
2561 const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2562 const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2563 const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2564 const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2565
2566 const unsigned char arg_32bit_rc[] = { RC };
2567 const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2568 const unsigned char arg_32bit_limm[] = { LIMM };
2569
2570 /* The opcode table.
2571
2572 The format of the opcode table is:
2573
2574 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2575
2576 The table is organised such that, where possible, all instructions with
2577 the same mnemonic are together in a block. When the assembler searches
2578 for a suitable instruction the entries are checked in table order, so
2579 more specific, or specialised cases should appear earlier in the table.
2580
2581 As an example, consider two instructions 'add a,b,u6' and 'add
2582 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2583 32-bit instruction, while the second takes a 32-bit immediate that is
2584 encoded in a follow-on 32-bit, making the total instruction length
2585 64-bits. In this case the u6 variant must appear first in the table, as
2586 all u6 immediates could also be encoded using the 'limm' extension,
2587 however, we want to use the shorter instruction wherever possible.
2588
2589 It is possible though to split instructions with the same mnemonic into
2590 multiple groups. However, the instructions are still checked in table
2591 order, even across groups. The only time that instructions with the
2592 same mnemonic should be split into different groups is when different
2593 variants of the instruction appear in different architectures, in which
2594 case, grouping all instructions from a particular architecture together
2595 might be preferable to merging the instruction into the main instruction
2596 table.
2597
2598 An example of this split instruction groups can be found with the 'sync'
2599 instruction. The core arc architecture provides a 'sync' instruction,
2600 while the nps instruction set extension provides 'sync.rd' and
2601 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2602 mnemonic, so we end up with two groups for the sync instruction, the
2603 first within the core arc instruction table, and the second within the
2604 nps extension instructions. */
2605 const struct arc_opcode arc_opcodes[] =
2606 {
2607 #include "arc-tbl.h"
2608 #include "arc-nps400-tbl.h"
2609 #include "arc-ext-tbl.h"
2610
2611 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2612 };
2613
2614 /* List with special cases instructions and the applicable flags. */
2615 const struct arc_flag_special arc_flag_special_cases[] =
2616 {
2617 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2618 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2619 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2620 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
2621 F_NO_T, F_NULL } },
2622 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2623 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2624 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2625 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2626 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2627 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2628 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2629 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2630 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2631 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2632 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2633 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2634 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2635 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2636 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2637 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2638 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2639 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2640 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2641 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2642 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2643 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2644 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2645 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2646 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2647 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2648 };
2649
2650 const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
2651
2652 /* Relocations. */
2653 const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2654 {
2655 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2656 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2657 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2658 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2659 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2660 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2661 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2662 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2663
2664 /* Next two entries will cover the undefined behavior ldb/stb with
2665 address scaling. */
2666 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2667 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2668 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2669 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2670
2671 { "sda", "ld", { F_ASFAKE, F_NULL },
2672 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2673 { "sda", "st", { F_ASFAKE, F_NULL },
2674 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2675 { "sda", "ldd", { F_ASFAKE, F_NULL },
2676 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2677 { "sda", "std", { F_ASFAKE, F_NULL },
2678 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2679
2680 /* Short instructions. */
2681 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2682 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2683 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2684 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2685
2686 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2687 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2688
2689 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2690 BFD_RELOC_ARC_S25H_PCREL_PLT },
2691 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2692 BFD_RELOC_ARC_S21H_PCREL_PLT },
2693 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2694 BFD_RELOC_ARC_S25W_PCREL_PLT },
2695 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2696 BFD_RELOC_ARC_S21W_PCREL_PLT },
2697
2698 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
2699 };
2700
2701 const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
2702
2703 const struct arc_pseudo_insn arc_pseudo_insns[] =
2704 {
2705 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2706 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2707 { BRAKETdup, 1, 0, 4} } },
2708 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2709 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2710 { BRAKETdup, 1, 0, 4} } },
2711
2712 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2713 { SIMM9_A16_8, 0, 0, 2 } } },
2714 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2715 { SIMM9_A16_8, 0, 0, 2 } } },
2716 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2717 { SIMM9_A16_8, 0, 0, 2 } } },
2718 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2719 { SIMM9_A16_8, 0, 0, 2 } } },
2720 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2721 { SIMM9_A16_8, 0, 0, 2 } } },
2722
2723 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2724 { SIMM9_A16_8, 0, 0, 2 } } },
2725 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2726 { SIMM9_A16_8, 0, 0, 2 } } },
2727 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2728 { SIMM9_A16_8, 0, 0, 2 } } },
2729 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2730 { SIMM9_A16_8, 0, 0, 2 } } },
2731 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2732 { SIMM9_A16_8, 0, 0, 2 } } },
2733
2734 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2735 { SIMM9_A16_8, 0, 0, 2 } } },
2736 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2737 { SIMM9_A16_8, 0, 0, 2 } } },
2738 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2739 { SIMM9_A16_8, 0, 0, 2 } } },
2740 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2741 { SIMM9_A16_8, 0, 0, 2 } } },
2742 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2743 { SIMM9_A16_8, 0, 0, 2 } } },
2744
2745 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2746 { SIMM9_A16_8, 0, 0, 2 } } },
2747 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2748 { SIMM9_A16_8, 0, 0, 2 } } },
2749 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2750 { SIMM9_A16_8, 0, 0, 2 } } },
2751 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2752 { SIMM9_A16_8, 0, 0, 2 } } },
2753 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2754 { SIMM9_A16_8, 0, 0, 2 } } },
2755 };
2756
2757 const unsigned arc_num_pseudo_insn =
2758 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
2759
2760 const struct arc_aux_reg arc_aux_regs[] =
2761 {
2762 #undef DEF
2763 #define DEF(ADDR, CPU, SUBCLASS, NAME) \
2764 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
2765
2766 #include "arc-regs.h"
2767
2768 #undef DEF
2769 };
2770
2771 const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
2772
2773 /* NOTE: The order of this array MUST be consistent with 'enum
2774 arc_rlx_types' located in tc-arc.h! */
2775 const struct arc_opcode arc_relax_opcodes[] =
2776 {
2777 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2778
2779 /* bl_s s13 11111sssssssssss. */
2780 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2781 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2782 { SIMM13_A32_5_S }, { 0 }},
2783
2784 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2785 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2786 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2787 { SIMM25_A32_5 }, { C_D }},
2788
2789 /* b_s s10 1111000sssssssss. */
2790 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2791 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2792 { SIMM10_A16_7_S }, { 0 }},
2793
2794 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2795 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2796 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2797 { SIMM25_A16_5 }, { C_D }},
2798
2799 /* add_s c,b,u3 01101bbbccc00uuu. */
2800 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2801 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2802 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
2803
2804 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
2805 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2806 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2807 { RA, RB, UIMM6_20R }, { C_F }},
2808
2809 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2810 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2811 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2812 { RA, RB, LIMM }, { C_F }},
2813
2814 /* ld_s c,b,u7 10000bbbcccuuuuu. */
2815 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2816 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2817 { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
2818
2819 /* ld<.di><.aa><.x><zz> a,b,s9
2820 00010bbbssssssssSBBBDaaZZXAAAAAA. */
2821 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2822 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2823 { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
2824 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2825
2826 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2827 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2828 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2829 { RA, BRAKET, RB, LIMM, BRAKETdup },
2830 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2831
2832 /* mov_s b,u8 11011bbbuuuuuuuu. */
2833 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2834 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2835 { RB_S, UIMM8_8R_S }, { 0 }},
2836
2837 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
2838 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2839 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2840 { RB, SIMM12_20R }, { C_F }},
2841
2842 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2843 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2844 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2845 { RB, LIMM }, { C_F }},
2846
2847 /* sub_s c,b,u3 01101bbbccc01uuu. */
2848 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2849 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2850 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
2851
2852 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
2853 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2854 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2855 { RA, RB, UIMM6_20R }, { C_F }},
2856
2857 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2858 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2859 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2860 { RA, RB, LIMM }, { C_F }},
2861
2862 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
2863 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2864 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
2865
2866 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2867 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2868 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2869
2870 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
2871 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2872 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2873 { RB, UIMM6_20R }, { C_F, C_CC }},
2874
2875 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2876 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2877 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2878 { RB, LIMM }, { C_F, C_CC }},
2879
2880 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
2881 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2882 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2883 { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
2884
2885 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2886 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2887 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2888 { RB, RBdup, LIMM }, { C_F, C_CC }}
2889 };
2890
2891 const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
2892
2893 /* Return length of an opcode in bytes. */
2894
2895 int
2896 arc_opcode_len (const struct arc_opcode *opcode)
2897 {
2898 if (opcode->mask < 0x10000ull)
2899 return 2;
2900
2901 if (opcode->mask < 0x100000000ull)
2902 return 4;
2903
2904 if (opcode->mask < 0x1000000000000ull)
2905 return 6;
2906
2907 return 8;
2908 }
GDB Binutils - Deliverables
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