1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
181 enum mve_unpredictable
183 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
185 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
187 UNPRED_R13
, /* Unpredictable because r13 (sp) or
189 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
190 UNPRED_Q_GT_4
, /* Unpredictable because
191 vec reg start > 4 (vld4/st4). */
192 UNPRED_Q_GT_6
, /* Unpredictable because
193 vec reg start > 6 (vld2/st2). */
194 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
196 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
198 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
199 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
201 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
203 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
205 UNPRED_NONE
/* No unpredictable behavior. */
210 UNDEF_SIZE_0
, /* undefined because size == 0. */
211 UNDEF_SIZE_2
, /* undefined because size == 2. */
212 UNDEF_SIZE_3
, /* undefined because size == 3. */
213 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
214 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
215 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
216 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
218 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
220 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
221 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
222 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
223 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
225 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
226 op2 == 0 and op1 == (0 or 1). */
227 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
229 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
230 UNDEF_NONE
/* no undefined behavior. */
235 arm_feature_set arch
; /* Architecture defining this insn. */
236 unsigned long value
; /* If arch is 0 then value is a sentinel. */
237 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
238 const char * assembler
; /* How to disassemble this insn. */
245 arm_feature_set arch
; /* Architecture defining this insn. */
246 enum mve_instructions mve_op
; /* Specific mve instruction for faster
248 unsigned long value
; /* If arch is 0 then value is a sentinel. */
249 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
250 const char * assembler
; /* How to disassemble this insn. */
260 /* Shared (between Arm and Thumb mode) opcode. */
263 enum isa isa
; /* Execution mode instruction availability. */
264 arm_feature_set arch
; /* Architecture defining this insn. */
265 unsigned long value
; /* If arch is 0 then value is a sentinel. */
266 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
267 const char * assembler
; /* How to disassemble this insn. */
272 arm_feature_set arch
; /* Architecture defining this insn. */
273 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
274 const char *assembler
; /* How to disassemble this insn. */
277 /* print_insn_coprocessor recognizes the following format control codes:
281 %c print condition code (always bits 28-31 in ARM mode)
282 %q print shifter argument
283 %u print condition code (unconditional in ARM mode,
284 UNPREDICTABLE if not AL in Thumb)
285 %A print address for ldc/stc/ldf/stf instruction
286 %B print vstm/vldm register list
287 %C print vscclrm register list
288 %I print cirrus signed shift immediate: bits 0..3|4..6
289 %J print register for VLDR instruction
290 %K print address for VLDR instruction
291 %F print the COUNT field of a LFM/SFM instruction.
292 %P print floating point precision in arithmetic insn
293 %Q print floating point precision in ldf/stf insn
294 %R print floating point rounding mode
296 %<bitfield>c print as a condition code (for vsel)
297 %<bitfield>r print as an ARM register
298 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
299 %<bitfield>ru as %<>r but each u register must be unique.
300 %<bitfield>d print the bitfield in decimal
301 %<bitfield>k print immediate for VFPv3 conversion instruction
302 %<bitfield>x print the bitfield in hex
303 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
304 %<bitfield>f print a floating point constant if >7 else a
305 floating point register
306 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
307 %<bitfield>g print as an iWMMXt 64-bit register
308 %<bitfield>G print as an iWMMXt general purpose or control register
309 %<bitfield>D print as a NEON D register
310 %<bitfield>Q print as a NEON Q register
311 %<bitfield>V print as a NEON D or Q register
312 %<bitfield>E print a quarter-float immediate value
314 %y<code> print a single precision VFP reg.
315 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
316 %z<code> print a double precision VFP reg
317 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
319 %<bitfield>'c print specified char iff bitfield is all ones
320 %<bitfield>`c print specified char iff bitfield is all zeroes
321 %<bitfield>?ab... select from array of values in big endian order
323 %L print as an iWMMXt N/M width field.
324 %Z print the Immediate of a WSHUFH instruction.
325 %l like 'A' except use byte offsets for 'B' & 'H'
327 %i print 5-bit immediate in bits 8,3..0
329 %r print register offset address for wldt/wstr instruction. */
331 enum opcode_sentinel_enum
333 SENTINEL_IWMMXT_START
= 1,
335 SENTINEL_GENERIC_START
338 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
339 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
340 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
341 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
343 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
345 static const struct sopcode32 coprocessor_opcodes
[] =
347 /* XScale instructions. */
348 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
349 0x0e200010, 0x0fff0ff0,
350 "mia%c\tacc0, %0-3r, %12-15r"},
351 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
352 0x0e280010, 0x0fff0ff0,
353 "miaph%c\tacc0, %0-3r, %12-15r"},
354 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
355 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
356 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
357 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
358 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
359 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
361 /* Intel Wireless MMX technology instructions. */
362 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
363 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
364 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
365 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
366 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
367 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
368 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
369 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
370 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
371 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
372 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
373 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
374 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
375 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
376 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
377 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
378 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
379 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
380 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
381 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
382 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
383 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
384 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
385 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
386 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
387 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
388 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
389 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
390 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
391 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
392 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
393 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
394 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
395 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
396 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
397 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
398 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
399 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
400 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
401 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
402 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
403 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
404 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
405 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
406 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
407 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
408 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
409 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
410 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
411 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
412 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
413 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
414 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
415 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
416 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
417 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
418 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
419 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
420 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
421 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
422 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
423 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
424 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
425 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
426 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
427 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
428 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
429 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
430 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
431 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
432 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
433 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
434 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
435 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
436 0x0e800120, 0x0f800ff0,
437 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
438 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
439 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
440 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
441 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
442 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
443 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
444 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
445 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
446 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
447 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
448 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
449 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
450 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
451 0x0e8000a0, 0x0f800ff0,
452 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
453 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
454 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
455 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
456 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
457 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
458 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
459 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
460 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
461 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
462 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
463 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
464 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
465 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
466 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
467 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
468 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
469 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
470 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
471 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
472 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
473 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
474 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
475 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
476 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
477 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
478 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
479 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
480 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
481 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
482 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
483 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
484 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
485 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
486 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
487 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
488 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
489 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
490 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
491 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
492 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
493 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
494 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
495 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
496 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
497 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
498 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
499 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
500 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
501 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
502 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
503 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
504 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
505 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
506 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
507 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
508 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
509 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
510 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
511 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
512 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
513 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
514 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
515 {ANY
, ARM_FEATURE_CORE_LOW (0),
516 SENTINEL_IWMMXT_END
, 0, "" },
518 /* Floating point coprocessor (FPA) instructions. */
519 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
520 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
521 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
522 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
523 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
524 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
525 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
526 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
527 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
528 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
529 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
530 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
531 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
532 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
533 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
534 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
535 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
536 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
537 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
538 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
539 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
540 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
541 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
542 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
543 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
544 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
545 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
546 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
547 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
548 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
549 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
550 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
551 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
552 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
553 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
554 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
555 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
556 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
557 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
558 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
559 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
560 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
561 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
562 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
563 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
564 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
565 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
566 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
567 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
568 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
569 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
570 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
571 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
572 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
573 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
574 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
575 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
576 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
577 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
578 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
579 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
580 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
581 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
582 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
583 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
584 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
585 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
586 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
587 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
588 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
589 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
590 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
591 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
592 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
593 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
594 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
595 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
596 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
597 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
598 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
599 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
600 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
601 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
602 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
603 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
604 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
606 /* Armv8.1-M Mainline instructions. */
607 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
608 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
609 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
610 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
612 /* ARMv8-M Mainline Security Extensions instructions. */
613 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
614 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
615 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
616 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
618 /* Register load/store. */
619 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
620 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
621 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
622 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
623 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
624 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
625 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
626 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
627 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
628 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
629 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
630 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
631 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
632 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
633 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
634 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
635 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
636 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
637 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
638 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
639 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
640 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
641 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
642 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
643 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
644 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
645 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
646 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
647 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
648 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
649 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
650 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
651 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
652 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
653 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
654 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
656 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
657 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
658 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
659 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
660 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
661 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
662 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
663 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
665 /* Data transfer between ARM and NEON registers. */
666 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
667 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
668 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
669 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
670 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
671 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
672 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
673 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
674 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
675 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
676 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
677 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
678 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
679 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
680 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
681 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
682 /* Half-precision conversion instructions. */
683 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
684 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
685 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
686 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
687 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
688 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
689 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
690 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
692 /* Floating point coprocessor (VFP) instructions. */
693 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
694 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
695 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
696 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
697 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
698 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
699 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
700 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
701 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
702 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
703 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
704 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
705 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
706 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
707 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
708 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
709 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
710 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
711 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
712 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
713 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
714 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
715 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
716 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
717 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
718 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
719 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
720 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
721 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
722 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
723 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
724 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
725 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
726 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
727 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
728 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
729 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
730 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
731 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
732 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
733 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
734 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
735 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
736 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
737 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
738 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
739 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
740 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
741 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
742 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
743 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
744 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
745 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
746 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
747 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
748 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
749 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
750 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
751 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
752 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
753 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
754 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
755 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
756 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
757 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
758 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
759 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
760 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
761 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
762 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
763 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
764 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
765 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
766 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
767 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
768 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
769 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
770 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
771 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
772 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
773 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
774 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
775 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
776 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
777 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
778 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
779 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
780 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
781 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
782 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
783 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
784 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
785 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
786 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
787 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
788 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
789 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
790 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
791 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
792 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
793 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
794 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
795 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
796 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
797 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
798 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
799 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
800 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
801 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
802 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
803 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
804 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
805 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
806 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
807 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
808 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
809 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
810 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
811 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
812 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
813 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
814 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
815 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
816 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
817 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
818 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
819 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
820 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
821 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
822 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
823 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
824 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
825 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
826 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
827 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
828 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
829 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
830 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
832 /* Cirrus coprocessor instructions. */
833 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
834 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
835 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
836 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
837 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
838 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
839 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
840 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
841 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
842 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
843 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
844 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
845 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
846 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
847 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
848 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
849 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
850 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
851 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
852 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
853 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
854 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
855 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
856 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
857 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
858 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
859 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
860 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
861 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
862 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
863 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
864 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
865 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
866 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
867 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
868 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
869 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
870 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
871 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
872 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
873 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
874 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
875 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
876 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
877 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
878 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
879 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
880 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
881 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
882 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
883 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
884 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
885 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
886 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
887 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
888 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
889 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
890 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
891 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
892 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
893 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
894 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
895 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
896 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
897 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
898 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
899 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
900 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
901 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
902 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
903 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
904 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
905 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
906 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
907 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
908 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
909 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
910 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
911 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
912 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
913 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
914 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
915 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
916 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
917 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
918 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
919 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
920 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
921 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
922 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
923 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
924 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
925 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
926 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
927 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
928 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
929 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
930 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
931 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
932 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
933 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
934 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
935 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
936 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
937 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
938 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
939 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
940 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
941 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
942 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
943 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
944 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
945 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
946 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
947 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
948 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
949 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
950 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
951 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
952 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
953 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
954 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
955 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
956 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
957 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
958 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
959 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
960 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
961 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
962 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
963 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
964 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
965 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
966 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
967 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
968 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
969 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
970 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
971 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
972 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
973 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
974 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
975 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
976 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
977 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
978 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
979 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
980 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
981 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
982 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
983 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
984 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
985 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
986 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
987 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
988 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
989 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
990 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
991 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
992 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
993 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
994 0x0e000600, 0x0ff00f10,
995 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
996 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
997 0x0e100600, 0x0ff00f10,
998 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
999 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1000 0x0e200600, 0x0ff00f10,
1001 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1002 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1003 0x0e300600, 0x0ff00f10,
1004 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1006 /* VFP Fused multiply add instructions. */
1007 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1008 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1009 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1010 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1011 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1012 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1013 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1014 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1015 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1016 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1017 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1018 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1019 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1020 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1021 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1022 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1025 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1026 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1027 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1028 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1029 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1030 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1031 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1032 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1033 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1034 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1035 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1036 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1037 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1038 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1039 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1040 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1041 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1042 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1043 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1044 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1045 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1046 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1047 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1048 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1050 /* Generic coprocessor instructions. */
1051 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1052 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1053 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1054 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1055 0x0c500000, 0x0ff00000,
1056 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1057 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1058 0x0e000000, 0x0f000010,
1059 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1060 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1061 0x0e10f010, 0x0f10f010,
1062 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1063 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1064 0x0e100010, 0x0f100010,
1065 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1066 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1067 0x0e000010, 0x0f100010,
1068 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1069 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1070 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1071 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1072 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1074 /* V6 coprocessor instructions. */
1075 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1076 0xfc500000, 0xfff00000,
1077 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1078 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1079 0xfc400000, 0xfff00000,
1080 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1082 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1083 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1084 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1085 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1086 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1087 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1088 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1089 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1090 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1091 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1092 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1093 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1094 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1095 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1096 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1097 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1098 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1099 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1100 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1101 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1102 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1104 /* Dot Product instructions in the space of coprocessor 13. */
1105 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1106 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1107 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1108 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1110 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1111 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1112 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1113 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1114 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1115 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1116 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1117 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1118 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1119 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1120 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1121 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1122 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1123 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1124 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1125 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1126 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1128 /* V5 coprocessor instructions. */
1129 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1130 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1131 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1132 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1133 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1134 0xfe000000, 0xff000010,
1135 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1136 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1137 0xfe000010, 0xff100010,
1138 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1139 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1140 0xfe100010, 0xff100010,
1141 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1143 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1144 cp_num: bit <11:8> == 0b1001.
1145 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1146 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1147 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1148 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1149 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1150 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1151 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1152 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1153 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1154 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1155 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1156 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1157 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1158 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1159 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1160 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1161 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1162 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1163 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1164 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1165 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1166 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1167 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1168 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1169 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1170 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1171 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1172 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1173 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1174 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1175 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1176 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1177 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1178 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1179 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1180 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1181 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1182 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1183 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1184 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1185 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1186 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1187 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1188 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1189 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1190 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1191 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1192 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1193 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1194 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1195 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1196 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1197 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1198 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1199 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1200 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1201 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1202 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1203 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1204 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1205 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1206 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1207 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1208 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1209 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1210 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1211 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1212 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1213 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1214 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1215 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1217 /* ARMv8.3 javascript conversion instruction. */
1218 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1219 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1221 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1224 /* Neon opcode table: This does not encode the top byte -- that is
1225 checked by the print_insn_neon routine, as it depends on whether we are
1226 doing thumb32 or arm32 disassembly. */
1228 /* print_insn_neon recognizes the following format control codes:
1232 %c print condition code
1233 %u print condition code (unconditional in ARM mode,
1234 UNPREDICTABLE if not AL in Thumb)
1235 %A print v{st,ld}[1234] operands
1236 %B print v{st,ld}[1234] any one operands
1237 %C print v{st,ld}[1234] single->all operands
1239 %E print vmov, vmvn, vorr, vbic encoded constant
1240 %F print vtbl,vtbx register list
1242 %<bitfield>r print as an ARM register
1243 %<bitfield>d print the bitfield in decimal
1244 %<bitfield>e print the 2^N - bitfield in decimal
1245 %<bitfield>D print as a NEON D register
1246 %<bitfield>Q print as a NEON Q register
1247 %<bitfield>R print as a NEON D or Q register
1248 %<bitfield>Sn print byte scaled width limited by n
1249 %<bitfield>Tn print short scaled width limited by n
1250 %<bitfield>Un print long scaled width limited by n
1252 %<bitfield>'c print specified char iff bitfield is all ones
1253 %<bitfield>`c print specified char iff bitfield is all zeroes
1254 %<bitfield>?ab... select from array of values in big endian order. */
1256 static const struct opcode32 neon_opcodes
[] =
1259 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1260 0xf2b00840, 0xffb00850,
1261 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1263 0xf2b00000, 0xffb00810,
1264 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1266 /* Data transfer between ARM and NEON registers. */
1267 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1268 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1269 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1270 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1271 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1272 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1273 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1274 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1275 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1276 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1277 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1278 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1280 /* Move data element to all lanes. */
1281 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1282 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1283 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1284 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1285 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1286 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1289 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1290 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1291 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1292 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1294 /* Half-precision conversions. */
1295 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1296 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1297 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1298 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1300 /* NEON fused multiply add instructions. */
1301 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1302 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1304 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1306 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1308 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310 /* Two registers, miscellaneous. */
1311 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1312 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1313 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1314 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1315 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1316 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1317 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1318 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1319 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1320 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1321 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1322 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1323 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1324 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1325 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1326 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1327 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1328 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1329 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1330 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1331 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1332 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1333 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1334 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1336 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1337 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1338 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1339 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1340 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1342 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1343 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1344 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1345 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1346 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1348 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1349 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1350 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1351 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1352 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1354 0xf3b20300, 0xffb30fd0,
1355 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1357 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1358 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1359 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1360 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1361 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1362 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1363 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1364 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1365 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1366 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1367 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1369 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1370 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1371 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1372 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1373 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1375 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1376 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1377 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1378 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1379 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1381 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1382 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1383 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1384 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1385 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1387 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1388 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1389 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1390 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1391 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1393 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1394 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1395 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1397 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1398 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1399 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1400 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1401 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1402 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1403 0xf3bb0600, 0xffbf0e10,
1404 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1405 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1406 0xf3b70600, 0xffbf0e10,
1407 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1409 /* Three registers of the same length. */
1410 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1411 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1412 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1413 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1414 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1415 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1416 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1417 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1418 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1419 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1420 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1421 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1422 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1423 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1424 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1425 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1427 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1429 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1430 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1431 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1432 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1433 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1434 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1435 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1436 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1437 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1439 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1441 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1443 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1445 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1447 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1449 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1451 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1453 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1455 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1457 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1459 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1460 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1461 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1463 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1465 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1466 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1467 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1469 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1471 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1473 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1475 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1477 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1478 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1479 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1481 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1483 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1485 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1487 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1489 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1491 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1492 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1493 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1494 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1495 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1497 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1499 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1501 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1502 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1503 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1505 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1506 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1507 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1509 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1511 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1513 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1514 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1515 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1517 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1518 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1519 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1521 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1523 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1525 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1527 0xf2000b00, 0xff800f10,
1528 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1530 0xf2000b10, 0xff800f10,
1531 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1533 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1535 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1537 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1539 0xf3000b00, 0xff800f10,
1540 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1541 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1542 0xf2000000, 0xfe800f10,
1543 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1544 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1545 0xf2000010, 0xfe800f10,
1546 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1547 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1548 0xf2000100, 0xfe800f10,
1549 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1550 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1551 0xf2000200, 0xfe800f10,
1552 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1553 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1554 0xf2000210, 0xfe800f10,
1555 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1557 0xf2000300, 0xfe800f10,
1558 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1559 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1560 0xf2000310, 0xfe800f10,
1561 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1563 0xf2000400, 0xfe800f10,
1564 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1566 0xf2000410, 0xfe800f10,
1567 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1569 0xf2000500, 0xfe800f10,
1570 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1572 0xf2000510, 0xfe800f10,
1573 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1574 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1575 0xf2000600, 0xfe800f10,
1576 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1578 0xf2000610, 0xfe800f10,
1579 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1580 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1581 0xf2000700, 0xfe800f10,
1582 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1584 0xf2000710, 0xfe800f10,
1585 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1586 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1587 0xf2000910, 0xfe800f10,
1588 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1590 0xf2000a00, 0xfe800f10,
1591 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1593 0xf2000a10, 0xfe800f10,
1594 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1596 0xf3000b10, 0xff800f10,
1597 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1599 0xf3000c10, 0xff800f10,
1600 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1602 /* One register and an immediate value. */
1603 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1604 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1606 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1607 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1608 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1610 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1611 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1612 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1614 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1615 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1616 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1618 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1619 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1620 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1622 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1624 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1626 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1628 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1630 /* Two registers and a shift amount. */
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1632 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1634 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1636 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1638 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1640 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1642 0xf2880950, 0xfeb80fd0,
1643 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1645 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1647 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1648 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1649 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1651 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1653 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1655 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1656 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1657 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1658 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1659 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1661 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1662 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1663 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1664 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1665 0xf2900950, 0xfeb00fd0,
1666 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1667 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1668 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1670 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1672 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1674 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1676 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1677 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1678 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1679 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1680 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1682 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1683 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1684 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1686 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1688 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1690 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1692 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1694 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1696 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1698 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1700 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1702 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1704 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1706 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1707 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1708 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1710 0xf2a00950, 0xfea00fd0,
1711 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1715 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1716 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1717 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1718 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1719 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1721 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1722 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1723 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1724 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1725 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1727 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1728 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1729 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1730 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1731 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1733 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1734 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1735 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1736 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1737 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1738 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1739 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1743 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1745 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1747 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf2a00e10, 0xfea00e90,
1750 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1752 0xf2a00c10, 0xfea00e90,
1753 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1755 /* Three registers of different lengths. */
1756 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1757 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1761 0xf2800400, 0xff800f50,
1762 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1763 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1764 0xf2800600, 0xff800f50,
1765 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1766 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1767 0xf2800900, 0xff800f50,
1768 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1770 0xf2800b00, 0xff800f50,
1771 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf2800d00, 0xff800f50,
1774 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1775 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1776 0xf3800400, 0xff800f50,
1777 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1779 0xf3800600, 0xff800f50,
1780 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1782 0xf2800000, 0xfe800f50,
1783 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1784 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1785 0xf2800100, 0xfe800f50,
1786 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1788 0xf2800200, 0xfe800f50,
1789 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1790 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1791 0xf2800300, 0xfe800f50,
1792 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf2800500, 0xfe800f50,
1795 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1796 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1797 0xf2800700, 0xfe800f50,
1798 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1800 0xf2800800, 0xfe800f50,
1801 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1802 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1803 0xf2800a00, 0xfe800f50,
1804 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1805 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1806 0xf2800c00, 0xfe800f50,
1807 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1809 /* Two registers and a scalar. */
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1811 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1813 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1814 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1815 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1817 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1819 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1821 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1822 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1823 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1825 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1827 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1829 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1830 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1831 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1833 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1835 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1837 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1839 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1841 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1842 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1843 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1845 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1847 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1848 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1849 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1850 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1851 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1853 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1854 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1855 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1856 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1857 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1858 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1859 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1861 0xf2800240, 0xfe800f50,
1862 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1864 0xf2800640, 0xfe800f50,
1865 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1867 0xf2800a40, 0xfe800f50,
1868 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1870 0xf2800e40, 0xff800f50,
1871 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1873 0xf2800f40, 0xff800f50,
1874 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1876 0xf3800e40, 0xff800f50,
1877 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1879 0xf3800f40, 0xff800f50,
1880 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1883 /* Element and structure load/store. */
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1885 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1886 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1887 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1889 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1891 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1893 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1895 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1897 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1899 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1901 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1902 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1903 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1904 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1905 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1907 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1908 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1909 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1910 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1911 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1913 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1914 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1915 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1916 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1917 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1919 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1920 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1921 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1923 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1926 /* mve opcode table. */
1928 /* print_insn_mve recognizes the following format control codes:
1932 %a print '+' or '-' or imm offset in vldr[bhwd] and
1934 %c print condition code
1935 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
1936 %u print 'U' (unsigned) or 'S' for various mve instructions
1937 %i print MVE predicate(s) for vpt and vpst
1938 %m print rounding mode for vcvt and vrint
1939 %n print vector comparison code for predicated instruction
1940 %s print size for various vcvt instructions
1941 %v print vector predicate for instruction in predicated
1943 %o print offset scaled for vldr[hwd] and vstr[hwd]
1944 %w print writeback mode for MVE v{st,ld}[24]
1945 %B print v{st,ld}[24] any one operands
1946 %E print vmov, vmvn, vorr, vbic encoded constant
1947 %N print generic index for vmov
1948 %T print bottom ('b') or top ('t') of source register
1949 %X print exchange field in vmla* instructions
1951 %<bitfield>r print as an ARM register
1952 %<bitfield>d print the bitfield in decimal
1953 %<bitfield>A print accumulate or not
1954 %<bitfield>Q print as a MVE Q register
1955 %<bitfield>F print as a MVE S register
1956 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
1958 %<bitfield>s print size for vector predicate & non VMOV instructions
1959 %<bitfield>i print immediate for vstr/vldr reg +/- imm
1960 %<bitfield>k print immediate for vector conversion instruction
1961 %<bitfield>x print the bitfield in hex.
1964 static const struct mopcode32 mve_opcodes
[] =
1968 {ARM_FEATURE_COPROC (FPU_MVE
),
1970 0xfe310f4d, 0xffbf1fff,
1974 /* Floating point VPT T1. */
1975 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1977 0xee310f00, 0xefb10f50,
1978 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
1979 /* Floating point VPT T2. */
1980 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
1982 0xee310f40, 0xefb10f50,
1983 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
1985 /* Vector VPT T1. */
1986 {ARM_FEATURE_COPROC (FPU_MVE
),
1988 0xfe010f00, 0xff811f51,
1989 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
1990 /* Vector VPT T2. */
1991 {ARM_FEATURE_COPROC (FPU_MVE
),
1993 0xfe010f01, 0xff811f51,
1994 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
1995 /* Vector VPT T3. */
1996 {ARM_FEATURE_COPROC (FPU_MVE
),
1998 0xfe011f00, 0xff811f50,
1999 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2000 /* Vector VPT T4. */
2001 {ARM_FEATURE_COPROC (FPU_MVE
),
2003 0xfe010f40, 0xff811f70,
2004 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2005 /* Vector VPT T5. */
2006 {ARM_FEATURE_COPROC (FPU_MVE
),
2008 0xfe010f60, 0xff811f70,
2009 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2010 /* Vector VPT T6. */
2011 {ARM_FEATURE_COPROC (FPU_MVE
),
2013 0xfe011f40, 0xff811f50,
2014 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2016 /* Vector VBIC immediate. */
2017 {ARM_FEATURE_COPROC (FPU_MVE
),
2019 0xef800070, 0xefb81070,
2020 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2022 /* Vector VBIC register. */
2023 {ARM_FEATURE_COPROC (FPU_MVE
),
2025 0xef100150, 0xffb11f51,
2026 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2028 /* Vector VADDLV. */
2029 {ARM_FEATURE_COPROC (FPU_MVE
),
2031 0xee890f00, 0xef8f1fd1,
2032 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2035 {ARM_FEATURE_COPROC (FPU_MVE
),
2037 0xeef10f00, 0xeff31fd1,
2038 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2040 /* Vector VCMP floating point T1. */
2041 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2043 0xee310f00, 0xeff1ef50,
2044 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2046 /* Vector VCMP floating point T2. */
2047 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2049 0xee310f40, 0xeff1ef50,
2050 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2052 /* Vector VCMP T1. */
2053 {ARM_FEATURE_COPROC (FPU_MVE
),
2055 0xfe010f00, 0xffc1ff51,
2056 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2057 /* Vector VCMP T2. */
2058 {ARM_FEATURE_COPROC (FPU_MVE
),
2060 0xfe010f01, 0xffc1ff51,
2061 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2062 /* Vector VCMP T3. */
2063 {ARM_FEATURE_COPROC (FPU_MVE
),
2065 0xfe011f00, 0xffc1ff50,
2066 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2067 /* Vector VCMP T4. */
2068 {ARM_FEATURE_COPROC (FPU_MVE
),
2070 0xfe010f40, 0xffc1ff70,
2071 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2072 /* Vector VCMP T5. */
2073 {ARM_FEATURE_COPROC (FPU_MVE
),
2075 0xfe010f60, 0xffc1ff70,
2076 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2077 /* Vector VCMP T6. */
2078 {ARM_FEATURE_COPROC (FPU_MVE
),
2080 0xfe011f40, 0xffc1ff50,
2081 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2084 {ARM_FEATURE_COPROC (FPU_MVE
),
2086 0xeea00b10, 0xffb10f5f,
2087 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2090 {ARM_FEATURE_COPROC (FPU_MVE
),
2092 0xff000150, 0xffd11f51,
2093 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2095 /* Vector VFMA, vector * scalar. */
2096 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2098 0xee310e40, 0xefb11f70,
2099 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2101 /* Vector VFMA floating point. */
2102 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2104 0xef000c50, 0xffa11f51,
2105 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2107 /* Vector VFMS floating point. */
2108 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2110 0xef200c50, 0xffa11f51,
2111 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2113 /* Vector VFMAS, vector * scalar. */
2114 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2115 MVE_VFMAS_FP_SCALAR
,
2116 0xee311e40, 0xefb11f70,
2117 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2119 /* Vector VHADD T1. */
2120 {ARM_FEATURE_COPROC (FPU_MVE
),
2122 0xef000040, 0xef811f51,
2123 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2125 /* Vector VHADD T2. */
2126 {ARM_FEATURE_COPROC (FPU_MVE
),
2128 0xee000f40, 0xef811f70,
2129 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2131 /* Vector VHSUB T1. */
2132 {ARM_FEATURE_COPROC (FPU_MVE
),
2134 0xef000240, 0xef811f51,
2135 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2137 /* Vector VHSUB T2. */
2138 {ARM_FEATURE_COPROC (FPU_MVE
),
2140 0xee001f40, 0xef811f70,
2141 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2144 {ARM_FEATURE_COPROC (FPU_MVE
),
2146 0xeea00b10, 0xffb10f5f,
2147 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2149 /* Vector VRHADD. */
2150 {ARM_FEATURE_COPROC (FPU_MVE
),
2152 0xef000140, 0xef811f51,
2153 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2156 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2157 MVE_VCVT_FP_FIX_VEC
,
2158 0xef800c50, 0xef801cd1,
2159 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2162 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2163 MVE_VCVT_BETWEEN_FP_INT
,
2164 0xffb30640, 0xffb31e51,
2165 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2167 /* Vector VCVT between single and half-precision float, bottom half. */
2168 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2169 MVE_VCVT_FP_HALF_FP
,
2170 0xee3f0e01, 0xefbf1fd1,
2171 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2173 /* Vector VCVT between single and half-precision float, top half. */
2174 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2175 MVE_VCVT_FP_HALF_FP
,
2176 0xee3f1e01, 0xefbf1fd1,
2177 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2180 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2181 MVE_VCVT_FROM_FP_TO_INT
,
2182 0xffb30040, 0xffb31c51,
2183 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2186 {ARM_FEATURE_COPROC (FPU_MVE
),
2188 0xfc901e00, 0xff901e5f,
2189 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2192 {ARM_FEATURE_COPROC (FPU_MVE
),
2194 0xfc901e01, 0xff901e1f,
2195 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2197 /* Vector VLDRB gather load. */
2198 {ARM_FEATURE_COPROC (FPU_MVE
),
2199 MVE_VLDRB_GATHER_T1
,
2200 0xec900e00, 0xefb01e50,
2201 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2203 /* Vector VLDRH gather load. */
2204 {ARM_FEATURE_COPROC (FPU_MVE
),
2205 MVE_VLDRH_GATHER_T2
,
2206 0xec900e10, 0xefb01e50,
2207 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2209 /* Vector VLDRW gather load. */
2210 {ARM_FEATURE_COPROC (FPU_MVE
),
2211 MVE_VLDRW_GATHER_T3
,
2212 0xfc900f40, 0xffb01fd0,
2213 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2215 /* Vector VLDRD gather load. */
2216 {ARM_FEATURE_COPROC (FPU_MVE
),
2217 MVE_VLDRD_GATHER_T4
,
2218 0xec900fd0, 0xefb01fd0,
2219 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2221 /* Vector VLDRW gather load. */
2222 {ARM_FEATURE_COPROC (FPU_MVE
),
2223 MVE_VLDRW_GATHER_T5
,
2224 0xfd101e00, 0xff111f00,
2225 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2227 /* Vector VLDRD gather load, variant T6. */
2228 {ARM_FEATURE_COPROC (FPU_MVE
),
2229 MVE_VLDRD_GATHER_T6
,
2230 0xfd101f00, 0xff111f00,
2231 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2234 {ARM_FEATURE_COPROC (FPU_MVE
),
2236 0xec100e00, 0xee581e00,
2237 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2240 {ARM_FEATURE_COPROC (FPU_MVE
),
2242 0xec180e00, 0xee581e00,
2243 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2245 /* Vector VLDRB unsigned, variant T5. */
2246 {ARM_FEATURE_COPROC (FPU_MVE
),
2248 0xec101e00, 0xfe101f80,
2249 "vldrb%v.u8\t%13-15,22Q, %d"},
2251 /* Vector VLDRH unsigned, variant T6. */
2252 {ARM_FEATURE_COPROC (FPU_MVE
),
2254 0xec101e80, 0xfe101f80,
2255 "vldrh%v.u16\t%13-15,22Q, %d"},
2257 /* Vector VLDRW unsigned, variant T7. */
2258 {ARM_FEATURE_COPROC (FPU_MVE
),
2260 0xec101f00, 0xfe101f80,
2261 "vldrw%v.u32\t%13-15,22Q, %d"},
2263 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2265 {ARM_FEATURE_COPROC (FPU_MVE
),
2267 0xee801e00, 0xef801f51,
2268 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2270 {ARM_FEATURE_COPROC (FPU_MVE
),
2272 0xee800e00, 0xef801f51,
2273 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2275 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2276 {ARM_FEATURE_COPROC (FPU_MVE
),
2278 0xeef00e00, 0xeff01f51,
2279 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2281 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2282 {ARM_FEATURE_COPROC (FPU_MVE
),
2284 0xeef00f00, 0xeff11f51,
2285 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2287 /* Vector VMLADAV T1 variant. */
2288 {ARM_FEATURE_COPROC (FPU_MVE
),
2290 0xeef01e00, 0xeff01f51,
2291 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2293 /* Vector VMLADAV T2 variant. */
2294 {ARM_FEATURE_COPROC (FPU_MVE
),
2296 0xeef01f00, 0xeff11f51,
2297 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2300 {ARM_FEATURE_COPROC (FPU_MVE
),
2302 0xee011e40, 0xef811f70,
2303 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2305 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2307 {ARM_FEATURE_COPROC (FPU_MVE
),
2309 0xfe800e01, 0xff810f51,
2310 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2312 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2314 {ARM_FEATURE_COPROC (FPU_MVE
),
2316 0xee800e01, 0xff800f51,
2317 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2319 /* Vector VMLSDAV T1 Variant. */
2320 {ARM_FEATURE_COPROC (FPU_MVE
),
2322 0xeef00e01, 0xfff00f51,
2323 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2325 /* Vector VMLSDAV T2 Variant. */
2326 {ARM_FEATURE_COPROC (FPU_MVE
),
2328 0xfef00e01, 0xfff10f51,
2329 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2331 /* Vector VMOV between gpr and half precision register, op == 0. */
2332 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2334 0xee000910, 0xfff00f7f,
2335 "vmov.f16\t%7,16-19F, %12-15r"},
2337 /* Vector VMOV between gpr and half precision register, op == 1. */
2338 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2340 0xee100910, 0xfff00f7f,
2341 "vmov.f16\t%12-15r, %7,16-19F"},
2343 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2344 MVE_VMOV_GP_TO_VEC_LANE
,
2345 0xee000b10, 0xff900f1f,
2346 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2348 /* Vector VORR immediate to vector.
2349 NOTE: MVE_VORR_IMM must appear in the table
2350 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2351 {ARM_FEATURE_COPROC (FPU_MVE
),
2353 0xef800050, 0xefb810f0,
2354 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2356 /* Vector VMOV immediate to vector,
2357 cmode == 11x1 -> VMVN which is UNDEFINED
2358 for such a cmode. */
2359 {ARM_FEATURE_COPROC (FPU_MVE
),
2360 MVE_VMVN_IMM
, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION
},
2362 /* Vector VMOV immediate to vector. */
2363 {ARM_FEATURE_COPROC (FPU_MVE
),
2364 MVE_VMOV_IMM_TO_VEC
,
2365 0xef800050, 0xefb810d0,
2366 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2368 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2369 {ARM_FEATURE_COPROC (FPU_MVE
),
2370 MVE_VMOV2_VEC_LANE_TO_GP
,
2371 0xec000f00, 0xffb01ff0,
2372 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2374 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2375 {ARM_FEATURE_COPROC (FPU_MVE
),
2376 MVE_VMOV2_VEC_LANE_TO_GP
,
2377 0xec000f10, 0xffb01ff0,
2378 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2380 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2381 {ARM_FEATURE_COPROC (FPU_MVE
),
2382 MVE_VMOV2_GP_TO_VEC_LANE
,
2383 0xec100f00, 0xffb01ff0,
2384 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2386 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2387 {ARM_FEATURE_COPROC (FPU_MVE
),
2388 MVE_VMOV2_GP_TO_VEC_LANE
,
2389 0xec100f10, 0xffb01ff0,
2390 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2392 /* Vector VMOV Vector lane to gpr. */
2393 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2394 MVE_VMOV_VEC_LANE_TO_GP
,
2395 0xee100b10, 0xff100f1f,
2396 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2398 /* Vector VMOVL long. */
2399 {ARM_FEATURE_COPROC (FPU_MVE
),
2401 0xeea00f40, 0xefa70fd1,
2402 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2404 /* Vector VMOV and narrow. */
2405 {ARM_FEATURE_COPROC (FPU_MVE
),
2407 0xfe310e81, 0xffb30fd1,
2408 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2410 /* Floating point move extract. */
2411 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2413 0xfeb00a40, 0xffbf0fd0,
2414 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2416 /* Vector VMULL integer. */
2417 {ARM_FEATURE_COPROC (FPU_MVE
),
2419 0xee010e00, 0xef810f51,
2420 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2422 /* Vector VMULL polynomial. */
2423 {ARM_FEATURE_COPROC (FPU_MVE
),
2425 0xee310e00, 0xefb10f51,
2426 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2428 /* Vector VMVN immediate to vector. */
2429 {ARM_FEATURE_COPROC (FPU_MVE
),
2431 0xef800070, 0xefb810f0,
2432 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2434 /* Vector VMVN register. */
2435 {ARM_FEATURE_COPROC (FPU_MVE
),
2437 0xffb005c0, 0xffbf1fd1,
2438 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2440 /* Vector VORN, vector bitwise or not. */
2441 {ARM_FEATURE_COPROC (FPU_MVE
),
2443 0xef300150, 0xffb11f51,
2444 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2446 /* Vector VORR register. */
2447 {ARM_FEATURE_COPROC (FPU_MVE
),
2449 0xef200150, 0xffb11f51,
2450 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2452 /* Vector VQDMULL T1 variant. */
2453 {ARM_FEATURE_COPROC (FPU_MVE
),
2455 0xee300f01, 0xefb10f51,
2456 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2458 /* Vector VQDMULL T2 variant. */
2459 {ARM_FEATURE_COPROC (FPU_MVE
),
2461 0xee300f60, 0xefb10f70,
2462 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2464 /* Vector VQMOVN. */
2465 {ARM_FEATURE_COPROC (FPU_MVE
),
2467 0xee330e01, 0xefb30fd1,
2468 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
2470 /* Vector VQMOVUN. */
2471 {ARM_FEATURE_COPROC (FPU_MVE
),
2473 0xee310e81, 0xffb30fd1,
2474 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2476 /* Vector VQDMLADH. */
2477 {ARM_FEATURE_COPROC (FPU_MVE
),
2479 0xee000e00, 0xff810f51,
2480 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2482 /* Vector VQRDMLADH. */
2483 {ARM_FEATURE_COPROC (FPU_MVE
),
2485 0xee000e01, 0xff810f51,
2486 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2488 /* Vector VQDMLAH. */
2489 {ARM_FEATURE_COPROC (FPU_MVE
),
2491 0xee000e60, 0xef811f70,
2492 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2494 /* Vector VQRDMLAH. */
2495 {ARM_FEATURE_COPROC (FPU_MVE
),
2497 0xee000e40, 0xef811f70,
2498 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2500 /* Vector VQDMLASH. */
2501 {ARM_FEATURE_COPROC (FPU_MVE
),
2503 0xee001e60, 0xef811f70,
2504 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2506 /* Vector VQRDMLASH. */
2507 {ARM_FEATURE_COPROC (FPU_MVE
),
2509 0xee001e40, 0xef811f70,
2510 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2512 /* Vector VQDMLSDH. */
2513 {ARM_FEATURE_COPROC (FPU_MVE
),
2515 0xfe000e00, 0xff810f51,
2516 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2518 /* Vector VQRDMLSDH. */
2519 {ARM_FEATURE_COPROC (FPU_MVE
),
2521 0xfe000e01, 0xff810f51,
2522 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2524 /* Vector VQDMULH T1 variant. */
2525 {ARM_FEATURE_COPROC (FPU_MVE
),
2527 0xef000b40, 0xff811f51,
2528 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2530 /* Vector VQRDMULH T2 variant. */
2531 {ARM_FEATURE_COPROC (FPU_MVE
),
2533 0xff000b40, 0xff811f51,
2534 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2536 /* Vector VQDMULH T3 variant. */
2537 {ARM_FEATURE_COPROC (FPU_MVE
),
2539 0xee010e60, 0xff811f70,
2540 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2542 /* Vector VQRDMULH T4 variant. */
2543 {ARM_FEATURE_COPROC (FPU_MVE
),
2545 0xfe010e60, 0xff811f70,
2546 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2548 /* Vector VRINT floating point. */
2549 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2551 0xffb20440, 0xffb31c51,
2552 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2554 /* Vector VRMLALDAVH. */
2555 {ARM_FEATURE_COPROC (FPU_MVE
),
2557 0xee800f00, 0xef811f51,
2558 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2560 /* Vector VRMLALDAVH. */
2561 {ARM_FEATURE_COPROC (FPU_MVE
),
2563 0xee801f00, 0xef811f51,
2564 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2566 /* Vector VST2 no writeback. */
2567 {ARM_FEATURE_COPROC (FPU_MVE
),
2569 0xfc801e00, 0xffb01e5f,
2570 "vst2%5d.%7-8s\t%B, [%16-19r]"},
2572 /* Vector VST2 writeback. */
2573 {ARM_FEATURE_COPROC (FPU_MVE
),
2575 0xfca01e00, 0xffb01e5f,
2576 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
2578 /* Vector VST4 no writeback. */
2579 {ARM_FEATURE_COPROC (FPU_MVE
),
2581 0xfc801e01, 0xffb01e1f,
2582 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
2584 /* Vector VST4 writeback. */
2585 {ARM_FEATURE_COPROC (FPU_MVE
),
2587 0xfca01e01, 0xffb01e1f,
2588 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
2590 /* Vector VSTRB scatter store, T1 variant. */
2591 {ARM_FEATURE_COPROC (FPU_MVE
),
2592 MVE_VSTRB_SCATTER_T1
,
2593 0xec800e00, 0xffb01e50,
2594 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2596 /* Vector VSTRH scatter store, T2 variant. */
2597 {ARM_FEATURE_COPROC (FPU_MVE
),
2598 MVE_VSTRH_SCATTER_T2
,
2599 0xec800e10, 0xffb01e50,
2600 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2602 /* Vector VSTRW scatter store, T3 variant. */
2603 {ARM_FEATURE_COPROC (FPU_MVE
),
2604 MVE_VSTRW_SCATTER_T3
,
2605 0xec800e40, 0xffb01e50,
2606 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2608 /* Vector VSTRD scatter store, T4 variant. */
2609 {ARM_FEATURE_COPROC (FPU_MVE
),
2610 MVE_VSTRD_SCATTER_T4
,
2611 0xec800fd0, 0xffb01fd0,
2612 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2614 /* Vector VSTRW scatter store, T5 variant. */
2615 {ARM_FEATURE_COPROC (FPU_MVE
),
2616 MVE_VSTRW_SCATTER_T5
,
2617 0xfd001e00, 0xff111f00,
2618 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2620 /* Vector VSTRD scatter store, T6 variant. */
2621 {ARM_FEATURE_COPROC (FPU_MVE
),
2622 MVE_VSTRD_SCATTER_T6
,
2623 0xfd001f00, 0xff111f00,
2624 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2627 {ARM_FEATURE_COPROC (FPU_MVE
),
2629 0xec000e00, 0xfe581e00,
2630 "vstrb%v.%7-8s\t%13-15Q, %d"},
2633 {ARM_FEATURE_COPROC (FPU_MVE
),
2635 0xec080e00, 0xfe581e00,
2636 "vstrh%v.%7-8s\t%13-15Q, %d"},
2638 /* Vector VSTRB variant T5. */
2639 {ARM_FEATURE_COPROC (FPU_MVE
),
2641 0xec001e00, 0xfe101f80,
2642 "vstrb%v.8\t%13-15,22Q, %d"},
2644 /* Vector VSTRH variant T6. */
2645 {ARM_FEATURE_COPROC (FPU_MVE
),
2647 0xec001e80, 0xfe101f80,
2648 "vstrh%v.16\t%13-15,22Q, %d"},
2650 /* Vector VSTRW variant T7. */
2651 {ARM_FEATURE_COPROC (FPU_MVE
),
2653 0xec001f00, 0xfe101f80,
2654 "vstrw%v.32\t%13-15,22Q, %d"},
2656 {ARM_FEATURE_CORE_LOW (0),
2658 0x00000000, 0x00000000, 0}
2661 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
2662 ordered: they must be searched linearly from the top to obtain a correct
2665 /* print_insn_arm recognizes the following format control codes:
2669 %a print address for ldr/str instruction
2670 %s print address for ldr/str halfword/signextend instruction
2671 %S like %s but allow UNPREDICTABLE addressing
2672 %b print branch destination
2673 %c print condition code (always bits 28-31)
2674 %m print register mask for ldm/stm instruction
2675 %o print operand2 (immediate or register + shift)
2676 %p print 'p' iff bits 12-15 are 15
2677 %t print 't' iff bit 21 set and bit 24 clear
2678 %B print arm BLX(1) destination
2679 %C print the PSR sub type.
2680 %U print barrier type.
2681 %P print address for pli instruction.
2683 %<bitfield>r print as an ARM register
2684 %<bitfield>T print as an ARM register + 1
2685 %<bitfield>R as %r but r15 is UNPREDICTABLE
2686 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
2687 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
2688 %<bitfield>d print the bitfield in decimal
2689 %<bitfield>W print the bitfield plus one in decimal
2690 %<bitfield>x print the bitfield in hex
2691 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
2693 %<bitfield>'c print specified char iff bitfield is all ones
2694 %<bitfield>`c print specified char iff bitfield is all zeroes
2695 %<bitfield>?ab... select from array of values in big endian order
2697 %e print arm SMI operand (bits 0..7,8..19).
2698 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
2699 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
2700 %R print the SPSR/CPSR or banked register of an MRS. */
2702 static const struct opcode32 arm_opcodes
[] =
2704 /* ARM instructions. */
2705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2706 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
2707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2708 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
2710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
2711 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
2712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2713 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
2714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
2715 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
2717 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
2718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2719 0x00800090, 0x0fa000f0,
2720 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
2722 0x00a00090, 0x0fa000f0,
2723 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2725 /* V8.2 RAS extension instructions. */
2726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
2727 0xe320f010, 0xffffffff, "esb"},
2729 /* V8 instructions. */
2730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2731 0x0320f005, 0x0fffffff, "sevl"},
2732 /* Defined in V8 but is in NOP space so available to all arch. */
2733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2734 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
2735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
2736 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
2737 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2738 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2739 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2740 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
2741 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2742 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
2743 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2744 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
2745 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2746 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2747 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2748 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
2749 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2750 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2751 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2752 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
2753 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2754 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
2755 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2756 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
2757 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2758 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2759 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2760 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
2761 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
2762 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2763 /* CRC32 instructions. */
2764 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2765 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
2766 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2767 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
2768 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2769 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
2770 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2771 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
2772 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2773 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
2774 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2775 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
2777 /* Privileged Access Never extension instructions. */
2778 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
2779 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
2781 /* Virtualization Extension instructions. */
2782 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
2785 /* Integer Divide Extension instructions. */
2786 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2787 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
2788 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
2789 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
2791 /* MP Extension instructions. */
2792 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
2794 /* Speculation Barriers. */
2795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
2796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
2797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
2799 /* V7 instructions. */
2800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
2801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
2802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
2803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
2804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
2805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
2806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
2807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
2808 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
2810 /* ARM V6T2 instructions. */
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2812 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2814 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
2815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2816 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2818 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2821 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2823 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
2825 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2826 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
2827 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2828 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2830 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
2831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2832 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
2834 /* ARM Security extension instructions. */
2835 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
2836 0x01600070, 0x0ff000f0, "smc%c\t%e"},
2838 /* ARM V6K instructions. */
2839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2840 0xf57ff01f, 0xffffffff, "clrex"},
2841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2842 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2844 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2846 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2848 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2850 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
2851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2852 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
2854 /* ARMv8.5-A instructions. */
2855 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
2857 /* ARM V6K NOP hints. */
2858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2859 0x0320f001, 0x0fffffff, "yield%c"},
2860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2861 0x0320f002, 0x0fffffff, "wfe%c"},
2862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2863 0x0320f003, 0x0fffffff, "wfi%c"},
2864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2865 0x0320f004, 0x0fffffff, "sev%c"},
2866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
2867 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
2869 /* ARM V6 instructions. */
2870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2871 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
2872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2873 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
2874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2875 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
2876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2877 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
2878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2879 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
2880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2881 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
2882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2883 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
2884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2885 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
2886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2887 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
2888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2889 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
2890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2891 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
2892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2893 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
2894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2895 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
2896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2897 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
2898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2899 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
2900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2901 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
2902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2903 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
2904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2905 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
2906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2907 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
2908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2909 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
2910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2911 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
2912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2913 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
2914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2915 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
2916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2917 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
2918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2919 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
2920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2921 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
2922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2923 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
2924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2925 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
2926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2927 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
2928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2929 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
2930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2931 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
2932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2933 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
2934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2935 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
2936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2937 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
2938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2939 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
2940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2941 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2943 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2945 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2947 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2949 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2951 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2953 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2955 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2957 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2959 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2961 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2963 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2965 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2967 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2969 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2971 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2973 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2975 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2977 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2979 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2981 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2983 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2985 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2987 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2989 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2991 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2993 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2995 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2997 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2999 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3001 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3003 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3005 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3007 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3009 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3011 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3013 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3015 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3017 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3019 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3021 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3023 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3025 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3027 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3029 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3031 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3033 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3035 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3037 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3039 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3041 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3043 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3045 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3047 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3049 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3051 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3053 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3055 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3057 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3059 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3061 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3063 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3065 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3067 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3069 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3071 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3073 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3075 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3077 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3079 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3081 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3083 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3085 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3087 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3089 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3091 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3093 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3095 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3097 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3099 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3101 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3103 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3105 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3107 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3109 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3111 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3113 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3115 /* V5J instruction. */
3116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
3117 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3119 /* V5 Instructions. */
3120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3121 0xe1200070, 0xfff000f0,
3122 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3124 0xfa000000, 0xfe000000, "blx\t%B"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3126 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3127 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3128 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3130 /* V5E "El Segundo" Instructions. */
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3132 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3134 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3136 0xf450f000, 0xfc70f000, "pld\t%a"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3138 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3140 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3142 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3144 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3147 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3149 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3152 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3154 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3156 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3158 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3161 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3163 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3165 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3167 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3170 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3172 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3175 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3177 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3179 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3181 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3183 /* ARM Instructions. */
3184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3185 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3188 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3190 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3192 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3194 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3196 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3198 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3201 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3203 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3205 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3207 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3210 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3212 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3214 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
3215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3216 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3219 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3221 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3223 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3225 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3226 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3228 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3230 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3233 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3235 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3237 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3240 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3242 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3244 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3246 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3247 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3248 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3249 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3250 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3251 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3254 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3256 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3258 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3261 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3263 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3265 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3268 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3270 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3272 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3274 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
3275 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3277 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
3279 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3282 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3284 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3286 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3288 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3289 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
3290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3291 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
3292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3293 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
3295 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3296 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3298 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3300 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3302 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3303 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3305 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3307 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3310 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3312 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3314 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3316 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3317 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3319 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3321 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3323 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3324 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3325 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3327 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3329 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3332 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3334 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3336 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3338 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3339 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3341 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3343 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3346 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
3347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3348 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3351 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3354 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3356 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3359 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3361 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3363 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3365 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3367 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3369 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3371 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3373 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3375 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3377 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3379 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3381 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3383 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3385 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3387 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3389 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
3390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3391 0x092d0000, 0x0fff0000, "push%c\t%m"},
3392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3393 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3395 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3398 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3400 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3402 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3404 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3406 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3407 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3408 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3409 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3410 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3412 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3414 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3416 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3418 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3420 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3421 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3422 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3424 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3425 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3426 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3428 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
3429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3430 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3432 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3434 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3437 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3439 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3443 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
3444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3445 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3446 {ARM_FEATURE_CORE_LOW (0),
3447 0x00000000, 0x00000000, 0}
3450 /* print_insn_thumb16 recognizes the following format control codes:
3452 %S print Thumb register (bits 3..5 as high number if bit 6 set)
3453 %D print Thumb register (bits 0..2 as high number if bit 7 set)
3454 %<bitfield>I print bitfield as a signed decimal
3455 (top bit of range being the sign bit)
3456 %N print Thumb register mask (with LR)
3457 %O print Thumb register mask (with PC)
3458 %M print Thumb register mask
3459 %b print CZB's 6-bit unsigned branch destination
3460 %s print Thumb right-shift immediate (6..10; 0 == 32).
3461 %c print the condition code
3462 %C print the condition code, or "s" if not conditional
3463 %x print warning if conditional an not at end of IT block"
3464 %X print "\t; unpredictable <IT:code>" if conditional
3465 %I print IT instruction suffix and operands
3466 %W print Thumb Writeback indicator for LDMIA
3467 %<bitfield>r print bitfield as an ARM register
3468 %<bitfield>d print bitfield as a decimal
3469 %<bitfield>H print (bitfield * 2) as a decimal
3470 %<bitfield>W print (bitfield * 4) as a decimal
3471 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3472 %<bitfield>B print Thumb branch destination (signed displacement)
3473 %<bitfield>c print bitfield as a condition code
3474 %<bitnum>'c print specified char iff bit is one
3475 %<bitnum>?ab print a if bit is one else print b. */
3477 static const struct opcode16 thumb_opcodes
[] =
3479 /* Thumb instructions. */
3481 /* ARMv8-M Security Extensions instructions. */
3482 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
3483 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
3485 /* ARM V8 instructions. */
3486 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
3487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
3488 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
3490 /* ARM V6K no-argument instructions. */
3491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
3492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
3493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
3494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
3495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
3496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3498 /* ARM V6T2 instructions. */
3499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3500 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3501 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3502 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3503 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
3506 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3511 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
3513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3514 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3516 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3518 /* ARM V5 ISA extends Thumb. */
3519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3520 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3521 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3522 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
3523 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3524 /* ARM V4T ISA (Thumb v1). */
3525 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3526 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3529 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3530 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3532 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3534 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3535 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3538 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
3549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
3553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
3554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
3556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3557 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3559 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3560 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3561 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3562 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3563 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3566 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3568 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3570 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3573 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3575 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3578 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3579 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3588 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3591 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3594 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3596 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3598 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3600 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3603 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3605 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3608 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3610 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3613 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3615 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
3623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
3624 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3628 /* The E800 .. FFFF range is unconditionally redirected to the
3629 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3630 are processed via that table. Thus, we can never encounter a
3631 bare "second half of BL/BLX(1)" instruction here. */
3632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
3633 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3636 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
3637 We adopt the convention that hw1 is the high 16 bits of .value and
3638 .mask, hw2 the low 16 bits.
3640 print_insn_thumb32 recognizes the following format control codes:
3644 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3645 %M print a modified 12-bit immediate (same location)
3646 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3647 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3648 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
3649 %S print a possibly-shifted Rm
3651 %L print address for a ldrd/strd instruction
3652 %a print the address of a plain load/store
3653 %w print the width and signedness of a core load/store
3654 %m print register mask for ldm/stm
3655 %n print register mask for clrm
3657 %E print the lsb and width fields of a bfc/bfi instruction
3658 %F print the lsb and width fields of a sbfx/ubfx instruction
3659 %G print a fallback offset for Branch Future instructions
3660 %W print an offset for BF instruction
3661 %Y print an offset for BFL instruction
3662 %Z print an offset for BFCSEL instruction
3663 %Q print an offset for Low Overhead Loop instructions
3664 %P print an offset for Low Overhead Loop end instructions
3665 %b print a conditional branch offset
3666 %B print an unconditional branch offset
3667 %s print the shift field of an SSAT instruction
3668 %R print the rotation field of an SXT instruction
3669 %U print barrier type.
3670 %P print address for pli instruction.
3671 %c print the condition code
3672 %x print warning if conditional an not at end of IT block"
3673 %X print "\t; unpredictable <IT:code>" if conditional
3675 %<bitfield>d print bitfield in decimal
3676 %<bitfield>D print bitfield plus one in decimal
3677 %<bitfield>W print bitfield*4 in decimal
3678 %<bitfield>r print bitfield as an ARM register
3679 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
3680 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
3681 %<bitfield>c print bitfield as a condition code
3683 %<bitfield>'c print specified char iff bitfield is all ones
3684 %<bitfield>`c print specified char iff bitfield is all zeroes
3685 %<bitfield>?ab... select from array of values in big endian order
3687 With one exception at the bottom (done because BL and BLX(1) need
3688 to come dead last), this table was machine-sorted first in
3689 decreasing order of number of bits set in the mask, then in
3690 increasing numeric order of mask, then in increasing numeric order
3691 of opcode. This order is not the clearest for a human reader, but
3692 is guaranteed never to catch a special-case bit pattern with a more
3693 general mask, which is important, because this instruction encoding
3694 makes heavy use of special-case bit patterns. */
3695 static const struct opcode32 thumb32_opcodes
[] =
3697 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
3699 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3700 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
3701 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3702 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
3703 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3704 0xf02fc001, 0xfffff001, "le\t%P"},
3705 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3706 0xf00fc001, 0xfffff001, "le\tlr, %P"},
3708 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3709 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
3710 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3711 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
3712 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3713 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
3714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3715 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
3716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3717 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
3719 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3720 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
3722 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
3723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
3724 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3725 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
3726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3727 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
3728 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3729 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
3730 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
3731 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
3733 /* ARM V8.2 RAS extension instructions. */
3734 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3735 0xf3af8010, 0xffffffff, "esb"},
3737 /* V8 instructions. */
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3739 0xf3af8005, 0xffffffff, "sevl%c.w"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3741 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3743 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3745 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3747 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3749 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3751 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3753 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3755 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3757 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3759 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3761 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3763 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3765 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3767 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3769 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
3771 /* CRC32 instructions. */
3772 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3773 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
3774 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3775 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
3776 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3777 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
3778 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3779 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
3780 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3781 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
3782 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3783 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
3785 /* Speculation Barriers. */
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
3787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
3790 /* V7 instructions. */
3791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
3795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3799 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
3801 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3803 /* Virtualization Extension instructions. */
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3805 /* We skip ERET as that is SUBS pc, lr, #0. */
3807 /* MP Extension instructions. */
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
3810 /* Security extension instructions. */
3811 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3813 /* ARMv8.5-A instructions. */
3814 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
3816 /* Instructions defined in the basic V6T2 set. */
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3823 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
3826 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3827 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3829 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3831 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3833 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3835 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3837 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3839 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3841 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3843 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3845 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3847 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3849 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3851 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3853 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3854 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3855 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3856 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3857 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3859 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3861 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3863 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3865 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3867 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3869 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3871 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3873 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3874 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3875 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3877 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3879 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3881 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3883 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3885 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3887 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3889 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3891 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3893 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3895 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3897 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3899 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3901 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3903 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3905 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3907 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3909 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3911 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3913 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3915 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3917 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3919 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3921 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3923 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3925 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3927 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3929 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3931 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3933 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3935 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3937 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3939 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3941 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3943 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3945 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3947 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3949 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3951 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3953 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3955 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3957 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3959 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3961 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3963 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3965 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3967 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3969 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3971 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3973 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3975 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3977 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3979 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3981 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3982 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3983 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3985 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3987 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3989 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3991 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3993 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3995 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3997 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3999 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4001 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4003 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4005 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4007 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4009 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4011 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4013 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4015 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4017 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4019 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4021 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4023 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4025 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4027 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4029 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4031 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4033 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4035 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4037 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4039 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4041 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4043 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4045 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4047 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4049 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4051 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4053 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4055 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4057 0xf810f000, 0xff70f000, "pld%c\t%a"},
4058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4059 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4061 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4063 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4065 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4067 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4069 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4071 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4073 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4075 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4077 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4079 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4081 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4083 0xfb100000, 0xfff000c0,
4084 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4086 0xfbc00080, 0xfff000c0,
4087 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4089 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4091 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4093 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4095 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4097 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4098 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4099 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4101 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4102 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4103 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4105 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4107 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4109 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4111 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4113 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4115 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4117 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4119 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4121 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4123 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4124 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4125 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4127 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4129 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4131 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4133 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4135 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4137 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4139 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4141 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4143 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4145 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4147 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4149 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4151 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4153 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4155 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4157 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4159 0xe9400000, 0xff500000,
4160 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4162 0xe9500000, 0xff500000,
4163 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
4164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4165 0xe8600000, 0xff700000,
4166 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4168 0xe8700000, 0xff700000,
4169 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4171 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4173 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
4175 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4177 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
4178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4179 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
4180 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4181 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
4182 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4183 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
4185 /* These have been 32-bit since the invention of Thumb. */
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4187 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4189 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4193 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4194 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4197 static const char *const arm_conditional
[] =
4198 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
4199 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
4201 static const char *const arm_fp_const
[] =
4202 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
4204 static const char *const arm_shift
[] =
4205 {"lsl", "lsr", "asr", "ror"};
4210 const char *description
;
4211 const char *reg_names
[16];
4215 static const arm_regname regnames
[] =
4217 { "reg-names-raw", N_("Select raw register names"),
4218 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
4219 { "reg-names-gcc", N_("Select register names used by GCC"),
4220 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
4221 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
4222 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
4223 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
4224 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
4225 { "reg-names-apcs", N_("Select register names used in the APCS"),
4226 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
4227 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
4228 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
4229 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
4230 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
4233 static const char *const iwmmxt_wwnames
[] =
4234 {"b", "h", "w", "d"};
4236 static const char *const iwmmxt_wwssnames
[] =
4237 {"b", "bus", "bc", "bss",
4238 "h", "hus", "hc", "hss",
4239 "w", "wus", "wc", "wss",
4240 "d", "dus", "dc", "dss"
4243 static const char *const iwmmxt_regnames
[] =
4244 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
4245 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
4248 static const char *const iwmmxt_cregnames
[] =
4249 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
4250 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
4253 static const char *const vec_condnames
[] =
4254 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
4257 static const char *const mve_predicatenames
[] =
4258 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
4259 "eee", "ee", "eet", "e", "ett", "et", "ete"
4262 /* Names for 2-bit size field for mve vector isntructions. */
4263 static const char *const mve_vec_sizename
[] =
4264 { "8", "16", "32", "64"};
4266 /* Indicates whether we are processing a then predicate,
4267 else predicate or none at all. */
4275 /* Information used to process a vpt block and subsequent instructions. */
4278 /* Are we in a vpt block. */
4279 bfd_boolean in_vpt_block
;
4281 /* Next predicate state if in vpt block. */
4282 enum vpt_pred_state next_pred_state
;
4284 /* Mask from vpt/vpst instruction. */
4285 long predicate_mask
;
4287 /* Instruction number in vpt block. */
4288 long current_insn_num
;
4290 /* Number of instructions in vpt block.. */
4294 static struct vpt_block vpt_block_state
=
4303 /* Default to GCC register name set. */
4304 static unsigned int regname_selected
= 1;
4306 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
4307 #define arm_regnames regnames[regname_selected].reg_names
4309 static bfd_boolean force_thumb
= FALSE
;
4311 /* Current IT instruction state. This contains the same state as the IT
4312 bits in the CPSR. */
4313 static unsigned int ifthen_state
;
4314 /* IT state for the next instruction. */
4315 static unsigned int ifthen_next_state
;
4316 /* The address of the insn for which the IT state is valid. */
4317 static bfd_vma ifthen_address
;
4318 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
4319 /* Indicates that the current Conditional state is unconditional or outside
4321 #define COND_UNCOND 16
4325 /* Extract the predicate mask for a VPT or VPST instruction.
4326 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
4329 mve_extract_pred_mask (long given
)
4331 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
4334 /* Return the number of instructions in a MVE predicate block. */
4336 num_instructions_vpt_block (long given
)
4338 long mask
= mve_extract_pred_mask (given
);
4345 if ((mask
& 7) == 4)
4348 if ((mask
& 3) == 2)
4351 if ((mask
& 1) == 1)
4358 mark_outside_vpt_block (void)
4360 vpt_block_state
.in_vpt_block
= FALSE
;
4361 vpt_block_state
.next_pred_state
= PRED_NONE
;
4362 vpt_block_state
.predicate_mask
= 0;
4363 vpt_block_state
.current_insn_num
= 0;
4364 vpt_block_state
.num_pred_insn
= 0;
4368 mark_inside_vpt_block (long given
)
4370 vpt_block_state
.in_vpt_block
= TRUE
;
4371 vpt_block_state
.next_pred_state
= PRED_THEN
;
4372 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
4373 vpt_block_state
.current_insn_num
= 0;
4374 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
4375 assert (vpt_block_state
.num_pred_insn
>= 1);
4378 static enum vpt_pred_state
4379 invert_next_predicate_state (enum vpt_pred_state astate
)
4381 if (astate
== PRED_THEN
)
4383 else if (astate
== PRED_ELSE
)
4389 static enum vpt_pred_state
4390 update_next_predicate_state (void)
4392 long pred_mask
= vpt_block_state
.predicate_mask
;
4393 long mask_for_insn
= 0;
4395 switch (vpt_block_state
.current_insn_num
)
4413 if (pred_mask
& mask_for_insn
)
4414 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
4416 return vpt_block_state
.next_pred_state
;
4420 update_vpt_block_state (void)
4422 vpt_block_state
.current_insn_num
++;
4423 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
4425 /* No more instructions to process in vpt block. */
4426 mark_outside_vpt_block ();
4430 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
4433 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
4434 Returns pointer to following character of the format string and
4435 fills in *VALUEP and *WIDTHP with the extracted value and number of
4436 bits extracted. WIDTHP can be NULL. */
4439 arm_decode_bitfield (const char *ptr
,
4441 unsigned long *valuep
,
4444 unsigned long value
= 0;
4452 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4453 start
= start
* 10 + *ptr
- '0';
4455 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
4456 end
= end
* 10 + *ptr
- '0';
4462 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
4465 while (*ptr
++ == ',');
4473 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
4474 bfd_boolean print_shift
)
4476 func (stream
, "%s", arm_regnames
[given
& 0xf]);
4478 if ((given
& 0xff0) != 0)
4480 if ((given
& 0x10) == 0)
4482 int amount
= (given
& 0xf80) >> 7;
4483 int shift
= (given
& 0x60) >> 5;
4489 func (stream
, ", rrx");
4497 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
4499 func (stream
, ", #%d", amount
);
4501 else if ((given
& 0x80) == 0x80)
4502 func (stream
, "\t; <illegal shifter operand>");
4503 else if (print_shift
)
4504 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
4505 arm_regnames
[(given
& 0xf00) >> 8]);
4507 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
4511 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
4514 is_mve_okay_in_it (enum mve_instructions matched_insn
)
4516 switch (matched_insn
)
4518 case MVE_VMOV_GP_TO_VEC_LANE
:
4519 case MVE_VMOV2_VEC_LANE_TO_GP
:
4520 case MVE_VMOV2_GP_TO_VEC_LANE
:
4521 case MVE_VMOV_VEC_LANE_TO_GP
:
4529 is_mve_architecture (struct disassemble_info
*info
)
4531 struct arm_private_data
*private_data
= info
->private_data
;
4532 arm_feature_set allowed_arches
= private_data
->features
;
4534 arm_feature_set arm_ext_v8_1m_main
4535 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
4537 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
4538 && !ARM_CPU_IS_ANY (allowed_arches
))
4545 is_vpt_instruction (long given
)
4548 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
4549 if ((given
& 0x0040e000) == 0)
4552 /* VPT floating point T1 variant. */
4553 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
4554 /* VPT floating point T2 variant. */
4555 || ((given
& 0xefb10f50) == 0xee310f40)
4556 /* VPT vector T1 variant. */
4557 || ((given
& 0xff811f51) == 0xfe010f00)
4558 /* VPT vector T2 variant. */
4559 || ((given
& 0xff811f51) == 0xfe010f01
4560 && ((given
& 0x300000) != 0x300000))
4561 /* VPT vector T3 variant. */
4562 || ((given
& 0xff811f50) == 0xfe011f00)
4563 /* VPT vector T4 variant. */
4564 || ((given
& 0xff811f70) == 0xfe010f40)
4565 /* VPT vector T5 variant. */
4566 || ((given
& 0xff811f70) == 0xfe010f60)
4567 /* VPT vector T6 variant. */
4568 || ((given
& 0xff811f50) == 0xfe011f40)
4569 /* VPST vector T variant. */
4570 || ((given
& 0xffbf1fff) == 0xfe310f4d))
4576 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
4577 and ending bitfield = END. END must be greater than START. */
4579 static unsigned long
4580 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
4582 int bits
= end
- start
;
4587 return ((given
>> start
) & ((2ul << bits
) - 1));
4590 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
4591 START:END and START2:END2. END/END2 must be greater than
4594 static unsigned long
4595 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
4596 unsigned int end
, unsigned int start2
,
4599 int bits
= end
- start
;
4600 int bits2
= end2
- start2
;
4601 unsigned long value
= 0;
4607 value
= arm_decode_field (given
, start
, end
);
4610 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
4614 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
4615 This helps us decode instructions that change mnemonic depending on specific
4616 operand values/encodings. */
4619 is_mve_encoding_conflict (unsigned long given
,
4620 enum mve_instructions matched_insn
)
4622 switch (matched_insn
)
4625 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4631 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4633 if ((arm_decode_field (given
, 12, 12) == 0)
4634 && (arm_decode_field (given
, 0, 0) == 1))
4639 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4641 if (arm_decode_field (given
, 0, 3) == 0xd)
4645 case MVE_VPT_VEC_T1
:
4646 case MVE_VPT_VEC_T2
:
4647 case MVE_VPT_VEC_T3
:
4648 case MVE_VPT_VEC_T4
:
4649 case MVE_VPT_VEC_T5
:
4650 case MVE_VPT_VEC_T6
:
4651 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
4653 if (arm_decode_field (given
, 20, 21) == 3)
4657 case MVE_VCMP_FP_T1
:
4658 if ((arm_decode_field (given
, 12, 12) == 0)
4659 && (arm_decode_field (given
, 0, 0) == 1))
4664 case MVE_VCMP_FP_T2
:
4665 if (arm_decode_field (given
, 0, 3) == 0xd)
4677 case MVE_VQDMULH_T3
:
4678 case MVE_VQRDMULH_T4
:
4684 case MVE_VCMP_VEC_T1
:
4685 case MVE_VCMP_VEC_T2
:
4686 case MVE_VCMP_VEC_T3
:
4687 case MVE_VCMP_VEC_T4
:
4688 case MVE_VCMP_VEC_T5
:
4689 case MVE_VCMP_VEC_T6
:
4690 if (arm_decode_field (given
, 20, 21) == 3)
4699 if (arm_decode_field (given
, 7, 8) == 3)
4706 if ((arm_decode_field (given
, 24, 24) == 0)
4707 && (arm_decode_field (given
, 21, 21) == 0))
4711 else if ((arm_decode_field (given
, 7, 8) == 3))
4719 if ((arm_decode_field (given
, 24, 24) == 0)
4720 && (arm_decode_field (given
, 21, 21) == 0))
4727 case MVE_VCVT_FP_FIX_VEC
:
4728 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
4733 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4735 if ((cmode
& 1) == 0)
4737 else if ((cmode
& 0xc) == 0xc)
4745 unsigned long cmode
= arm_decode_field (given
, 8, 11);
4747 if ((cmode
& 9) == 1)
4749 else if ((cmode
& 5) == 1)
4751 else if ((cmode
& 0xe) == 0xe)
4757 case MVE_VMOV_IMM_TO_VEC
:
4758 if ((arm_decode_field (given
, 5, 5) == 1)
4759 && (arm_decode_field (given
, 8, 11) != 0xe))
4766 unsigned long size
= arm_decode_field (given
, 19, 20);
4767 if ((size
== 0) || (size
== 3))
4777 if (arm_decode_field (given
, 18, 19) == 3)
4783 case MVE_VRMLSLDAVH
:
4786 if (arm_decode_field (given
, 20, 22) == 7)
4791 case MVE_VRMLALDAVH
:
4792 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
4804 print_mve_vld_str_addr (struct disassemble_info
*info
,
4805 unsigned long given
,
4806 enum mve_instructions matched_insn
)
4808 void *stream
= info
->stream
;
4809 fprintf_ftype func
= info
->fprintf_func
;
4811 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
4813 imm
= arm_decode_field (given
, 0, 6);
4816 switch (matched_insn
)
4820 gpr
= arm_decode_field (given
, 16, 18);
4825 gpr
= arm_decode_field (given
, 16, 18);
4831 gpr
= arm_decode_field (given
, 16, 19);
4837 gpr
= arm_decode_field (given
, 16, 19);
4843 gpr
= arm_decode_field (given
, 16, 19);
4850 p
= arm_decode_field (given
, 24, 24);
4851 w
= arm_decode_field (given
, 21, 21);
4853 add
= arm_decode_field (given
, 23, 23);
4857 /* Don't print anything for '+' as it is implied. */
4867 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
4868 /* Pre-indexed mode. */
4870 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
4872 else if ((p
== 0) && (w
== 1))
4873 /* Post-index mode. */
4874 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
4877 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
4878 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
4879 this encoding is undefined. */
4882 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
4883 enum mve_undefined
*undefined_code
)
4885 *undefined_code
= UNDEF_NONE
;
4887 switch (matched_insn
)
4890 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
4892 *undefined_code
= UNDEF_SIZE_3
;
4898 case MVE_VQDMULH_T1
:
4899 case MVE_VQRDMULH_T2
:
4903 if (arm_decode_field (given
, 20, 21) == 3)
4905 *undefined_code
= UNDEF_SIZE_3
;
4912 if (arm_decode_field (given
, 7, 8) == 3)
4914 *undefined_code
= UNDEF_SIZE_3
;
4921 if (arm_decode_field (given
, 7, 8) <= 1)
4923 *undefined_code
= UNDEF_SIZE_LE_1
;
4930 if ((arm_decode_field (given
, 7, 8) == 0))
4932 *undefined_code
= UNDEF_SIZE_0
;
4939 if ((arm_decode_field (given
, 7, 8) <= 1))
4941 *undefined_code
= UNDEF_SIZE_LE_1
;
4947 case MVE_VLDRB_GATHER_T1
:
4948 if (arm_decode_field (given
, 7, 8) == 3)
4950 *undefined_code
= UNDEF_SIZE_3
;
4953 else if ((arm_decode_field (given
, 28, 28) == 0)
4954 && (arm_decode_field (given
, 7, 8) == 0))
4956 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
4962 case MVE_VLDRH_GATHER_T2
:
4963 if (arm_decode_field (given
, 7, 8) == 3)
4965 *undefined_code
= UNDEF_SIZE_3
;
4968 else if ((arm_decode_field (given
, 28, 28) == 0)
4969 && (arm_decode_field (given
, 7, 8) == 1))
4971 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
4974 else if (arm_decode_field (given
, 7, 8) == 0)
4976 *undefined_code
= UNDEF_SIZE_0
;
4982 case MVE_VLDRW_GATHER_T3
:
4983 if (arm_decode_field (given
, 7, 8) != 2)
4985 *undefined_code
= UNDEF_SIZE_NOT_2
;
4988 else if (arm_decode_field (given
, 28, 28) == 0)
4990 *undefined_code
= UNDEF_NOT_UNSIGNED
;
4996 case MVE_VLDRD_GATHER_T4
:
4997 if (arm_decode_field (given
, 7, 8) != 3)
4999 *undefined_code
= UNDEF_SIZE_NOT_3
;
5002 else if (arm_decode_field (given
, 28, 28) == 0)
5004 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5010 case MVE_VSTRB_SCATTER_T1
:
5011 if (arm_decode_field (given
, 7, 8) == 3)
5013 *undefined_code
= UNDEF_SIZE_3
;
5019 case MVE_VSTRH_SCATTER_T2
:
5021 unsigned long size
= arm_decode_field (given
, 7, 8);
5024 *undefined_code
= UNDEF_SIZE_3
;
5029 *undefined_code
= UNDEF_SIZE_0
;
5036 case MVE_VSTRW_SCATTER_T3
:
5037 if (arm_decode_field (given
, 7, 8) != 2)
5039 *undefined_code
= UNDEF_SIZE_NOT_2
;
5045 case MVE_VSTRD_SCATTER_T4
:
5046 if (arm_decode_field (given
, 7, 8) != 3)
5048 *undefined_code
= UNDEF_SIZE_NOT_3
;
5054 case MVE_VCVT_FP_FIX_VEC
:
5056 unsigned long imm6
= arm_decode_field (given
, 16, 21);
5057 if ((imm6
& 0x20) == 0)
5059 *undefined_code
= UNDEF_VCVT_IMM6
;
5063 if ((arm_decode_field (given
, 9, 9) == 0)
5064 && ((imm6
& 0x30) == 0x20))
5066 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
5073 case MVE_VCVT_BETWEEN_FP_INT
:
5074 case MVE_VCVT_FROM_FP_TO_INT
:
5076 unsigned long size
= arm_decode_field (given
, 18, 19);
5079 *undefined_code
= UNDEF_SIZE_0
;
5084 *undefined_code
= UNDEF_SIZE_3
;
5091 case MVE_VMOV_VEC_LANE_TO_GP
:
5093 unsigned long op1
= arm_decode_field (given
, 21, 22);
5094 unsigned long op2
= arm_decode_field (given
, 5, 6);
5095 unsigned long u
= arm_decode_field (given
, 23, 23);
5097 if ((op2
== 0) && (u
== 1))
5099 if ((op1
== 0) || (op1
== 1))
5101 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
5109 if ((op1
== 0) || (op1
== 1))
5111 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5121 case MVE_VMOV_GP_TO_VEC_LANE
:
5122 if (arm_decode_field (given
, 5, 6) == 2)
5124 unsigned long op1
= arm_decode_field (given
, 21, 22);
5125 if ((op1
== 0) || (op1
== 1))
5127 *undefined_code
= UNDEF_BAD_OP1_OP2
;
5136 case MVE_VMOV_IMM_TO_VEC
:
5137 if (arm_decode_field (given
, 5, 5) == 0)
5139 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5141 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
5143 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
5153 if (arm_decode_field (given
, 18, 19) == 2)
5155 *undefined_code
= UNDEF_SIZE_2
;
5161 case MVE_VRMLALDAVH
:
5162 case MVE_VMLADAV_T1
:
5163 case MVE_VMLADAV_T2
:
5165 if ((arm_decode_field (given
, 28, 28) == 1)
5166 && (arm_decode_field (given
, 12, 12) == 1))
5168 *undefined_code
= UNDEF_XCHG_UNS
;
5179 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
5180 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
5181 why this encoding is unpredictable. */
5184 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
5185 enum mve_unpredictable
*unpredictable_code
)
5187 *unpredictable_code
= UNPRED_NONE
;
5189 switch (matched_insn
)
5191 case MVE_VCMP_FP_T2
:
5193 if ((arm_decode_field (given
, 12, 12) == 0)
5194 && (arm_decode_field (given
, 5, 5) == 1))
5196 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
5202 case MVE_VPT_VEC_T4
:
5203 case MVE_VPT_VEC_T5
:
5204 case MVE_VPT_VEC_T6
:
5205 case MVE_VCMP_VEC_T4
:
5206 case MVE_VCMP_VEC_T5
:
5207 case MVE_VCMP_VEC_T6
:
5208 if (arm_decode_field (given
, 0, 3) == 0xd)
5210 *unpredictable_code
= UNPRED_R13
;
5218 unsigned long gpr
= arm_decode_field (given
, 12, 15);
5221 *unpredictable_code
= UNPRED_R13
;
5224 else if (gpr
== 0xf)
5226 *unpredictable_code
= UNPRED_R15
;
5237 case MVE_VQDMULH_T3
:
5238 case MVE_VQRDMULH_T4
:
5240 case MVE_VFMA_FP_SCALAR
:
5241 case MVE_VFMAS_FP_SCALAR
:
5245 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5248 *unpredictable_code
= UNPRED_R13
;
5251 else if (gpr
== 0xf)
5253 *unpredictable_code
= UNPRED_R15
;
5263 unsigned long rn
= arm_decode_field (given
, 16, 19);
5265 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5267 *unpredictable_code
= UNPRED_R13_AND_WB
;
5273 *unpredictable_code
= UNPRED_R15
;
5277 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
5279 *unpredictable_code
= UNPRED_Q_GT_6
;
5289 unsigned long rn
= arm_decode_field (given
, 16, 19);
5291 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5293 *unpredictable_code
= UNPRED_R13_AND_WB
;
5299 *unpredictable_code
= UNPRED_R15
;
5303 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
5305 *unpredictable_code
= UNPRED_Q_GT_4
;
5319 unsigned long rn
= arm_decode_field (given
, 16, 19);
5321 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
5323 *unpredictable_code
= UNPRED_R13_AND_WB
;
5328 *unpredictable_code
= UNPRED_R15
;
5335 case MVE_VLDRB_GATHER_T1
:
5336 if (arm_decode_field (given
, 0, 0) == 1)
5338 *unpredictable_code
= UNPRED_OS
;
5343 /* To handle common code with T2-T4 variants. */
5344 case MVE_VLDRH_GATHER_T2
:
5345 case MVE_VLDRW_GATHER_T3
:
5346 case MVE_VLDRD_GATHER_T4
:
5348 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5349 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5353 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5357 if (arm_decode_field (given
, 16, 19) == 0xf)
5359 *unpredictable_code
= UNPRED_R15
;
5366 case MVE_VLDRW_GATHER_T5
:
5367 case MVE_VLDRD_GATHER_T6
:
5369 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5370 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5374 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
5381 case MVE_VSTRB_SCATTER_T1
:
5382 if (arm_decode_field (given
, 16, 19) == 0xf)
5384 *unpredictable_code
= UNPRED_R15
;
5387 else if (arm_decode_field (given
, 0, 0) == 1)
5389 *unpredictable_code
= UNPRED_OS
;
5395 case MVE_VSTRH_SCATTER_T2
:
5396 case MVE_VSTRW_SCATTER_T3
:
5397 case MVE_VSTRD_SCATTER_T4
:
5398 if (arm_decode_field (given
, 16, 19) == 0xf)
5400 *unpredictable_code
= UNPRED_R15
;
5406 case MVE_VMOV2_VEC_LANE_TO_GP
:
5407 case MVE_VMOV2_GP_TO_VEC_LANE
:
5408 case MVE_VCVT_BETWEEN_FP_INT
:
5409 case MVE_VCVT_FROM_FP_TO_INT
:
5411 unsigned long rt
= arm_decode_field (given
, 0, 3);
5412 unsigned long rt2
= arm_decode_field (given
, 16, 19);
5414 if ((rt
== 0xd) || (rt2
== 0xd))
5416 *unpredictable_code
= UNPRED_R13
;
5419 else if ((rt
== 0xf) || (rt2
== 0xf))
5421 *unpredictable_code
= UNPRED_R15
;
5426 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
5433 case MVE_VMOV_HFP_TO_GP
:
5434 case MVE_VMOV_GP_TO_VEC_LANE
:
5435 case MVE_VMOV_VEC_LANE_TO_GP
:
5437 unsigned long rda
= arm_decode_field (given
, 12, 15);
5440 *unpredictable_code
= UNPRED_R13
;
5443 else if (rda
== 0xf)
5445 *unpredictable_code
= UNPRED_R15
;
5462 if (arm_decode_field (given
, 20, 21) == 2)
5464 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5465 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5466 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5468 if ((Qd
== Qn
) || (Qd
== Qm
))
5470 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
5480 case MVE_VQDMULL_T1
:
5486 if (arm_decode_field (given
, 28, 28) == 1)
5488 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
5489 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
5490 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5492 if ((Qd
== Qn
) || (Qd
== Qm
))
5494 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5504 case MVE_VQDMULL_T2
:
5506 unsigned long gpr
= arm_decode_field (given
, 0, 3);
5509 *unpredictable_code
= UNPRED_R13
;
5512 else if (gpr
== 0xf)
5514 *unpredictable_code
= UNPRED_R15
;
5518 if (arm_decode_field (given
, 28, 28) == 1)
5521 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
5522 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
5526 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
5537 case MVE_VRMLSLDAVH
:
5540 if (arm_decode_field (given
, 20, 22) == 6)
5542 *unpredictable_code
= UNPRED_R13
;
5554 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
5556 unsigned long op1
= arm_decode_field (given
, 21, 22);
5557 unsigned long op2
= arm_decode_field (given
, 5, 6);
5558 unsigned long h
= arm_decode_field (given
, 16, 16);
5559 unsigned long index
, esize
, targetBeat
, idx
;
5560 void *stream
= info
->stream
;
5561 fprintf_ftype func
= info
->fprintf_func
;
5563 if ((op1
& 0x2) == 0x2)
5568 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
5573 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
5580 func (stream
, "<undefined index>");
5584 targetBeat
= (op1
& 0x1) | (h
<< 1);
5585 idx
= index
+ targetBeat
* (32/esize
);
5587 func (stream
, "%lu", idx
);
5590 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
5591 in length and integer of floating-point type. */
5593 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
5594 unsigned int ibit_loc
, const struct mopcode32
*insn
)
5597 int cmode
= (given
>> 8) & 0xf;
5598 int op
= (given
>> 5) & 0x1;
5599 unsigned long value
= 0, hival
= 0;
5603 void *stream
= info
->stream
;
5604 fprintf_ftype func
= info
->fprintf_func
;
5606 /* On Neon the 'i' bit is at bit 24, on mve it is
5608 bits
|= ((given
>> ibit_loc
) & 1) << 7;
5609 bits
|= ((given
>> 16) & 7) << 4;
5610 bits
|= ((given
>> 0) & 15) << 0;
5614 shift
= (cmode
>> 1) & 3;
5615 value
= (unsigned long) bits
<< (8 * shift
);
5618 else if (cmode
< 12)
5620 shift
= (cmode
>> 1) & 1;
5621 value
= (unsigned long) bits
<< (8 * shift
);
5624 else if (cmode
< 14)
5626 shift
= (cmode
& 1) + 1;
5627 value
= (unsigned long) bits
<< (8 * shift
);
5628 value
|= (1ul << (8 * shift
)) - 1;
5631 else if (cmode
== 14)
5635 /* Bit replication into bytes. */
5641 for (ix
= 7; ix
>= 0; ix
--)
5643 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
5645 value
= (value
<< 8) | mask
;
5647 hival
= (hival
<< 8) | mask
;
5653 /* Byte replication. */
5654 value
= (unsigned long) bits
;
5660 /* Floating point encoding. */
5663 value
= (unsigned long) (bits
& 0x7f) << 19;
5664 value
|= (unsigned long) (bits
& 0x80) << 24;
5665 tmp
= bits
& 0x40 ? 0x3c : 0x40;
5666 value
|= (unsigned long) tmp
<< 24;
5672 func (stream
, "<illegal constant %.8x:%x:%x>",
5678 // printU determines whether the immediate value should be printed as
5680 unsigned printU
= 0;
5681 switch (insn
->mve_op
)
5685 // We want this for instructions that don't have a 'signed' type
5689 case MVE_VMOV_IMM_TO_VEC
:
5696 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
5703 : "#%ld\t; 0x%.4lx", value
, value
);
5709 unsigned char valbytes
[4];
5712 /* Do this a byte at a time so we don't have to
5713 worry about the host's endianness. */
5714 valbytes
[0] = value
& 0xff;
5715 valbytes
[1] = (value
>> 8) & 0xff;
5716 valbytes
[2] = (value
>> 16) & 0xff;
5717 valbytes
[3] = (value
>> 24) & 0xff;
5719 floatformat_to_double
5720 (& floatformat_ieee_single_little
, valbytes
,
5723 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
5730 : "#%ld\t; 0x%.8lx",
5731 (long) (((value
& 0x80000000L
) != 0)
5733 ? value
| ~0xffffffffL
: value
),
5738 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
5748 print_mve_undefined (struct disassemble_info
*info
,
5749 enum mve_undefined undefined_code
)
5751 void *stream
= info
->stream
;
5752 fprintf_ftype func
= info
->fprintf_func
;
5754 func (stream
, "\t\tundefined instruction: ");
5756 switch (undefined_code
)
5759 func (stream
, "size equals zero");
5763 func (stream
, "size equals two");
5767 func (stream
, "size equals three");
5770 case UNDEF_SIZE_LE_1
:
5771 func (stream
, "size <= 1");
5774 case UNDEF_SIZE_NOT_2
:
5775 func (stream
, "size not equal to 2");
5778 case UNDEF_SIZE_NOT_3
:
5779 func (stream
, "size not equal to 3");
5782 case UNDEF_NOT_UNS_SIZE_0
:
5783 func (stream
, "not unsigned and size = zero");
5786 case UNDEF_NOT_UNS_SIZE_1
:
5787 func (stream
, "not unsigned and size = one");
5790 case UNDEF_NOT_UNSIGNED
:
5791 func (stream
, "not unsigned");
5794 case UNDEF_VCVT_IMM6
:
5795 func (stream
, "invalid imm6");
5798 case UNDEF_VCVT_FSI_IMM6
:
5799 func (stream
, "fsi = 0 and invalid imm6");
5802 case UNDEF_BAD_OP1_OP2
:
5803 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
5806 case UNDEF_BAD_U_OP1_OP2
:
5807 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
5810 case UNDEF_OP_0_BAD_CMODE
:
5811 func (stream
, "op field equal 0 and bad cmode");
5814 case UNDEF_XCHG_UNS
:
5815 func (stream
, "exchange and unsigned together");
5825 print_mve_unpredictable (struct disassemble_info
*info
,
5826 enum mve_unpredictable unpredict_code
)
5828 void *stream
= info
->stream
;
5829 fprintf_ftype func
= info
->fprintf_func
;
5831 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
5833 switch (unpredict_code
)
5835 case UNPRED_IT_BLOCK
:
5836 func (stream
, "mve instruction in it block");
5839 case UNPRED_FCA_0_FCB_1
:
5840 func (stream
, "condition bits, fca = 0 and fcb = 1");
5844 func (stream
, "use of r13 (sp)");
5848 func (stream
, "use of r15 (pc)");
5852 func (stream
, "start register block > r4");
5856 func (stream
, "start register block > r6");
5859 case UNPRED_R13_AND_WB
:
5860 func (stream
, "use of r13 and write back");
5863 case UNPRED_Q_REGS_EQUAL
:
5865 "same vector register used for destination and other operand");
5869 func (stream
, "use of offset scaled");
5872 case UNPRED_GP_REGS_EQUAL
:
5873 func (stream
, "same general-purpose register used for both operands");
5876 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
5877 func (stream
, "use of identical q registers and size = 1");
5880 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
5881 func (stream
, "use of identical q registers and size = 1");
5889 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
5892 print_mve_register_blocks (struct disassemble_info
*info
,
5893 unsigned long given
,
5894 enum mve_instructions matched_insn
)
5896 void *stream
= info
->stream
;
5897 fprintf_ftype func
= info
->fprintf_func
;
5899 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
5902 switch (matched_insn
)
5906 if (q_reg_start
<= 6)
5907 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
5909 func (stream
, "<illegal reg q%ld>", q_reg_start
);
5914 if (q_reg_start
<= 4)
5915 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
5916 q_reg_start
+ 1, q_reg_start
+ 2,
5919 func (stream
, "<illegal reg q%ld>", q_reg_start
);
5928 print_mve_rounding_mode (struct disassemble_info
*info
,
5929 unsigned long given
,
5930 enum mve_instructions matched_insn
)
5932 void *stream
= info
->stream
;
5933 fprintf_ftype func
= info
->fprintf_func
;
5935 switch (matched_insn
)
5937 case MVE_VCVT_FROM_FP_TO_INT
:
5939 switch (arm_decode_field (given
, 8, 9))
5965 switch (arm_decode_field (given
, 7, 9))
6004 print_mve_vcvt_size (struct disassemble_info
*info
,
6005 unsigned long given
,
6006 enum mve_instructions matched_insn
)
6008 unsigned long mode
= 0;
6009 void *stream
= info
->stream
;
6010 fprintf_ftype func
= info
->fprintf_func
;
6012 switch (matched_insn
)
6014 case MVE_VCVT_FP_FIX_VEC
:
6016 mode
= (((given
& 0x200) >> 7)
6017 | ((given
& 0x10000000) >> 27)
6018 | ((given
& 0x100) >> 8));
6023 func (stream
, "f16.s16");
6027 func (stream
, "s16.f16");
6031 func (stream
, "f16.u16");
6035 func (stream
, "u16.f16");
6039 func (stream
, "f32.s32");
6043 func (stream
, "s32.f32");
6047 func (stream
, "f32.u32");
6051 func (stream
, "u32.f32");
6059 case MVE_VCVT_BETWEEN_FP_INT
:
6061 unsigned long size
= arm_decode_field (given
, 18, 19);
6062 unsigned long op
= arm_decode_field (given
, 7, 8);
6069 func (stream
, "f16.s16");
6073 func (stream
, "f16.u16");
6077 func (stream
, "s16.f16");
6081 func (stream
, "u16.f16");
6093 func (stream
, "f32.s32");
6097 func (stream
, "f32.u32");
6101 func (stream
, "s32.f32");
6105 func (stream
, "u32.f32");
6112 case MVE_VCVT_FP_HALF_FP
:
6114 unsigned long op
= arm_decode_field (given
, 28, 28);
6116 func (stream
, "f16.f32");
6118 func (stream
, "f32.f16");
6122 case MVE_VCVT_FROM_FP_TO_INT
:
6124 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
6129 func (stream
, "s16.f16");
6133 func (stream
, "u16.f16");
6137 func (stream
, "s32.f32");
6141 func (stream
, "u32.f32");
6156 print_instruction_predicate (struct disassemble_info
*info
)
6158 void *stream
= info
->stream
;
6159 fprintf_ftype func
= info
->fprintf_func
;
6161 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
6163 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
6168 print_mve_size (struct disassemble_info
*info
,
6170 enum mve_instructions matched_insn
)
6172 void *stream
= info
->stream
;
6173 fprintf_ftype func
= info
->fprintf_func
;
6175 switch (matched_insn
)
6178 case MVE_VCMP_VEC_T1
:
6179 case MVE_VCMP_VEC_T2
:
6180 case MVE_VCMP_VEC_T3
:
6181 case MVE_VCMP_VEC_T4
:
6182 case MVE_VCMP_VEC_T5
:
6183 case MVE_VCMP_VEC_T6
:
6190 case MVE_VLDRB_GATHER_T1
:
6191 case MVE_VLDRH_GATHER_T2
:
6192 case MVE_VLDRW_GATHER_T3
:
6193 case MVE_VLDRD_GATHER_T4
:
6197 case MVE_VPT_VEC_T1
:
6198 case MVE_VPT_VEC_T2
:
6199 case MVE_VPT_VEC_T3
:
6200 case MVE_VPT_VEC_T4
:
6201 case MVE_VPT_VEC_T5
:
6202 case MVE_VPT_VEC_T6
:
6211 case MVE_VQDMULH_T1
:
6212 case MVE_VQRDMULH_T2
:
6213 case MVE_VQDMULH_T3
:
6214 case MVE_VQRDMULH_T4
:
6219 case MVE_VSTRB_SCATTER_T1
:
6220 case MVE_VSTRH_SCATTER_T2
:
6221 case MVE_VSTRW_SCATTER_T3
:
6225 func (stream
, "%s", mve_vec_sizename
[size
]);
6227 func (stream
, "<undef size>");
6230 case MVE_VCMP_FP_T1
:
6231 case MVE_VCMP_FP_T2
:
6232 case MVE_VFMA_FP_SCALAR
:
6235 case MVE_VFMAS_FP_SCALAR
:
6239 func (stream
, "32");
6241 func (stream
, "16");
6244 case MVE_VMLADAV_T1
:
6246 case MVE_VMLSDAV_T1
:
6249 case MVE_VQDMULL_T1
:
6250 case MVE_VQDMULL_T2
:
6254 func (stream
, "16");
6256 func (stream
, "32");
6263 func (stream
, "16");
6270 func (stream
, "32");
6273 func (stream
, "16");
6283 case MVE_VMOV_GP_TO_VEC_LANE
:
6284 case MVE_VMOV_VEC_LANE_TO_GP
:
6288 func (stream
, "32");
6293 func (stream
, "16");
6296 case 8: case 9: case 10: case 11:
6297 case 12: case 13: case 14: case 15:
6306 case MVE_VMOV_IMM_TO_VEC
:
6309 case 0: case 4: case 8:
6310 case 12: case 24: case 26:
6311 func (stream
, "i32");
6314 func (stream
, "i16");
6317 func (stream
, "i8");
6320 func (stream
, "i64");
6323 func (stream
, "f32");
6330 case MVE_VMULL_POLY
:
6332 func (stream
, "p8");
6334 func (stream
, "p16");
6340 case 0: case 2: case 4:
6341 case 6: case 12: case 13:
6342 func (stream
, "32");
6346 func (stream
, "16");
6360 func (stream
, "32");
6364 func (stream
, "16");
6378 print_vec_condition (struct disassemble_info
*info
, long given
,
6379 enum mve_instructions matched_insn
)
6381 void *stream
= info
->stream
;
6382 fprintf_ftype func
= info
->fprintf_func
;
6385 switch (matched_insn
)
6388 case MVE_VCMP_FP_T1
:
6389 vec_cond
= (((given
& 0x1000) >> 10)
6390 | ((given
& 1) << 1)
6391 | ((given
& 0x0080) >> 7));
6392 func (stream
, "%s",vec_condnames
[vec_cond
]);
6396 case MVE_VCMP_FP_T2
:
6397 vec_cond
= (((given
& 0x1000) >> 10)
6398 | ((given
& 0x0020) >> 4)
6399 | ((given
& 0x0080) >> 7));
6400 func (stream
, "%s",vec_condnames
[vec_cond
]);
6403 case MVE_VPT_VEC_T1
:
6404 case MVE_VCMP_VEC_T1
:
6405 vec_cond
= (given
& 0x0080) >> 7;
6406 func (stream
, "%s",vec_condnames
[vec_cond
]);
6409 case MVE_VPT_VEC_T2
:
6410 case MVE_VCMP_VEC_T2
:
6411 vec_cond
= 2 | ((given
& 0x0080) >> 7);
6412 func (stream
, "%s",vec_condnames
[vec_cond
]);
6415 case MVE_VPT_VEC_T3
:
6416 case MVE_VCMP_VEC_T3
:
6417 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
6418 func (stream
, "%s",vec_condnames
[vec_cond
]);
6421 case MVE_VPT_VEC_T4
:
6422 case MVE_VCMP_VEC_T4
:
6423 vec_cond
= (given
& 0x0080) >> 7;
6424 func (stream
, "%s",vec_condnames
[vec_cond
]);
6427 case MVE_VPT_VEC_T5
:
6428 case MVE_VCMP_VEC_T5
:
6429 vec_cond
= 2 | ((given
& 0x0080) >> 7);
6430 func (stream
, "%s",vec_condnames
[vec_cond
]);
6433 case MVE_VPT_VEC_T6
:
6434 case MVE_VCMP_VEC_T6
:
6435 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
6436 func (stream
, "%s",vec_condnames
[vec_cond
]);
6451 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
6452 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
6453 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
6454 #define PRE_BIT_SET (given & (1 << P_BIT))
6457 /* Print one coprocessor instruction on INFO->STREAM.
6458 Return TRUE if the instuction matched, FALSE if this is not a
6459 recognised coprocessor instruction. */
6462 print_insn_coprocessor (bfd_vma pc
,
6463 struct disassemble_info
*info
,
6467 const struct sopcode32
*insn
;
6468 void *stream
= info
->stream
;
6469 fprintf_ftype func
= info
->fprintf_func
;
6471 unsigned long value
= 0;
6474 struct arm_private_data
*private_data
= info
->private_data
;
6475 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
6476 arm_feature_set arm_ext_v8_1m_main
=
6477 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
6479 allowed_arches
= private_data
->features
;
6481 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
6483 unsigned long u_reg
= 16;
6484 bfd_boolean is_unpredictable
= FALSE
;
6485 signed long value_in_comment
= 0;
6488 if (ARM_FEATURE_ZERO (insn
->arch
))
6489 switch (insn
->value
)
6491 case SENTINEL_IWMMXT_START
:
6492 if (info
->mach
!= bfd_mach_arm_XScale
6493 && info
->mach
!= bfd_mach_arm_iWMMXt
6494 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
6497 while ((! ARM_FEATURE_ZERO (insn
->arch
))
6498 && insn
->value
!= SENTINEL_IWMMXT_END
);
6501 case SENTINEL_IWMMXT_END
:
6504 case SENTINEL_GENERIC_START
:
6505 allowed_arches
= private_data
->features
;
6513 value
= insn
->value
;
6514 cp_num
= (given
>> 8) & 0xf;
6518 /* The high 4 bits are 0xe for Arm conditional instructions, and
6519 0xe for arm unconditional instructions. The rest of the
6520 encoding is the same. */
6522 value
|= 0xe0000000;
6530 /* Only match unconditional instuctions against unconditional
6532 if ((given
& 0xf0000000) == 0xf0000000)
6539 cond
= (given
>> 28) & 0xf;
6545 if ((insn
->isa
== T32
&& !thumb
)
6546 || (insn
->isa
== ARM
&& thumb
))
6549 if ((given
& mask
) != value
)
6552 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
6555 if (insn
->value
== 0xfe000010 /* mcr2 */
6556 || insn
->value
== 0xfe100010 /* mrc2 */
6557 || insn
->value
== 0xfc100000 /* ldc2 */
6558 || insn
->value
== 0xfc000000) /* stc2 */
6560 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
6561 is_unpredictable
= TRUE
;
6563 /* Armv8.1-M Mainline FP & MVE instructions. */
6564 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
6565 && !ARM_CPU_IS_ANY (allowed_arches
)
6566 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
6570 else if (insn
->value
== 0x0e000000 /* cdp */
6571 || insn
->value
== 0xfe000000 /* cdp2 */
6572 || insn
->value
== 0x0e000010 /* mcr */
6573 || insn
->value
== 0x0e100010 /* mrc */
6574 || insn
->value
== 0x0c100000 /* ldc */
6575 || insn
->value
== 0x0c000000) /* stc */
6577 /* Floating-point instructions. */
6578 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
6581 /* Armv8.1-M Mainline FP & MVE instructions. */
6582 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
6583 && !ARM_CPU_IS_ANY (allowed_arches
)
6584 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
6587 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
6588 || insn
->value
== 0xec000f80) /* vstr (system register) */
6589 && arm_decode_field (given
, 24, 24) == 0
6590 && arm_decode_field (given
, 21, 21) == 0)
6591 /* If the P and W bits are both 0 then these encodings match the MVE
6592 VLDR and VSTR instructions, these are in a different table, so we
6593 don't let it match here. */
6596 for (c
= insn
->assembler
; *c
; c
++)
6600 const char mod
= *++c
;
6604 func (stream
, "%%");
6610 int rn
= (given
>> 16) & 0xf;
6611 bfd_vma offset
= given
& 0xff;
6614 offset
= given
& 0x7f;
6616 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
6618 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
6620 /* Not unindexed. The offset is scaled. */
6622 /* vldr.16/vstr.16 will shift the address
6623 left by 1 bit only. */
6624 offset
= offset
* 2;
6626 offset
= offset
* 4;
6628 if (NEGATIVE_BIT_SET
)
6631 value_in_comment
= offset
;
6637 func (stream
, ", #%d]%s",
6639 WRITEBACK_BIT_SET
? "!" : "");
6640 else if (NEGATIVE_BIT_SET
)
6641 func (stream
, ", #-0]");
6649 if (WRITEBACK_BIT_SET
)
6652 func (stream
, ", #%d", (int) offset
);
6653 else if (NEGATIVE_BIT_SET
)
6654 func (stream
, ", #-0");
6658 func (stream
, ", {%s%d}",
6659 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
6661 value_in_comment
= offset
;
6664 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
6666 func (stream
, "\t; ");
6667 /* For unaligned PCs, apply off-by-alignment
6669 info
->print_address_func (offset
+ pc
6670 + info
->bytes_per_chunk
* 2
6679 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
6680 int offset
= (given
>> 1) & 0x3f;
6683 func (stream
, "{d%d}", regno
);
6684 else if (regno
+ offset
> 32)
6685 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
6687 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
6693 bfd_boolean single
= ((given
>> 8) & 1) == 0;
6694 char reg_prefix
= single
? 's' : 'd';
6695 int Dreg
= (given
>> 22) & 0x1;
6696 int Vdreg
= (given
>> 12) & 0xf;
6697 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
6698 : ((Dreg
<< 4) | Vdreg
);
6699 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
6700 int maxreg
= single
? 31 : 15;
6701 int topreg
= reg
+ num
- 1;
6704 func (stream
, "{VPR}");
6706 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
6707 else if (topreg
> maxreg
)
6708 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
6709 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
6711 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
6712 reg_prefix
, topreg
);
6717 if (cond
!= COND_UNCOND
)
6718 is_unpredictable
= TRUE
;
6722 if (cond
!= COND_UNCOND
&& cp_num
== 9)
6723 is_unpredictable
= TRUE
;
6725 func (stream
, "%s", arm_conditional
[cond
]);
6729 /* Print a Cirrus/DSP shift immediate. */
6730 /* Immediates are 7bit signed ints with bits 0..3 in
6731 bits 0..3 of opcode and bits 4..6 in bits 5..7
6736 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
6738 /* Is ``imm'' a negative number? */
6742 func (stream
, "%d", imm
);
6750 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6755 func (stream
, "FPSCR");
6758 func (stream
, "FPSCR_nzcvqc");
6761 func (stream
, "VPR");
6764 func (stream
, "P0");
6767 func (stream
, "FPCXTNS");
6770 func (stream
, "FPCXTS");
6773 func (stream
, "<invalid reg %lu>", regno
);
6780 switch (given
& 0x00408000)
6797 switch (given
& 0x00080080)
6809 func (stream
, _("<illegal precision>"));
6815 switch (given
& 0x00408000)
6833 switch (given
& 0x60)
6849 case '0': case '1': case '2': case '3': case '4':
6850 case '5': case '6': case '7': case '8': case '9':
6854 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
6860 is_unpredictable
= TRUE
;
6865 /* Eat the 'u' character. */
6869 is_unpredictable
= TRUE
;
6872 func (stream
, "%s", arm_regnames
[value
]);
6875 if (given
& (1 << 6))
6879 func (stream
, "d%ld", value
);
6884 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
6886 func (stream
, "q%ld", value
>> 1);
6889 func (stream
, "%ld", value
);
6890 value_in_comment
= value
;
6894 /* Converts immediate 8 bit back to float value. */
6895 unsigned floatVal
= (value
& 0x80) << 24
6896 | (value
& 0x3F) << 19
6897 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
6899 /* Quarter float have a maximum value of 31.0.
6900 Get floating point value multiplied by 1e7.
6901 The maximum value stays in limit of a 32-bit int. */
6903 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
6904 (16 + (value
& 0xF));
6906 if (!(decVal
% 1000000))
6907 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
6908 floatVal
, value
& 0x80 ? '-' : ' ',
6910 decVal
% 10000000 / 1000000);
6911 else if (!(decVal
% 10000))
6912 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
6913 floatVal
, value
& 0x80 ? '-' : ' ',
6915 decVal
% 10000000 / 10000);
6917 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
6918 floatVal
, value
& 0x80 ? '-' : ' ',
6919 decVal
/ 10000000, decVal
% 10000000);
6924 int from
= (given
& (1 << 7)) ? 32 : 16;
6925 func (stream
, "%ld", from
- value
);
6931 func (stream
, "#%s", arm_fp_const
[value
& 7]);
6933 func (stream
, "f%ld", value
);
6938 func (stream
, "%s", iwmmxt_wwnames
[value
]);
6940 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
6944 func (stream
, "%s", iwmmxt_regnames
[value
]);
6947 func (stream
, "%s", iwmmxt_cregnames
[value
]);
6951 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
6958 func (stream
, "eq");
6962 func (stream
, "vs");
6966 func (stream
, "ge");
6970 func (stream
, "gt");
6974 func (stream
, "??");
6982 func (stream
, "%c", *c
);
6986 if (value
== ((1ul << width
) - 1))
6987 func (stream
, "%c", *c
);
6990 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7002 int single
= *c
++ == 'y';
7007 case '4': /* Sm pair */
7008 case '0': /* Sm, Dm */
7009 regno
= given
& 0x0000000f;
7013 regno
+= (given
>> 5) & 1;
7016 regno
+= ((given
>> 5) & 1) << 4;
7019 case '1': /* Sd, Dd */
7020 regno
= (given
>> 12) & 0x0000000f;
7024 regno
+= (given
>> 22) & 1;
7027 regno
+= ((given
>> 22) & 1) << 4;
7030 case '2': /* Sn, Dn */
7031 regno
= (given
>> 16) & 0x0000000f;
7035 regno
+= (given
>> 7) & 1;
7038 regno
+= ((given
>> 7) & 1) << 4;
7041 case '3': /* List */
7043 regno
= (given
>> 12) & 0x0000000f;
7047 regno
+= (given
>> 22) & 1;
7050 regno
+= ((given
>> 22) & 1) << 4;
7057 func (stream
, "%c%d", single
? 's' : 'd', regno
);
7061 int count
= given
& 0xff;
7068 func (stream
, "-%c%d",
7076 func (stream
, ", %c%d", single
? 's' : 'd',
7082 switch (given
& 0x00400100)
7084 case 0x00000000: func (stream
, "b"); break;
7085 case 0x00400000: func (stream
, "h"); break;
7086 case 0x00000100: func (stream
, "w"); break;
7087 case 0x00400100: func (stream
, "d"); break;
7095 /* given (20, 23) | given (0, 3) */
7096 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
7097 func (stream
, "%d", (int) value
);
7102 /* This is like the 'A' operator, except that if
7103 the width field "M" is zero, then the offset is
7104 *not* multiplied by four. */
7106 int offset
= given
& 0xff;
7107 int multiplier
= (given
& 0x00000100) ? 4 : 1;
7109 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
7113 value_in_comment
= offset
* multiplier
;
7114 if (NEGATIVE_BIT_SET
)
7115 value_in_comment
= - value_in_comment
;
7121 func (stream
, ", #%s%d]%s",
7122 NEGATIVE_BIT_SET
? "-" : "",
7123 offset
* multiplier
,
7124 WRITEBACK_BIT_SET
? "!" : "");
7126 func (stream
, "], #%s%d",
7127 NEGATIVE_BIT_SET
? "-" : "",
7128 offset
* multiplier
);
7137 int imm4
= (given
>> 4) & 0xf;
7138 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
7139 int ubit
= ! NEGATIVE_BIT_SET
;
7140 const char *rm
= arm_regnames
[given
& 0xf];
7141 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
7147 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
7149 func (stream
, ", lsl #%d", imm4
);
7156 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
7158 func (stream
, ", lsl #%d", imm4
);
7160 if (puw_bits
== 5 || puw_bits
== 7)
7165 func (stream
, "INVALID");
7173 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
7174 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
7183 func (stream
, "%c", *c
);
7186 if (value_in_comment
> 32 || value_in_comment
< -16)
7187 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
7189 if (is_unpredictable
)
7190 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7197 /* Decodes and prints ARM addressing modes. Returns the offset
7198 used in the address, if any, if it is worthwhile printing the
7199 offset as a hexadecimal value in a comment at the end of the
7200 line of disassembly. */
7203 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
7205 void *stream
= info
->stream
;
7206 fprintf_ftype func
= info
->fprintf_func
;
7209 if (((given
& 0x000f0000) == 0x000f0000)
7210 && ((given
& 0x02000000) == 0))
7212 offset
= given
& 0xfff;
7214 func (stream
, "[pc");
7218 /* Pre-indexed. Elide offset of positive zero when
7220 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7221 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7223 if (NEGATIVE_BIT_SET
)
7228 /* Cope with the possibility of write-back
7229 being used. Probably a very dangerous thing
7230 for the programmer to do, but who are we to
7232 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
7234 else /* Post indexed. */
7236 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7238 /* Ie ignore the offset. */
7242 func (stream
, "\t; ");
7243 info
->print_address_func (offset
, info
);
7248 func (stream
, "[%s",
7249 arm_regnames
[(given
>> 16) & 0xf]);
7253 if ((given
& 0x02000000) == 0)
7255 /* Elide offset of positive zero when non-writeback. */
7256 offset
= given
& 0xfff;
7257 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
7258 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7262 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
7263 arm_decode_shift (given
, func
, stream
, TRUE
);
7266 func (stream
, "]%s",
7267 WRITEBACK_BIT_SET
? "!" : "");
7271 if ((given
& 0x02000000) == 0)
7273 /* Always show offset. */
7274 offset
= given
& 0xfff;
7275 func (stream
, "], #%s%d",
7276 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
7280 func (stream
, "], %s",
7281 NEGATIVE_BIT_SET
? "-" : "");
7282 arm_decode_shift (given
, func
, stream
, TRUE
);
7285 if (NEGATIVE_BIT_SET
)
7289 return (signed long) offset
;
7292 /* Print one neon instruction on INFO->STREAM.
7293 Return TRUE if the instuction matched, FALSE if this is not a
7294 recognised neon instruction. */
7297 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
7299 const struct opcode32
*insn
;
7300 void *stream
= info
->stream
;
7301 fprintf_ftype func
= info
->fprintf_func
;
7305 if ((given
& 0xef000000) == 0xef000000)
7307 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
7308 unsigned long bit28
= given
& (1 << 28);
7310 given
&= 0x00ffffff;
7312 given
|= 0xf3000000;
7314 given
|= 0xf2000000;
7316 else if ((given
& 0xff000000) == 0xf9000000)
7317 given
^= 0xf9000000 ^ 0xf4000000;
7318 /* vdup is also a valid neon instruction. */
7319 else if ((given
& 0xff910f5f) != 0xee800b10)
7323 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
7325 if ((given
& insn
->mask
) == insn
->value
)
7327 signed long value_in_comment
= 0;
7328 bfd_boolean is_unpredictable
= FALSE
;
7331 for (c
= insn
->assembler
; *c
; c
++)
7338 func (stream
, "%%");
7342 if (thumb
&& ifthen_state
)
7343 is_unpredictable
= TRUE
;
7347 if (thumb
&& ifthen_state
)
7348 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7353 static const unsigned char enc
[16] =
7355 0x4, 0x14, /* st4 0,1 */
7367 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7368 int rn
= ((given
>> 16) & 0xf);
7369 int rm
= ((given
>> 0) & 0xf);
7370 int align
= ((given
>> 4) & 0x3);
7371 int type
= ((given
>> 8) & 0xf);
7372 int n
= enc
[type
] & 0xf;
7373 int stride
= (enc
[type
] >> 4) + 1;
7378 for (ix
= 0; ix
!= n
; ix
++)
7379 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
7381 func (stream
, "d%d", rd
);
7383 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
7384 func (stream
, "}, [%s", arm_regnames
[rn
]);
7386 func (stream
, " :%d", 32 << align
);
7391 func (stream
, ", %s", arm_regnames
[rm
]);
7397 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7398 int rn
= ((given
>> 16) & 0xf);
7399 int rm
= ((given
>> 0) & 0xf);
7400 int idx_align
= ((given
>> 4) & 0xf);
7402 int size
= ((given
>> 10) & 0x3);
7403 int idx
= idx_align
>> (size
+ 1);
7404 int length
= ((given
>> 8) & 3) + 1;
7408 if (length
> 1 && size
> 0)
7409 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
7415 int amask
= (1 << size
) - 1;
7416 if ((idx_align
& (1 << size
)) != 0)
7420 if ((idx_align
& amask
) == amask
)
7422 else if ((idx_align
& amask
) != 0)
7429 if (size
== 2 && (idx_align
& 2) != 0)
7431 align
= (idx_align
& 1) ? 16 << size
: 0;
7435 if ((size
== 2 && (idx_align
& 3) != 0)
7436 || (idx_align
& 1) != 0)
7443 if ((idx_align
& 3) == 3)
7445 align
= (idx_align
& 3) * 64;
7448 align
= (idx_align
& 1) ? 32 << size
: 0;
7456 for (i
= 0; i
< length
; i
++)
7457 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
7458 rd
+ i
* stride
, idx
);
7459 func (stream
, "}, [%s", arm_regnames
[rn
]);
7461 func (stream
, " :%d", align
);
7466 func (stream
, ", %s", arm_regnames
[rm
]);
7472 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
7473 int rn
= ((given
>> 16) & 0xf);
7474 int rm
= ((given
>> 0) & 0xf);
7475 int align
= ((given
>> 4) & 0x1);
7476 int size
= ((given
>> 6) & 0x3);
7477 int type
= ((given
>> 8) & 0x3);
7479 int stride
= ((given
>> 5) & 0x1);
7482 if (stride
&& (n
== 1))
7489 for (ix
= 0; ix
!= n
; ix
++)
7490 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
7492 func (stream
, "d%d[]", rd
);
7494 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
7495 func (stream
, "}, [%s", arm_regnames
[rn
]);
7498 align
= (8 * (type
+ 1)) << size
;
7500 align
= (size
> 1) ? align
>> 1 : align
;
7501 if (type
== 2 || (type
== 0 && !size
))
7502 func (stream
, " :<bad align %d>", align
);
7504 func (stream
, " :%d", align
);
7510 func (stream
, ", %s", arm_regnames
[rm
]);
7516 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
7517 int size
= (given
>> 20) & 3;
7518 int reg
= raw_reg
& ((4 << size
) - 1);
7519 int ix
= raw_reg
>> size
>> 2;
7521 func (stream
, "d%d[%d]", reg
, ix
);
7526 /* Neon encoded constant for mov, mvn, vorr, vbic. */
7529 int cmode
= (given
>> 8) & 0xf;
7530 int op
= (given
>> 5) & 0x1;
7531 unsigned long value
= 0, hival
= 0;
7536 bits
|= ((given
>> 24) & 1) << 7;
7537 bits
|= ((given
>> 16) & 7) << 4;
7538 bits
|= ((given
>> 0) & 15) << 0;
7542 shift
= (cmode
>> 1) & 3;
7543 value
= (unsigned long) bits
<< (8 * shift
);
7546 else if (cmode
< 12)
7548 shift
= (cmode
>> 1) & 1;
7549 value
= (unsigned long) bits
<< (8 * shift
);
7552 else if (cmode
< 14)
7554 shift
= (cmode
& 1) + 1;
7555 value
= (unsigned long) bits
<< (8 * shift
);
7556 value
|= (1ul << (8 * shift
)) - 1;
7559 else if (cmode
== 14)
7563 /* Bit replication into bytes. */
7569 for (ix
= 7; ix
>= 0; ix
--)
7571 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
7573 value
= (value
<< 8) | mask
;
7575 hival
= (hival
<< 8) | mask
;
7581 /* Byte replication. */
7582 value
= (unsigned long) bits
;
7588 /* Floating point encoding. */
7591 value
= (unsigned long) (bits
& 0x7f) << 19;
7592 value
|= (unsigned long) (bits
& 0x80) << 24;
7593 tmp
= bits
& 0x40 ? 0x3c : 0x40;
7594 value
|= (unsigned long) tmp
<< 24;
7600 func (stream
, "<illegal constant %.8x:%x:%x>",
7608 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
7612 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
7618 unsigned char valbytes
[4];
7621 /* Do this a byte at a time so we don't have to
7622 worry about the host's endianness. */
7623 valbytes
[0] = value
& 0xff;
7624 valbytes
[1] = (value
>> 8) & 0xff;
7625 valbytes
[2] = (value
>> 16) & 0xff;
7626 valbytes
[3] = (value
>> 24) & 0xff;
7628 floatformat_to_double
7629 (& floatformat_ieee_single_little
, valbytes
,
7632 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
7636 func (stream
, "#%ld\t; 0x%.8lx",
7637 (long) (((value
& 0x80000000L
) != 0)
7638 ? value
| ~0xffffffffL
: value
),
7643 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
7654 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
7655 int num
= (given
>> 8) & 0x3;
7658 func (stream
, "{d%d}", regno
);
7659 else if (num
+ regno
>= 32)
7660 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
7662 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
7667 case '0': case '1': case '2': case '3': case '4':
7668 case '5': case '6': case '7': case '8': case '9':
7671 unsigned long value
;
7673 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7678 func (stream
, "%s", arm_regnames
[value
]);
7681 func (stream
, "%ld", value
);
7682 value_in_comment
= value
;
7685 func (stream
, "%ld", (1ul << width
) - value
);
7691 /* Various width encodings. */
7693 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
7698 if (*c
>= '0' && *c
<= '9')
7700 else if (*c
>= 'a' && *c
<= 'f')
7701 limit
= *c
- 'a' + 10;
7707 if (value
< low
|| value
> high
)
7708 func (stream
, "<illegal width %d>", base
<< value
);
7710 func (stream
, "%d", base
<< value
);
7714 if (given
& (1 << 6))
7718 func (stream
, "d%ld", value
);
7723 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
7725 func (stream
, "q%ld", value
>> 1);
7731 func (stream
, "%c", *c
);
7735 if (value
== ((1ul << width
) - 1))
7736 func (stream
, "%c", *c
);
7739 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
7753 func (stream
, "%c", *c
);
7756 if (value_in_comment
> 32 || value_in_comment
< -16)
7757 func (stream
, "\t; 0x%lx", value_in_comment
);
7759 if (is_unpredictable
)
7760 func (stream
, UNPREDICTABLE_INSTRUCTION
);
7768 /* Print one mve instruction on INFO->STREAM.
7769 Return TRUE if the instuction matched, FALSE if this is not a
7770 recognised mve instruction. */
7773 print_insn_mve (struct disassemble_info
*info
, long given
)
7775 const struct mopcode32
*insn
;
7776 void *stream
= info
->stream
;
7777 fprintf_ftype func
= info
->fprintf_func
;
7779 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
7781 if (((given
& insn
->mask
) == insn
->value
)
7782 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
7784 signed long value_in_comment
= 0;
7785 bfd_boolean is_unpredictable
= FALSE
;
7786 bfd_boolean is_undefined
= FALSE
;
7788 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
7789 enum mve_undefined undefined_cond
= UNDEF_NONE
;
7791 /* Most vector mve instruction are illegal in a it block.
7792 There are a few exceptions; check for them. */
7793 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
7795 is_unpredictable
= TRUE
;
7796 unpredictable_cond
= UNPRED_IT_BLOCK
;
7798 else if (is_mve_unpredictable (given
, insn
->mve_op
,
7799 &unpredictable_cond
))
7800 is_unpredictable
= TRUE
;
7802 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
7803 is_undefined
= TRUE
;
7805 for (c
= insn
->assembler
; *c
; c
++)
7812 func (stream
, "%%");
7816 /* Don't print anything for '+' as it is implied. */
7817 if (arm_decode_field (given
, 23, 23) == 0)
7823 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
7827 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
7832 long mve_mask
= mve_extract_pred_mask (given
);
7833 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
7838 print_vec_condition (info
, given
, insn
->mve_op
);
7842 if (arm_decode_field (given
, 0, 0) == 1)
7845 = arm_decode_field (given
, 4, 4)
7846 | (arm_decode_field (given
, 6, 6) << 1);
7848 func (stream
, ", uxtw #%lu", size
);
7853 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
7857 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
7862 unsigned long op1
= arm_decode_field (given
, 21, 22);
7864 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
7866 /* Check for signed. */
7867 if (arm_decode_field (given
, 23, 23) == 0)
7869 /* We don't print 's' for S32. */
7870 if ((arm_decode_field (given
, 5, 6) == 0)
7871 && ((op1
== 0) || (op1
== 1)))
7881 if (arm_decode_field (given
, 28, 28) == 0)
7890 print_instruction_predicate (info
);
7894 if (arm_decode_field (given
, 21, 21) == 1)
7899 print_mve_register_blocks (info
, given
, insn
->mve_op
);
7903 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
7905 print_simd_imm8 (info
, given
, 28, insn
);
7909 print_mve_vmov_index (info
, given
);
7913 if (arm_decode_field (given
, 12, 12) == 0)
7920 if (arm_decode_field (given
, 12, 12) == 1)
7924 case '0': case '1': case '2': case '3': case '4':
7925 case '5': case '6': case '7': case '8': case '9':
7928 unsigned long value
;
7930 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
7936 is_unpredictable
= TRUE
;
7937 else if (value
== 15)
7938 func (stream
, "zr");
7940 func (stream
, "%s", arm_regnames
[value
]);
7943 print_mve_size (info
,
7954 = arm_decode_field (given
, 0, 6);
7955 unsigned long mod_imm
= imm
;
7957 switch (insn
->mve_op
)
7959 case MVE_VLDRW_GATHER_T5
:
7960 case MVE_VSTRW_SCATTER_T5
:
7961 mod_imm
= mod_imm
<< 2;
7963 case MVE_VSTRD_SCATTER_T6
:
7964 case MVE_VLDRD_GATHER_T6
:
7965 mod_imm
= mod_imm
<< 3;
7972 func (stream
, "%lu", mod_imm
);
7976 func (stream
, "%lu", 64 - value
);
7979 func (stream
, "%s", arm_regnames
[value
]);
7982 func (stream
, "%ld", value
);
7983 value_in_comment
= value
;
7986 func (stream
, "s%ld", value
);
7990 func (stream
, "<illegal reg q%ld.5>", value
);
7992 func (stream
, "q%ld", value
);
7995 func (stream
, "0x%08lx", value
);
8007 func (stream
, "%c", *c
);
8010 if (value_in_comment
> 32 || value_in_comment
< -16)
8011 func (stream
, "\t; 0x%lx", value_in_comment
);
8013 if (is_unpredictable
)
8014 print_mve_unpredictable (info
, unpredictable_cond
);
8017 print_mve_undefined (info
, undefined_cond
);
8019 if ((vpt_block_state
.in_vpt_block
== FALSE
)
8021 && (is_vpt_instruction (given
) == TRUE
))
8022 mark_inside_vpt_block (given
);
8023 else if (vpt_block_state
.in_vpt_block
== TRUE
)
8024 update_vpt_block_state ();
8033 /* Return the name of a v7A special register. */
8036 banked_regname (unsigned reg
)
8040 case 15: return "CPSR";
8041 case 32: return "R8_usr";
8042 case 33: return "R9_usr";
8043 case 34: return "R10_usr";
8044 case 35: return "R11_usr";
8045 case 36: return "R12_usr";
8046 case 37: return "SP_usr";
8047 case 38: return "LR_usr";
8048 case 40: return "R8_fiq";
8049 case 41: return "R9_fiq";
8050 case 42: return "R10_fiq";
8051 case 43: return "R11_fiq";
8052 case 44: return "R12_fiq";
8053 case 45: return "SP_fiq";
8054 case 46: return "LR_fiq";
8055 case 48: return "LR_irq";
8056 case 49: return "SP_irq";
8057 case 50: return "LR_svc";
8058 case 51: return "SP_svc";
8059 case 52: return "LR_abt";
8060 case 53: return "SP_abt";
8061 case 54: return "LR_und";
8062 case 55: return "SP_und";
8063 case 60: return "LR_mon";
8064 case 61: return "SP_mon";
8065 case 62: return "ELR_hyp";
8066 case 63: return "SP_hyp";
8067 case 79: return "SPSR";
8068 case 110: return "SPSR_fiq";
8069 case 112: return "SPSR_irq";
8070 case 114: return "SPSR_svc";
8071 case 116: return "SPSR_abt";
8072 case 118: return "SPSR_und";
8073 case 124: return "SPSR_mon";
8074 case 126: return "SPSR_hyp";
8075 default: return NULL
;
8079 /* Return the name of the DMB/DSB option. */
8081 data_barrier_option (unsigned option
)
8083 switch (option
& 0xf)
8085 case 0xf: return "sy";
8086 case 0xe: return "st";
8087 case 0xd: return "ld";
8088 case 0xb: return "ish";
8089 case 0xa: return "ishst";
8090 case 0x9: return "ishld";
8091 case 0x7: return "un";
8092 case 0x6: return "unst";
8093 case 0x5: return "nshld";
8094 case 0x3: return "osh";
8095 case 0x2: return "oshst";
8096 case 0x1: return "oshld";
8097 default: return NULL
;
8101 /* Print one ARM instruction from PC on INFO->STREAM. */
8104 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8106 const struct opcode32
*insn
;
8107 void *stream
= info
->stream
;
8108 fprintf_ftype func
= info
->fprintf_func
;
8109 struct arm_private_data
*private_data
= info
->private_data
;
8111 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
8114 if (print_insn_neon (info
, given
, FALSE
))
8117 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
8119 if ((given
& insn
->mask
) != insn
->value
)
8122 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
8125 /* Special case: an instruction with all bits set in the condition field
8126 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
8127 or by the catchall at the end of the table. */
8128 if ((given
& 0xF0000000) != 0xF0000000
8129 || (insn
->mask
& 0xF0000000) == 0xF0000000
8130 || (insn
->mask
== 0 && insn
->value
== 0))
8132 unsigned long u_reg
= 16;
8133 unsigned long U_reg
= 16;
8134 bfd_boolean is_unpredictable
= FALSE
;
8135 signed long value_in_comment
= 0;
8138 for (c
= insn
->assembler
; *c
; c
++)
8142 bfd_boolean allow_unpredictable
= FALSE
;
8147 func (stream
, "%%");
8151 value_in_comment
= print_arm_address (pc
, info
, given
);
8155 /* Set P address bit and use normal address
8156 printing routine. */
8157 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
8161 allow_unpredictable
= TRUE
;
8164 if ((given
& 0x004f0000) == 0x004f0000)
8166 /* PC relative with immediate offset. */
8167 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8171 /* Elide positive zero offset. */
8172 if (offset
|| NEGATIVE_BIT_SET
)
8173 func (stream
, "[pc, #%s%d]\t; ",
8174 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8176 func (stream
, "[pc]\t; ");
8177 if (NEGATIVE_BIT_SET
)
8179 info
->print_address_func (offset
+ pc
+ 8, info
);
8183 /* Always show the offset. */
8184 func (stream
, "[pc], #%s%d",
8185 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8186 if (! allow_unpredictable
)
8187 is_unpredictable
= TRUE
;
8192 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
8194 func (stream
, "[%s",
8195 arm_regnames
[(given
>> 16) & 0xf]);
8199 if (IMMEDIATE_BIT_SET
)
8201 /* Elide offset for non-writeback
8203 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
8205 func (stream
, ", #%s%d",
8206 NEGATIVE_BIT_SET
? "-" : "", offset
);
8208 if (NEGATIVE_BIT_SET
)
8211 value_in_comment
= offset
;
8215 /* Register Offset or Register Pre-Indexed. */
8216 func (stream
, ", %s%s",
8217 NEGATIVE_BIT_SET
? "-" : "",
8218 arm_regnames
[given
& 0xf]);
8220 /* Writing back to the register that is the source/
8221 destination of the load/store is unpredictable. */
8222 if (! allow_unpredictable
8223 && WRITEBACK_BIT_SET
8224 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
8225 is_unpredictable
= TRUE
;
8228 func (stream
, "]%s",
8229 WRITEBACK_BIT_SET
? "!" : "");
8233 if (IMMEDIATE_BIT_SET
)
8235 /* Immediate Post-indexed. */
8236 /* PR 10924: Offset must be printed, even if it is zero. */
8237 func (stream
, "], #%s%d",
8238 NEGATIVE_BIT_SET
? "-" : "", offset
);
8239 if (NEGATIVE_BIT_SET
)
8241 value_in_comment
= offset
;
8245 /* Register Post-indexed. */
8246 func (stream
, "], %s%s",
8247 NEGATIVE_BIT_SET
? "-" : "",
8248 arm_regnames
[given
& 0xf]);
8250 /* Writing back to the register that is the source/
8251 destination of the load/store is unpredictable. */
8252 if (! allow_unpredictable
8253 && (given
& 0xf) == ((given
>> 12) & 0xf))
8254 is_unpredictable
= TRUE
;
8257 if (! allow_unpredictable
)
8259 /* Writeback is automatically implied by post- addressing.
8260 Setting the W bit is unnecessary and ARM specify it as
8261 being unpredictable. */
8262 if (WRITEBACK_BIT_SET
8263 /* Specifying the PC register as the post-indexed
8264 registers is also unpredictable. */
8265 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
8266 is_unpredictable
= TRUE
;
8274 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
8275 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
8280 if (((given
>> 28) & 0xf) != 0xe)
8282 arm_conditional
[(given
>> 28) & 0xf]);
8291 for (reg
= 0; reg
< 16; reg
++)
8292 if ((given
& (1 << reg
)) != 0)
8295 func (stream
, ", ");
8297 func (stream
, "%s", arm_regnames
[reg
]);
8301 is_unpredictable
= TRUE
;
8306 arm_decode_shift (given
, func
, stream
, FALSE
);
8310 if ((given
& 0x02000000) != 0)
8312 unsigned int rotate
= (given
& 0xf00) >> 7;
8313 unsigned int immed
= (given
& 0xff);
8316 a
= (((immed
<< (32 - rotate
))
8317 | (immed
>> rotate
)) & 0xffffffff);
8318 /* If there is another encoding with smaller rotate,
8319 the rotate should be specified directly. */
8320 for (i
= 0; i
< 32; i
+= 2)
8321 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
8325 func (stream
, "#%d, %d", immed
, rotate
);
8327 func (stream
, "#%d", a
);
8328 value_in_comment
= a
;
8331 arm_decode_shift (given
, func
, stream
, TRUE
);
8335 if ((given
& 0x0000f000) == 0x0000f000)
8337 arm_feature_set arm_ext_v6
=
8338 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
8340 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
8341 mechanism for setting PSR flag bits. They are
8342 obsolete in V6 onwards. */
8343 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
8347 is_unpredictable
= TRUE
;
8352 if ((given
& 0x01200000) == 0x00200000)
8358 int offset
= given
& 0xff;
8360 value_in_comment
= offset
* 4;
8361 if (NEGATIVE_BIT_SET
)
8362 value_in_comment
= - value_in_comment
;
8364 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8369 func (stream
, ", #%d]%s",
8370 (int) value_in_comment
,
8371 WRITEBACK_BIT_SET
? "!" : "");
8379 if (WRITEBACK_BIT_SET
)
8382 func (stream
, ", #%d", (int) value_in_comment
);
8386 func (stream
, ", {%d}", (int) offset
);
8387 value_in_comment
= offset
;
8394 /* Print ARM V5 BLX(1) address: pc+25 bits. */
8399 if (! NEGATIVE_BIT_SET
)
8400 /* Is signed, hi bits should be ones. */
8401 offset
= (-1) ^ 0x00ffffff;
8403 /* Offset is (SignExtend(offset field)<<2). */
8404 offset
+= given
& 0x00ffffff;
8406 address
= offset
+ pc
+ 8;
8408 if (given
& 0x01000000)
8409 /* H bit allows addressing to 2-byte boundaries. */
8412 info
->print_address_func (address
, info
);
8417 if ((given
& 0x02000200) == 0x200)
8420 unsigned sysm
= (given
& 0x004f0000) >> 16;
8422 sysm
|= (given
& 0x300) >> 4;
8423 name
= banked_regname (sysm
);
8426 func (stream
, "%s", name
);
8428 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
8432 func (stream
, "%cPSR_",
8433 (given
& 0x00400000) ? 'S' : 'C');
8434 if (given
& 0x80000)
8436 if (given
& 0x40000)
8438 if (given
& 0x20000)
8440 if (given
& 0x10000)
8446 if ((given
& 0xf0) == 0x60)
8448 switch (given
& 0xf)
8450 case 0xf: func (stream
, "sy"); break;
8452 func (stream
, "#%d", (int) given
& 0xf);
8458 const char * opt
= data_barrier_option (given
& 0xf);
8460 func (stream
, "%s", opt
);
8462 func (stream
, "#%d", (int) given
& 0xf);
8466 case '0': case '1': case '2': case '3': case '4':
8467 case '5': case '6': case '7': case '8': case '9':
8470 unsigned long value
;
8472 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8478 is_unpredictable
= TRUE
;
8482 /* We want register + 1 when decoding T. */
8488 /* Eat the 'u' character. */
8492 is_unpredictable
= TRUE
;
8497 /* Eat the 'U' character. */
8501 is_unpredictable
= TRUE
;
8504 func (stream
, "%s", arm_regnames
[value
]);
8507 func (stream
, "%ld", value
);
8508 value_in_comment
= value
;
8511 func (stream
, "%ld", value
* 8);
8512 value_in_comment
= value
* 8;
8515 func (stream
, "%ld", value
+ 1);
8516 value_in_comment
= value
+ 1;
8519 func (stream
, "0x%08lx", value
);
8521 /* Some SWI instructions have special
8523 if ((given
& 0x0fffffff) == 0x0FF00000)
8524 func (stream
, "\t; IMB");
8525 else if ((given
& 0x0fffffff) == 0x0FF00001)
8526 func (stream
, "\t; IMBRange");
8529 func (stream
, "%01lx", value
& 0xf);
8530 value_in_comment
= value
;
8535 func (stream
, "%c", *c
);
8539 if (value
== ((1ul << width
) - 1))
8540 func (stream
, "%c", *c
);
8543 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8556 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
8557 func (stream
, "%d", imm
);
8558 value_in_comment
= imm
;
8563 /* LSB and WIDTH fields of BFI or BFC. The machine-
8564 language instruction encodes LSB and MSB. */
8566 long msb
= (given
& 0x001f0000) >> 16;
8567 long lsb
= (given
& 0x00000f80) >> 7;
8568 long w
= msb
- lsb
+ 1;
8571 func (stream
, "#%lu, #%lu", lsb
, w
);
8573 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
8578 /* Get the PSR/banked register name. */
8581 unsigned sysm
= (given
& 0x004f0000) >> 16;
8583 sysm
|= (given
& 0x300) >> 4;
8584 name
= banked_regname (sysm
);
8587 func (stream
, "%s", name
);
8589 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
8594 /* 16-bit unsigned immediate from a MOVT or MOVW
8595 instruction, encoded in bits 0:11 and 15:19. */
8597 long hi
= (given
& 0x000f0000) >> 4;
8598 long lo
= (given
& 0x00000fff);
8599 long imm16
= hi
| lo
;
8601 func (stream
, "#%lu", imm16
);
8602 value_in_comment
= imm16
;
8611 func (stream
, "%c", *c
);
8614 if (value_in_comment
> 32 || value_in_comment
< -16)
8615 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8617 if (is_unpredictable
)
8618 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8623 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
8627 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
8630 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8632 const struct opcode16
*insn
;
8633 void *stream
= info
->stream
;
8634 fprintf_ftype func
= info
->fprintf_func
;
8636 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
8637 if ((given
& insn
->mask
) == insn
->value
)
8639 signed long value_in_comment
= 0;
8640 const char *c
= insn
->assembler
;
8649 func (stream
, "%c", *c
);
8656 func (stream
, "%%");
8661 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8666 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8675 ifthen_next_state
= given
& 0xff;
8676 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
8677 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
8678 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
8683 if (ifthen_next_state
)
8684 func (stream
, "\t; unpredictable branch in IT block\n");
8689 func (stream
, "\t; unpredictable <IT:%s>",
8690 arm_conditional
[IFTHEN_COND
]);
8697 reg
= (given
>> 3) & 0x7;
8698 if (given
& (1 << 6))
8701 func (stream
, "%s", arm_regnames
[reg
]);
8710 if (given
& (1 << 7))
8713 func (stream
, "%s", arm_regnames
[reg
]);
8718 if (given
& (1 << 8))
8722 if (*c
== 'O' && (given
& (1 << 8)))
8732 /* It would be nice if we could spot
8733 ranges, and generate the rS-rE format: */
8734 for (reg
= 0; (reg
< 8); reg
++)
8735 if ((given
& (1 << reg
)) != 0)
8738 func (stream
, ", ");
8740 func (stream
, "%s", arm_regnames
[reg
]);
8746 func (stream
, ", ");
8748 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
8754 func (stream
, ", ");
8755 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
8763 /* Print writeback indicator for a LDMIA. We are doing a
8764 writeback if the base register is not in the register
8766 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
8771 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
8773 bfd_vma address
= (pc
+ 4
8774 + ((given
& 0x00f8) >> 2)
8775 + ((given
& 0x0200) >> 3));
8776 info
->print_address_func (address
, info
);
8781 /* Right shift immediate -- bits 6..10; 1-31 print
8782 as themselves, 0 prints as 32. */
8784 long imm
= (given
& 0x07c0) >> 6;
8787 func (stream
, "#%ld", imm
);
8791 case '0': case '1': case '2': case '3': case '4':
8792 case '5': case '6': case '7': case '8': case '9':
8794 int bitstart
= *c
++ - '0';
8797 while (*c
>= '0' && *c
<= '9')
8798 bitstart
= (bitstart
* 10) + *c
++ - '0';
8807 while (*c
>= '0' && *c
<= '9')
8808 bitend
= (bitend
* 10) + *c
++ - '0';
8811 reg
= given
>> bitstart
;
8812 reg
&= (2 << (bitend
- bitstart
)) - 1;
8817 func (stream
, "%s", arm_regnames
[reg
]);
8821 func (stream
, "%ld", (long) reg
);
8822 value_in_comment
= reg
;
8826 func (stream
, "%ld", (long) (reg
<< 1));
8827 value_in_comment
= reg
<< 1;
8831 func (stream
, "%ld", (long) (reg
<< 2));
8832 value_in_comment
= reg
<< 2;
8836 /* PC-relative address -- the bottom two
8837 bits of the address are dropped
8838 before the calculation. */
8839 info
->print_address_func
8840 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
8841 value_in_comment
= 0;
8845 func (stream
, "0x%04lx", (long) reg
);
8849 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
8850 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
8851 value_in_comment
= 0;
8855 func (stream
, "%s", arm_conditional
[reg
]);
8866 if ((given
& (1 << bitstart
)) != 0)
8867 func (stream
, "%c", *c
);
8872 if ((given
& (1 << bitstart
)) != 0)
8873 func (stream
, "%c", *c
++);
8875 func (stream
, "%c", *++c
);
8889 if (value_in_comment
> 32 || value_in_comment
< -16)
8890 func (stream
, "\t; 0x%lx", value_in_comment
);
8895 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
8899 /* Return the name of an V7M special register. */
8902 psr_name (int regno
)
8906 case 0x0: return "APSR";
8907 case 0x1: return "IAPSR";
8908 case 0x2: return "EAPSR";
8909 case 0x3: return "PSR";
8910 case 0x5: return "IPSR";
8911 case 0x6: return "EPSR";
8912 case 0x7: return "IEPSR";
8913 case 0x8: return "MSP";
8914 case 0x9: return "PSP";
8915 case 0xa: return "MSPLIM";
8916 case 0xb: return "PSPLIM";
8917 case 0x10: return "PRIMASK";
8918 case 0x11: return "BASEPRI";
8919 case 0x12: return "BASEPRI_MAX";
8920 case 0x13: return "FAULTMASK";
8921 case 0x14: return "CONTROL";
8922 case 0x88: return "MSP_NS";
8923 case 0x89: return "PSP_NS";
8924 case 0x8a: return "MSPLIM_NS";
8925 case 0x8b: return "PSPLIM_NS";
8926 case 0x90: return "PRIMASK_NS";
8927 case 0x91: return "BASEPRI_NS";
8928 case 0x93: return "FAULTMASK_NS";
8929 case 0x94: return "CONTROL_NS";
8930 case 0x98: return "SP_NS";
8931 default: return "<unknown>";
8935 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
8938 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8940 const struct opcode32
*insn
;
8941 void *stream
= info
->stream
;
8942 fprintf_ftype func
= info
->fprintf_func
;
8943 bfd_boolean is_mve
= is_mve_architecture (info
);
8945 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
8948 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
8951 if (is_mve
&& print_insn_mve (info
, given
))
8954 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
8955 if ((given
& insn
->mask
) == insn
->value
)
8957 bfd_boolean is_clrm
= FALSE
;
8958 bfd_boolean is_unpredictable
= FALSE
;
8959 signed long value_in_comment
= 0;
8960 const char *c
= insn
->assembler
;
8966 func (stream
, "%c", *c
);
8973 func (stream
, "%%");
8978 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8982 if (ifthen_next_state
)
8983 func (stream
, "\t; unpredictable branch in IT block\n");
8988 func (stream
, "\t; unpredictable <IT:%s>",
8989 arm_conditional
[IFTHEN_COND
]);
8994 unsigned int imm12
= 0;
8996 imm12
|= (given
& 0x000000ffu
);
8997 imm12
|= (given
& 0x00007000u
) >> 4;
8998 imm12
|= (given
& 0x04000000u
) >> 15;
8999 func (stream
, "#%u", imm12
);
9000 value_in_comment
= imm12
;
9006 unsigned int bits
= 0, imm
, imm8
, mod
;
9008 bits
|= (given
& 0x000000ffu
);
9009 bits
|= (given
& 0x00007000u
) >> 4;
9010 bits
|= (given
& 0x04000000u
) >> 15;
9011 imm8
= (bits
& 0x0ff);
9012 mod
= (bits
& 0xf00) >> 8;
9015 case 0: imm
= imm8
; break;
9016 case 1: imm
= ((imm8
<< 16) | imm8
); break;
9017 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
9018 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
9020 mod
= (bits
& 0xf80) >> 7;
9021 imm8
= (bits
& 0x07f) | 0x80;
9022 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
9024 func (stream
, "#%u", imm
);
9025 value_in_comment
= imm
;
9031 unsigned int imm
= 0;
9033 imm
|= (given
& 0x000000ffu
);
9034 imm
|= (given
& 0x00007000u
) >> 4;
9035 imm
|= (given
& 0x04000000u
) >> 15;
9036 imm
|= (given
& 0x000f0000u
) >> 4;
9037 func (stream
, "#%u", imm
);
9038 value_in_comment
= imm
;
9044 unsigned int imm
= 0;
9046 imm
|= (given
& 0x000f0000u
) >> 16;
9047 imm
|= (given
& 0x00000ff0u
) >> 0;
9048 imm
|= (given
& 0x0000000fu
) << 12;
9049 func (stream
, "#%u", imm
);
9050 value_in_comment
= imm
;
9056 unsigned int imm
= 0;
9058 imm
|= (given
& 0x000f0000u
) >> 4;
9059 imm
|= (given
& 0x00000fffu
) >> 0;
9060 func (stream
, "#%u", imm
);
9061 value_in_comment
= imm
;
9067 unsigned int imm
= 0;
9069 imm
|= (given
& 0x00000fffu
);
9070 imm
|= (given
& 0x000f0000u
) >> 4;
9071 func (stream
, "#%u", imm
);
9072 value_in_comment
= imm
;
9078 unsigned int reg
= (given
& 0x0000000fu
);
9079 unsigned int stp
= (given
& 0x00000030u
) >> 4;
9080 unsigned int imm
= 0;
9081 imm
|= (given
& 0x000000c0u
) >> 6;
9082 imm
|= (given
& 0x00007000u
) >> 10;
9084 func (stream
, "%s", arm_regnames
[reg
]);
9089 func (stream
, ", lsl #%u", imm
);
9095 func (stream
, ", lsr #%u", imm
);
9101 func (stream
, ", asr #%u", imm
);
9106 func (stream
, ", rrx");
9108 func (stream
, ", ror #%u", imm
);
9115 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9116 unsigned int U
= ! NEGATIVE_BIT_SET
;
9117 unsigned int op
= (given
& 0x00000f00) >> 8;
9118 unsigned int i12
= (given
& 0x00000fff);
9119 unsigned int i8
= (given
& 0x000000ff);
9120 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
9123 func (stream
, "[%s", arm_regnames
[Rn
]);
9124 if (U
) /* 12-bit positive immediate offset. */
9128 value_in_comment
= offset
;
9130 else if (Rn
== 15) /* 12-bit negative immediate offset. */
9131 offset
= - (int) i12
;
9132 else if (op
== 0x0) /* Shifted register offset. */
9134 unsigned int Rm
= (i8
& 0x0f);
9135 unsigned int sh
= (i8
& 0x30) >> 4;
9137 func (stream
, ", %s", arm_regnames
[Rm
]);
9139 func (stream
, ", lsl #%u", sh
);
9145 case 0xE: /* 8-bit positive immediate offset. */
9149 case 0xC: /* 8-bit negative immediate offset. */
9153 case 0xF: /* 8-bit + preindex with wb. */
9158 case 0xD: /* 8-bit - preindex with wb. */
9163 case 0xB: /* 8-bit + postindex. */
9168 case 0x9: /* 8-bit - postindex. */
9174 func (stream
, ", <undefined>]");
9179 func (stream
, "], #%d", (int) offset
);
9183 func (stream
, ", #%d", (int) offset
);
9184 func (stream
, writeback
? "]!" : "]");
9189 func (stream
, "\t; ");
9190 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
9198 unsigned int U
= ! NEGATIVE_BIT_SET
;
9199 unsigned int W
= WRITEBACK_BIT_SET
;
9200 unsigned int Rn
= (given
& 0x000f0000) >> 16;
9201 unsigned int off
= (given
& 0x000000ff);
9203 func (stream
, "[%s", arm_regnames
[Rn
]);
9209 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
9210 value_in_comment
= off
* 4 * (U
? 1 : -1);
9218 func (stream
, "], ");
9221 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
9222 value_in_comment
= off
* 4 * (U
? 1 : -1);
9226 func (stream
, "{%u}", off
);
9227 value_in_comment
= off
;
9235 unsigned int Sbit
= (given
& 0x01000000) >> 24;
9236 unsigned int type
= (given
& 0x00600000) >> 21;
9240 case 0: func (stream
, Sbit
? "sb" : "b"); break;
9241 case 1: func (stream
, Sbit
? "sh" : "h"); break;
9244 func (stream
, "??");
9247 func (stream
, "??");
9262 for (reg
= 0; reg
< 16; reg
++)
9263 if ((given
& (1 << reg
)) != 0)
9266 func (stream
, ", ");
9268 if (is_clrm
&& reg
== 13)
9269 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
9270 else if (is_clrm
&& reg
== 15)
9271 func (stream
, "%s", "APSR");
9273 func (stream
, "%s", arm_regnames
[reg
]);
9281 unsigned int msb
= (given
& 0x0000001f);
9282 unsigned int lsb
= 0;
9284 lsb
|= (given
& 0x000000c0u
) >> 6;
9285 lsb
|= (given
& 0x00007000u
) >> 10;
9286 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
9292 unsigned int width
= (given
& 0x0000001f) + 1;
9293 unsigned int lsb
= 0;
9295 lsb
|= (given
& 0x000000c0u
) >> 6;
9296 lsb
|= (given
& 0x00007000u
) >> 10;
9297 func (stream
, "#%u, #%u", lsb
, width
);
9303 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
9304 func (stream
, "%x", boff
);
9310 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
9311 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9312 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9315 offset
|= immA
<< 12;
9316 offset
|= immB
<< 2;
9317 offset
|= immC
<< 1;
9319 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
9321 info
->print_address_func (pc
+ 4 + offset
, info
);
9327 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
9328 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9329 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9332 offset
|= immA
<< 12;
9333 offset
|= immB
<< 2;
9334 offset
|= immC
<< 1;
9336 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
9338 info
->print_address_func (pc
+ 4 + offset
, info
);
9344 unsigned int immA
= (given
& 0x00010000u
) >> 16;
9345 unsigned int immB
= (given
& 0x000007feu
) >> 1;
9346 unsigned int immC
= (given
& 0x00000800u
) >> 11;
9349 offset
|= immA
<< 12;
9350 offset
|= immB
<< 2;
9351 offset
|= immC
<< 1;
9353 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
9355 info
->print_address_func (pc
+ 4 + offset
, info
);
9357 unsigned int T
= (given
& 0x00020000u
) >> 17;
9358 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
9359 unsigned int boffset
= (T
== 1) ? 4 : 2;
9360 func (stream
, ", ");
9361 func (stream
, "%x", endoffset
+ boffset
);
9367 unsigned int immh
= (given
& 0x000007feu
) >> 1;
9368 unsigned int imml
= (given
& 0x00000800u
) >> 11;
9374 info
->print_address_func (pc
+ 4 + imm32
, info
);
9380 unsigned int immh
= (given
& 0x000007feu
) >> 1;
9381 unsigned int imml
= (given
& 0x00000800u
) >> 11;
9387 info
->print_address_func (pc
+ 4 - imm32
, info
);
9393 unsigned int S
= (given
& 0x04000000u
) >> 26;
9394 unsigned int J1
= (given
& 0x00002000u
) >> 13;
9395 unsigned int J2
= (given
& 0x00000800u
) >> 11;
9401 offset
|= (given
& 0x003f0000) >> 4;
9402 offset
|= (given
& 0x000007ff) << 1;
9403 offset
-= (1 << 20);
9405 info
->print_address_func (pc
+ 4 + offset
, info
);
9411 unsigned int S
= (given
& 0x04000000u
) >> 26;
9412 unsigned int I1
= (given
& 0x00002000u
) >> 13;
9413 unsigned int I2
= (given
& 0x00000800u
) >> 11;
9417 offset
|= !(I1
^ S
) << 23;
9418 offset
|= !(I2
^ S
) << 22;
9419 offset
|= (given
& 0x03ff0000u
) >> 4;
9420 offset
|= (given
& 0x000007ffu
) << 1;
9421 offset
-= (1 << 24);
9424 /* BLX target addresses are always word aligned. */
9425 if ((given
& 0x00001000u
) == 0)
9428 info
->print_address_func (offset
, info
);
9434 unsigned int shift
= 0;
9436 shift
|= (given
& 0x000000c0u
) >> 6;
9437 shift
|= (given
& 0x00007000u
) >> 10;
9438 if (WRITEBACK_BIT_SET
)
9439 func (stream
, ", asr #%u", shift
);
9441 func (stream
, ", lsl #%u", shift
);
9442 /* else print nothing - lsl #0 */
9448 unsigned int rot
= (given
& 0x00000030) >> 4;
9451 func (stream
, ", ror #%u", rot
* 8);
9456 if ((given
& 0xf0) == 0x60)
9458 switch (given
& 0xf)
9460 case 0xf: func (stream
, "sy"); break;
9462 func (stream
, "#%d", (int) given
& 0xf);
9468 const char * opt
= data_barrier_option (given
& 0xf);
9470 func (stream
, "%s", opt
);
9472 func (stream
, "#%d", (int) given
& 0xf);
9477 if ((given
& 0xff) == 0)
9479 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
9489 else if ((given
& 0x20) == 0x20)
9492 unsigned sysm
= (given
& 0xf00) >> 8;
9494 sysm
|= (given
& 0x30);
9495 sysm
|= (given
& 0x00100000) >> 14;
9496 name
= banked_regname (sysm
);
9499 func (stream
, "%s", name
);
9501 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
9505 func (stream
, "%s", psr_name (given
& 0xff));
9510 if (((given
& 0xff) == 0)
9511 || ((given
& 0x20) == 0x20))
9514 unsigned sm
= (given
& 0xf0000) >> 16;
9516 sm
|= (given
& 0x30);
9517 sm
|= (given
& 0x00100000) >> 14;
9518 name
= banked_regname (sm
);
9521 func (stream
, "%s", name
);
9523 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
9526 func (stream
, "%s", psr_name (given
& 0xff));
9529 case '0': case '1': case '2': case '3': case '4':
9530 case '5': case '6': case '7': case '8': case '9':
9535 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
9540 func (stream
, "%lu", val
);
9541 value_in_comment
= val
;
9545 func (stream
, "%lu", val
+ 1);
9546 value_in_comment
= val
+ 1;
9550 func (stream
, "%lu", val
* 4);
9551 value_in_comment
= val
* 4;
9556 is_unpredictable
= TRUE
;
9560 is_unpredictable
= TRUE
;
9563 func (stream
, "%s", arm_regnames
[val
]);
9567 func (stream
, "%s", arm_conditional
[val
]);
9572 if (val
== ((1ul << width
) - 1))
9573 func (stream
, "%c", *c
);
9579 func (stream
, "%c", *c
);
9583 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
9588 func (stream
, "0x%lx", val
& 0xffffffffUL
);
9598 /* PR binutils/12534
9599 If we have a PC relative offset in an LDRD or STRD
9600 instructions then display the decoded address. */
9601 if (((given
>> 16) & 0xf) == 0xf)
9603 bfd_vma offset
= (given
& 0xff) * 4;
9605 if ((given
& (1 << 23)) == 0)
9607 func (stream
, "\t; ");
9608 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
9617 if (value_in_comment
> 32 || value_in_comment
< -16)
9618 func (stream
, "\t; 0x%lx", value_in_comment
);
9620 if (is_unpredictable
)
9621 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9627 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
9631 /* Print data bytes on INFO->STREAM. */
9634 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
9635 struct disassemble_info
*info
,
9638 switch (info
->bytes_per_chunk
)
9641 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
9644 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
9647 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
9654 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
9655 being displayed in symbol relative addresses.
9657 Also disallow private symbol, with __tagsym$$ prefix,
9658 from ARM RVCT toolchain being displayed. */
9661 arm_symbol_is_valid (asymbol
* sym
,
9662 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
9669 name
= bfd_asymbol_name (sym
);
9671 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
9674 /* Parse the string of disassembler options. */
9677 parse_arm_disassembler_options (const char *options
)
9681 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
9683 if (CONST_STRNEQ (opt
, "reg-names-"))
9686 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
9687 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
9689 regname_selected
= i
;
9693 if (i
>= NUM_ARM_OPTIONS
)
9694 /* xgettext: c-format */
9695 opcodes_error_handler (_("unrecognised register name set: %s"),
9698 else if (CONST_STRNEQ (opt
, "force-thumb"))
9700 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
9703 /* xgettext: c-format */
9704 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
9711 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
9712 enum map_type
*map_symbol
);
9714 /* Search back through the insn stream to determine if this instruction is
9715 conditionally executed. */
9718 find_ifthen_state (bfd_vma pc
,
9719 struct disassemble_info
*info
,
9725 /* COUNT is twice the number of instructions seen. It will be odd if we
9726 just crossed an instruction boundary. */
9729 unsigned int seen_it
;
9732 ifthen_address
= pc
;
9739 /* Scan backwards looking for IT instructions, keeping track of where
9740 instruction boundaries are. We don't know if something is actually an
9741 IT instruction until we find a definite instruction boundary. */
9744 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
9746 /* A symbol must be on an instruction boundary, and will not
9747 be within an IT block. */
9748 if (seen_it
&& (count
& 1))
9754 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
9759 insn
= (b
[0]) | (b
[1] << 8);
9761 insn
= (b
[1]) | (b
[0] << 8);
9764 if ((insn
& 0xf800) < 0xe800)
9766 /* Addr + 2 is an instruction boundary. See if this matches
9767 the expected boundary based on the position of the last
9774 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
9776 enum map_type type
= MAP_ARM
;
9777 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
9779 if (!found
|| (found
&& type
== MAP_THUMB
))
9781 /* This could be an IT instruction. */
9783 it_count
= count
>> 1;
9786 if ((insn
& 0xf800) >= 0xe800)
9789 count
= (count
+ 2) | 1;
9790 /* IT blocks contain at most 4 instructions. */
9791 if (count
>= 8 && !seen_it
)
9794 /* We found an IT instruction. */
9795 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
9796 if ((ifthen_state
& 0xf) == 0)
9800 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
9804 is_mapping_symbol (struct disassemble_info
*info
, int n
,
9805 enum map_type
*map_type
)
9809 name
= bfd_asymbol_name (info
->symtab
[n
]);
9810 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
9811 && (name
[2] == 0 || name
[2] == '.'))
9813 *map_type
= ((name
[1] == 'a') ? MAP_ARM
9814 : (name
[1] == 't') ? MAP_THUMB
9822 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
9823 Returns nonzero if *MAP_TYPE was set. */
9826 get_map_sym_type (struct disassemble_info
*info
,
9828 enum map_type
*map_type
)
9830 /* If the symbol is in a different section, ignore it. */
9831 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
9834 return is_mapping_symbol (info
, n
, map_type
);
9837 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
9838 Returns nonzero if *MAP_TYPE was set. */
9841 get_sym_code_type (struct disassemble_info
*info
,
9843 enum map_type
*map_type
)
9845 elf_symbol_type
*es
;
9848 /* If the symbol is in a different section, ignore it. */
9849 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
9852 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
9853 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
9855 /* If the symbol has function type then use that. */
9856 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
9858 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
9859 == ST_BRANCH_TO_THUMB
)
9860 *map_type
= MAP_THUMB
;
9862 *map_type
= MAP_ARM
;
9869 /* Search the mapping symbol state for instruction at pc. This is only
9870 applicable for elf target.
9872 There is an assumption Here, info->private_data contains the correct AND
9873 up-to-date information about current scan process. The information will be
9874 used to speed this search process.
9876 Return TRUE if the mapping state can be determined, and map_symbol
9877 will be updated accordingly. Otherwise, return FALSE. */
9880 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
9881 enum map_type
*map_symbol
)
9883 bfd_vma addr
, section_vma
= 0;
9884 int n
, last_sym
= -1;
9885 bfd_boolean found
= FALSE
;
9886 bfd_boolean can_use_search_opt_p
= FALSE
;
9888 /* Default to DATA. A text section is required by the ABI to contain an
9889 INSN mapping symbol at the start. A data section has no such
9890 requirement, hence if no mapping symbol is found the section must
9891 contain only data. This however isn't very useful if the user has
9892 fully stripped the binaries. If this is the case use the section
9893 attributes to determine the default. If we have no section default to
9894 INSN as well, as we may be disassembling some raw bytes on a baremetal
9895 HEX file or similar. */
9896 enum map_type type
= MAP_DATA
;
9897 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
9899 struct arm_private_data
*private_data
;
9901 if (info
->private_data
== NULL
9902 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
9905 private_data
= info
->private_data
;
9907 /* First, look for mapping symbols. */
9908 if (info
->symtab_size
!= 0)
9910 if (pc
<= private_data
->last_mapping_addr
)
9911 private_data
->last_mapping_sym
= -1;
9913 /* Start scanning at the start of the function, or wherever
9914 we finished last time. */
9915 n
= info
->symtab_pos
+ 1;
9917 /* If the last stop offset is different from the current one it means we
9918 are disassembling a different glob of bytes. As such the optimization
9919 would not be safe and we should start over. */
9920 can_use_search_opt_p
9921 = private_data
->last_mapping_sym
>= 0
9922 && info
->stop_offset
== private_data
->last_stop_offset
;
9924 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
9925 n
= private_data
->last_mapping_sym
;
9927 /* Look down while we haven't passed the location being disassembled.
9928 The reason for this is that there's no defined order between a symbol
9929 and an mapping symbol that may be at the same address. We may have to
9930 look at least one position ahead. */
9931 for (; n
< info
->symtab_size
; n
++)
9933 addr
= bfd_asymbol_value (info
->symtab
[n
]);
9936 if (get_map_sym_type (info
, n
, &type
))
9945 n
= info
->symtab_pos
;
9946 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
9947 n
= private_data
->last_mapping_sym
;
9949 /* No mapping symbol found at this address. Look backwards
9950 for a preceeding one, but don't go pass the section start
9951 otherwise a data section with no mapping symbol can pick up
9952 a text mapping symbol of a preceeding section. The documentation
9953 says section can be NULL, in which case we will seek up all the
9956 section_vma
= info
->section
->vma
;
9960 addr
= bfd_asymbol_value (info
->symtab
[n
]);
9961 if (addr
< section_vma
)
9964 if (get_map_sym_type (info
, n
, &type
))
9974 /* If no mapping symbol was found, try looking up without a mapping
9975 symbol. This is done by walking up from the current PC to the nearest
9976 symbol. We don't actually have to loop here since symtab_pos will
9977 contain the nearest symbol already. */
9980 n
= info
->symtab_pos
;
9981 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
9988 private_data
->last_mapping_sym
= last_sym
;
9989 private_data
->last_type
= type
;
9990 private_data
->last_stop_offset
= info
->stop_offset
;
9996 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
9997 of the supplied arm_feature_set structure with bitmasks indicating
9998 the supported base architectures and coprocessor extensions.
10000 FIXME: This could more efficiently implemented as a constant array,
10001 although it would also be less robust. */
10004 select_arm_features (unsigned long mach
,
10005 arm_feature_set
* features
)
10007 arm_feature_set arch_fset
;
10008 const arm_feature_set fpu_any
= FPU_ANY
;
10010 #undef ARM_SET_FEATURES
10011 #define ARM_SET_FEATURES(FSET) \
10013 const arm_feature_set fset = FSET; \
10014 arch_fset = fset; \
10017 /* When several architecture versions share the same bfd_mach_arm_XXX value
10018 the most featureful is chosen. */
10021 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
10022 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
10023 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
10024 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
10025 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
10026 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
10027 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
10028 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
10029 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
10030 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
10031 case bfd_mach_arm_ep9312
:
10032 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
10033 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
10035 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
10036 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
10037 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
10038 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
10039 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
10040 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
10041 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
10042 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
10043 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
10044 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
10045 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
10046 case bfd_mach_arm_8
:
10048 /* Add bits for extensions that Armv8.5-A recognizes. */
10049 arm_feature_set armv8_5_ext_fset
10050 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
10051 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
10052 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
10055 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
10056 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
10057 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
10058 case bfd_mach_arm_8_1M_MAIN
:
10059 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
10062 /* If the machine type is unknown allow all architecture types and all
10064 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
10068 #undef ARM_SET_FEATURES
10070 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
10071 and thus on bfd_mach_arm_XXX value. Therefore for a given
10072 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
10073 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
10077 /* NOTE: There are no checks in these routines that
10078 the relevant number of data bytes exist. */
10081 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
10083 unsigned char b
[4];
10086 int is_thumb
= FALSE
;
10087 int is_data
= FALSE
;
10089 unsigned int size
= 4;
10090 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
10091 bfd_boolean found
= FALSE
;
10092 struct arm_private_data
*private_data
;
10094 if (info
->disassembler_options
)
10096 parse_arm_disassembler_options (info
->disassembler_options
);
10098 /* To avoid repeated parsing of these options, we remove them here. */
10099 info
->disassembler_options
= NULL
;
10102 /* PR 10288: Control which instructions will be disassembled. */
10103 if (info
->private_data
== NULL
)
10105 static struct arm_private_data
private;
10107 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
10108 /* If the user did not use the -m command line switch then default to
10109 disassembling all types of ARM instruction.
10111 The info->mach value has to be ignored as this will be based on
10112 the default archictecture for the target and/or hints in the notes
10113 section, but it will never be greater than the current largest arm
10114 machine value (iWMMXt2), which is only equivalent to the V5TE
10115 architecture. ARM architectures have advanced beyond the machine
10116 value encoding, and these newer architectures would be ignored if
10117 the machine value was used.
10119 Ie the -m switch is used to restrict which instructions will be
10120 disassembled. If it is necessary to use the -m switch to tell
10121 objdump that an ARM binary is being disassembled, eg because the
10122 input is a raw binary file, but it is also desired to disassemble
10123 all ARM instructions then use "-marm". This will select the
10124 "unknown" arm architecture which is compatible with any ARM
10126 info
->mach
= bfd_mach_arm_unknown
;
10128 /* Compute the architecture bitmask from the machine number.
10129 Note: This assumes that the machine number will not change
10130 during disassembly.... */
10131 select_arm_features (info
->mach
, & private.features
);
10133 private.last_mapping_sym
= -1;
10134 private.last_mapping_addr
= 0;
10135 private.last_stop_offset
= 0;
10137 info
->private_data
= & private;
10140 private_data
= info
->private_data
;
10142 /* Decide if our code is going to be little-endian, despite what the
10143 function argument might say. */
10144 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
10146 /* For ELF, consult the symbol table to determine what kind of code
10147 or data we have. */
10148 if (info
->symtab_size
!= 0
10149 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
10154 enum map_type type
= MAP_ARM
;
10156 found
= mapping_symbol_for_insn (pc
, info
, &type
);
10157 last_sym
= private_data
->last_mapping_sym
;
10159 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
10160 is_data
= (private_data
->last_type
== MAP_DATA
);
10162 /* Look a little bit ahead to see if we should print out
10163 two or four bytes of data. If there's a symbol,
10164 mapping or otherwise, after two bytes then don't
10168 size
= 4 - (pc
& 3);
10169 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
10171 addr
= bfd_asymbol_value (info
->symtab
[n
]);
10173 && (info
->section
== NULL
10174 || info
->section
== info
->symtab
[n
]->section
))
10176 if (addr
- pc
< size
)
10181 /* If the next symbol is after three bytes, we need to
10182 print only part of the data, so that we can use either
10183 .byte or .short. */
10185 size
= (pc
& 1) ? 1 : 2;
10189 if (info
->symbols
!= NULL
)
10191 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
10193 coff_symbol_type
* cs
;
10195 cs
= coffsymbol (*info
->symbols
);
10196 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
10197 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
10198 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
10199 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
10200 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
10202 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
10205 /* If no mapping symbol has been found then fall back to the type
10206 of the function symbol. */
10207 elf_symbol_type
* es
;
10210 es
= *(elf_symbol_type
**)(info
->symbols
);
10211 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
10214 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
10215 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
10217 else if (bfd_asymbol_flavour (*info
->symbols
)
10218 == bfd_target_mach_o_flavour
)
10220 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
10222 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
10230 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
10232 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
10234 info
->bytes_per_line
= 4;
10236 /* PR 10263: Disassemble data if requested to do so by the user. */
10237 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
10241 /* Size was already set above. */
10242 info
->bytes_per_chunk
= size
;
10243 printer
= print_insn_data
;
10245 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
10248 for (i
= size
- 1; i
>= 0; i
--)
10249 given
= b
[i
] | (given
<< 8);
10251 for (i
= 0; i
< (int) size
; i
++)
10252 given
= b
[i
] | (given
<< 8);
10254 else if (!is_thumb
)
10256 /* In ARM mode endianness is a straightforward issue: the instruction
10257 is four bytes long and is either ordered 0123 or 3210. */
10258 printer
= print_insn_arm
;
10259 info
->bytes_per_chunk
= 4;
10262 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
10264 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
10266 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
10270 /* In Thumb mode we have the additional wrinkle of two
10271 instruction lengths. Fortunately, the bits that determine
10272 the length of the current instruction are always to be found
10273 in the first two bytes. */
10274 printer
= print_insn_thumb16
;
10275 info
->bytes_per_chunk
= 2;
10278 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
10280 given
= (b
[0]) | (b
[1] << 8);
10282 given
= (b
[1]) | (b
[0] << 8);
10286 /* These bit patterns signal a four-byte Thumb
10288 if ((given
& 0xF800) == 0xF800
10289 || (given
& 0xF800) == 0xF000
10290 || (given
& 0xF800) == 0xE800)
10292 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
10294 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
10296 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
10298 printer
= print_insn_thumb32
;
10303 if (ifthen_address
!= pc
)
10304 find_ifthen_state (pc
, info
, little_code
);
10308 if ((ifthen_state
& 0xf) == 0x8)
10309 ifthen_next_state
= 0;
10311 ifthen_next_state
= (ifthen_state
& 0xe0)
10312 | ((ifthen_state
& 0xf) << 1);
10318 info
->memory_error_func (status
, pc
, info
);
10321 if (info
->flags
& INSN_HAS_RELOC
)
10322 /* If the instruction has a reloc associated with it, then
10323 the offset field in the instruction will actually be the
10324 addend for the reloc. (We are using REL type relocs).
10325 In such cases, we can ignore the pc when computing
10326 addresses, since the addend is not currently pc-relative. */
10329 printer (pc
, info
, given
);
10333 ifthen_state
= ifthen_next_state
;
10334 ifthen_address
+= size
;
10340 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
10342 /* Detect BE8-ness and record it in the disassembler info. */
10343 if (info
->flavour
== bfd_target_elf_flavour
10344 && info
->section
!= NULL
10345 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
10346 info
->endian_code
= BFD_ENDIAN_LITTLE
;
10348 return print_insn (pc
, info
, FALSE
);
10352 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
10354 return print_insn (pc
, info
, TRUE
);
10357 const disasm_options_and_args_t
*
10358 disassembler_options_arm (void)
10360 static disasm_options_and_args_t
*opts_and_args
;
10362 if (opts_and_args
== NULL
)
10364 disasm_options_t
*opts
;
10367 opts_and_args
= XNEW (disasm_options_and_args_t
);
10368 opts_and_args
->args
= NULL
;
10370 opts
= &opts_and_args
->options
;
10371 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
10372 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
10374 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
10376 opts
->name
[i
] = regnames
[i
].name
;
10377 if (regnames
[i
].description
!= NULL
)
10378 opts
->description
[i
] = _(regnames
[i
].description
);
10380 opts
->description
[i
] = NULL
;
10382 /* The array we return must be NULL terminated. */
10383 opts
->name
[i
] = NULL
;
10384 opts
->description
[i
] = NULL
;
10387 return opts_and_args
;
10391 print_arm_disassembler_options (FILE *stream
)
10393 unsigned int i
, max_len
= 0;
10394 fprintf (stream
, _("\n\
10395 The following ARM specific disassembler options are supported for use with\n\
10396 the -M switch:\n"));
10398 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
10400 unsigned int len
= strlen (regnames
[i
].name
);
10405 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
10406 fprintf (stream
, " %s%*c %s\n",
10408 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
10409 _(regnames
[i
].description
));