1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "disassemble.h"
26 #include "opcode/arm.h"
28 #include "safe-ctype.h"
29 #include "libiberty.h"
30 #include "floatformat.h"
32 /* FIXME: This shouldn't be done here. */
33 #include "coff/internal.h"
37 #include "elf/internal.h"
41 /* FIXME: Belongs in global header. */
43 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
46 /* Cached mapping symbol state. */
54 struct arm_private_data
56 /* The features to use when disassembling optional instructions. */
57 arm_feature_set features
;
59 /* Whether any mapping symbols are present in the provided symbol
60 table. -1 if we do not know yet, otherwise 0 or 1. */
61 int has_mapping_symbols
;
63 /* Track the last type (although this doesn't seem to be useful) */
64 enum map_type last_type
;
66 /* Tracking symbol table information */
68 bfd_vma last_mapping_addr
;
73 arm_feature_set arch
; /* Architecture defining this insn. */
74 unsigned long value
; /* If arch is 0 then value is a sentinel. */
75 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
76 const char * assembler
; /* How to disassemble this insn. */
81 arm_feature_set arch
; /* Architecture defining this insn. */
82 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
83 const char *assembler
; /* How to disassemble this insn. */
86 /* print_insn_coprocessor recognizes the following format control codes:
90 %c print condition code (always bits 28-31 in ARM mode)
91 %q print shifter argument
92 %u print condition code (unconditional in ARM mode,
93 UNPREDICTABLE if not AL in Thumb)
94 %A print address for ldc/stc/ldf/stf instruction
95 %B print vstm/vldm register list
96 %I print cirrus signed shift immediate: bits 0..3|4..6
97 %F print the COUNT field of a LFM/SFM instruction.
98 %P print floating point precision in arithmetic insn
99 %Q print floating point precision in ldf/stf insn
100 %R print floating point rounding mode
102 %<bitfield>c print as a condition code (for vsel)
103 %<bitfield>r print as an ARM register
104 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
105 %<bitfield>ru as %<>r but each u register must be unique.
106 %<bitfield>d print the bitfield in decimal
107 %<bitfield>k print immediate for VFPv3 conversion instruction
108 %<bitfield>x print the bitfield in hex
109 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
110 %<bitfield>f print a floating point constant if >7 else a
111 floating point register
112 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
113 %<bitfield>g print as an iWMMXt 64-bit register
114 %<bitfield>G print as an iWMMXt general purpose or control register
115 %<bitfield>D print as a NEON D register
116 %<bitfield>Q print as a NEON Q register
117 %<bitfield>V print as a NEON D or Q register
118 %<bitfield>E print a quarter-float immediate value
120 %y<code> print a single precision VFP reg.
121 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
122 %z<code> print a double precision VFP reg
123 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
125 %<bitfield>'c print specified char iff bitfield is all ones
126 %<bitfield>`c print specified char iff bitfield is all zeroes
127 %<bitfield>?ab... select from array of values in big endian order
129 %L print as an iWMMXt N/M width field.
130 %Z print the Immediate of a WSHUFH instruction.
131 %l like 'A' except use byte offsets for 'B' & 'H'
133 %i print 5-bit immediate in bits 8,3..0
135 %r print register offset address for wldt/wstr instruction. */
137 enum opcode_sentinel_enum
139 SENTINEL_IWMMXT_START
= 1,
141 SENTINEL_GENERIC_START
144 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
145 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
146 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
147 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
149 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
151 static const struct opcode32 coprocessor_opcodes
[] =
153 /* XScale instructions. */
154 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
155 0x0e200010, 0x0fff0ff0,
156 "mia%c\tacc0, %0-3r, %12-15r"},
157 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
158 0x0e280010, 0x0fff0ff0,
159 "miaph%c\tacc0, %0-3r, %12-15r"},
160 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
161 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
162 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
163 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
164 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
165 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
167 /* Intel Wireless MMX technology instructions. */
168 {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
169 {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
170 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
171 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
172 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
173 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
174 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
175 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
176 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
177 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
178 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
179 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
180 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
181 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
182 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
183 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
184 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
185 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
186 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
187 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
188 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
189 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
190 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
191 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
192 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
193 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
194 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
195 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
196 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
197 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
198 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
199 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
200 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
201 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
202 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
203 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
204 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
205 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
206 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
207 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
208 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
209 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
210 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
211 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
212 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
213 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
214 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
215 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
216 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
217 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
218 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
219 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
220 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
221 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
222 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
223 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
224 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
225 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
226 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
227 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
228 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
229 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
230 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
231 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
232 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
233 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
234 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
235 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
236 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
237 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
238 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
239 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
240 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
241 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
242 0x0e800120, 0x0f800ff0,
243 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
244 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
245 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
246 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
247 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
248 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
249 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
250 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
251 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
252 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
253 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
254 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
255 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
256 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
257 0x0e8000a0, 0x0f800ff0,
258 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
259 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
260 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
261 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
262 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
263 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
264 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
265 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
266 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
267 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
268 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
269 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
270 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
271 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
272 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
273 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
274 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
275 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
276 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
277 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
278 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
279 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
280 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
281 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
282 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
283 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
284 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
285 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
286 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
287 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
288 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
289 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
290 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
291 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
292 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
293 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
294 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
295 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
296 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
297 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
298 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
299 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
300 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
301 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
302 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
303 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
304 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
305 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
306 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
307 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
308 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
309 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
310 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
311 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
312 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
313 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
314 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
315 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
316 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
317 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
318 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
319 {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
320 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
321 {ARM_FEATURE_CORE_LOW (0),
322 SENTINEL_IWMMXT_END
, 0, "" },
324 /* Floating point coprocessor (FPA) instructions. */
325 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
326 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
327 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
328 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
329 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
330 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
331 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
332 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
333 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
334 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
335 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
336 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
337 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
338 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
339 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
340 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
341 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
342 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
343 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
344 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
345 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
346 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
347 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
348 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
349 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
350 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
351 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
352 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
353 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
354 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
355 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
356 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
357 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
358 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
359 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
360 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
361 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
362 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
363 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
364 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
365 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
366 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
367 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
368 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
369 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
370 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
371 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
372 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
373 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
374 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
375 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
376 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
377 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
378 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
379 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
380 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
381 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
382 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
383 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
384 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
385 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
386 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
387 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
388 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
389 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
390 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
391 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
392 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
393 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
394 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
395 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
396 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
397 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
398 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
399 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
400 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
401 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
402 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
403 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
404 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
405 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
406 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
407 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
408 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
409 {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
410 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
412 /* ARMv8-M Mainline Security Extensions instructions. */
413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
414 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
415 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
416 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
418 /* Register load/store. */
419 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
420 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
421 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
422 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
423 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
424 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
425 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
426 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
427 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
428 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
429 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
430 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
431 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
432 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
433 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
434 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
435 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
436 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
437 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
438 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
439 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
440 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
441 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
442 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
443 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
444 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
445 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
446 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
447 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
448 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
449 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
450 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
452 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
453 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
454 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
455 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
456 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
457 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
458 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
459 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
461 /* Data transfer between ARM and NEON registers. */
462 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
463 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
464 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
465 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
466 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
467 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
468 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
469 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
471 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
473 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
475 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
477 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
479 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
481 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
483 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
485 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
487 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
489 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
490 /* Half-precision conversion instructions. */
491 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
492 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
493 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
494 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
495 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
496 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
497 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
498 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
500 /* Floating point coprocessor (VFP) instructions. */
501 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
502 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
503 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
504 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
505 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
506 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
507 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
508 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
509 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
510 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
511 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
512 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
513 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
514 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
515 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
516 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
517 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
518 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
519 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
520 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
521 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
522 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
523 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
524 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
525 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
526 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
527 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
528 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
529 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
530 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
531 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
532 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
533 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
534 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
535 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
536 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
537 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
538 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
539 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
540 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
541 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
542 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
543 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
544 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
545 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
546 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
547 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
548 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
549 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
550 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
551 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
552 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
553 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
554 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
555 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
556 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
557 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
558 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
559 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
560 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
561 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
562 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
563 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
564 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
565 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
566 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
567 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
568 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
569 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
570 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
571 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
572 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
573 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
574 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
575 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
576 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
577 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
578 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
579 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
580 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
581 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
582 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
583 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
584 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
585 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
586 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
587 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
588 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
589 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
590 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
591 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
592 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
593 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
594 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
595 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
596 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
597 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
598 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
599 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
600 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
601 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
602 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
603 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
604 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
605 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
606 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
607 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
608 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
609 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
610 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
611 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
612 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
613 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
614 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
615 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
616 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
617 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
618 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
619 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
620 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
621 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
622 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
623 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
624 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
625 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
626 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
627 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
628 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
629 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
630 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
631 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
632 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
633 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
634 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
635 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
636 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
637 {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
638 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
640 /* Cirrus coprocessor instructions. */
641 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
642 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
643 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
644 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
645 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
646 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
647 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
648 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
649 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
650 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
651 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
652 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
653 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
654 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
655 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
656 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
657 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
658 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
659 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
660 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
661 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
662 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
663 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
664 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
665 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
666 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
667 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
668 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
669 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
670 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
671 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
672 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
673 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
674 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
675 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
676 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
677 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
678 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
679 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
680 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
681 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
682 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
683 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
684 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
685 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
686 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
687 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
688 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
689 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
690 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
691 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
692 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
693 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
694 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
695 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
696 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
697 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
698 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
699 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
700 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
701 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
702 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
703 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
704 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
705 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
706 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
707 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
708 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
709 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
710 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
711 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
712 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
713 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
714 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
715 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
716 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
717 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
718 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
719 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
720 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
721 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
722 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
723 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
724 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
725 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
726 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
727 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
728 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
729 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
730 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
731 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
732 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
733 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
734 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
735 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
736 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
737 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
738 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
739 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
740 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
741 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
742 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
743 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
744 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
745 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
746 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
747 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
748 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
749 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
750 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
751 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
752 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
753 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
754 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
755 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
756 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
757 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
758 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
759 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
760 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
761 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
762 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
763 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
764 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
765 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
766 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
767 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
768 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
769 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
770 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
771 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
772 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
773 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
774 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
775 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
776 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
777 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
778 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
779 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
780 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
781 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
782 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
783 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
784 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
785 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
786 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
787 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
788 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
789 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
790 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
791 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
792 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
793 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
794 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
795 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
796 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
797 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
798 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
799 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
800 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
801 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
802 0x0e000600, 0x0ff00f10,
803 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
804 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
805 0x0e100600, 0x0ff00f10,
806 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
807 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
808 0x0e200600, 0x0ff00f10,
809 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
810 {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
811 0x0e300600, 0x0ff00f10,
812 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
814 /* VFP Fused multiply add instructions. */
815 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
816 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
817 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
818 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
819 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
820 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
821 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
822 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
823 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
824 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
825 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
826 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
827 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
828 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
829 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
830 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
833 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
834 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
835 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
836 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
837 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
838 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
839 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
840 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
841 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
842 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
843 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
844 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
845 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
846 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
847 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
848 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
849 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
850 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
851 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
852 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
853 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
854 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
855 {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
856 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
858 /* Generic coprocessor instructions. */
859 {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
861 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
863 0x0c500000, 0x0ff00000,
864 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
866 0x0e000000, 0x0f000010,
867 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
869 0x0e10f010, 0x0f10f010,
870 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
872 0x0e100010, 0x0f100010,
873 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
875 0x0e000010, 0x0f100010,
876 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
878 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
880 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
882 /* V6 coprocessor instructions. */
883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
884 0xfc500000, 0xfff00000,
885 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
887 0xfc400000, 0xfff00000,
888 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
890 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
891 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
892 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
893 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
894 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
895 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
896 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
897 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
898 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
900 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
901 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
902 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
903 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
904 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
905 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
906 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
907 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
908 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
909 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
910 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
912 /* Dot Product instructions in the space of coprocessor 13. */
913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
914 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
916 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
918 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
919 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
920 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
921 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
922 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
923 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
924 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
926 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
927 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
928 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
929 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
930 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
931 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
932 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
933 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
934 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
936 /* V5 coprocessor instructions. */
937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
938 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
940 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
942 0xfe000000, 0xff000010,
943 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
945 0xfe000010, 0xff100010,
946 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
948 0xfe100010, 0xff100010,
949 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
951 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
952 cp_num: bit <11:8> == 0b1001.
953 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
954 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
955 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
956 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
957 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
958 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
959 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
960 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
961 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
962 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
963 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
964 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
965 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
967 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
968 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
969 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
970 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
971 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
973 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
974 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
975 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
976 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
977 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
979 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
980 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
981 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
982 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
983 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
985 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
986 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
987 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
988 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
989 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
991 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
992 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
993 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
994 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
995 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
997 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
998 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
999 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1000 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1001 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1003 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1004 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1005 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1006 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1007 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1009 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1010 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1011 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1012 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1013 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1014 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1015 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1016 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1017 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1018 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1019 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1021 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1022 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1023 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1025 /* ARMv8.3 javascript conversion instruction. */
1026 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1027 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1029 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1032 /* Neon opcode table: This does not encode the top byte -- that is
1033 checked by the print_insn_neon routine, as it depends on whether we are
1034 doing thumb32 or arm32 disassembly. */
1036 /* print_insn_neon recognizes the following format control codes:
1040 %c print condition code
1041 %u print condition code (unconditional in ARM mode,
1042 UNPREDICTABLE if not AL in Thumb)
1043 %A print v{st,ld}[1234] operands
1044 %B print v{st,ld}[1234] any one operands
1045 %C print v{st,ld}[1234] single->all operands
1047 %E print vmov, vmvn, vorr, vbic encoded constant
1048 %F print vtbl,vtbx register list
1050 %<bitfield>r print as an ARM register
1051 %<bitfield>d print the bitfield in decimal
1052 %<bitfield>e print the 2^N - bitfield in decimal
1053 %<bitfield>D print as a NEON D register
1054 %<bitfield>Q print as a NEON Q register
1055 %<bitfield>R print as a NEON D or Q register
1056 %<bitfield>Sn print byte scaled width limited by n
1057 %<bitfield>Tn print short scaled width limited by n
1058 %<bitfield>Un print long scaled width limited by n
1060 %<bitfield>'c print specified char iff bitfield is all ones
1061 %<bitfield>`c print specified char iff bitfield is all zeroes
1062 %<bitfield>?ab... select from array of values in big endian order. */
1064 static const struct opcode32 neon_opcodes
[] =
1067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1068 0xf2b00840, 0xffb00850,
1069 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1070 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1071 0xf2b00000, 0xffb00810,
1072 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1074 /* Move data element to all lanes. */
1075 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1076 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1077 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1078 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1079 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1080 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1084 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1086 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1088 /* Half-precision conversions. */
1089 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1090 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1091 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1092 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1094 /* NEON fused multiply add instructions. */
1095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1096 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1097 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1098 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1099 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1100 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1101 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1102 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1104 /* Two registers, miscellaneous. */
1105 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1106 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1107 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1108 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1110 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1111 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1112 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1113 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1114 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1115 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1116 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1117 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1118 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1119 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1120 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1121 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1122 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1123 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1124 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1125 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1126 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1127 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1128 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1130 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1131 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1132 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1133 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1134 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1136 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1137 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1138 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1139 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1140 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1142 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1144 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1146 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1148 0xf3b20300, 0xffb30fd0,
1149 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1150 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1151 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1152 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1153 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1154 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1155 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1156 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1157 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1158 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1159 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1160 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1161 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1162 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1163 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1164 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1165 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1166 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1167 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1168 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1169 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1170 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1171 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1172 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1173 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1174 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1175 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1176 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1177 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1178 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1179 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1180 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1181 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1182 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1183 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1184 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1185 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1186 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1187 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1188 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1189 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1190 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1191 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1192 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1193 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1194 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1195 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1196 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1197 0xf3bb0600, 0xffbf0e10,
1198 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1199 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1200 0xf3b70600, 0xffbf0e10,
1201 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1203 /* Three registers of the same length. */
1204 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1205 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1206 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1207 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1208 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1209 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1210 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1211 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1212 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1213 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1214 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1215 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1216 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1217 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1218 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1219 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1220 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1221 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1222 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1223 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1224 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1225 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1226 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1227 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1228 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1229 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1230 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1231 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1232 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1233 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1234 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1235 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1236 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1237 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1238 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1239 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1240 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1241 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1242 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1243 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1244 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1245 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1246 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1247 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1249 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1250 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1251 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1253 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1254 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1255 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1256 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1257 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1258 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1259 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1260 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1261 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1262 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1263 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1265 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1266 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1267 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1268 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1269 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1270 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1271 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1272 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1273 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1274 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1275 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1277 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1278 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1279 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1280 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1281 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1282 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1283 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1284 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1285 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1286 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1287 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1289 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1290 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1291 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1292 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1293 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1294 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1295 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1296 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1297 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1298 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1299 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1301 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1302 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1303 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1304 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1305 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1306 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1307 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1308 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1309 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1311 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1313 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1314 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1315 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1317 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1318 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1319 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1320 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1321 0xf2000b00, 0xff800f10,
1322 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1323 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1324 0xf2000b10, 0xff800f10,
1325 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1326 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1327 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1328 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1329 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1330 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1331 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1332 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1333 0xf3000b00, 0xff800f10,
1334 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1335 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1336 0xf2000000, 0xfe800f10,
1337 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1338 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1339 0xf2000010, 0xfe800f10,
1340 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1341 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1342 0xf2000100, 0xfe800f10,
1343 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1344 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1345 0xf2000200, 0xfe800f10,
1346 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1347 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1348 0xf2000210, 0xfe800f10,
1349 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1350 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1351 0xf2000300, 0xfe800f10,
1352 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1353 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1354 0xf2000310, 0xfe800f10,
1355 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1356 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1357 0xf2000400, 0xfe800f10,
1358 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1359 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1360 0xf2000410, 0xfe800f10,
1361 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1362 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1363 0xf2000500, 0xfe800f10,
1364 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1365 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1366 0xf2000510, 0xfe800f10,
1367 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1368 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1369 0xf2000600, 0xfe800f10,
1370 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1371 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1372 0xf2000610, 0xfe800f10,
1373 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1374 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1375 0xf2000700, 0xfe800f10,
1376 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1377 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1378 0xf2000710, 0xfe800f10,
1379 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1380 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1381 0xf2000910, 0xfe800f10,
1382 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1383 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1384 0xf2000a00, 0xfe800f10,
1385 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1386 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1387 0xf2000a10, 0xfe800f10,
1388 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1389 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1390 0xf3000b10, 0xff800f10,
1391 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1392 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1393 0xf3000c10, 0xff800f10,
1394 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1396 /* One register and an immediate value. */
1397 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1398 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1400 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1401 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1402 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1403 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1404 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1405 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1406 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1407 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1408 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1409 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1410 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1411 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1412 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1413 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1414 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1415 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1416 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1417 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1418 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1419 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1420 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1421 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1422 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1424 /* Two registers and a shift amount. */
1425 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1426 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1427 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1428 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1429 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1430 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1431 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1432 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1433 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1434 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1435 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1436 0xf2880950, 0xfeb80fd0,
1437 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1439 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1440 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1441 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1443 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1444 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1445 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1446 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1447 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1449 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1450 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1451 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1453 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1454 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1455 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1456 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1457 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1458 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1459 0xf2900950, 0xfeb00fd0,
1460 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1461 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1462 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1463 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1464 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1465 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1466 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1467 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1468 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1469 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1470 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1471 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1472 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1473 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1474 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1475 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1476 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1477 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1478 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1479 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1480 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1481 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1482 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1483 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1484 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1485 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1486 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1487 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1488 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1489 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1490 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1492 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1494 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1495 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1496 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1498 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1499 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1500 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1502 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1504 0xf2a00950, 0xfea00fd0,
1505 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1507 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1508 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1509 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1511 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1513 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1515 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1516 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1517 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1519 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1521 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1522 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1523 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1524 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1525 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1526 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1527 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1528 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1529 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1531 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1532 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1533 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1535 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1536 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1537 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1538 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1539 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1540 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1541 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1542 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1543 0xf2a00e10, 0xfea00e90,
1544 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1546 0xf2a00c10, 0xfea00e90,
1547 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1549 /* Three registers of different lengths. */
1550 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1551 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1552 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1553 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1554 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1555 0xf2800400, 0xff800f50,
1556 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1558 0xf2800600, 0xff800f50,
1559 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1560 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1561 0xf2800900, 0xff800f50,
1562 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1563 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1564 0xf2800b00, 0xff800f50,
1565 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1566 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1567 0xf2800d00, 0xff800f50,
1568 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1570 0xf3800400, 0xff800f50,
1571 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1573 0xf3800600, 0xff800f50,
1574 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1576 0xf2800000, 0xfe800f50,
1577 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1578 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1579 0xf2800100, 0xfe800f50,
1580 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf2800200, 0xfe800f50,
1583 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1584 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1585 0xf2800300, 0xfe800f50,
1586 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1587 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1588 0xf2800500, 0xfe800f50,
1589 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1591 0xf2800700, 0xfe800f50,
1592 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf2800800, 0xfe800f50,
1595 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1597 0xf2800a00, 0xfe800f50,
1598 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1599 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1600 0xf2800c00, 0xfe800f50,
1601 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1603 /* Two registers and a scalar. */
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1605 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1607 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1608 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1609 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1611 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1612 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1613 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1614 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1615 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1616 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1617 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1618 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1619 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1620 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1621 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1622 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1623 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1624 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1625 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1626 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1627 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1628 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1629 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1630 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1631 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1632 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1633 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1634 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1635 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1636 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1637 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1638 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1639 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1640 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1641 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1642 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1643 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1644 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1645 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1646 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1647 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1648 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1649 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1650 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1651 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1652 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1653 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1654 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1655 0xf2800240, 0xfe800f50,
1656 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1658 0xf2800640, 0xfe800f50,
1659 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1660 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1661 0xf2800a40, 0xfe800f50,
1662 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1664 0xf2800e40, 0xff800f50,
1665 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1667 0xf2800f40, 0xff800f50,
1668 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1670 0xf3800e40, 0xff800f50,
1671 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1672 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1673 0xf3800f40, 0xff800f50,
1674 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1677 /* Element and structure load/store. */
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1679 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1680 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1681 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1682 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1683 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1686 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1687 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1688 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1689 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1692 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1693 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1694 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1695 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1698 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1699 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1700 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1701 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1703 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1704 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1705 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1706 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1707 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1710 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1711 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1712 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1713 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1715 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1717 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1720 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
1721 ordered: they must be searched linearly from the top to obtain a correct
1724 /* print_insn_arm recognizes the following format control codes:
1728 %a print address for ldr/str instruction
1729 %s print address for ldr/str halfword/signextend instruction
1730 %S like %s but allow UNPREDICTABLE addressing
1731 %b print branch destination
1732 %c print condition code (always bits 28-31)
1733 %m print register mask for ldm/stm instruction
1734 %o print operand2 (immediate or register + shift)
1735 %p print 'p' iff bits 12-15 are 15
1736 %t print 't' iff bit 21 set and bit 24 clear
1737 %B print arm BLX(1) destination
1738 %C print the PSR sub type.
1739 %U print barrier type.
1740 %P print address for pli instruction.
1742 %<bitfield>r print as an ARM register
1743 %<bitfield>T print as an ARM register + 1
1744 %<bitfield>R as %r but r15 is UNPREDICTABLE
1745 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1746 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1747 %<bitfield>d print the bitfield in decimal
1748 %<bitfield>W print the bitfield plus one in decimal
1749 %<bitfield>x print the bitfield in hex
1750 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
1752 %<bitfield>'c print specified char iff bitfield is all ones
1753 %<bitfield>`c print specified char iff bitfield is all zeroes
1754 %<bitfield>?ab... select from array of values in big endian order
1756 %e print arm SMI operand (bits 0..7,8..19).
1757 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
1758 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
1759 %R print the SPSR/CPSR or banked register of an MRS. */
1761 static const struct opcode32 arm_opcodes
[] =
1763 /* ARM instructions. */
1764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
1765 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
1767 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
1770 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1772 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1774 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
1776 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
1778 0x00800090, 0x0fa000f0,
1779 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
1781 0x00a00090, 0x0fa000f0,
1782 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1784 /* V8.2 RAS extension instructions. */
1785 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
1786 0xe320f010, 0xffffffff, "esb"},
1788 /* V8 instructions. */
1789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1790 0x0320f005, 0x0fffffff, "sevl"},
1791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1792 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
1794 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1795 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1796 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1798 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
1800 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1801 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1802 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1803 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1804 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1805 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1806 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1807 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1808 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1809 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1810 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1811 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1812 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1813 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1814 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1815 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1816 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1817 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1818 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1819 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
1820 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1821 /* CRC32 instructions. */
1822 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1823 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1824 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1825 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1826 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1827 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1828 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1829 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1830 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1831 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1832 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
1833 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1835 /* Privileged Access Never extension instructions. */
1836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
1837 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1839 /* Virtualization Extension instructions. */
1840 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
1841 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1843 /* Integer Divide Extension instructions. */
1844 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
1845 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1846 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
1847 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1849 /* MP Extension instructions. */
1850 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1852 /* Speculation Barriers. */
1853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
1854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
1855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
1857 /* V7 instructions. */
1858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
1859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
1866 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1868 /* ARM V6T2 instructions. */
1869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1870 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1872 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1874 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1876 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1879 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
1880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1881 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1883 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
1884 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1885 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
1886 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1888 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
1890 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1892 /* ARM Security extension instructions. */
1893 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
1894 0x01600070, 0x0ff000f0, "smc%c\t%e"},
1896 /* ARM V6K instructions. */
1897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1898 0xf57ff01f, 0xffffffff, "clrex"},
1899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1900 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1902 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1904 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1906 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1908 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1910 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1912 /* ARMv8.5-A instructions. */
1913 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
1915 /* ARM V6K NOP hints. */
1916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1917 0x0320f001, 0x0fffffff, "yield%c"},
1918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1919 0x0320f002, 0x0fffffff, "wfe%c"},
1920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1921 0x0320f003, 0x0fffffff, "wfi%c"},
1922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1923 0x0320f004, 0x0fffffff, "sev%c"},
1924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
1925 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1927 /* ARM V6 instructions. */
1928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1929 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1931 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1933 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1935 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1937 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1939 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1941 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1943 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1945 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1947 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1949 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1951 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1953 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1955 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1957 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1959 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1961 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1963 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1965 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1966 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1967 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1969 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1971 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1973 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1975 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1977 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1979 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1981 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1983 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1985 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1987 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1989 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1991 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1993 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1995 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1997 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1999 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
2000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2001 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
2002 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2003 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
2004 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2005 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
2006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2007 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
2008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2009 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
2010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2011 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
2012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2013 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
2014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2015 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
2016 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2017 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
2018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2019 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
2020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2021 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
2022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2023 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
2024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2025 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
2026 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2027 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
2028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2029 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
2030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2031 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
2032 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2033 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2035 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2037 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2039 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2041 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2042 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2043 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2044 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2045 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2046 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2047 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2048 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2049 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2050 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2051 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2053 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2055 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2057 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2058 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2059 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2060 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2061 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2062 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2063 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2064 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2065 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2067 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2069 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2071 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2072 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2073 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2074 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2075 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2076 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2077 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2078 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2079 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2081 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2083 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2085 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2087 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2088 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2089 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2091 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2093 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2095 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2097 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2099 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2101 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2103 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2104 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2105 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2106 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2107 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2108 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2109 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2111 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2113 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2115 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2117 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2118 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2119 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2120 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2121 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2123 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2125 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2127 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2129 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2131 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2132 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2133 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2135 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2137 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2139 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2141 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2142 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2143 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2144 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2145 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2147 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2149 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2151 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2153 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2155 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2157 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2159 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2161 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2163 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2164 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2165 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2166 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2167 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2169 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
2171 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2173 /* V5J instruction. */
2174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
2175 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2177 /* V5 Instructions. */
2178 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2179 0xe1200070, 0xfff000f0,
2180 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2182 0xfa000000, 0xfe000000, "blx\t%B"},
2183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2184 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2185 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
2186 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2188 /* V5E "El Segundo" Instructions. */
2189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2190 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2192 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
2194 0xf450f000, 0xfc70f000, "pld\t%a"},
2195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2196 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2198 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2199 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2200 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2202 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2205 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2207 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2210 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2212 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2214 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2215 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2216 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2219 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2221 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2223 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2225 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2227 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2228 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2229 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2230 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2232 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2233 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
2234 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2235 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2236 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2237 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
2238 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
2239 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2241 /* ARM Instructions. */
2242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2243 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2246 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2248 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2250 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2252 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2254 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2256 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2259 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2260 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2261 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2262 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2263 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2264 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2265 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2268 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
2269 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2270 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2271 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2272 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
2273 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2274 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2277 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2279 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2280 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2281 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2284 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2286 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2288 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2291 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2293 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2295 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2298 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2300 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2302 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2305 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2307 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2308 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2309 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2311 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2312 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2313 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2314 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2315 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2316 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2318 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2319 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2321 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2322 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2323 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2326 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2328 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2330 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2332 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
2333 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2334 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
2335 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2336 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
2337 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2340 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2342 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2344 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2347 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2349 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2351 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2354 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2355 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2356 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2357 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2358 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2361 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2363 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2365 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2368 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2370 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2372 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2375 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2377 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2379 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2381 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2383 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2385 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2387 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2389 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2390 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2391 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2392 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2393 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2394 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2397 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2398 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2399 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2400 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2401 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2404 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
2405 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2406 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2409 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2412 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2413 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2414 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2416 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2417 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2419 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2421 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2422 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2423 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2424 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2425 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2426 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2427 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2428 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2429 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2430 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2431 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2432 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2433 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2434 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2435 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2437 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2439 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2440 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2441 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2442 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2443 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2444 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2445 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2447 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2449 0x092d0000, 0x0fff0000, "push%c\t%m"},
2450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2451 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2453 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2456 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2458 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2459 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2460 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2461 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2462 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2463 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2464 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2466 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2468 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2470 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2472 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2474 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2476 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2477 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2478 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2479 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2480 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2482 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2483 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2484 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2485 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2486 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2488 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2490 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2492 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2495 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2497 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
2501 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
2502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
2503 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
2504 {ARM_FEATURE_CORE_LOW (0),
2505 0x00000000, 0x00000000, 0}
2508 /* print_insn_thumb16 recognizes the following format control codes:
2510 %S print Thumb register (bits 3..5 as high number if bit 6 set)
2511 %D print Thumb register (bits 0..2 as high number if bit 7 set)
2512 %<bitfield>I print bitfield as a signed decimal
2513 (top bit of range being the sign bit)
2514 %N print Thumb register mask (with LR)
2515 %O print Thumb register mask (with PC)
2516 %M print Thumb register mask
2517 %b print CZB's 6-bit unsigned branch destination
2518 %s print Thumb right-shift immediate (6..10; 0 == 32).
2519 %c print the condition code
2520 %C print the condition code, or "s" if not conditional
2521 %x print warning if conditional an not at end of IT block"
2522 %X print "\t; unpredictable <IT:code>" if conditional
2523 %I print IT instruction suffix and operands
2524 %W print Thumb Writeback indicator for LDMIA
2525 %<bitfield>r print bitfield as an ARM register
2526 %<bitfield>d print bitfield as a decimal
2527 %<bitfield>H print (bitfield * 2) as a decimal
2528 %<bitfield>W print (bitfield * 4) as a decimal
2529 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
2530 %<bitfield>B print Thumb branch destination (signed displacement)
2531 %<bitfield>c print bitfield as a condition code
2532 %<bitnum>'c print specified char iff bit is one
2533 %<bitnum>?ab print a if bit is one else print b. */
2535 static const struct opcode16 thumb_opcodes
[] =
2537 /* Thumb instructions. */
2539 /* ARMv8-M Security Extensions instructions. */
2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
2541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
2543 /* ARM V8 instructions. */
2544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
2545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
2546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
2548 /* ARM V6K no-argument instructions. */
2549 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
2550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
2551 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
2552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
2553 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
2554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2556 /* ARM V6T2 instructions. */
2557 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2558 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2559 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2560 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
2564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2565 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2569 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2570 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2572 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2574 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2576 /* ARM V5 ISA extends Thumb. */
2577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
2578 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
2579 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
2580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
2581 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
2582 /* ARM V4T ISA (Thumb v1). */
2583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2584 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2587 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2589 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2593 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2595 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2597 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2599 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2601 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2603 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
2607 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
2608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2609 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2611 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
2612 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
2614 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2615 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2616 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2617 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2618 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2619 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2620 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2621 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2623 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2624 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2625 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2626 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2627 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2628 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2631 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2632 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2633 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2637 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2642 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2643 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2644 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2646 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2649 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2652 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2653 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2654 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2655 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2656 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2657 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2658 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2661 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2663 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2666 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2667 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2668 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2671 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
2673 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
2682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2686 /* The E800 .. FFFF range is unconditionally redirected to the
2687 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2688 are processed via that table. Thus, we can never encounter a
2689 bare "second half of BL/BLX(1)" instruction here. */
2690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
2691 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2694 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2695 We adopt the convention that hw1 is the high 16 bits of .value and
2696 .mask, hw2 the low 16 bits.
2698 print_insn_thumb32 recognizes the following format control codes:
2702 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2703 %M print a modified 12-bit immediate (same location)
2704 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2705 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2706 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
2707 %S print a possibly-shifted Rm
2709 %L print address for a ldrd/strd instruction
2710 %a print the address of a plain load/store
2711 %w print the width and signedness of a core load/store
2712 %m print register mask for ldm/stm
2714 %E print the lsb and width fields of a bfc/bfi instruction
2715 %F print the lsb and width fields of a sbfx/ubfx instruction
2716 %b print a conditional branch offset
2717 %B print an unconditional branch offset
2718 %s print the shift field of an SSAT instruction
2719 %R print the rotation field of an SXT instruction
2720 %U print barrier type.
2721 %P print address for pli instruction.
2722 %c print the condition code
2723 %x print warning if conditional an not at end of IT block"
2724 %X print "\t; unpredictable <IT:code>" if conditional
2726 %<bitfield>d print bitfield in decimal
2727 %<bitfield>D print bitfield plus one in decimal
2728 %<bitfield>W print bitfield*4 in decimal
2729 %<bitfield>r print bitfield as an ARM register
2730 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
2731 %<bitfield>c print bitfield as a condition code
2733 %<bitfield>'c print specified char iff bitfield is all ones
2734 %<bitfield>`c print specified char iff bitfield is all zeroes
2735 %<bitfield>?ab... select from array of values in big endian order
2737 With one exception at the bottom (done because BL and BLX(1) need
2738 to come dead last), this table was machine-sorted first in
2739 decreasing order of number of bits set in the mask, then in
2740 increasing numeric order of mask, then in increasing numeric order
2741 of opcode. This order is not the clearest for a human reader, but
2742 is guaranteed never to catch a special-case bit pattern with a more
2743 general mask, which is important, because this instruction encoding
2744 makes heavy use of special-case bit patterns. */
2745 static const struct opcode32 thumb32_opcodes
[] =
2747 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
2748 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
2749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2750 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2752 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2753 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2754 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
2756 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2758 /* ARM V8.2 RAS extension instructions. */
2759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
2760 0xf3af8010, 0xffffffff, "esb"},
2762 /* V8 instructions. */
2763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2764 0xf3af8005, 0xffffffff, "sevl%c.w"},
2765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2766 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2767 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2768 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2769 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2770 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2771 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2772 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2773 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2774 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2775 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2776 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2777 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2778 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2780 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2782 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2783 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2784 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2786 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2788 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2790 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2792 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2793 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
2794 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2796 /* CRC32 instructions. */
2797 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2798 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
2799 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2800 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
2801 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2802 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
2803 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2804 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
2805 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2806 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
2807 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
2808 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
2810 /* Speculation Barriers. */
2811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
2812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
2813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
2815 /* V7 instructions. */
2816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2823 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
2824 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2825 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
2826 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2828 /* Virtualization Extension instructions. */
2829 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2830 /* We skip ERET as that is SUBS pc, lr, #0. */
2832 /* MP Extension instructions. */
2833 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
2835 /* Security extension instructions. */
2836 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2838 /* ARMv8.5-A instructions. */
2839 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
2841 /* Instructions defined in the basic V6T2 set. */
2842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
2843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
2844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
2847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2848 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2851 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2852 0xf3bf8f2f, 0xffffffff, "clrex%c"},
2853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2854 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2856 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2858 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2860 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2862 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2864 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2866 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2868 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2870 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2872 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2874 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2876 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2878 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2879 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2880 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2881 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2882 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2884 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2886 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2888 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2890 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2892 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2894 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2896 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2898 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2899 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
2900 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2902 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2904 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2906 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2908 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2910 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2912 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2914 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2916 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2918 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2920 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2922 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2924 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2926 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2928 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2930 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2932 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2934 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2936 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2938 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2940 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2942 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2944 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2946 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2948 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2950 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2952 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2954 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2956 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2958 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2960 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2962 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2964 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2966 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2968 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2970 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2972 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2974 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2976 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2978 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2980 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2982 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2984 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2986 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2988 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2990 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2992 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2994 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2996 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
2998 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3000 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3002 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3004 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3006 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3007 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3008 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3010 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
3011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3012 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3014 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3016 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3018 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3020 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3022 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3024 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3026 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3028 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3030 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3032 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3034 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3036 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3038 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3040 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3042 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3044 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3046 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3048 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3050 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3052 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3054 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3056 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3058 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3060 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3062 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3064 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3066 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3068 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3070 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3072 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3074 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3075 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3076 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3078 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3080 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3082 0xf810f000, 0xff70f000, "pld%c\t%a"},
3083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3084 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3086 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3088 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3090 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3092 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3094 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3096 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3098 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3100 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3102 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3104 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3106 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3108 0xfb100000, 0xfff000c0,
3109 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3111 0xfbc00080, 0xfff000c0,
3112 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3114 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3116 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3118 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3120 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3122 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3123 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3124 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3126 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3127 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3128 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3130 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3132 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3134 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3136 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3138 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3140 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3141 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3142 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3144 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3146 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3148 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3149 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3150 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3151 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3152 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3154 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3156 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3157 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3158 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3160 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3162 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3164 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3166 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3168 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3170 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3171 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3172 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3173 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3174 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3175 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3176 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3178 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3180 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3182 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3183 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3184 0xe9400000, 0xff500000,
3185 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3187 0xe9500000, 0xff500000,
3188 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3190 0xe8600000, 0xff700000,
3191 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3193 0xe8700000, 0xff700000,
3194 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3196 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3197 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3198 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3200 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3201 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3202 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3203 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3204 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3206 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3208 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3210 /* These have been 32-bit since the invention of Thumb. */
3211 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3212 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3213 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
3214 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3217 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3218 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
3219 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3222 static const char *const arm_conditional
[] =
3223 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3224 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3226 static const char *const arm_fp_const
[] =
3227 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3229 static const char *const arm_shift
[] =
3230 {"lsl", "lsr", "asr", "ror"};
3235 const char *description
;
3236 const char *reg_names
[16];
3240 static const arm_regname regnames
[] =
3242 { "reg-names-raw", N_("Select raw register names"),
3243 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3244 { "reg-names-gcc", N_("Select register names used by GCC"),
3245 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3246 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3247 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3248 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
3249 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
3250 { "reg-names-apcs", N_("Select register names used in the APCS"),
3251 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3252 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3253 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3254 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3255 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
3258 static const char *const iwmmxt_wwnames
[] =
3259 {"b", "h", "w", "d"};
3261 static const char *const iwmmxt_wwssnames
[] =
3262 {"b", "bus", "bc", "bss",
3263 "h", "hus", "hc", "hss",
3264 "w", "wus", "wc", "wss",
3265 "d", "dus", "dc", "dss"
3268 static const char *const iwmmxt_regnames
[] =
3269 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3270 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3273 static const char *const iwmmxt_cregnames
[] =
3274 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3275 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3278 /* Default to GCC register name set. */
3279 static unsigned int regname_selected
= 1;
3281 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
3282 #define arm_regnames regnames[regname_selected].reg_names
3284 static bfd_boolean force_thumb
= FALSE
;
3286 /* Current IT instruction state. This contains the same state as the IT
3287 bits in the CPSR. */
3288 static unsigned int ifthen_state
;
3289 /* IT state for the next instruction. */
3290 static unsigned int ifthen_next_state
;
3291 /* The address of the insn for which the IT state is valid. */
3292 static bfd_vma ifthen_address
;
3293 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3294 /* Indicates that the current Conditional state is unconditional or outside
3296 #define COND_UNCOND 16
3301 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3302 Returns pointer to following character of the format string and
3303 fills in *VALUEP and *WIDTHP with the extracted value and number of
3304 bits extracted. WIDTHP can be NULL. */
3307 arm_decode_bitfield (const char *ptr
,
3309 unsigned long *valuep
,
3312 unsigned long value
= 0;
3320 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
3321 start
= start
* 10 + *ptr
- '0';
3323 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
3324 end
= end
* 10 + *ptr
- '0';
3330 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
3333 while (*ptr
++ == ',');
3341 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
3342 bfd_boolean print_shift
)
3344 func (stream
, "%s", arm_regnames
[given
& 0xf]);
3346 if ((given
& 0xff0) != 0)
3348 if ((given
& 0x10) == 0)
3350 int amount
= (given
& 0xf80) >> 7;
3351 int shift
= (given
& 0x60) >> 5;
3357 func (stream
, ", rrx");
3365 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
3367 func (stream
, ", #%d", amount
);
3369 else if ((given
& 0x80) == 0x80)
3370 func (stream
, "\t; <illegal shifter operand>");
3371 else if (print_shift
)
3372 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
3373 arm_regnames
[(given
& 0xf00) >> 8]);
3375 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
3384 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3385 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3386 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3387 #define PRE_BIT_SET (given & (1 << P_BIT))
3389 /* Print one coprocessor instruction on INFO->STREAM.
3390 Return TRUE if the instuction matched, FALSE if this is not a
3391 recognised coprocessor instruction. */
3394 print_insn_coprocessor (bfd_vma pc
,
3395 struct disassemble_info
*info
,
3399 const struct opcode32
*insn
;
3400 void *stream
= info
->stream
;
3401 fprintf_ftype func
= info
->fprintf_func
;
3403 unsigned long value
= 0;
3406 struct arm_private_data
*private_data
= info
->private_data
;
3407 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
3409 allowed_arches
= private_data
->features
;
3411 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
3413 unsigned long u_reg
= 16;
3414 bfd_boolean is_unpredictable
= FALSE
;
3415 signed long value_in_comment
= 0;
3418 if (ARM_FEATURE_ZERO (insn
->arch
))
3419 switch (insn
->value
)
3421 case SENTINEL_IWMMXT_START
:
3422 if (info
->mach
!= bfd_mach_arm_XScale
3423 && info
->mach
!= bfd_mach_arm_iWMMXt
3424 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
3427 while ((! ARM_FEATURE_ZERO (insn
->arch
))
3428 && insn
->value
!= SENTINEL_IWMMXT_END
);
3431 case SENTINEL_IWMMXT_END
:
3434 case SENTINEL_GENERIC_START
:
3435 allowed_arches
= private_data
->features
;
3443 value
= insn
->value
;
3444 cp_num
= (given
>> 8) & 0xf;
3448 /* The high 4 bits are 0xe for Arm conditional instructions, and
3449 0xe for arm unconditional instructions. The rest of the
3450 encoding is the same. */
3452 value
|= 0xe0000000;
3460 /* Only match unconditional instuctions against unconditional
3462 if ((given
& 0xf0000000) == 0xf0000000)
3469 cond
= (given
>> 28) & 0xf;
3475 if ((given
& mask
) != value
)
3478 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
3481 if (insn
->value
== 0xfe000010 /* mcr2 */
3482 || insn
->value
== 0xfe100010 /* mrc2 */
3483 || insn
->value
== 0xfc100000 /* ldc2 */
3484 || insn
->value
== 0xfc000000) /* stc2 */
3486 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
3487 is_unpredictable
= TRUE
;
3489 else if (insn
->value
== 0x0e000000 /* cdp */
3490 || insn
->value
== 0xfe000000 /* cdp2 */
3491 || insn
->value
== 0x0e000010 /* mcr */
3492 || insn
->value
== 0x0e100010 /* mrc */
3493 || insn
->value
== 0x0c100000 /* ldc */
3494 || insn
->value
== 0x0c000000) /* stc */
3496 /* Floating-point instructions. */
3497 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
3501 for (c
= insn
->assembler
; *c
; c
++)
3508 func (stream
, "%%");
3513 int rn
= (given
>> 16) & 0xf;
3514 bfd_vma offset
= given
& 0xff;
3516 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
3518 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
3520 /* Not unindexed. The offset is scaled. */
3522 /* vldr.16/vstr.16 will shift the address
3523 left by 1 bit only. */
3524 offset
= offset
* 2;
3526 offset
= offset
* 4;
3528 if (NEGATIVE_BIT_SET
)
3531 value_in_comment
= offset
;
3537 func (stream
, ", #%d]%s",
3539 WRITEBACK_BIT_SET
? "!" : "");
3540 else if (NEGATIVE_BIT_SET
)
3541 func (stream
, ", #-0]");
3549 if (WRITEBACK_BIT_SET
)
3552 func (stream
, ", #%d", (int) offset
);
3553 else if (NEGATIVE_BIT_SET
)
3554 func (stream
, ", #-0");
3558 func (stream
, ", {%s%d}",
3559 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
3561 value_in_comment
= offset
;
3564 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
3566 func (stream
, "\t; ");
3567 /* For unaligned PCs, apply off-by-alignment
3569 info
->print_address_func (offset
+ pc
3570 + info
->bytes_per_chunk
* 2
3579 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
3580 int offset
= (given
>> 1) & 0x3f;
3583 func (stream
, "{d%d}", regno
);
3584 else if (regno
+ offset
> 32)
3585 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
3587 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
3592 if (cond
!= COND_UNCOND
)
3593 is_unpredictable
= TRUE
;
3597 if (cond
!= COND_UNCOND
&& cp_num
== 9)
3598 is_unpredictable
= TRUE
;
3600 func (stream
, "%s", arm_conditional
[cond
]);
3604 /* Print a Cirrus/DSP shift immediate. */
3605 /* Immediates are 7bit signed ints with bits 0..3 in
3606 bits 0..3 of opcode and bits 4..6 in bits 5..7
3611 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
3613 /* Is ``imm'' a negative number? */
3617 func (stream
, "%d", imm
);
3623 switch (given
& 0x00408000)
3640 switch (given
& 0x00080080)
3652 func (stream
, _("<illegal precision>"));
3658 switch (given
& 0x00408000)
3676 switch (given
& 0x60)
3692 case '0': case '1': case '2': case '3': case '4':
3693 case '5': case '6': case '7': case '8': case '9':
3697 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
3703 is_unpredictable
= TRUE
;
3708 /* Eat the 'u' character. */
3712 is_unpredictable
= TRUE
;
3715 func (stream
, "%s", arm_regnames
[value
]);
3718 if (given
& (1 << 6))
3722 func (stream
, "d%ld", value
);
3727 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
3729 func (stream
, "q%ld", value
>> 1);
3732 func (stream
, "%ld", value
);
3733 value_in_comment
= value
;
3737 /* Converts immediate 8 bit back to float value. */
3738 unsigned floatVal
= (value
& 0x80) << 24
3739 | (value
& 0x3F) << 19
3740 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
3742 /* Quarter float have a maximum value of 31.0.
3743 Get floating point value multiplied by 1e7.
3744 The maximum value stays in limit of a 32-bit int. */
3746 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
3747 (16 + (value
& 0xF));
3749 if (!(decVal
% 1000000))
3750 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
3751 floatVal
, value
& 0x80 ? '-' : ' ',
3753 decVal
% 10000000 / 1000000);
3754 else if (!(decVal
% 10000))
3755 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
3756 floatVal
, value
& 0x80 ? '-' : ' ',
3758 decVal
% 10000000 / 10000);
3760 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
3761 floatVal
, value
& 0x80 ? '-' : ' ',
3762 decVal
/ 10000000, decVal
% 10000000);
3767 int from
= (given
& (1 << 7)) ? 32 : 16;
3768 func (stream
, "%ld", from
- value
);
3774 func (stream
, "#%s", arm_fp_const
[value
& 7]);
3776 func (stream
, "f%ld", value
);
3781 func (stream
, "%s", iwmmxt_wwnames
[value
]);
3783 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
3787 func (stream
, "%s", iwmmxt_regnames
[value
]);
3790 func (stream
, "%s", iwmmxt_cregnames
[value
]);
3794 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
3801 func (stream
, "eq");
3805 func (stream
, "vs");
3809 func (stream
, "ge");
3813 func (stream
, "gt");
3817 func (stream
, "??");
3825 func (stream
, "%c", *c
);
3829 if (value
== ((1ul << width
) - 1))
3830 func (stream
, "%c", *c
);
3833 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
3844 int single
= *c
++ == 'y';
3849 case '4': /* Sm pair */
3850 case '0': /* Sm, Dm */
3851 regno
= given
& 0x0000000f;
3855 regno
+= (given
>> 5) & 1;
3858 regno
+= ((given
>> 5) & 1) << 4;
3861 case '1': /* Sd, Dd */
3862 regno
= (given
>> 12) & 0x0000000f;
3866 regno
+= (given
>> 22) & 1;
3869 regno
+= ((given
>> 22) & 1) << 4;
3872 case '2': /* Sn, Dn */
3873 regno
= (given
>> 16) & 0x0000000f;
3877 regno
+= (given
>> 7) & 1;
3880 regno
+= ((given
>> 7) & 1) << 4;
3883 case '3': /* List */
3885 regno
= (given
>> 12) & 0x0000000f;
3889 regno
+= (given
>> 22) & 1;
3892 regno
+= ((given
>> 22) & 1) << 4;
3899 func (stream
, "%c%d", single
? 's' : 'd', regno
);
3903 int count
= given
& 0xff;
3910 func (stream
, "-%c%d",
3918 func (stream
, ", %c%d", single
? 's' : 'd',
3924 switch (given
& 0x00400100)
3926 case 0x00000000: func (stream
, "b"); break;
3927 case 0x00400000: func (stream
, "h"); break;
3928 case 0x00000100: func (stream
, "w"); break;
3929 case 0x00400100: func (stream
, "d"); break;
3937 /* given (20, 23) | given (0, 3) */
3938 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
3939 func (stream
, "%d", (int) value
);
3944 /* This is like the 'A' operator, except that if
3945 the width field "M" is zero, then the offset is
3946 *not* multiplied by four. */
3948 int offset
= given
& 0xff;
3949 int multiplier
= (given
& 0x00000100) ? 4 : 1;
3951 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
3955 value_in_comment
= offset
* multiplier
;
3956 if (NEGATIVE_BIT_SET
)
3957 value_in_comment
= - value_in_comment
;
3963 func (stream
, ", #%s%d]%s",
3964 NEGATIVE_BIT_SET
? "-" : "",
3965 offset
* multiplier
,
3966 WRITEBACK_BIT_SET
? "!" : "");
3968 func (stream
, "], #%s%d",
3969 NEGATIVE_BIT_SET
? "-" : "",
3970 offset
* multiplier
);
3979 int imm4
= (given
>> 4) & 0xf;
3980 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
3981 int ubit
= ! NEGATIVE_BIT_SET
;
3982 const char *rm
= arm_regnames
[given
& 0xf];
3983 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
3989 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
3991 func (stream
, ", lsl #%d", imm4
);
3998 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
4000 func (stream
, ", lsl #%d", imm4
);
4002 if (puw_bits
== 5 || puw_bits
== 7)
4007 func (stream
, "INVALID");
4015 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
4016 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
4026 func (stream
, "%c", *c
);
4029 if (value_in_comment
> 32 || value_in_comment
< -16)
4030 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
4032 if (is_unpredictable
)
4033 func (stream
, UNPREDICTABLE_INSTRUCTION
);
4040 /* Decodes and prints ARM addressing modes. Returns the offset
4041 used in the address, if any, if it is worthwhile printing the
4042 offset as a hexadecimal value in a comment at the end of the
4043 line of disassembly. */
4046 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
4048 void *stream
= info
->stream
;
4049 fprintf_ftype func
= info
->fprintf_func
;
4052 if (((given
& 0x000f0000) == 0x000f0000)
4053 && ((given
& 0x02000000) == 0))
4055 offset
= given
& 0xfff;
4057 func (stream
, "[pc");
4061 /* Pre-indexed. Elide offset of positive zero when
4063 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
4064 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4066 if (NEGATIVE_BIT_SET
)
4071 /* Cope with the possibility of write-back
4072 being used. Probably a very dangerous thing
4073 for the programmer to do, but who are we to
4075 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
4077 else /* Post indexed. */
4079 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4081 /* Ie ignore the offset. */
4085 func (stream
, "\t; ");
4086 info
->print_address_func (offset
, info
);
4091 func (stream
, "[%s",
4092 arm_regnames
[(given
>> 16) & 0xf]);
4096 if ((given
& 0x02000000) == 0)
4098 /* Elide offset of positive zero when non-writeback. */
4099 offset
= given
& 0xfff;
4100 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
4101 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4105 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
4106 arm_decode_shift (given
, func
, stream
, TRUE
);
4109 func (stream
, "]%s",
4110 WRITEBACK_BIT_SET
? "!" : "");
4114 if ((given
& 0x02000000) == 0)
4116 /* Always show offset. */
4117 offset
= given
& 0xfff;
4118 func (stream
, "], #%s%d",
4119 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4123 func (stream
, "], %s",
4124 NEGATIVE_BIT_SET
? "-" : "");
4125 arm_decode_shift (given
, func
, stream
, TRUE
);
4128 if (NEGATIVE_BIT_SET
)
4132 return (signed long) offset
;
4135 /* Print one neon instruction on INFO->STREAM.
4136 Return TRUE if the instuction matched, FALSE if this is not a
4137 recognised neon instruction. */
4140 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
4142 const struct opcode32
*insn
;
4143 void *stream
= info
->stream
;
4144 fprintf_ftype func
= info
->fprintf_func
;
4148 if ((given
& 0xef000000) == 0xef000000)
4150 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
4151 unsigned long bit28
= given
& (1 << 28);
4153 given
&= 0x00ffffff;
4155 given
|= 0xf3000000;
4157 given
|= 0xf2000000;
4159 else if ((given
& 0xff000000) == 0xf9000000)
4160 given
^= 0xf9000000 ^ 0xf4000000;
4165 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
4167 if ((given
& insn
->mask
) == insn
->value
)
4169 signed long value_in_comment
= 0;
4170 bfd_boolean is_unpredictable
= FALSE
;
4173 for (c
= insn
->assembler
; *c
; c
++)
4180 func (stream
, "%%");
4184 if (thumb
&& ifthen_state
)
4185 is_unpredictable
= TRUE
;
4189 if (thumb
&& ifthen_state
)
4190 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
4195 static const unsigned char enc
[16] =
4197 0x4, 0x14, /* st4 0,1 */
4209 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
4210 int rn
= ((given
>> 16) & 0xf);
4211 int rm
= ((given
>> 0) & 0xf);
4212 int align
= ((given
>> 4) & 0x3);
4213 int type
= ((given
>> 8) & 0xf);
4214 int n
= enc
[type
] & 0xf;
4215 int stride
= (enc
[type
] >> 4) + 1;
4220 for (ix
= 0; ix
!= n
; ix
++)
4221 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
4223 func (stream
, "d%d", rd
);
4225 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
4226 func (stream
, "}, [%s", arm_regnames
[rn
]);
4228 func (stream
, " :%d", 32 << align
);
4233 func (stream
, ", %s", arm_regnames
[rm
]);
4239 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
4240 int rn
= ((given
>> 16) & 0xf);
4241 int rm
= ((given
>> 0) & 0xf);
4242 int idx_align
= ((given
>> 4) & 0xf);
4244 int size
= ((given
>> 10) & 0x3);
4245 int idx
= idx_align
>> (size
+ 1);
4246 int length
= ((given
>> 8) & 3) + 1;
4250 if (length
> 1 && size
> 0)
4251 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
4257 int amask
= (1 << size
) - 1;
4258 if ((idx_align
& (1 << size
)) != 0)
4262 if ((idx_align
& amask
) == amask
)
4264 else if ((idx_align
& amask
) != 0)
4271 if (size
== 2 && (idx_align
& 2) != 0)
4273 align
= (idx_align
& 1) ? 16 << size
: 0;
4277 if ((size
== 2 && (idx_align
& 3) != 0)
4278 || (idx_align
& 1) != 0)
4285 if ((idx_align
& 3) == 3)
4287 align
= (idx_align
& 3) * 64;
4290 align
= (idx_align
& 1) ? 32 << size
: 0;
4298 for (i
= 0; i
< length
; i
++)
4299 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
4300 rd
+ i
* stride
, idx
);
4301 func (stream
, "}, [%s", arm_regnames
[rn
]);
4303 func (stream
, " :%d", align
);
4308 func (stream
, ", %s", arm_regnames
[rm
]);
4314 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
4315 int rn
= ((given
>> 16) & 0xf);
4316 int rm
= ((given
>> 0) & 0xf);
4317 int align
= ((given
>> 4) & 0x1);
4318 int size
= ((given
>> 6) & 0x3);
4319 int type
= ((given
>> 8) & 0x3);
4321 int stride
= ((given
>> 5) & 0x1);
4324 if (stride
&& (n
== 1))
4331 for (ix
= 0; ix
!= n
; ix
++)
4332 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
4334 func (stream
, "d%d[]", rd
);
4336 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
4337 func (stream
, "}, [%s", arm_regnames
[rn
]);
4340 align
= (8 * (type
+ 1)) << size
;
4342 align
= (size
> 1) ? align
>> 1 : align
;
4343 if (type
== 2 || (type
== 0 && !size
))
4344 func (stream
, " :<bad align %d>", align
);
4346 func (stream
, " :%d", align
);
4352 func (stream
, ", %s", arm_regnames
[rm
]);
4358 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
4359 int size
= (given
>> 20) & 3;
4360 int reg
= raw_reg
& ((4 << size
) - 1);
4361 int ix
= raw_reg
>> size
>> 2;
4363 func (stream
, "d%d[%d]", reg
, ix
);
4368 /* Neon encoded constant for mov, mvn, vorr, vbic. */
4371 int cmode
= (given
>> 8) & 0xf;
4372 int op
= (given
>> 5) & 0x1;
4373 unsigned long value
= 0, hival
= 0;
4378 bits
|= ((given
>> 24) & 1) << 7;
4379 bits
|= ((given
>> 16) & 7) << 4;
4380 bits
|= ((given
>> 0) & 15) << 0;
4384 shift
= (cmode
>> 1) & 3;
4385 value
= (unsigned long) bits
<< (8 * shift
);
4388 else if (cmode
< 12)
4390 shift
= (cmode
>> 1) & 1;
4391 value
= (unsigned long) bits
<< (8 * shift
);
4394 else if (cmode
< 14)
4396 shift
= (cmode
& 1) + 1;
4397 value
= (unsigned long) bits
<< (8 * shift
);
4398 value
|= (1ul << (8 * shift
)) - 1;
4401 else if (cmode
== 14)
4405 /* Bit replication into bytes. */
4411 for (ix
= 7; ix
>= 0; ix
--)
4413 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
4415 value
= (value
<< 8) | mask
;
4417 hival
= (hival
<< 8) | mask
;
4423 /* Byte replication. */
4424 value
= (unsigned long) bits
;
4430 /* Floating point encoding. */
4433 value
= (unsigned long) (bits
& 0x7f) << 19;
4434 value
|= (unsigned long) (bits
& 0x80) << 24;
4435 tmp
= bits
& 0x40 ? 0x3c : 0x40;
4436 value
|= (unsigned long) tmp
<< 24;
4442 func (stream
, "<illegal constant %.8x:%x:%x>",
4450 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
4454 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
4460 unsigned char valbytes
[4];
4463 /* Do this a byte at a time so we don't have to
4464 worry about the host's endianness. */
4465 valbytes
[0] = value
& 0xff;
4466 valbytes
[1] = (value
>> 8) & 0xff;
4467 valbytes
[2] = (value
>> 16) & 0xff;
4468 valbytes
[3] = (value
>> 24) & 0xff;
4470 floatformat_to_double
4471 (& floatformat_ieee_single_little
, valbytes
,
4474 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
4478 func (stream
, "#%ld\t; 0x%.8lx",
4479 (long) (((value
& 0x80000000L
) != 0)
4480 ? value
| ~0xffffffffL
: value
),
4485 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
4496 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
4497 int num
= (given
>> 8) & 0x3;
4500 func (stream
, "{d%d}", regno
);
4501 else if (num
+ regno
>= 32)
4502 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
4504 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
4509 case '0': case '1': case '2': case '3': case '4':
4510 case '5': case '6': case '7': case '8': case '9':
4513 unsigned long value
;
4515 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
4520 func (stream
, "%s", arm_regnames
[value
]);
4523 func (stream
, "%ld", value
);
4524 value_in_comment
= value
;
4527 func (stream
, "%ld", (1ul << width
) - value
);
4533 /* Various width encodings. */
4535 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
4540 if (*c
>= '0' && *c
<= '9')
4542 else if (*c
>= 'a' && *c
<= 'f')
4543 limit
= *c
- 'a' + 10;
4549 if (value
< low
|| value
> high
)
4550 func (stream
, "<illegal width %d>", base
<< value
);
4552 func (stream
, "%d", base
<< value
);
4556 if (given
& (1 << 6))
4560 func (stream
, "d%ld", value
);
4565 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
4567 func (stream
, "q%ld", value
>> 1);
4573 func (stream
, "%c", *c
);
4577 if (value
== ((1ul << width
) - 1))
4578 func (stream
, "%c", *c
);
4581 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
4595 func (stream
, "%c", *c
);
4598 if (value_in_comment
> 32 || value_in_comment
< -16)
4599 func (stream
, "\t; 0x%lx", value_in_comment
);
4601 if (is_unpredictable
)
4602 func (stream
, UNPREDICTABLE_INSTRUCTION
);
4610 /* Return the name of a v7A special register. */
4613 banked_regname (unsigned reg
)
4617 case 15: return "CPSR";
4618 case 32: return "R8_usr";
4619 case 33: return "R9_usr";
4620 case 34: return "R10_usr";
4621 case 35: return "R11_usr";
4622 case 36: return "R12_usr";
4623 case 37: return "SP_usr";
4624 case 38: return "LR_usr";
4625 case 40: return "R8_fiq";
4626 case 41: return "R9_fiq";
4627 case 42: return "R10_fiq";
4628 case 43: return "R11_fiq";
4629 case 44: return "R12_fiq";
4630 case 45: return "SP_fiq";
4631 case 46: return "LR_fiq";
4632 case 48: return "LR_irq";
4633 case 49: return "SP_irq";
4634 case 50: return "LR_svc";
4635 case 51: return "SP_svc";
4636 case 52: return "LR_abt";
4637 case 53: return "SP_abt";
4638 case 54: return "LR_und";
4639 case 55: return "SP_und";
4640 case 60: return "LR_mon";
4641 case 61: return "SP_mon";
4642 case 62: return "ELR_hyp";
4643 case 63: return "SP_hyp";
4644 case 79: return "SPSR";
4645 case 110: return "SPSR_fiq";
4646 case 112: return "SPSR_irq";
4647 case 114: return "SPSR_svc";
4648 case 116: return "SPSR_abt";
4649 case 118: return "SPSR_und";
4650 case 124: return "SPSR_mon";
4651 case 126: return "SPSR_hyp";
4652 default: return NULL
;
4656 /* Return the name of the DMB/DSB option. */
4658 data_barrier_option (unsigned option
)
4660 switch (option
& 0xf)
4662 case 0xf: return "sy";
4663 case 0xe: return "st";
4664 case 0xd: return "ld";
4665 case 0xb: return "ish";
4666 case 0xa: return "ishst";
4667 case 0x9: return "ishld";
4668 case 0x7: return "un";
4669 case 0x6: return "unst";
4670 case 0x5: return "nshld";
4671 case 0x3: return "osh";
4672 case 0x2: return "oshst";
4673 case 0x1: return "oshld";
4674 default: return NULL
;
4678 /* Print one ARM instruction from PC on INFO->STREAM. */
4681 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
4683 const struct opcode32
*insn
;
4684 void *stream
= info
->stream
;
4685 fprintf_ftype func
= info
->fprintf_func
;
4686 struct arm_private_data
*private_data
= info
->private_data
;
4688 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
4691 if (print_insn_neon (info
, given
, FALSE
))
4694 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
4696 if ((given
& insn
->mask
) != insn
->value
)
4699 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
4702 /* Special case: an instruction with all bits set in the condition field
4703 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4704 or by the catchall at the end of the table. */
4705 if ((given
& 0xF0000000) != 0xF0000000
4706 || (insn
->mask
& 0xF0000000) == 0xF0000000
4707 || (insn
->mask
== 0 && insn
->value
== 0))
4709 unsigned long u_reg
= 16;
4710 unsigned long U_reg
= 16;
4711 bfd_boolean is_unpredictable
= FALSE
;
4712 signed long value_in_comment
= 0;
4715 for (c
= insn
->assembler
; *c
; c
++)
4719 bfd_boolean allow_unpredictable
= FALSE
;
4724 func (stream
, "%%");
4728 value_in_comment
= print_arm_address (pc
, info
, given
);
4732 /* Set P address bit and use normal address
4733 printing routine. */
4734 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
4738 allow_unpredictable
= TRUE
;
4741 if ((given
& 0x004f0000) == 0x004f0000)
4743 /* PC relative with immediate offset. */
4744 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
4748 /* Elide positive zero offset. */
4749 if (offset
|| NEGATIVE_BIT_SET
)
4750 func (stream
, "[pc, #%s%d]\t; ",
4751 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4753 func (stream
, "[pc]\t; ");
4754 if (NEGATIVE_BIT_SET
)
4756 info
->print_address_func (offset
+ pc
+ 8, info
);
4760 /* Always show the offset. */
4761 func (stream
, "[pc], #%s%d",
4762 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
4763 if (! allow_unpredictable
)
4764 is_unpredictable
= TRUE
;
4769 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
4771 func (stream
, "[%s",
4772 arm_regnames
[(given
>> 16) & 0xf]);
4776 if (IMMEDIATE_BIT_SET
)
4778 /* Elide offset for non-writeback
4780 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
4782 func (stream
, ", #%s%d",
4783 NEGATIVE_BIT_SET
? "-" : "", offset
);
4785 if (NEGATIVE_BIT_SET
)
4788 value_in_comment
= offset
;
4792 /* Register Offset or Register Pre-Indexed. */
4793 func (stream
, ", %s%s",
4794 NEGATIVE_BIT_SET
? "-" : "",
4795 arm_regnames
[given
& 0xf]);
4797 /* Writing back to the register that is the source/
4798 destination of the load/store is unpredictable. */
4799 if (! allow_unpredictable
4800 && WRITEBACK_BIT_SET
4801 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
4802 is_unpredictable
= TRUE
;
4805 func (stream
, "]%s",
4806 WRITEBACK_BIT_SET
? "!" : "");
4810 if (IMMEDIATE_BIT_SET
)
4812 /* Immediate Post-indexed. */
4813 /* PR 10924: Offset must be printed, even if it is zero. */
4814 func (stream
, "], #%s%d",
4815 NEGATIVE_BIT_SET
? "-" : "", offset
);
4816 if (NEGATIVE_BIT_SET
)
4818 value_in_comment
= offset
;
4822 /* Register Post-indexed. */
4823 func (stream
, "], %s%s",
4824 NEGATIVE_BIT_SET
? "-" : "",
4825 arm_regnames
[given
& 0xf]);
4827 /* Writing back to the register that is the source/
4828 destination of the load/store is unpredictable. */
4829 if (! allow_unpredictable
4830 && (given
& 0xf) == ((given
>> 12) & 0xf))
4831 is_unpredictable
= TRUE
;
4834 if (! allow_unpredictable
)
4836 /* Writeback is automatically implied by post- addressing.
4837 Setting the W bit is unnecessary and ARM specify it as
4838 being unpredictable. */
4839 if (WRITEBACK_BIT_SET
4840 /* Specifying the PC register as the post-indexed
4841 registers is also unpredictable. */
4842 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
4843 is_unpredictable
= TRUE
;
4851 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
4852 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
4857 if (((given
>> 28) & 0xf) != 0xe)
4859 arm_conditional
[(given
>> 28) & 0xf]);
4868 for (reg
= 0; reg
< 16; reg
++)
4869 if ((given
& (1 << reg
)) != 0)
4872 func (stream
, ", ");
4874 func (stream
, "%s", arm_regnames
[reg
]);
4878 is_unpredictable
= TRUE
;
4883 arm_decode_shift (given
, func
, stream
, FALSE
);
4887 if ((given
& 0x02000000) != 0)
4889 unsigned int rotate
= (given
& 0xf00) >> 7;
4890 unsigned int immed
= (given
& 0xff);
4893 a
= (((immed
<< (32 - rotate
))
4894 | (immed
>> rotate
)) & 0xffffffff);
4895 /* If there is another encoding with smaller rotate,
4896 the rotate should be specified directly. */
4897 for (i
= 0; i
< 32; i
+= 2)
4898 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
4902 func (stream
, "#%d, %d", immed
, rotate
);
4904 func (stream
, "#%d", a
);
4905 value_in_comment
= a
;
4908 arm_decode_shift (given
, func
, stream
, TRUE
);
4912 if ((given
& 0x0000f000) == 0x0000f000)
4914 arm_feature_set arm_ext_v6
=
4915 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
4917 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4918 mechanism for setting PSR flag bits. They are
4919 obsolete in V6 onwards. */
4920 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
4924 is_unpredictable
= TRUE
;
4929 if ((given
& 0x01200000) == 0x00200000)
4935 int offset
= given
& 0xff;
4937 value_in_comment
= offset
* 4;
4938 if (NEGATIVE_BIT_SET
)
4939 value_in_comment
= - value_in_comment
;
4941 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
4946 func (stream
, ", #%d]%s",
4947 (int) value_in_comment
,
4948 WRITEBACK_BIT_SET
? "!" : "");
4956 if (WRITEBACK_BIT_SET
)
4959 func (stream
, ", #%d", (int) value_in_comment
);
4963 func (stream
, ", {%d}", (int) offset
);
4964 value_in_comment
= offset
;
4971 /* Print ARM V5 BLX(1) address: pc+25 bits. */
4976 if (! NEGATIVE_BIT_SET
)
4977 /* Is signed, hi bits should be ones. */
4978 offset
= (-1) ^ 0x00ffffff;
4980 /* Offset is (SignExtend(offset field)<<2). */
4981 offset
+= given
& 0x00ffffff;
4983 address
= offset
+ pc
+ 8;
4985 if (given
& 0x01000000)
4986 /* H bit allows addressing to 2-byte boundaries. */
4989 info
->print_address_func (address
, info
);
4994 if ((given
& 0x02000200) == 0x200)
4997 unsigned sysm
= (given
& 0x004f0000) >> 16;
4999 sysm
|= (given
& 0x300) >> 4;
5000 name
= banked_regname (sysm
);
5003 func (stream
, "%s", name
);
5005 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
5009 func (stream
, "%cPSR_",
5010 (given
& 0x00400000) ? 'S' : 'C');
5011 if (given
& 0x80000)
5013 if (given
& 0x40000)
5015 if (given
& 0x20000)
5017 if (given
& 0x10000)
5023 if ((given
& 0xf0) == 0x60)
5025 switch (given
& 0xf)
5027 case 0xf: func (stream
, "sy"); break;
5029 func (stream
, "#%d", (int) given
& 0xf);
5035 const char * opt
= data_barrier_option (given
& 0xf);
5037 func (stream
, "%s", opt
);
5039 func (stream
, "#%d", (int) given
& 0xf);
5043 case '0': case '1': case '2': case '3': case '4':
5044 case '5': case '6': case '7': case '8': case '9':
5047 unsigned long value
;
5049 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
5055 is_unpredictable
= TRUE
;
5059 /* We want register + 1 when decoding T. */
5065 /* Eat the 'u' character. */
5069 is_unpredictable
= TRUE
;
5074 /* Eat the 'U' character. */
5078 is_unpredictable
= TRUE
;
5081 func (stream
, "%s", arm_regnames
[value
]);
5084 func (stream
, "%ld", value
);
5085 value_in_comment
= value
;
5088 func (stream
, "%ld", value
* 8);
5089 value_in_comment
= value
* 8;
5092 func (stream
, "%ld", value
+ 1);
5093 value_in_comment
= value
+ 1;
5096 func (stream
, "0x%08lx", value
);
5098 /* Some SWI instructions have special
5100 if ((given
& 0x0fffffff) == 0x0FF00000)
5101 func (stream
, "\t; IMB");
5102 else if ((given
& 0x0fffffff) == 0x0FF00001)
5103 func (stream
, "\t; IMBRange");
5106 func (stream
, "%01lx", value
& 0xf);
5107 value_in_comment
= value
;
5112 func (stream
, "%c", *c
);
5116 if (value
== ((1ul << width
) - 1))
5117 func (stream
, "%c", *c
);
5120 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
5132 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
5133 func (stream
, "%d", imm
);
5134 value_in_comment
= imm
;
5139 /* LSB and WIDTH fields of BFI or BFC. The machine-
5140 language instruction encodes LSB and MSB. */
5142 long msb
= (given
& 0x001f0000) >> 16;
5143 long lsb
= (given
& 0x00000f80) >> 7;
5144 long w
= msb
- lsb
+ 1;
5147 func (stream
, "#%lu, #%lu", lsb
, w
);
5149 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
5154 /* Get the PSR/banked register name. */
5157 unsigned sysm
= (given
& 0x004f0000) >> 16;
5159 sysm
|= (given
& 0x300) >> 4;
5160 name
= banked_regname (sysm
);
5163 func (stream
, "%s", name
);
5165 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
5170 /* 16-bit unsigned immediate from a MOVT or MOVW
5171 instruction, encoded in bits 0:11 and 15:19. */
5173 long hi
= (given
& 0x000f0000) >> 4;
5174 long lo
= (given
& 0x00000fff);
5175 long imm16
= hi
| lo
;
5177 func (stream
, "#%lu", imm16
);
5178 value_in_comment
= imm16
;
5188 func (stream
, "%c", *c
);
5191 if (value_in_comment
> 32 || value_in_comment
< -16)
5192 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
5194 if (is_unpredictable
)
5195 func (stream
, UNPREDICTABLE_INSTRUCTION
);
5200 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
5204 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
5207 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
5209 const struct opcode16
*insn
;
5210 void *stream
= info
->stream
;
5211 fprintf_ftype func
= info
->fprintf_func
;
5213 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
5214 if ((given
& insn
->mask
) == insn
->value
)
5216 signed long value_in_comment
= 0;
5217 const char *c
= insn
->assembler
;
5226 func (stream
, "%c", *c
);
5233 func (stream
, "%%");
5238 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
5243 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
5252 ifthen_next_state
= given
& 0xff;
5253 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
5254 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
5255 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
5260 if (ifthen_next_state
)
5261 func (stream
, "\t; unpredictable branch in IT block\n");
5266 func (stream
, "\t; unpredictable <IT:%s>",
5267 arm_conditional
[IFTHEN_COND
]);
5274 reg
= (given
>> 3) & 0x7;
5275 if (given
& (1 << 6))
5278 func (stream
, "%s", arm_regnames
[reg
]);
5287 if (given
& (1 << 7))
5290 func (stream
, "%s", arm_regnames
[reg
]);
5295 if (given
& (1 << 8))
5299 if (*c
== 'O' && (given
& (1 << 8)))
5309 /* It would be nice if we could spot
5310 ranges, and generate the rS-rE format: */
5311 for (reg
= 0; (reg
< 8); reg
++)
5312 if ((given
& (1 << reg
)) != 0)
5315 func (stream
, ", ");
5317 func (stream
, "%s", arm_regnames
[reg
]);
5323 func (stream
, ", ");
5325 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
5331 func (stream
, ", ");
5332 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
5340 /* Print writeback indicator for a LDMIA. We are doing a
5341 writeback if the base register is not in the register
5343 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
5348 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
5350 bfd_vma address
= (pc
+ 4
5351 + ((given
& 0x00f8) >> 2)
5352 + ((given
& 0x0200) >> 3));
5353 info
->print_address_func (address
, info
);
5358 /* Right shift immediate -- bits 6..10; 1-31 print
5359 as themselves, 0 prints as 32. */
5361 long imm
= (given
& 0x07c0) >> 6;
5364 func (stream
, "#%ld", imm
);
5368 case '0': case '1': case '2': case '3': case '4':
5369 case '5': case '6': case '7': case '8': case '9':
5371 int bitstart
= *c
++ - '0';
5374 while (*c
>= '0' && *c
<= '9')
5375 bitstart
= (bitstart
* 10) + *c
++ - '0';
5384 while (*c
>= '0' && *c
<= '9')
5385 bitend
= (bitend
* 10) + *c
++ - '0';
5388 reg
= given
>> bitstart
;
5389 reg
&= (2 << (bitend
- bitstart
)) - 1;
5394 func (stream
, "%s", arm_regnames
[reg
]);
5398 func (stream
, "%ld", (long) reg
);
5399 value_in_comment
= reg
;
5403 func (stream
, "%ld", (long) (reg
<< 1));
5404 value_in_comment
= reg
<< 1;
5408 func (stream
, "%ld", (long) (reg
<< 2));
5409 value_in_comment
= reg
<< 2;
5413 /* PC-relative address -- the bottom two
5414 bits of the address are dropped
5415 before the calculation. */
5416 info
->print_address_func
5417 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
5418 value_in_comment
= 0;
5422 func (stream
, "0x%04lx", (long) reg
);
5426 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
5427 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
5428 value_in_comment
= 0;
5432 func (stream
, "%s", arm_conditional
[reg
]);
5443 if ((given
& (1 << bitstart
)) != 0)
5444 func (stream
, "%c", *c
);
5449 if ((given
& (1 << bitstart
)) != 0)
5450 func (stream
, "%c", *c
++);
5452 func (stream
, "%c", *++c
);
5466 if (value_in_comment
> 32 || value_in_comment
< -16)
5467 func (stream
, "\t; 0x%lx", value_in_comment
);
5472 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
5476 /* Return the name of an V7M special register. */
5479 psr_name (int regno
)
5483 case 0x0: return "APSR";
5484 case 0x1: return "IAPSR";
5485 case 0x2: return "EAPSR";
5486 case 0x3: return "PSR";
5487 case 0x5: return "IPSR";
5488 case 0x6: return "EPSR";
5489 case 0x7: return "IEPSR";
5490 case 0x8: return "MSP";
5491 case 0x9: return "PSP";
5492 case 0xa: return "MSPLIM";
5493 case 0xb: return "PSPLIM";
5494 case 0x10: return "PRIMASK";
5495 case 0x11: return "BASEPRI";
5496 case 0x12: return "BASEPRI_MAX";
5497 case 0x13: return "FAULTMASK";
5498 case 0x14: return "CONTROL";
5499 case 0x88: return "MSP_NS";
5500 case 0x89: return "PSP_NS";
5501 case 0x8a: return "MSPLIM_NS";
5502 case 0x8b: return "PSPLIM_NS";
5503 case 0x90: return "PRIMASK_NS";
5504 case 0x91: return "BASEPRI_NS";
5505 case 0x93: return "FAULTMASK_NS";
5506 case 0x94: return "CONTROL_NS";
5507 case 0x98: return "SP_NS";
5508 default: return "<unknown>";
5512 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
5515 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
5517 const struct opcode32
*insn
;
5518 void *stream
= info
->stream
;
5519 fprintf_ftype func
= info
->fprintf_func
;
5521 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
5524 if (print_insn_neon (info
, given
, TRUE
))
5527 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
5528 if ((given
& insn
->mask
) == insn
->value
)
5530 bfd_boolean is_unpredictable
= FALSE
;
5531 signed long value_in_comment
= 0;
5532 const char *c
= insn
->assembler
;
5538 func (stream
, "%c", *c
);
5545 func (stream
, "%%");
5550 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
5554 if (ifthen_next_state
)
5555 func (stream
, "\t; unpredictable branch in IT block\n");
5560 func (stream
, "\t; unpredictable <IT:%s>",
5561 arm_conditional
[IFTHEN_COND
]);
5566 unsigned int imm12
= 0;
5568 imm12
|= (given
& 0x000000ffu
);
5569 imm12
|= (given
& 0x00007000u
) >> 4;
5570 imm12
|= (given
& 0x04000000u
) >> 15;
5571 func (stream
, "#%u", imm12
);
5572 value_in_comment
= imm12
;
5578 unsigned int bits
= 0, imm
, imm8
, mod
;
5580 bits
|= (given
& 0x000000ffu
);
5581 bits
|= (given
& 0x00007000u
) >> 4;
5582 bits
|= (given
& 0x04000000u
) >> 15;
5583 imm8
= (bits
& 0x0ff);
5584 mod
= (bits
& 0xf00) >> 8;
5587 case 0: imm
= imm8
; break;
5588 case 1: imm
= ((imm8
<< 16) | imm8
); break;
5589 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
5590 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
5592 mod
= (bits
& 0xf80) >> 7;
5593 imm8
= (bits
& 0x07f) | 0x80;
5594 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
5596 func (stream
, "#%u", imm
);
5597 value_in_comment
= imm
;
5603 unsigned int imm
= 0;
5605 imm
|= (given
& 0x000000ffu
);
5606 imm
|= (given
& 0x00007000u
) >> 4;
5607 imm
|= (given
& 0x04000000u
) >> 15;
5608 imm
|= (given
& 0x000f0000u
) >> 4;
5609 func (stream
, "#%u", imm
);
5610 value_in_comment
= imm
;
5616 unsigned int imm
= 0;
5618 imm
|= (given
& 0x000f0000u
) >> 16;
5619 imm
|= (given
& 0x00000ff0u
) >> 0;
5620 imm
|= (given
& 0x0000000fu
) << 12;
5621 func (stream
, "#%u", imm
);
5622 value_in_comment
= imm
;
5628 unsigned int imm
= 0;
5630 imm
|= (given
& 0x000f0000u
) >> 4;
5631 imm
|= (given
& 0x00000fffu
) >> 0;
5632 func (stream
, "#%u", imm
);
5633 value_in_comment
= imm
;
5639 unsigned int imm
= 0;
5641 imm
|= (given
& 0x00000fffu
);
5642 imm
|= (given
& 0x000f0000u
) >> 4;
5643 func (stream
, "#%u", imm
);
5644 value_in_comment
= imm
;
5650 unsigned int reg
= (given
& 0x0000000fu
);
5651 unsigned int stp
= (given
& 0x00000030u
) >> 4;
5652 unsigned int imm
= 0;
5653 imm
|= (given
& 0x000000c0u
) >> 6;
5654 imm
|= (given
& 0x00007000u
) >> 10;
5656 func (stream
, "%s", arm_regnames
[reg
]);
5661 func (stream
, ", lsl #%u", imm
);
5667 func (stream
, ", lsr #%u", imm
);
5673 func (stream
, ", asr #%u", imm
);
5678 func (stream
, ", rrx");
5680 func (stream
, ", ror #%u", imm
);
5687 unsigned int Rn
= (given
& 0x000f0000) >> 16;
5688 unsigned int U
= ! NEGATIVE_BIT_SET
;
5689 unsigned int op
= (given
& 0x00000f00) >> 8;
5690 unsigned int i12
= (given
& 0x00000fff);
5691 unsigned int i8
= (given
& 0x000000ff);
5692 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
5695 func (stream
, "[%s", arm_regnames
[Rn
]);
5696 if (U
) /* 12-bit positive immediate offset. */
5700 value_in_comment
= offset
;
5702 else if (Rn
== 15) /* 12-bit negative immediate offset. */
5703 offset
= - (int) i12
;
5704 else if (op
== 0x0) /* Shifted register offset. */
5706 unsigned int Rm
= (i8
& 0x0f);
5707 unsigned int sh
= (i8
& 0x30) >> 4;
5709 func (stream
, ", %s", arm_regnames
[Rm
]);
5711 func (stream
, ", lsl #%u", sh
);
5717 case 0xE: /* 8-bit positive immediate offset. */
5721 case 0xC: /* 8-bit negative immediate offset. */
5725 case 0xF: /* 8-bit + preindex with wb. */
5730 case 0xD: /* 8-bit - preindex with wb. */
5735 case 0xB: /* 8-bit + postindex. */
5740 case 0x9: /* 8-bit - postindex. */
5746 func (stream
, ", <undefined>]");
5751 func (stream
, "], #%d", (int) offset
);
5755 func (stream
, ", #%d", (int) offset
);
5756 func (stream
, writeback
? "]!" : "]");
5761 func (stream
, "\t; ");
5762 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
5770 unsigned int U
= ! NEGATIVE_BIT_SET
;
5771 unsigned int W
= WRITEBACK_BIT_SET
;
5772 unsigned int Rn
= (given
& 0x000f0000) >> 16;
5773 unsigned int off
= (given
& 0x000000ff);
5775 func (stream
, "[%s", arm_regnames
[Rn
]);
5781 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
5782 value_in_comment
= off
* 4 * (U
? 1 : -1);
5790 func (stream
, "], ");
5793 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
5794 value_in_comment
= off
* 4 * (U
? 1 : -1);
5798 func (stream
, "{%u}", off
);
5799 value_in_comment
= off
;
5807 unsigned int Sbit
= (given
& 0x01000000) >> 24;
5808 unsigned int type
= (given
& 0x00600000) >> 21;
5812 case 0: func (stream
, Sbit
? "sb" : "b"); break;
5813 case 1: func (stream
, Sbit
? "sh" : "h"); break;
5816 func (stream
, "??");
5819 func (stream
, "??");
5831 for (reg
= 0; reg
< 16; reg
++)
5832 if ((given
& (1 << reg
)) != 0)
5835 func (stream
, ", ");
5837 func (stream
, "%s", arm_regnames
[reg
]);
5845 unsigned int msb
= (given
& 0x0000001f);
5846 unsigned int lsb
= 0;
5848 lsb
|= (given
& 0x000000c0u
) >> 6;
5849 lsb
|= (given
& 0x00007000u
) >> 10;
5850 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
5856 unsigned int width
= (given
& 0x0000001f) + 1;
5857 unsigned int lsb
= 0;
5859 lsb
|= (given
& 0x000000c0u
) >> 6;
5860 lsb
|= (given
& 0x00007000u
) >> 10;
5861 func (stream
, "#%u, #%u", lsb
, width
);
5867 unsigned int S
= (given
& 0x04000000u
) >> 26;
5868 unsigned int J1
= (given
& 0x00002000u
) >> 13;
5869 unsigned int J2
= (given
& 0x00000800u
) >> 11;
5875 offset
|= (given
& 0x003f0000) >> 4;
5876 offset
|= (given
& 0x000007ff) << 1;
5877 offset
-= (1 << 20);
5879 info
->print_address_func (pc
+ 4 + offset
, info
);
5885 unsigned int S
= (given
& 0x04000000u
) >> 26;
5886 unsigned int I1
= (given
& 0x00002000u
) >> 13;
5887 unsigned int I2
= (given
& 0x00000800u
) >> 11;
5891 offset
|= !(I1
^ S
) << 23;
5892 offset
|= !(I2
^ S
) << 22;
5893 offset
|= (given
& 0x03ff0000u
) >> 4;
5894 offset
|= (given
& 0x000007ffu
) << 1;
5895 offset
-= (1 << 24);
5898 /* BLX target addresses are always word aligned. */
5899 if ((given
& 0x00001000u
) == 0)
5902 info
->print_address_func (offset
, info
);
5908 unsigned int shift
= 0;
5910 shift
|= (given
& 0x000000c0u
) >> 6;
5911 shift
|= (given
& 0x00007000u
) >> 10;
5912 if (WRITEBACK_BIT_SET
)
5913 func (stream
, ", asr #%u", shift
);
5915 func (stream
, ", lsl #%u", shift
);
5916 /* else print nothing - lsl #0 */
5922 unsigned int rot
= (given
& 0x00000030) >> 4;
5925 func (stream
, ", ror #%u", rot
* 8);
5930 if ((given
& 0xf0) == 0x60)
5932 switch (given
& 0xf)
5934 case 0xf: func (stream
, "sy"); break;
5936 func (stream
, "#%d", (int) given
& 0xf);
5942 const char * opt
= data_barrier_option (given
& 0xf);
5944 func (stream
, "%s", opt
);
5946 func (stream
, "#%d", (int) given
& 0xf);
5951 if ((given
& 0xff) == 0)
5953 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
5963 else if ((given
& 0x20) == 0x20)
5966 unsigned sysm
= (given
& 0xf00) >> 8;
5968 sysm
|= (given
& 0x30);
5969 sysm
|= (given
& 0x00100000) >> 14;
5970 name
= banked_regname (sysm
);
5973 func (stream
, "%s", name
);
5975 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
5979 func (stream
, "%s", psr_name (given
& 0xff));
5984 if (((given
& 0xff) == 0)
5985 || ((given
& 0x20) == 0x20))
5988 unsigned sm
= (given
& 0xf0000) >> 16;
5990 sm
|= (given
& 0x30);
5991 sm
|= (given
& 0x00100000) >> 14;
5992 name
= banked_regname (sm
);
5995 func (stream
, "%s", name
);
5997 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
6000 func (stream
, "%s", psr_name (given
& 0xff));
6003 case '0': case '1': case '2': case '3': case '4':
6004 case '5': case '6': case '7': case '8': case '9':
6009 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
6014 func (stream
, "%lu", val
);
6015 value_in_comment
= val
;
6019 func (stream
, "%lu", val
+ 1);
6020 value_in_comment
= val
+ 1;
6024 func (stream
, "%lu", val
* 4);
6025 value_in_comment
= val
* 4;
6030 is_unpredictable
= TRUE
;
6033 func (stream
, "%s", arm_regnames
[val
]);
6037 func (stream
, "%s", arm_conditional
[val
]);
6042 if (val
== ((1ul << width
) - 1))
6043 func (stream
, "%c", *c
);
6049 func (stream
, "%c", *c
);
6053 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
6058 func (stream
, "0x%lx", val
& 0xffffffffUL
);
6068 /* PR binutils/12534
6069 If we have a PC relative offset in an LDRD or STRD
6070 instructions then display the decoded address. */
6071 if (((given
>> 16) & 0xf) == 0xf)
6073 bfd_vma offset
= (given
& 0xff) * 4;
6075 if ((given
& (1 << 23)) == 0)
6077 func (stream
, "\t; ");
6078 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
6087 if (value_in_comment
> 32 || value_in_comment
< -16)
6088 func (stream
, "\t; 0x%lx", value_in_comment
);
6090 if (is_unpredictable
)
6091 func (stream
, UNPREDICTABLE_INSTRUCTION
);
6097 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
6101 /* Print data bytes on INFO->STREAM. */
6104 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
6105 struct disassemble_info
*info
,
6108 switch (info
->bytes_per_chunk
)
6111 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
6114 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
6117 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
6124 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6125 being displayed in symbol relative addresses.
6127 Also disallow private symbol, with __tagsym$$ prefix,
6128 from ARM RVCT toolchain being displayed. */
6131 arm_symbol_is_valid (asymbol
* sym
,
6132 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
6139 name
= bfd_asymbol_name (sym
);
6141 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
6144 /* Parse the string of disassembler options. */
6147 parse_arm_disassembler_options (const char *options
)
6151 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
6153 if (CONST_STRNEQ (opt
, "reg-names-"))
6156 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
6157 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
6159 regname_selected
= i
;
6163 if (i
>= NUM_ARM_OPTIONS
)
6164 /* xgettext: c-format */
6165 opcodes_error_handler (_("unrecognised register name set: %s"),
6168 else if (CONST_STRNEQ (opt
, "force-thumb"))
6170 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
6173 /* xgettext: c-format */
6174 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
6181 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
6182 enum map_type
*map_symbol
);
6184 /* Search back through the insn stream to determine if this instruction is
6185 conditionally executed. */
6188 find_ifthen_state (bfd_vma pc
,
6189 struct disassemble_info
*info
,
6195 /* COUNT is twice the number of instructions seen. It will be odd if we
6196 just crossed an instruction boundary. */
6199 unsigned int seen_it
;
6202 ifthen_address
= pc
;
6209 /* Scan backwards looking for IT instructions, keeping track of where
6210 instruction boundaries are. We don't know if something is actually an
6211 IT instruction until we find a definite instruction boundary. */
6214 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
6216 /* A symbol must be on an instruction boundary, and will not
6217 be within an IT block. */
6218 if (seen_it
&& (count
& 1))
6224 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
6229 insn
= (b
[0]) | (b
[1] << 8);
6231 insn
= (b
[1]) | (b
[0] << 8);
6234 if ((insn
& 0xf800) < 0xe800)
6236 /* Addr + 2 is an instruction boundary. See if this matches
6237 the expected boundary based on the position of the last
6244 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
6246 enum map_type type
= MAP_ARM
;
6247 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
6249 if (!found
|| (found
&& type
== MAP_THUMB
))
6251 /* This could be an IT instruction. */
6253 it_count
= count
>> 1;
6256 if ((insn
& 0xf800) >= 0xe800)
6259 count
= (count
+ 2) | 1;
6260 /* IT blocks contain at most 4 instructions. */
6261 if (count
>= 8 && !seen_it
)
6264 /* We found an IT instruction. */
6265 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
6266 if ((ifthen_state
& 0xf) == 0)
6270 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6274 is_mapping_symbol (struct disassemble_info
*info
, int n
,
6275 enum map_type
*map_type
)
6279 name
= bfd_asymbol_name (info
->symtab
[n
]);
6280 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
6281 && (name
[2] == 0 || name
[2] == '.'))
6283 *map_type
= ((name
[1] == 'a') ? MAP_ARM
6284 : (name
[1] == 't') ? MAP_THUMB
6292 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6293 Returns nonzero if *MAP_TYPE was set. */
6296 get_map_sym_type (struct disassemble_info
*info
,
6298 enum map_type
*map_type
)
6300 /* If the symbol is in a different section, ignore it. */
6301 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
6304 return is_mapping_symbol (info
, n
, map_type
);
6307 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6308 Returns nonzero if *MAP_TYPE was set. */
6311 get_sym_code_type (struct disassemble_info
*info
,
6313 enum map_type
*map_type
)
6315 elf_symbol_type
*es
;
6318 /* If the symbol is in a different section, ignore it. */
6319 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
6322 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
6323 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
6325 /* If the symbol has function type then use that. */
6326 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
6328 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
6329 == ST_BRANCH_TO_THUMB
)
6330 *map_type
= MAP_THUMB
;
6332 *map_type
= MAP_ARM
;
6339 /* Search the mapping symbol state for instruction at pc. This is only
6340 applicable for elf target.
6342 There is an assumption Here, info->private_data contains the correct AND
6343 up-to-date information about current scan process. The information will be
6344 used to speed this search process.
6346 Return TRUE if the mapping state can be determined, and map_symbol
6347 will be updated accordingly. Otherwise, return FALSE. */
6350 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
6351 enum map_type
*map_symbol
)
6355 bfd_boolean found
= FALSE
;
6356 enum map_type type
= MAP_ARM
;
6357 struct arm_private_data
*private_data
;
6359 if (info
->private_data
== NULL
|| info
->symtab_size
== 0
6360 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
6363 private_data
= info
->private_data
;
6367 start
= private_data
->last_mapping_sym
;
6369 start
= (start
== -1)? 0 : start
;
6370 addr
= bfd_asymbol_value (info
->symtab
[start
]);
6374 if (get_map_sym_type (info
, start
, &type
))
6379 for (n
= start
- 1; n
>= 0; n
--)
6381 if (get_map_sym_type (info
, n
, &type
))
6389 /* No mapping symbols were found. A leading $d may be
6390 omitted for sections which start with data; but for
6391 compatibility with legacy and stripped binaries, only
6392 assume the leading $d if there is at least one mapping
6393 symbol in the file. */
6394 if (!found
&& private_data
->has_mapping_symbols
== 1)
6404 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6405 of the supplied arm_feature_set structure with bitmasks indicating
6406 the supported base architectures and coprocessor extensions.
6408 FIXME: This could more efficiently implemented as a constant array,
6409 although it would also be less robust. */
6412 select_arm_features (unsigned long mach
,
6413 arm_feature_set
* features
)
6415 arm_feature_set arch_fset
;
6416 const arm_feature_set fpu_any
= FPU_ANY
;
6418 #undef ARM_SET_FEATURES
6419 #define ARM_SET_FEATURES(FSET) \
6421 const arm_feature_set fset = FSET; \
6425 /* When several architecture versions share the same bfd_mach_arm_XXX value
6426 the most featureful is chosen. */
6429 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
6430 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
6431 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
6432 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
6433 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
6434 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
6435 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
6436 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
6437 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
6438 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
6439 case bfd_mach_arm_ep9312
:
6440 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
6441 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
6443 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
6444 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
6445 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
6446 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
6447 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
6448 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
6449 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
6450 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
6451 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
6452 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
6453 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
6454 case bfd_mach_arm_8
:
6456 /* Add bits for extensions that Armv8.5-A recognizes. */
6457 arm_feature_set armv8_5_ext_fset
6458 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
6459 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
6460 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
6463 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
6464 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
6465 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
6466 /* If the machine type is unknown allow all architecture types and all
6468 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
6472 #undef ARM_SET_FEATURES
6474 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
6475 and thus on bfd_mach_arm_XXX value. Therefore for a given
6476 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
6477 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
6481 /* NOTE: There are no checks in these routines that
6482 the relevant number of data bytes exist. */
6485 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
6490 int is_thumb
= FALSE
;
6491 int is_data
= FALSE
;
6493 unsigned int size
= 4;
6494 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
6495 bfd_boolean found
= FALSE
;
6496 struct arm_private_data
*private_data
;
6498 if (info
->disassembler_options
)
6500 parse_arm_disassembler_options (info
->disassembler_options
);
6502 /* To avoid repeated parsing of these options, we remove them here. */
6503 info
->disassembler_options
= NULL
;
6506 /* PR 10288: Control which instructions will be disassembled. */
6507 if (info
->private_data
== NULL
)
6509 static struct arm_private_data
private;
6511 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
6512 /* If the user did not use the -m command line switch then default to
6513 disassembling all types of ARM instruction.
6515 The info->mach value has to be ignored as this will be based on
6516 the default archictecture for the target and/or hints in the notes
6517 section, but it will never be greater than the current largest arm
6518 machine value (iWMMXt2), which is only equivalent to the V5TE
6519 architecture. ARM architectures have advanced beyond the machine
6520 value encoding, and these newer architectures would be ignored if
6521 the machine value was used.
6523 Ie the -m switch is used to restrict which instructions will be
6524 disassembled. If it is necessary to use the -m switch to tell
6525 objdump that an ARM binary is being disassembled, eg because the
6526 input is a raw binary file, but it is also desired to disassemble
6527 all ARM instructions then use "-marm". This will select the
6528 "unknown" arm architecture which is compatible with any ARM
6530 info
->mach
= bfd_mach_arm_unknown
;
6532 /* Compute the architecture bitmask from the machine number.
6533 Note: This assumes that the machine number will not change
6534 during disassembly.... */
6535 select_arm_features (info
->mach
, & private.features
);
6537 private.has_mapping_symbols
= -1;
6538 private.last_mapping_sym
= -1;
6539 private.last_mapping_addr
= 0;
6541 info
->private_data
= & private;
6544 private_data
= info
->private_data
;
6546 /* Decide if our code is going to be little-endian, despite what the
6547 function argument might say. */
6548 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
6550 /* For ELF, consult the symbol table to determine what kind of code
6552 if (info
->symtab_size
!= 0
6553 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
6558 enum map_type type
= MAP_ARM
;
6560 /* Start scanning at the start of the function, or wherever
6561 we finished last time. */
6562 /* PR 14006. When the address is 0 we are either at the start of the
6563 very first function, or else the first function in a new, unlinked
6564 executable section (eg because of -ffunction-sections). Either way
6565 start scanning from the beginning of the symbol table, not where we
6566 left off last time. */
6571 start
= info
->symtab_pos
+ 1;
6572 if (start
< private_data
->last_mapping_sym
)
6573 start
= private_data
->last_mapping_sym
;
6577 /* First, look for mapping symbols. */
6578 if (private_data
->has_mapping_symbols
!= 0)
6580 /* Scan up to the location being disassembled. */
6581 for (n
= start
; n
< info
->symtab_size
; n
++)
6583 addr
= bfd_asymbol_value (info
->symtab
[n
]);
6586 if (get_map_sym_type (info
, n
, &type
))
6595 /* No mapping symbol found at this address. Look backwards
6596 for a preceding one. */
6597 for (n
= start
- 1; n
>= 0; n
--)
6599 if (get_map_sym_type (info
, n
, &type
))
6609 private_data
->has_mapping_symbols
= 1;
6611 /* No mapping symbols were found. A leading $d may be
6612 omitted for sections which start with data; but for
6613 compatibility with legacy and stripped binaries, only
6614 assume the leading $d if there is at least one mapping
6615 symbol in the file. */
6616 if (!found
&& private_data
->has_mapping_symbols
== -1)
6618 /* Look for mapping symbols, in any section. */
6619 for (n
= 0; n
< info
->symtab_size
; n
++)
6620 if (is_mapping_symbol (info
, n
, &type
))
6622 private_data
->has_mapping_symbols
= 1;
6625 if (private_data
->has_mapping_symbols
== -1)
6626 private_data
->has_mapping_symbols
= 0;
6629 if (!found
&& private_data
->has_mapping_symbols
== 1)
6636 /* Next search for function symbols to separate ARM from Thumb
6637 in binaries without mapping symbols. */
6640 /* Scan up to the location being disassembled. */
6641 for (n
= start
; n
< info
->symtab_size
; n
++)
6643 addr
= bfd_asymbol_value (info
->symtab
[n
]);
6646 if (get_sym_code_type (info
, n
, &type
))
6655 /* No mapping symbol found at this address. Look backwards
6656 for a preceding one. */
6657 for (n
= start
- 1; n
>= 0; n
--)
6659 if (get_sym_code_type (info
, n
, &type
))
6669 private_data
->last_mapping_sym
= last_sym
;
6670 private_data
->last_type
= type
;
6671 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
6672 is_data
= (private_data
->last_type
== MAP_DATA
);
6674 /* Look a little bit ahead to see if we should print out
6675 two or four bytes of data. If there's a symbol,
6676 mapping or otherwise, after two bytes then don't
6680 size
= 4 - (pc
& 3);
6681 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
6683 addr
= bfd_asymbol_value (info
->symtab
[n
]);
6685 && (info
->section
== NULL
6686 || info
->section
== info
->symtab
[n
]->section
))
6688 if (addr
- pc
< size
)
6693 /* If the next symbol is after three bytes, we need to
6694 print only part of the data, so that we can use either
6697 size
= (pc
& 1) ? 1 : 2;
6701 if (info
->symbols
!= NULL
)
6703 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
6705 coff_symbol_type
* cs
;
6707 cs
= coffsymbol (*info
->symbols
);
6708 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
6709 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
6710 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
6711 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
6712 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
6714 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
6717 /* If no mapping symbol has been found then fall back to the type
6718 of the function symbol. */
6719 elf_symbol_type
* es
;
6722 es
= *(elf_symbol_type
**)(info
->symbols
);
6723 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
6726 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
6727 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
6729 else if (bfd_asymbol_flavour (*info
->symbols
)
6730 == bfd_target_mach_o_flavour
)
6732 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
6734 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
6742 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
6744 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
6746 info
->bytes_per_line
= 4;
6748 /* PR 10263: Disassemble data if requested to do so by the user. */
6749 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
6753 /* Size was already set above. */
6754 info
->bytes_per_chunk
= size
;
6755 printer
= print_insn_data
;
6757 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
6760 for (i
= size
- 1; i
>= 0; i
--)
6761 given
= b
[i
] | (given
<< 8);
6763 for (i
= 0; i
< (int) size
; i
++)
6764 given
= b
[i
] | (given
<< 8);
6768 /* In ARM mode endianness is a straightforward issue: the instruction
6769 is four bytes long and is either ordered 0123 or 3210. */
6770 printer
= print_insn_arm
;
6771 info
->bytes_per_chunk
= 4;
6774 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
6776 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
6778 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
6782 /* In Thumb mode we have the additional wrinkle of two
6783 instruction lengths. Fortunately, the bits that determine
6784 the length of the current instruction are always to be found
6785 in the first two bytes. */
6786 printer
= print_insn_thumb16
;
6787 info
->bytes_per_chunk
= 2;
6790 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
6792 given
= (b
[0]) | (b
[1] << 8);
6794 given
= (b
[1]) | (b
[0] << 8);
6798 /* These bit patterns signal a four-byte Thumb
6800 if ((given
& 0xF800) == 0xF800
6801 || (given
& 0xF800) == 0xF000
6802 || (given
& 0xF800) == 0xE800)
6804 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
6806 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
6808 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
6810 printer
= print_insn_thumb32
;
6815 if (ifthen_address
!= pc
)
6816 find_ifthen_state (pc
, info
, little_code
);
6820 if ((ifthen_state
& 0xf) == 0x8)
6821 ifthen_next_state
= 0;
6823 ifthen_next_state
= (ifthen_state
& 0xe0)
6824 | ((ifthen_state
& 0xf) << 1);
6830 info
->memory_error_func (status
, pc
, info
);
6833 if (info
->flags
& INSN_HAS_RELOC
)
6834 /* If the instruction has a reloc associated with it, then
6835 the offset field in the instruction will actually be the
6836 addend for the reloc. (We are using REL type relocs).
6837 In such cases, we can ignore the pc when computing
6838 addresses, since the addend is not currently pc-relative. */
6841 printer (pc
, info
, given
);
6845 ifthen_state
= ifthen_next_state
;
6846 ifthen_address
+= size
;
6852 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
6854 /* Detect BE8-ness and record it in the disassembler info. */
6855 if (info
->flavour
== bfd_target_elf_flavour
6856 && info
->section
!= NULL
6857 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
6858 info
->endian_code
= BFD_ENDIAN_LITTLE
;
6860 return print_insn (pc
, info
, FALSE
);
6864 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
6866 return print_insn (pc
, info
, TRUE
);
6869 const disasm_options_and_args_t
*
6870 disassembler_options_arm (void)
6872 static disasm_options_and_args_t
*opts_and_args
;
6874 if (opts_and_args
== NULL
)
6876 disasm_options_t
*opts
;
6879 opts_and_args
= XNEW (disasm_options_and_args_t
);
6880 opts_and_args
->args
= NULL
;
6882 opts
= &opts_and_args
->options
;
6883 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
6884 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
6886 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
6888 opts
->name
[i
] = regnames
[i
].name
;
6889 if (regnames
[i
].description
!= NULL
)
6890 opts
->description
[i
] = _(regnames
[i
].description
);
6892 opts
->description
[i
] = NULL
;
6894 /* The array we return must be NULL terminated. */
6895 opts
->name
[i
] = NULL
;
6896 opts
->description
[i
] = NULL
;
6899 return opts_and_args
;
6903 print_arm_disassembler_options (FILE *stream
)
6905 unsigned int i
, max_len
= 0;
6906 fprintf (stream
, _("\n\
6907 The following ARM specific disassembler options are supported for use with\n\
6908 the -M switch:\n"));
6910 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
6912 unsigned int len
= strlen (regnames
[i
].name
);
6917 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
6918 fprintf (stream
, " %s%*c %s\n",
6920 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
6921 _(regnames
[i
].description
));