1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
296 enum mve_unpredictable
298 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
300 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
302 UNPRED_R13
, /* Unpredictable because r13 (sp) or
304 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
305 UNPRED_Q_GT_4
, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6
, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
311 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
313 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
314 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
316 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
318 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
320 UNPRED_NONE
/* No unpredictable behavior. */
325 UNDEF_SIZE
, /* undefined size. */
326 UNDEF_SIZE_0
, /* undefined because size == 0. */
327 UNDEF_SIZE_2
, /* undefined because size == 2. */
328 UNDEF_SIZE_3
, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
330 UNDEF_SIZE_NOT_0
, /* undefined because size != 0. */
331 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
335 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
337 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
338 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
340 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
342 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
346 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
347 UNDEF_NONE
/* no undefined behavior. */
352 arm_feature_set arch
; /* Architecture defining this insn. */
353 unsigned long value
; /* If arch is 0 then value is a sentinel. */
354 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
355 const char * assembler
; /* How to disassemble this insn. */
360 arm_feature_set arch
; /* Architecture defining this insn. */
361 uint8_t coproc_shift
; /* coproc is this far into op. */
362 uint16_t coproc_mask
; /* Length of coproc field in op. */
363 unsigned long value
; /* If arch is 0 then value is a sentinel. */
364 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
365 const char * assembler
; /* How to disassemble this insn. */
372 arm_feature_set arch
; /* Architecture defining this insn. */
373 enum mve_instructions mve_op
; /* Specific mve instruction for faster
375 unsigned long value
; /* If arch is 0 then value is a sentinel. */
376 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
377 const char * assembler
; /* How to disassemble this insn. */
387 /* Shared (between Arm and Thumb mode) opcode. */
390 enum isa isa
; /* Execution mode instruction availability. */
391 arm_feature_set arch
; /* Architecture defining this insn. */
392 unsigned long value
; /* If arch is 0 then value is a sentinel. */
393 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
394 const char * assembler
; /* How to disassemble this insn. */
399 arm_feature_set arch
; /* Architecture defining this insn. */
400 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
401 const char *assembler
; /* How to disassemble this insn. */
404 /* print_insn_coprocessor recognizes the following format control codes:
408 %c print condition code (always bits 28-31 in ARM mode)
409 %b print condition code allowing cp_num == 9
410 %q print shifter argument
411 %u print condition code (unconditional in ARM mode,
412 UNPREDICTABLE if not AL in Thumb)
413 %A print address for ldc/stc/ldf/stf instruction
414 %B print vstm/vldm register list
415 %C print vscclrm register list
416 %I print cirrus signed shift immediate: bits 0..3|4..6
417 %J print register for VLDR instruction
418 %K print address for VLDR instruction
419 %F print the COUNT field of a LFM/SFM instruction.
420 %P print floating point precision in arithmetic insn
421 %Q print floating point precision in ldf/stf insn
422 %R print floating point rounding mode
424 %<bitfield>c print as a condition code (for vsel)
425 %<bitfield>r print as an ARM register
426 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
427 %<bitfield>ru as %<>r but each u register must be unique.
428 %<bitfield>d print the bitfield in decimal
429 %<bitfield>k print immediate for VFPv3 conversion instruction
430 %<bitfield>x print the bitfield in hex
431 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
432 %<bitfield>f print a floating point constant if >7 else a
433 floating point register
434 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
435 %<bitfield>g print as an iWMMXt 64-bit register
436 %<bitfield>G print as an iWMMXt general purpose or control register
437 %<bitfield>D print as a NEON D register
438 %<bitfield>Q print as a NEON Q register
439 %<bitfield>V print as a NEON D or Q register
440 %<bitfield>E print a quarter-float immediate value
442 %y<code> print a single precision VFP reg.
443 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
444 %z<code> print a double precision VFP reg
445 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
447 %<bitfield>'c print specified char iff bitfield is all ones
448 %<bitfield>`c print specified char iff bitfield is all zeroes
449 %<bitfield>?ab... select from array of values in big endian order
451 %L print as an iWMMXt N/M width field.
452 %Z print the Immediate of a WSHUFH instruction.
453 %l like 'A' except use byte offsets for 'B' & 'H'
455 %i print 5-bit immediate in bits 8,3..0
457 %r print register offset address for wldt/wstr instruction. */
459 enum opcode_sentinel_enum
461 SENTINEL_IWMMXT_START
= 1,
463 SENTINEL_GENERIC_START
466 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
467 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
468 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
469 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
471 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
473 /* print_insn_cde recognizes the following format control codes:
477 %a print 'a' iff bit 28 is 1
478 %p print bits 8-10 as coprocessor
479 %<bitfield>d print as decimal
480 %<bitfield>r print as an ARM register
481 %<bitfield>n print as an ARM register but r15 is APSR_nzcv
482 %<bitfield>T print as an ARM register + 1
483 %<bitfield>R as %r but r13 is UNPREDICTABLE
484 %<bitfield>S as %r but rX where X > 10 is UNPREDICTABLE
485 %j print immediate taken from bits (16..21,7,0..5)
486 %k print immediate taken from bits (20..21,7,0..5).
487 %l print immediate taken from bits (20..22,7,4..5). */
489 /* At the moment there is only one valid position for the coprocessor number,
490 and hence that's encoded in the macro below. */
491 #define CDE_OPCODE(ARCH, VALUE, MASK, ASM) \
492 { ARCH, 8, 7, VALUE, MASK, ASM }
493 static const struct cdeopcode32 cde_opcodes
[] =
495 /* Custom Datapath Extension instructions. */
496 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
497 0xee000000, 0xefc00840,
498 "cx1%a\t%p, %12-15n, #%0-5,7,16-21d"),
499 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
500 0xee000040, 0xefc00840,
501 "cx1d%a\t%p, %12-15S, %12-15T, #%0-5,7,16-21d"),
503 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
504 0xee400000, 0xefc00840,
505 "cx2%a\t%p, %12-15n, %16-19n, #%0-5,7,20-21d"),
506 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
507 0xee400040, 0xefc00840,
508 "cx2d%a\t%p, %12-15S, %12-15T, %16-19n, #%0-5,7,20-21d"),
510 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
511 0xee800000, 0xef800840,
512 "cx3%a\t%p, %0-3n, %16-19n, %12-15n, #%4-5,7,20-22d"),
513 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
514 0xee800040, 0xef800840,
515 "cx3d%a\t%p, %0-3S, %0-3T, %16-19n, %12-15n, #%4-5,7,20-22d"),
517 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
518 0xec200000, 0xeeb00840,
519 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19d"),
520 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
521 0xec200040, 0xeeb00840,
522 "vcx1%a\t%p, %12-15,22V, #%0-5,7,16-19,24d"),
524 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
525 0xec300000, 0xeeb00840,
526 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19d"),
527 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
528 0xec300040, 0xeeb00840,
529 "vcx2%a\t%p, %12-15,22V, %0-3,5V, #%4,7,16-19,24d"),
531 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
532 0xec800000, 0xee800840,
533 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21d"),
534 CDE_OPCODE (ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
),
535 0xec800040, 0xee800840,
536 "vcx3%a\t%p, %12-15,22V, %16-19,7V, %0-3,5V, #%4,20-21,24d"),
538 CDE_OPCODE (ARM_FEATURE_CORE_LOW (0), 0, 0, 0)
542 static const struct sopcode32 coprocessor_opcodes
[] =
544 /* XScale instructions. */
545 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
546 0x0e200010, 0x0fff0ff0,
547 "mia%c\tacc0, %0-3r, %12-15r"},
548 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
549 0x0e280010, 0x0fff0ff0,
550 "miaph%c\tacc0, %0-3r, %12-15r"},
551 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
552 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
553 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
554 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
555 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
556 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
558 /* Intel Wireless MMX technology instructions. */
559 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
560 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
561 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
562 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
563 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
564 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
565 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
566 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
567 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
568 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
569 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
570 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
571 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
572 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
573 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
574 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
575 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
576 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
577 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
578 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
579 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
580 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
581 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
582 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
583 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
584 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
585 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
586 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
587 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
588 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
589 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
590 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
591 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
592 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
593 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
594 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
595 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
596 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
597 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
598 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
599 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
600 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
601 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
602 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
603 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
604 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
605 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
606 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
607 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
608 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
609 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
610 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
611 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
612 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
613 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
614 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
615 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
616 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
617 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
618 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
619 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
620 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
621 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
622 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
623 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
624 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
625 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
626 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
627 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
628 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
629 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
630 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
631 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
632 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
633 0x0e800120, 0x0f800ff0,
634 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
635 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
636 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
637 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
638 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
639 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
640 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
641 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
642 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
643 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
644 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
645 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
646 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
647 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
648 0x0e8000a0, 0x0f800ff0,
649 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
650 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
651 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
652 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
653 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
654 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
655 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
656 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
657 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
658 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
659 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
660 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
661 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
662 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
663 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
664 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
665 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
666 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
667 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
668 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
669 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
670 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
671 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
672 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
673 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
674 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
675 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
676 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
677 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
678 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
679 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
680 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
681 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
682 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
683 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
684 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
685 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
686 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
687 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
688 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
689 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
690 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
691 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
692 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
693 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
694 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
695 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
696 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
697 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
698 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
699 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
700 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
701 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
702 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
703 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
704 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
705 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
706 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
707 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
708 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
709 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
710 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
711 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
712 {ANY
, ARM_FEATURE_CORE_LOW (0),
713 SENTINEL_IWMMXT_END
, 0, "" },
715 /* Floating point coprocessor (FPA) instructions. */
716 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
717 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
718 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
719 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
720 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
721 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
722 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
723 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
724 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
725 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
726 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
727 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
728 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
729 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
730 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
731 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
732 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
733 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
734 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
735 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
736 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
737 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
738 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
739 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
740 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
741 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
742 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
743 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
744 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
745 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
746 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
747 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
748 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
749 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
750 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
751 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
752 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
753 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
754 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
755 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
756 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
757 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
758 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
759 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
760 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
761 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
762 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
763 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
764 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
765 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
766 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
767 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
768 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
769 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
770 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
771 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
772 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
773 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
774 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
775 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
776 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
777 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
778 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
779 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
780 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
781 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
782 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
783 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
784 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
785 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
786 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
787 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
788 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
789 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
790 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
791 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
792 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
793 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
794 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
795 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
796 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
797 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
798 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
799 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
800 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
801 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
803 /* Armv8.1-M Mainline instructions. */
804 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
805 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
806 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
807 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
809 /* ARMv8-M Mainline Security Extensions instructions. */
810 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
811 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
812 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
813 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
815 /* Register load/store. */
816 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
817 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
818 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
819 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
820 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
821 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
822 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
823 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
824 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
825 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
826 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
827 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
828 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
829 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
830 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
831 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
832 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
833 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
834 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
835 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
836 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
837 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
838 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
839 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
840 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
841 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
842 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
843 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
844 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
845 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
846 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
847 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
848 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
849 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
850 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
851 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
853 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
854 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
855 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
856 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
857 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
858 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
859 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
860 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
862 /* Data transfer between ARM and NEON registers. */
863 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
864 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
865 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
866 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
867 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
868 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
869 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
870 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
871 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
872 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
873 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
874 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
875 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
876 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
877 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
878 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
879 /* Half-precision conversion instructions. */
880 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
881 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
882 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
883 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
884 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
885 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
886 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
887 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
889 /* Floating point coprocessor (VFP) instructions. */
890 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
891 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
892 {ANY
, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN
, FPU_VFP_EXT_V1xD
),
893 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
894 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
895 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
896 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
897 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
898 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
899 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
900 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
901 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
902 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
903 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
904 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
905 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
906 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
907 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
908 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
909 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
910 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
911 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
912 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
913 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
914 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
915 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
916 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
917 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
918 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
919 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
920 {ANY
, ARM_FEATURE (0, ARM_EXT2_V8_1M_MAIN
, FPU_VFP_EXT_V1xD
),
921 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
922 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
923 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
924 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
925 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
926 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
927 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
928 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
929 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
930 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
931 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
932 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
933 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
934 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
935 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
936 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
937 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
938 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
939 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
940 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
941 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
942 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
943 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
944 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
945 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
946 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
947 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
948 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
949 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
950 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
951 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
952 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
953 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
954 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
955 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
956 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
957 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
958 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
959 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
960 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
961 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
962 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
963 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
964 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
965 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
966 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
967 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
968 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
969 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
970 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
971 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
972 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
973 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
974 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
975 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
976 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
977 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
978 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
979 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
980 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
981 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
982 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
983 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
984 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
985 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
986 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
987 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
988 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
989 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
990 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
991 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
992 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
993 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
994 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
995 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
996 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
997 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
998 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
999 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
1000 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1001 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
1002 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
1003 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
1004 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
1005 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
1006 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
1007 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
1008 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
1009 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
1010 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
1011 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
1012 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1013 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
1014 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1015 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
1016 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1017 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
1018 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1019 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
1020 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1021 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
1022 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1023 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
1024 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1025 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
1026 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1027 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
1028 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1029 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
1030 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1031 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
1032 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1033 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
1034 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1035 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
1036 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1037 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
1038 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1039 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
1040 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1041 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
1042 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1043 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
1044 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
1045 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
1046 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
1047 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
1049 /* Cirrus coprocessor instructions. */
1050 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1051 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1052 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1053 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
1054 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1055 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1056 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1057 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
1058 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1059 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1060 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1061 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
1062 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1063 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1064 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1065 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
1066 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1067 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1068 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1069 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
1070 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1071 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1072 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1073 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
1074 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1075 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1076 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1077 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
1078 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1079 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1080 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1081 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1082 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1083 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1084 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1085 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1086 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1087 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1088 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1089 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1090 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1091 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1092 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1093 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1094 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1095 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1096 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1097 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1098 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1099 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1100 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1101 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1102 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1103 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1104 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1105 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1106 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1107 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1108 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1109 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1110 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1111 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1112 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1113 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1114 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1115 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1116 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1117 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1118 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1119 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1120 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1121 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1122 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1123 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1124 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1125 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1126 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1127 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1128 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1129 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1130 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1131 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1132 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1133 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1134 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1135 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1136 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1137 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1138 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1139 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1140 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1141 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1142 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1143 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1144 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1145 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1146 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1147 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1148 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1149 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1150 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1151 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1152 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1153 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1154 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1155 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1156 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1157 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1158 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1159 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1160 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1161 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1162 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1163 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1164 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1165 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1166 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1167 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1168 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1169 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1170 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1171 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1172 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1173 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1174 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1175 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1176 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1177 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1178 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1179 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1180 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1181 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1182 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1183 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1184 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1185 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1186 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1187 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1188 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1189 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1190 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1191 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1192 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1193 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1194 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1195 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1196 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1197 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1198 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1199 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1200 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1201 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1202 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1203 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1204 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1205 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1206 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1207 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1208 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1209 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1210 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1211 0x0e000600, 0x0ff00f10,
1212 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1213 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1214 0x0e100600, 0x0ff00f10,
1215 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1216 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1217 0x0e200600, 0x0ff00f10,
1218 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1219 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1220 0x0e300600, 0x0ff00f10,
1221 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1223 /* VFP Fused multiply add instructions. */
1224 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1225 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1226 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1227 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1228 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1229 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1230 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1231 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1232 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1233 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1234 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1235 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1236 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1237 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1238 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1239 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1242 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1243 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1244 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1245 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1246 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1247 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1248 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1249 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1250 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1251 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1252 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1253 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1254 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1255 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1256 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1257 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1258 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1259 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1260 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1261 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1262 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1263 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1264 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1265 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1267 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1268 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1269 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1270 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1271 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1272 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1273 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1274 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1275 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1276 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1277 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1278 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1279 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1280 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1281 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1282 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1283 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1284 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1285 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1286 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1287 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1288 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1290 /* BFloat16 instructions. */
1291 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1292 0x0eb30940, 0x0fbf0f50, "vcvt%7?tb%b.bf16.f32\t%y1, %y0"},
1294 /* Dot Product instructions in the space of coprocessor 13. */
1295 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1296 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1297 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1298 0xfe200d00, 0xff200f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1300 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1301 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1302 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1303 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1304 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1305 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1306 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1307 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1308 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1309 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1310 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1311 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1312 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1313 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1314 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1315 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1316 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1318 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1319 cp_num: bit <11:8> == 0b1001.
1320 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1321 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1322 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1323 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1324 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1325 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1326 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1327 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1328 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1329 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1330 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1331 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1332 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1333 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1334 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1335 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1336 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1337 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1338 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1339 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1340 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1341 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1342 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1343 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1344 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1345 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1346 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1347 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1348 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1349 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1350 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1351 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1352 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1353 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1354 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1355 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1356 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1357 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1358 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1359 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1360 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1361 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1362 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1363 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1364 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1365 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1366 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1367 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1368 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1369 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1370 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1371 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1372 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1373 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1374 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1375 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1376 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1377 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1378 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1379 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1380 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1381 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1382 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1383 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1384 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1385 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1386 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1387 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1388 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1389 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1390 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1392 /* ARMv8.3 javascript conversion instruction. */
1393 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1394 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1396 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1399 /* Generic coprocessor instructions. These are only matched if a more specific
1400 SIMD or co-processor instruction does not match first. */
1402 static const struct sopcode32 generic_coprocessor_opcodes
[] =
1404 /* Generic coprocessor instructions. */
1405 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1406 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1407 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1408 0x0c500000, 0x0ff00000,
1409 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1410 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1411 0x0e000000, 0x0f000010,
1412 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1413 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1414 0x0e10f010, 0x0f10f010,
1415 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1416 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1417 0x0e100010, 0x0f100010,
1418 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1419 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1420 0x0e000010, 0x0f100010,
1421 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1422 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1423 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1424 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1425 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1427 /* V6 coprocessor instructions. */
1428 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1429 0xfc500000, 0xfff00000,
1430 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1431 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1432 0xfc400000, 0xfff00000,
1433 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1435 /* V5 coprocessor instructions. */
1436 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1437 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1438 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1439 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1440 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1441 0xfe000000, 0xff000010,
1442 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1443 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1444 0xfe000010, 0xff100010,
1445 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1446 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1447 0xfe100010, 0xff100010,
1448 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1450 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1453 /* Neon opcode table: This does not encode the top byte -- that is
1454 checked by the print_insn_neon routine, as it depends on whether we are
1455 doing thumb32 or arm32 disassembly. */
1457 /* print_insn_neon recognizes the following format control codes:
1461 %c print condition code
1462 %u print condition code (unconditional in ARM mode,
1463 UNPREDICTABLE if not AL in Thumb)
1464 %A print v{st,ld}[1234] operands
1465 %B print v{st,ld}[1234] any one operands
1466 %C print v{st,ld}[1234] single->all operands
1468 %E print vmov, vmvn, vorr, vbic encoded constant
1469 %F print vtbl,vtbx register list
1471 %<bitfield>r print as an ARM register
1472 %<bitfield>d print the bitfield in decimal
1473 %<bitfield>e print the 2^N - bitfield in decimal
1474 %<bitfield>D print as a NEON D register
1475 %<bitfield>Q print as a NEON Q register
1476 %<bitfield>R print as a NEON D or Q register
1477 %<bitfield>Sn print byte scaled width limited by n
1478 %<bitfield>Tn print short scaled width limited by n
1479 %<bitfield>Un print long scaled width limited by n
1481 %<bitfield>'c print specified char iff bitfield is all ones
1482 %<bitfield>`c print specified char iff bitfield is all zeroes
1483 %<bitfield>?ab... select from array of values in big endian order. */
1485 static const struct opcode32 neon_opcodes
[] =
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1489 0xf2b00840, 0xffb00850,
1490 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1491 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1492 0xf2b00000, 0xffb00810,
1493 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1495 /* Data transfer between ARM and NEON registers. */
1496 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1497 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1498 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1499 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1500 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1501 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1502 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1503 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1504 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1505 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1506 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1507 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1509 /* Move data element to all lanes. */
1510 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1511 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1512 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1513 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1514 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1515 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1518 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1519 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1520 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1521 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1523 /* Half-precision conversions. */
1524 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1525 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1526 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1527 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1529 /* NEON fused multiply add instructions. */
1530 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1531 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1532 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1533 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1534 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1535 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1536 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1537 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1539 /* BFloat16 instructions. */
1540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1541 0xfc000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1543 0xfe000d00, 0xffb00f10, "vdot.bf16\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1544 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1545 0xfc000c40, 0xffb00f50, "vmmla.bf16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1547 0xf3b60640, 0xffbf0fd0, "vcvt%c.bf16.f32\t%12-15,22D, %0-3,5Q"},
1548 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1549 0xfc300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
),
1551 0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
1553 /* Matrix Multiply instructions. */
1554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1555 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1557 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1559 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1561 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
1562 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1563 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
),
1565 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
1567 /* Two registers, miscellaneous. */
1568 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1569 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1571 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1572 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1573 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1574 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1575 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1576 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1577 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1578 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1579 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1580 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1581 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1582 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1583 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1584 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1585 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1586 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1587 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1588 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1589 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1590 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1591 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1592 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1593 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1594 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1595 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1596 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1597 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1598 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1599 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1600 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1601 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1602 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1603 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1604 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1605 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1606 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1607 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1608 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1609 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1610 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1611 0xf3b20300, 0xffb30fd0,
1612 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1614 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1616 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1618 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1620 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1622 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1623 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1624 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1626 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1627 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1628 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1630 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1631 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1632 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1634 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1635 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1636 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1638 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1639 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1640 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1642 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1643 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1644 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1646 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1647 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1648 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1650 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1651 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1652 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1654 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1655 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1656 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1658 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1660 0xf3bb0600, 0xffbf0e10,
1661 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1663 0xf3b70600, 0xffbf0e10,
1664 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1666 /* Three registers of the same length. */
1667 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1668 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1669 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1670 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1671 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1672 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1673 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1674 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1675 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1676 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1677 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1678 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1679 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1680 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1682 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1683 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1684 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1685 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1686 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1687 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1688 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1689 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1690 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1691 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1692 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1694 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1695 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1696 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1697 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1698 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1700 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1701 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1702 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1703 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1704 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1706 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1707 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1708 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1709 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1710 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1711 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1712 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1713 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1714 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1715 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1716 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1718 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1719 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1720 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1721 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1722 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1724 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1725 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1726 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1728 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1730 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1732 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1733 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1734 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1735 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1736 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1737 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1738 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1740 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1741 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1742 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1744 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1745 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1746 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1748 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1749 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1750 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1751 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1752 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1753 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1754 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1755 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1756 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1757 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1758 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1759 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1760 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1761 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1762 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1763 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1764 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1765 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1766 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1767 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1768 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1769 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1770 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1771 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1772 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1773 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1774 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1776 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1777 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1778 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1779 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1780 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1782 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1784 0xf2000b00, 0xff800f10,
1785 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1786 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1787 0xf2000b10, 0xff800f10,
1788 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1790 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1792 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1796 0xf3000b00, 0xff800f10,
1797 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1798 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1799 0xf2000000, 0xfe800f10,
1800 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1802 0xf2000010, 0xfe800f10,
1803 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1805 0xf2000100, 0xfe800f10,
1806 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1807 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1808 0xf2000200, 0xfe800f10,
1809 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1811 0xf2000210, 0xfe800f10,
1812 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1813 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1814 0xf2000300, 0xfe800f10,
1815 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1817 0xf2000310, 0xfe800f10,
1818 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1819 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1820 0xf2000400, 0xfe800f10,
1821 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1823 0xf2000410, 0xfe800f10,
1824 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1825 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1826 0xf2000500, 0xfe800f10,
1827 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1829 0xf2000510, 0xfe800f10,
1830 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1831 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1832 0xf2000600, 0xfe800f10,
1833 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1835 0xf2000610, 0xfe800f10,
1836 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1837 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1838 0xf2000700, 0xfe800f10,
1839 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1841 0xf2000710, 0xfe800f10,
1842 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1843 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1844 0xf2000910, 0xfe800f10,
1845 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1847 0xf2000a00, 0xfe800f10,
1848 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1850 0xf2000a10, 0xfe800f10,
1851 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1852 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1853 0xf3000b10, 0xff800f10,
1854 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1856 0xf3000c10, 0xff800f10,
1857 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1859 /* One register and an immediate value. */
1860 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1861 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1862 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1863 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1864 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1865 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1866 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1867 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1868 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1869 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1870 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1871 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1872 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1873 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1874 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1875 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1876 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1877 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1878 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1879 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1880 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1881 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1882 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1883 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1884 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1885 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1887 /* Two registers and a shift amount. */
1888 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1889 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1890 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1891 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1892 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1893 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1894 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1895 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1896 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1897 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1898 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1899 0xf2880950, 0xfeb80fd0,
1900 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1901 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1902 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1904 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1905 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1906 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1907 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1908 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1910 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1911 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1912 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1913 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1914 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1916 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1917 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1918 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1919 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1920 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1922 0xf2900950, 0xfeb00fd0,
1923 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1925 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1926 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1927 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1928 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1929 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1931 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1932 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1933 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1934 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1935 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1937 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1938 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1939 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1940 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1941 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1943 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1944 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1945 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1946 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1947 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1948 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1949 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1950 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1951 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1952 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1953 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1954 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1955 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1956 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1957 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1958 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1959 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1960 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1961 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1962 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1963 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1964 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1965 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1966 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1967 0xf2a00950, 0xfea00fd0,
1968 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1970 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1972 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1974 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1976 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1978 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1979 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1980 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1982 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1984 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1985 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1986 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1988 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1990 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1991 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1992 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1994 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1996 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1998 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1999 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2000 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
2001 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2002 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2004 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
2005 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2006 0xf2a00e10, 0xfea00e90,
2007 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
2008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
2009 0xf2a00c10, 0xfea00e90,
2010 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
2012 /* Three registers of different lengths. */
2013 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
2014 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2016 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2017 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2018 0xf2800400, 0xff800f50,
2019 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2020 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2021 0xf2800600, 0xff800f50,
2022 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2024 0xf2800900, 0xff800f50,
2025 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2026 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2027 0xf2800b00, 0xff800f50,
2028 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2030 0xf2800d00, 0xff800f50,
2031 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2032 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2033 0xf3800400, 0xff800f50,
2034 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2036 0xf3800600, 0xff800f50,
2037 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
2038 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2039 0xf2800000, 0xfe800f50,
2040 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2042 0xf2800100, 0xfe800f50,
2043 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2044 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2045 0xf2800200, 0xfe800f50,
2046 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2048 0xf2800300, 0xfe800f50,
2049 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
2050 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2051 0xf2800500, 0xfe800f50,
2052 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2054 0xf2800700, 0xfe800f50,
2055 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2056 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2057 0xf2800800, 0xfe800f50,
2058 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2059 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2060 0xf2800a00, 0xfe800f50,
2061 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2062 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2063 0xf2800c00, 0xfe800f50,
2064 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
2066 /* Two registers and a scalar. */
2067 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2068 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2069 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2070 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2071 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2072 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
2073 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2074 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2075 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2076 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2077 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2078 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2079 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2080 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
2081 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2082 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2083 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2084 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2085 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2086 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
2087 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2088 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
2089 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2090 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2091 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2092 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2093 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2094 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2095 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2096 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2097 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2098 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2099 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2100 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2101 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2102 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2103 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2104 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2105 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2106 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2107 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2108 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2109 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2110 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
2111 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
2112 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
2113 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2114 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2115 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2116 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2117 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2118 0xf2800240, 0xfe800f50,
2119 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2120 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2121 0xf2800640, 0xfe800f50,
2122 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2123 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2124 0xf2800a40, 0xfe800f50,
2125 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2126 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2127 0xf2800e40, 0xff800f50,
2128 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2129 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2130 0xf2800f40, 0xff800f50,
2131 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2132 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2133 0xf3800e40, 0xff800f50,
2134 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2135 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2136 0xf3800f40, 0xff800f50,
2137 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2140 /* Element and structure load/store. */
2141 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2142 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2143 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2144 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2145 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2146 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2147 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2148 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2149 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2150 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2151 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2152 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2153 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2154 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2155 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2156 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2157 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2158 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2159 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2160 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2161 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2162 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2163 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2164 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2165 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2166 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2167 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2168 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2169 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2170 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2171 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2172 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2173 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2174 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2175 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2176 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2177 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2178 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2180 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2183 /* mve opcode table. */
2185 /* print_insn_mve recognizes the following format control codes:
2189 %a print '+' or '-' or imm offset in vldr[bhwd] and
2191 %c print condition code
2192 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2193 %u print 'U' (unsigned) or 'S' for various mve instructions
2194 %i print MVE predicate(s) for vpt and vpst
2195 %j print a 5-bit immediate from hw2[14:12,7:6]
2196 %k print 48 if the 7th position bit is set else print 64.
2197 %m print rounding mode for vcvt and vrint
2198 %n print vector comparison code for predicated instruction
2199 %s print size for various vcvt instructions
2200 %v print vector predicate for instruction in predicated
2202 %o print offset scaled for vldr[hwd] and vstr[hwd]
2203 %w print writeback mode for MVE v{st,ld}[24]
2204 %B print v{st,ld}[24] any one operands
2205 %E print vmov, vmvn, vorr, vbic encoded constant
2206 %N print generic index for vmov
2207 %T print bottom ('b') or top ('t') of source register
2208 %X print exchange field in vmla* instructions
2210 %<bitfield>r print as an ARM register
2211 %<bitfield>d print the bitfield in decimal
2212 %<bitfield>A print accumulate or not
2213 %<bitfield>c print bitfield as a condition code
2214 %<bitfield>C print bitfield as an inverted condition code
2215 %<bitfield>Q print as a MVE Q register
2216 %<bitfield>F print as a MVE S register
2217 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2220 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2221 %<bitfield>s print size for vector predicate & non VMOV instructions
2222 %<bitfield>I print carry flag or not
2223 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2224 %<bitfield>h print high half of 64-bit destination reg
2225 %<bitfield>k print immediate for vector conversion instruction
2226 %<bitfield>l print low half of 64-bit destination reg
2227 %<bitfield>o print rotate value for vcmul
2228 %<bitfield>u print immediate value for vddup/vdwdup
2229 %<bitfield>x print the bitfield in hex.
2232 static const struct mopcode32 mve_opcodes
[] =
2236 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2238 0xfe310f4d, 0xffbf1fff,
2242 /* Floating point VPT T1. */
2243 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2245 0xee310f00, 0xefb10f50,
2246 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2247 /* Floating point VPT T2. */
2248 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2250 0xee310f40, 0xefb10f50,
2251 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2253 /* Vector VPT T1. */
2254 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2256 0xfe010f00, 0xff811f51,
2257 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2258 /* Vector VPT T2. */
2259 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2261 0xfe010f01, 0xff811f51,
2262 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2263 /* Vector VPT T3. */
2264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2266 0xfe011f00, 0xff811f50,
2267 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2268 /* Vector VPT T4. */
2269 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2271 0xfe010f40, 0xff811f70,
2272 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2273 /* Vector VPT T5. */
2274 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2276 0xfe010f60, 0xff811f70,
2277 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2278 /* Vector VPT T6. */
2279 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2281 0xfe011f40, 0xff811f50,
2282 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2284 /* Vector VBIC immediate. */
2285 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2287 0xef800070, 0xefb81070,
2288 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2290 /* Vector VBIC register. */
2291 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2293 0xef100150, 0xffb11f51,
2294 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2297 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2299 0xee800f01, 0xefc10f51,
2300 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2302 /* Vector VABD floating point. */
2303 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2305 0xff200d40, 0xffa11f51,
2306 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2309 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2311 0xef000740, 0xef811f51,
2312 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2314 /* Vector VABS floating point. */
2315 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2317 0xFFB10740, 0xFFB31FD1,
2318 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2320 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2322 0xffb10340, 0xffb31fd1,
2323 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2325 /* Vector VADD floating point T1. */
2326 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2328 0xef000d40, 0xffa11f51,
2329 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2330 /* Vector VADD floating point T2. */
2331 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2333 0xee300f40, 0xefb11f70,
2334 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2335 /* Vector VADD T1. */
2336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2338 0xef000840, 0xff811f51,
2339 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2340 /* Vector VADD T2. */
2341 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2343 0xee010f40, 0xff811f70,
2344 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2346 /* Vector VADDLV. */
2347 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2349 0xee890f00, 0xef8f1fd1,
2350 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2353 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2355 0xeef10f00, 0xeff31fd1,
2356 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2359 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2361 0xee300f00, 0xffb10f51,
2362 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2365 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2367 0xef000150, 0xffb11f51,
2368 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2370 /* Vector VBRSR register. */
2371 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2373 0xfe011e60, 0xff811f70,
2374 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2376 /* Vector VCADD floating point. */
2377 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2379 0xfc800840, 0xfea11f51,
2380 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2383 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2385 0xfe000f00, 0xff810f51,
2386 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2389 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2391 0xffb00440, 0xffb31fd1,
2392 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2395 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2397 0xffb004c0, 0xffb31fd1,
2398 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2401 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2403 0xfc200840, 0xfe211f51,
2404 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2406 /* Vector VCMP floating point T1. */
2407 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2409 0xee310f00, 0xeff1ef50,
2410 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2412 /* Vector VCMP floating point T2. */
2413 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2415 0xee310f40, 0xeff1ef50,
2416 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2418 /* Vector VCMP T1. */
2419 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2421 0xfe010f00, 0xffc1ff51,
2422 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2423 /* Vector VCMP T2. */
2424 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2426 0xfe010f01, 0xffc1ff51,
2427 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2428 /* Vector VCMP T3. */
2429 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2431 0xfe011f00, 0xffc1ff50,
2432 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2433 /* Vector VCMP T4. */
2434 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2436 0xfe010f40, 0xffc1ff70,
2437 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2438 /* Vector VCMP T5. */
2439 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2441 0xfe010f60, 0xffc1ff70,
2442 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2443 /* Vector VCMP T6. */
2444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2446 0xfe011f40, 0xffc1ff50,
2447 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2452 0xeea00b10, 0xffb10f5f,
2453 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2458 0xff000150, 0xffd11f51,
2459 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2461 /* Vector VFMA, vector * scalar. */
2462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2464 0xee310e40, 0xefb11f70,
2465 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2467 /* Vector VFMA floating point. */
2468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2470 0xef000c50, 0xffa11f51,
2471 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2473 /* Vector VFMS floating point. */
2474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2476 0xef200c50, 0xffa11f51,
2477 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2479 /* Vector VFMAS, vector * scalar. */
2480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2481 MVE_VFMAS_FP_SCALAR
,
2482 0xee311e40, 0xefb11f70,
2483 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2485 /* Vector VHADD T1. */
2486 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2488 0xef000040, 0xef811f51,
2489 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2491 /* Vector VHADD T2. */
2492 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2494 0xee000f40, 0xef811f70,
2495 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2497 /* Vector VHSUB T1. */
2498 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2500 0xef000240, 0xef811f51,
2501 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2503 /* Vector VHSUB T2. */
2504 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2506 0xee001f40, 0xef811f70,
2507 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2512 0xee300e00, 0xefb10f50,
2513 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2516 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2518 0xf000e801, 0xffc0ffff,
2519 "vctp%v.%20-21s\t%16-19r"},
2522 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2524 0xeea00b10, 0xffb10f5f,
2525 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2527 /* Vector VRHADD. */
2528 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2530 0xef000140, 0xef811f51,
2531 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2534 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2535 MVE_VCVT_FP_FIX_VEC
,
2536 0xef800c50, 0xef801cd1,
2537 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2541 MVE_VCVT_BETWEEN_FP_INT
,
2542 0xffb30640, 0xffb31e51,
2543 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2545 /* Vector VCVT between single and half-precision float, bottom half. */
2546 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2547 MVE_VCVT_FP_HALF_FP
,
2548 0xee3f0e01, 0xefbf1fd1,
2549 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2551 /* Vector VCVT between single and half-precision float, top half. */
2552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2553 MVE_VCVT_FP_HALF_FP
,
2554 0xee3f1e01, 0xefbf1fd1,
2555 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2559 MVE_VCVT_FROM_FP_TO_INT
,
2560 0xffb30040, 0xffb31c51,
2561 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2564 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2566 0xee011f6e, 0xff811f7e,
2567 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2569 /* Vector VDWDUP. */
2570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2572 0xee011f60, 0xff811f70,
2573 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2575 /* Vector VHCADD. */
2576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2578 0xee000f00, 0xff810f51,
2579 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2581 /* Vector VIWDUP. */
2582 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2584 0xee010f60, 0xff811f70,
2585 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2588 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2590 0xee010f6e, 0xff811f7e,
2591 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2594 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2596 0xfc901e00, 0xff901e5f,
2597 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2602 0xfc901e01, 0xff901e1f,
2603 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2605 /* Vector VLDRB gather load. */
2606 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2607 MVE_VLDRB_GATHER_T1
,
2608 0xec900e00, 0xefb01e50,
2609 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2611 /* Vector VLDRH gather load. */
2612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2613 MVE_VLDRH_GATHER_T2
,
2614 0xec900e10, 0xefb01e50,
2615 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2617 /* Vector VLDRW gather load. */
2618 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2619 MVE_VLDRW_GATHER_T3
,
2620 0xfc900f40, 0xffb01fd0,
2621 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2623 /* Vector VLDRD gather load. */
2624 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2625 MVE_VLDRD_GATHER_T4
,
2626 0xec900fd0, 0xefb01fd0,
2627 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2629 /* Vector VLDRW gather load. */
2630 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2631 MVE_VLDRW_GATHER_T5
,
2632 0xfd101e00, 0xff111f00,
2633 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2635 /* Vector VLDRD gather load, variant T6. */
2636 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2637 MVE_VLDRD_GATHER_T6
,
2638 0xfd101f00, 0xff111f00,
2639 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2642 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2644 0xec100e00, 0xee581e00,
2645 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2648 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2650 0xec180e00, 0xee581e00,
2651 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2653 /* Vector VLDRB unsigned, variant T5. */
2654 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2656 0xec101e00, 0xfe101f80,
2657 "vldrb%v.u8\t%13-15,22Q, %d"},
2659 /* Vector VLDRH unsigned, variant T6. */
2660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2662 0xec101e80, 0xfe101f80,
2663 "vldrh%v.u16\t%13-15,22Q, %d"},
2665 /* Vector VLDRW unsigned, variant T7. */
2666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2668 0xec101f00, 0xfe101f80,
2669 "vldrw%v.u32\t%13-15,22Q, %d"},
2672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2674 0xef000640, 0xef811f51,
2675 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2678 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2680 0xee330e81, 0xffb31fd1,
2681 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2683 /* Vector VMAXNM floating point. */
2684 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2686 0xff000f50, 0xffa11f51,
2687 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2689 /* Vector VMAXNMA floating point. */
2690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2692 0xee3f0e81, 0xefbf1fd1,
2693 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2695 /* Vector VMAXNMV floating point. */
2696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2698 0xeeee0f00, 0xefff0fd1,
2699 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2701 /* Vector VMAXNMAV floating point. */
2702 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2704 0xeeec0f00, 0xefff0fd1,
2705 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2708 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2710 0xeee20f00, 0xeff30fd1,
2711 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2713 /* Vector VMAXAV. */
2714 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2716 0xeee00f00, 0xfff30fd1,
2717 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2720 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2722 0xef000650, 0xef811f51,
2723 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2726 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2728 0xee331e81, 0xffb31fd1,
2729 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2731 /* Vector VMINNM floating point. */
2732 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2734 0xff200f50, 0xffa11f51,
2735 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2737 /* Vector VMINNMA floating point. */
2738 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2740 0xee3f1e81, 0xefbf1fd1,
2741 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2743 /* Vector VMINNMV floating point. */
2744 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2746 0xeeee0f80, 0xefff0fd1,
2747 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2749 /* Vector VMINNMAV floating point. */
2750 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2752 0xeeec0f80, 0xefff0fd1,
2753 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2756 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2758 0xeee20f80, 0xeff30fd1,
2759 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2761 /* Vector VMINAV. */
2762 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2764 0xeee00f80, 0xfff30fd1,
2765 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2768 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2770 0xee010e40, 0xef811f70,
2771 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2773 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2775 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2777 0xee801e00, 0xef801f51,
2778 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2780 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2782 0xee800e00, 0xef801f51,
2783 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2785 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2788 0xeef00e00, 0xeff01f51,
2789 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2791 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2792 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2794 0xeef00f00, 0xeff11f51,
2795 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2797 /* Vector VMLADAV T1 variant. */
2798 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2800 0xeef01e00, 0xeff01f51,
2801 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2803 /* Vector VMLADAV T2 variant. */
2804 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2806 0xeef01f00, 0xeff11f51,
2807 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2810 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2812 0xee011e40, 0xef811f70,
2813 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2815 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2817 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2819 0xfe800e01, 0xff810f51,
2820 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2822 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2824 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2826 0xee800e01, 0xff800f51,
2827 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2829 /* Vector VMLSDAV T1 Variant. */
2830 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2832 0xeef00e01, 0xfff00f51,
2833 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2835 /* Vector VMLSDAV T2 Variant. */
2836 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2838 0xfef00e01, 0xfff10f51,
2839 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2841 /* Vector VMOV between gpr and half precision register, op == 0. */
2842 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2844 0xee000910, 0xfff00f7f,
2845 "vmov.f16\t%7,16-19F, %12-15r"},
2847 /* Vector VMOV between gpr and half precision register, op == 1. */
2848 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2850 0xee100910, 0xfff00f7f,
2851 "vmov.f16\t%12-15r, %7,16-19F"},
2853 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2854 MVE_VMOV_GP_TO_VEC_LANE
,
2855 0xee000b10, 0xff900f1f,
2856 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2858 /* Vector VORR immediate to vector.
2859 NOTE: MVE_VORR_IMM must appear in the table
2860 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2861 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2863 0xef800050, 0xefb810f0,
2864 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2866 /* Vector VQSHL T2 Variant.
2867 NOTE: MVE_VQSHL_T2 must appear in the table before
2868 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2869 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2871 0xef800750, 0xef801fd1,
2872 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2874 /* Vector VQSHLU T3 Variant
2875 NOTE: MVE_VQSHL_T2 must appear in the table before
2876 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2878 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2880 0xff800650, 0xff801fd1,
2881 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2884 NOTE: MVE_VRSHR must appear in the table before
2885 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2886 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2888 0xef800250, 0xef801fd1,
2889 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2892 NOTE: MVE_VSHL must appear in the table before
2893 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2894 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2896 0xef800550, 0xff801fd1,
2897 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2900 NOTE: MVE_VSHR must appear in the table before
2901 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2902 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2904 0xef800050, 0xef801fd1,
2905 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2908 NOTE: MVE_VSLI must appear in the table before
2909 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2910 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2912 0xff800550, 0xff801fd1,
2913 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2916 NOTE: MVE_VSRI must appear in the table before
2917 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2918 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2920 0xff800450, 0xff801fd1,
2921 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2923 /* Vector VMOV immediate to vector,
2924 undefinded for cmode == 1111 */
2925 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2926 MVE_VMVN_IMM
, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION
},
2928 /* Vector VMOV immediate to vector,
2930 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2931 MVE_VMOV_IMM_TO_VEC
, 0xef800d50, 0xefb81fd0,
2932 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2934 /* Vector VMOV immediate to vector. */
2935 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2936 MVE_VMOV_IMM_TO_VEC
,
2937 0xef800050, 0xefb810d0,
2938 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2940 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2941 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2942 MVE_VMOV2_VEC_LANE_TO_GP
,
2943 0xec000f00, 0xffb01ff0,
2944 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2946 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2947 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2948 MVE_VMOV2_VEC_LANE_TO_GP
,
2949 0xec000f10, 0xffb01ff0,
2950 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2952 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2953 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2954 MVE_VMOV2_GP_TO_VEC_LANE
,
2955 0xec100f00, 0xffb01ff0,
2956 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2958 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2959 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2960 MVE_VMOV2_GP_TO_VEC_LANE
,
2961 0xec100f10, 0xffb01ff0,
2962 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2964 /* Vector VMOV Vector lane to gpr. */
2965 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2966 MVE_VMOV_VEC_LANE_TO_GP
,
2967 0xee100b10, 0xff100f1f,
2968 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2970 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2971 to instruction opcode aliasing. */
2972 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2974 0xeea00f40, 0xefa00fd1,
2975 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2977 /* Vector VMOVL long. */
2978 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2980 0xeea00f40, 0xefa70fd1,
2981 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2983 /* Vector VMOV and narrow. */
2984 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
2986 0xfe310e81, 0xffb30fd1,
2987 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2989 /* Floating point move extract. */
2990 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2992 0xfeb00a40, 0xffbf0fd0,
2993 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2995 /* Vector VMUL floating-point T1 variant. */
2996 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
2998 0xff000d50, 0xffa11f51,
2999 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3001 /* Vector VMUL floating-point T2 variant. */
3002 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3004 0xee310e60, 0xefb11f70,
3005 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3007 /* Vector VMUL T1 variant. */
3008 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3010 0xef000950, 0xff811f51,
3011 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3013 /* Vector VMUL T2 variant. */
3014 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3016 0xee011e60, 0xff811f70,
3017 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3020 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3022 0xee010e01, 0xef811f51,
3023 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3025 /* Vector VRMULH. */
3026 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3028 0xee011e01, 0xef811f51,
3029 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3031 /* Vector VMULL integer. */
3032 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3034 0xee010e00, 0xef810f51,
3035 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3037 /* Vector VMULL polynomial. */
3038 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3040 0xee310e00, 0xefb10f51,
3041 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3043 /* Vector VMVN immediate to vector. */
3044 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3046 0xef800070, 0xefb810f0,
3047 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
3049 /* Vector VMVN register. */
3050 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3052 0xffb005c0, 0xffbf1fd1,
3053 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
3055 /* Vector VNEG floating point. */
3056 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3058 0xffb107c0, 0xffb31fd1,
3059 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3062 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3064 0xffb103c0, 0xffb31fd1,
3065 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3067 /* Vector VORN, vector bitwise or not. */
3068 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3070 0xef300150, 0xffb11f51,
3071 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3073 /* Vector VORR register. */
3074 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3076 0xef200150, 0xffb11f51,
3077 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3079 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
3080 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
3081 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
3084 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3085 MVE_VMOV_VEC_TO_VEC
,
3086 0xef200150, 0xffb11f51,
3087 "vmov%v\t%13-15,22Q, %17-19,7Q"},
3089 /* Vector VQDMULL T1 variant. */
3090 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3092 0xee300f01, 0xefb10f51,
3093 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3096 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3098 0xfe310f4d, 0xffffffff,
3102 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3104 0xfe310f01, 0xffb11f51,
3105 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3108 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3110 0xffb00740, 0xffb31fd1,
3111 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3113 /* Vector VQADD T1 variant. */
3114 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3116 0xef000050, 0xef811f51,
3117 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3119 /* Vector VQADD T2 variant. */
3120 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3122 0xee000f60, 0xef811f70,
3123 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3125 /* Vector VQDMULL T2 variant. */
3126 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3128 0xee300f60, 0xefb10f70,
3129 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3131 /* Vector VQMOVN. */
3132 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3134 0xee330e01, 0xefb30fd1,
3135 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3137 /* Vector VQMOVUN. */
3138 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3140 0xee310e81, 0xffb30fd1,
3141 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3143 /* Vector VQDMLADH. */
3144 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3146 0xee000e00, 0xff810f51,
3147 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3149 /* Vector VQRDMLADH. */
3150 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3152 0xee000e01, 0xff810f51,
3153 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3155 /* Vector VQDMLAH. */
3156 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3158 0xee000e60, 0xff811f70,
3159 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3161 /* Vector VQRDMLAH. */
3162 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3164 0xee000e40, 0xff811f70,
3165 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3167 /* Vector VQDMLASH. */
3168 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3170 0xee001e60, 0xff811f70,
3171 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3173 /* Vector VQRDMLASH. */
3174 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3176 0xee001e40, 0xff811f70,
3177 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3179 /* Vector VQDMLSDH. */
3180 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3182 0xfe000e00, 0xff810f51,
3183 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3185 /* Vector VQRDMLSDH. */
3186 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3188 0xfe000e01, 0xff810f51,
3189 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3191 /* Vector VQDMULH T1 variant. */
3192 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3194 0xef000b40, 0xff811f51,
3195 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3197 /* Vector VQRDMULH T2 variant. */
3198 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3200 0xff000b40, 0xff811f51,
3201 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3203 /* Vector VQDMULH T3 variant. */
3204 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3206 0xee010e60, 0xff811f70,
3207 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3209 /* Vector VQRDMULH T4 variant. */
3210 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3212 0xfe010e60, 0xff811f70,
3213 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3216 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3218 0xffb007c0, 0xffb31fd1,
3219 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3221 /* Vector VQRSHL T1 variant. */
3222 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3224 0xef000550, 0xef811f51,
3225 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3227 /* Vector VQRSHL T2 variant. */
3228 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3230 0xee331ee0, 0xefb31ff0,
3231 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3233 /* Vector VQRSHRN. */
3234 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3236 0xee800f41, 0xefa00fd1,
3237 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3239 /* Vector VQRSHRUN. */
3240 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3242 0xfe800fc0, 0xffa00fd1,
3243 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3245 /* Vector VQSHL T1 Variant. */
3246 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3248 0xee311ee0, 0xefb31ff0,
3249 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3251 /* Vector VQSHL T4 Variant. */
3252 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3254 0xef000450, 0xef811f51,
3255 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3257 /* Vector VQSHRN. */
3258 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3260 0xee800f40, 0xefa00fd1,
3261 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3263 /* Vector VQSHRUN. */
3264 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3266 0xee800fc0, 0xffa00fd1,
3267 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3269 /* Vector VQSUB T1 Variant. */
3270 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3272 0xef000250, 0xef811f51,
3273 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3275 /* Vector VQSUB T2 Variant. */
3276 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3278 0xee001f60, 0xef811f70,
3279 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3281 /* Vector VREV16. */
3282 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3284 0xffb00140, 0xffb31fd1,
3285 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3287 /* Vector VREV32. */
3288 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3290 0xffb000c0, 0xffb31fd1,
3291 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3293 /* Vector VREV64. */
3294 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3296 0xffb00040, 0xffb31fd1,
3297 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3299 /* Vector VRINT floating point. */
3300 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3302 0xffb20440, 0xffb31c51,
3303 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3305 /* Vector VRMLALDAVH. */
3306 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3308 0xee800f00, 0xef811f51,
3309 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3311 /* Vector VRMLALDAVH. */
3312 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3314 0xee801f00, 0xef811f51,
3315 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3317 /* Vector VRSHL T1 Variant. */
3318 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3320 0xef000540, 0xef811f51,
3321 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3323 /* Vector VRSHL T2 Variant. */
3324 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3326 0xee331e60, 0xefb31ff0,
3327 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3329 /* Vector VRSHRN. */
3330 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3332 0xfe800fc1, 0xffa00fd1,
3333 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3336 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3338 0xfe300f00, 0xffb10f51,
3339 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3341 /* Vector VSHL T2 Variant. */
3342 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3344 0xee311e60, 0xefb31ff0,
3345 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3347 /* Vector VSHL T3 Variant. */
3348 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3350 0xef000440, 0xef811f51,
3351 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3354 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3356 0xeea00fc0, 0xffa01ff0,
3357 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3359 /* Vector VSHLL T2 Variant. */
3360 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3362 0xee310e01, 0xefb30fd1,
3363 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3366 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3368 0xee800fc1, 0xffa00fd1,
3369 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3371 /* Vector VST2 no writeback. */
3372 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3374 0xfc801e00, 0xffb01e5f,
3375 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3377 /* Vector VST2 writeback. */
3378 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3380 0xfca01e00, 0xffb01e5f,
3381 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3383 /* Vector VST4 no writeback. */
3384 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3386 0xfc801e01, 0xffb01e1f,
3387 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3389 /* Vector VST4 writeback. */
3390 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3392 0xfca01e01, 0xffb01e1f,
3393 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3395 /* Vector VSTRB scatter store, T1 variant. */
3396 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3397 MVE_VSTRB_SCATTER_T1
,
3398 0xec800e00, 0xffb01e50,
3399 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3401 /* Vector VSTRH scatter store, T2 variant. */
3402 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3403 MVE_VSTRH_SCATTER_T2
,
3404 0xec800e10, 0xffb01e50,
3405 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3407 /* Vector VSTRW scatter store, T3 variant. */
3408 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3409 MVE_VSTRW_SCATTER_T3
,
3410 0xec800e40, 0xffb01e50,
3411 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3413 /* Vector VSTRD scatter store, T4 variant. */
3414 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3415 MVE_VSTRD_SCATTER_T4
,
3416 0xec800fd0, 0xffb01fd0,
3417 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3419 /* Vector VSTRW scatter store, T5 variant. */
3420 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3421 MVE_VSTRW_SCATTER_T5
,
3422 0xfd001e00, 0xff111f00,
3423 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3425 /* Vector VSTRD scatter store, T6 variant. */
3426 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3427 MVE_VSTRD_SCATTER_T6
,
3428 0xfd001f00, 0xff111f00,
3429 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3432 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3434 0xec000e00, 0xfe581e00,
3435 "vstrb%v.%7-8s\t%13-15Q, %d"},
3438 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3440 0xec080e00, 0xfe581e00,
3441 "vstrh%v.%7-8s\t%13-15Q, %d"},
3443 /* Vector VSTRB variant T5. */
3444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3446 0xec001e00, 0xfe101f80,
3447 "vstrb%v.8\t%13-15,22Q, %d"},
3449 /* Vector VSTRH variant T6. */
3450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3452 0xec001e80, 0xfe101f80,
3453 "vstrh%v.16\t%13-15,22Q, %d"},
3455 /* Vector VSTRW variant T7. */
3456 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3458 0xec001f00, 0xfe101f80,
3459 "vstrw%v.32\t%13-15,22Q, %d"},
3461 /* Vector VSUB floating point T1 variant. */
3462 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3464 0xef200d40, 0xffa11f51,
3465 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3467 /* Vector VSUB floating point T2 variant. */
3468 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
),
3470 0xee301f40, 0xefb11f70,
3471 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3473 /* Vector VSUB T1 variant. */
3474 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3476 0xff000840, 0xff811f51,
3477 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3479 /* Vector VSUB T2 variant. */
3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3482 0xee011f40, 0xff811f70,
3483 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3487 0xea50012f, 0xfff1813f,
3488 "asrl%c\t%17-19l, %9-11h, %j"},
3490 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3492 0xea50012d, 0xfff101ff,
3493 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3497 0xea50010f, 0xfff1813f,
3498 "lsll%c\t%17-19l, %9-11h, %j"},
3500 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3502 0xea50010d, 0xfff101ff,
3503 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3505 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3507 0xea50011f, 0xfff1813f,
3508 "lsrl%c\t%17-19l, %9-11h, %j"},
3510 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3512 0xea51012d, 0xfff1017f,
3513 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3515 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3517 0xea500f2d, 0xfff00fff,
3518 "sqrshr%c\t%16-19S, %12-15S"},
3520 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3522 0xea51013f, 0xfff1813f,
3523 "sqshll%c\t%17-19l, %9-11h, %j"},
3525 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3527 0xea500f3f, 0xfff08f3f,
3528 "sqshl%c\t%16-19S, %j"},
3530 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3532 0xea51012f, 0xfff1813f,
3533 "srshrl%c\t%17-19l, %9-11h, %j"},
3535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3537 0xea500f2f, 0xfff08f3f,
3538 "srshr%c\t%16-19S, %j"},
3540 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3542 0xea51010d, 0xfff1017f,
3543 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3547 0xea500f0d, 0xfff00fff,
3548 "uqrshl%c\t%16-19S, %12-15S"},
3550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3552 0xea51010f, 0xfff1813f,
3553 "uqshll%c\t%17-19l, %9-11h, %j"},
3555 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3557 0xea500f0f, 0xfff08f3f,
3558 "uqshl%c\t%16-19S, %j"},
3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3562 0xea51011f, 0xfff1813f,
3563 "urshrl%c\t%17-19l, %9-11h, %j"},
3565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
),
3567 0xea500f1f, 0xfff08f3f,
3568 "urshr%c\t%16-19S, %j"},
3570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3572 0xea509000, 0xfff0f000,
3573 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3575 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3577 0xea50a000, 0xfff0f000,
3578 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3580 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3582 0xea5f900f, 0xfffff00f,
3583 "cset\t%8-11S, %4-7C"},
3585 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3587 0xea5fa00f, 0xfffff00f,
3588 "csetm\t%8-11S, %4-7C"},
3590 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3592 0xea508000, 0xfff0f000,
3593 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3597 0xea50b000, 0xfff0f000,
3598 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3600 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3602 0xea509000, 0xfff0f000,
3603 "cinc\t%8-11S, %16-19Z, %4-7C"},
3605 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3607 0xea50a000, 0xfff0f000,
3608 "cinv\t%8-11S, %16-19Z, %4-7C"},
3610 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3612 0xea50b000, 0xfff0f000,
3613 "cneg\t%8-11S, %16-19Z, %4-7C"},
3615 {ARM_FEATURE_CORE_LOW (0),
3617 0x00000000, 0x00000000, 0}
3620 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3621 ordered: they must be searched linearly from the top to obtain a correct
3624 /* print_insn_arm recognizes the following format control codes:
3628 %a print address for ldr/str instruction
3629 %s print address for ldr/str halfword/signextend instruction
3630 %S like %s but allow UNPREDICTABLE addressing
3631 %b print branch destination
3632 %c print condition code (always bits 28-31)
3633 %m print register mask for ldm/stm instruction
3634 %o print operand2 (immediate or register + shift)
3635 %p print 'p' iff bits 12-15 are 15
3636 %t print 't' iff bit 21 set and bit 24 clear
3637 %B print arm BLX(1) destination
3638 %C print the PSR sub type.
3639 %U print barrier type.
3640 %P print address for pli instruction.
3642 %<bitfield>r print as an ARM register
3643 %<bitfield>T print as an ARM register + 1
3644 %<bitfield>R as %r but r15 is UNPREDICTABLE
3645 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3646 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3647 %<bitfield>d print the bitfield in decimal
3648 %<bitfield>W print the bitfield plus one in decimal
3649 %<bitfield>x print the bitfield in hex
3650 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3652 %<bitfield>'c print specified char iff bitfield is all ones
3653 %<bitfield>`c print specified char iff bitfield is all zeroes
3654 %<bitfield>?ab... select from array of values in big endian order
3656 %e print arm SMI operand (bits 0..7,8..19).
3657 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3658 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3659 %R print the SPSR/CPSR or banked register of an MRS. */
3661 static const struct opcode32 arm_opcodes
[] =
3663 /* ARM instructions. */
3664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3665 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3667 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
3670 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3671 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3672 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3674 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
3676 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3678 0x00800090, 0x0fa000f0,
3679 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3681 0x00a00090, 0x0fa000f0,
3682 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3684 /* V8.2 RAS extension instructions. */
3685 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3686 0xe320f010, 0xffffffff, "esb"},
3688 /* V8 instructions. */
3689 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3690 0x0320f005, 0x0fffffff, "sevl"},
3691 /* Defined in V8 but is in NOP space so available to all arch. */
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3693 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3694 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
3695 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3697 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3699 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3701 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3702 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3703 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3705 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3707 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3709 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3711 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3713 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3715 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3717 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3719 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3721 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3722 /* CRC32 instructions. */
3723 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3724 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3725 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3726 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3727 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3728 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3729 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3730 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3731 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3732 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3733 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
3734 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3736 /* Privileged Access Never extension instructions. */
3737 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
3738 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3740 /* Virtualization Extension instructions. */
3741 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3744 /* Integer Divide Extension instructions. */
3745 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3746 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3747 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3748 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3750 /* MP Extension instructions. */
3751 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3753 /* Speculation Barriers. */
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
3755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
3758 /* V7 instructions. */
3759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3765 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3767 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3769 /* ARM V6T2 instructions. */
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3771 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3773 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3775 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3777 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3779 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3780 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
3781 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3782 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3784 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3785 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3786 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3787 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3789 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3791 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3793 /* ARM Security extension instructions. */
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
3795 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3797 /* ARM V6K instructions. */
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3799 0xf57ff01f, 0xffffffff, "clrex"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3801 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3803 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3805 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3807 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3809 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3811 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3813 /* ARMv8.5-A instructions. */
3814 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
3816 /* ARM V6K NOP hints. */
3817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3818 0x0320f001, 0x0fffffff, "yield%c"},
3819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3820 0x0320f002, 0x0fffffff, "wfe%c"},
3821 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3822 0x0320f003, 0x0fffffff, "wfi%c"},
3823 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3824 0x0320f004, 0x0fffffff, "sev%c"},
3825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3826 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3828 /* ARM V6 instructions. */
3829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3830 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3832 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3834 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3836 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3838 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3840 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3841 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3842 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3844 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3846 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3848 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3850 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3852 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3854 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3856 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3858 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3860 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3862 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3864 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3866 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3868 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3870 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3872 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3874 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3876 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3878 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3880 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3882 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3884 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3886 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3888 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3890 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3892 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3894 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3896 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3898 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3900 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3902 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3904 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3906 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3908 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3910 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3912 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3914 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3916 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3918 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3920 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3922 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3924 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3926 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3928 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3930 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3932 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3934 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3936 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3938 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3940 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3942 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3944 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3946 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3948 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3949 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3950 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3952 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3954 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3956 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3958 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3960 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3962 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3964 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3966 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3968 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3970 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3972 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3974 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3976 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3978 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3980 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3982 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3984 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3986 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3988 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3990 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3992 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3994 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3996 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3998 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4000 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4002 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4004 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4006 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4008 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4010 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
4011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4012 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4014 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4016 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
4017 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4018 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
4019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4020 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4022 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4024 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4026 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4028 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4030 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4032 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
4033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4034 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4036 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4038 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4040 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4042 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4044 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4046 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4048 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4050 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
4051 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4052 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
4053 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4054 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
4055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4056 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
4057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4058 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4060 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4062 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4064 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4065 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4066 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
4067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4068 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
4069 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4070 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
4071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
4072 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
4074 /* V5J instruction. */
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
4076 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
4078 /* V5 Instructions. */
4079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4080 0xe1200070, 0xfff000f0,
4081 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4083 0xfa000000, 0xfe000000, "blx\t%B"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4085 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
4086 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
4087 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
4089 /* V5E "El Segundo" Instructions. */
4090 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4091 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
4092 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4093 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
4095 0xf450f000, 0xfc70f000, "pld\t%a"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4097 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4099 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4100 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4101 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4102 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4103 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4106 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
4107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4108 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4111 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4113 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4114 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4115 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4116 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4117 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4120 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
4121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4122 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
4123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4124 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4126 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4129 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4130 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4131 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4134 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4135 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4136 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4138 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4140 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4142 /* ARM Instructions. */
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4144 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4146 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4147 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4148 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4149 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4151 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4153 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4155 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4157 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4160 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4161 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4162 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4163 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4164 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4166 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4168 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4169 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
4170 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4171 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4173 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4175 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4177 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4178 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4180 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4182 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4185 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4186 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4187 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4188 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4189 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4191 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4192 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4193 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4194 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4195 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4196 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4199 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4201 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4203 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4205 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4206 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4207 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4208 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4209 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4210 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4213 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4215 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4217 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4219 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4220 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4221 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4222 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4223 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4224 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4227 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4229 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4230 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4231 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
4234 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4236 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4238 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4240 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4241 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4242 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4243 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4244 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4245 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4248 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4250 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4252 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4254 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4255 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4256 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4257 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4258 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4259 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4262 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4264 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4266 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4268 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4269 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4271 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4273 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4275 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4276 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4277 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4278 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4279 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4280 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4281 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4282 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4283 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4284 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4285 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4286 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4287 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4288 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4290 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4291 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4292 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4293 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4294 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4295 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4297 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4298 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4299 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4300 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4301 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4302 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4304 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4305 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
4306 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4307 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4309 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4310 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4312 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4313 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4314 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4315 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4317 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4318 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4319 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4320 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4322 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4323 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4324 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4326 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4328 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4330 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4331 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4332 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4333 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4334 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4335 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4336 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4338 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4339 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4340 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4342 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4344 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4346 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4348 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4350 0x092d0000, 0x0fff0000, "push%c\t%m"},
4351 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4352 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4354 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4357 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4358 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4359 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4360 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4361 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4363 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4365 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4367 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4369 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4371 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4373 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4375 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4377 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4378 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4379 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4381 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4383 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4385 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4386 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4387 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4389 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4391 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4393 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4395 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4396 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4397 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4398 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
4402 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
4403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4404 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4405 {ARM_FEATURE_CORE_LOW (0),
4406 0x00000000, 0x00000000, 0}
4409 /* print_insn_thumb16 recognizes the following format control codes:
4411 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4412 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4413 %<bitfield>I print bitfield as a signed decimal
4414 (top bit of range being the sign bit)
4415 %N print Thumb register mask (with LR)
4416 %O print Thumb register mask (with PC)
4417 %M print Thumb register mask
4418 %b print CZB's 6-bit unsigned branch destination
4419 %s print Thumb right-shift immediate (6..10; 0 == 32).
4420 %c print the condition code
4421 %C print the condition code, or "s" if not conditional
4422 %x print warning if conditional an not at end of IT block"
4423 %X print "\t; unpredictable <IT:code>" if conditional
4424 %I print IT instruction suffix and operands
4425 %W print Thumb Writeback indicator for LDMIA
4426 %<bitfield>r print bitfield as an ARM register
4427 %<bitfield>d print bitfield as a decimal
4428 %<bitfield>H print (bitfield * 2) as a decimal
4429 %<bitfield>W print (bitfield * 4) as a decimal
4430 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4431 %<bitfield>B print Thumb branch destination (signed displacement)
4432 %<bitfield>c print bitfield as a condition code
4433 %<bitnum>'c print specified char iff bit is one
4434 %<bitnum>?ab print a if bit is one else print b. */
4436 static const struct opcode16 thumb_opcodes
[] =
4438 /* Thumb instructions. */
4440 /* ARMv8-M Security Extensions instructions. */
4441 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
4442 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
4444 /* ARM V8 instructions. */
4445 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
4447 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4449 /* ARM V6K no-argument instructions. */
4450 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
4453 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
4455 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4457 /* ARM V6T2 instructions. */
4458 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4459 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4461 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4462 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
4465 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4467 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4468 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4469 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4470 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4471 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4472 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4473 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4474 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4475 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4477 /* ARM V5 ISA extends Thumb. */
4478 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4479 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4480 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4481 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4482 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4483 /* ARM V4T ISA (Thumb v1). */
4484 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4485 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4487 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4488 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4489 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4490 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4491 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4492 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4493 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4494 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4495 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4496 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4497 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4498 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4499 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4500 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4501 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4502 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4504 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4505 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4507 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
4508 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
4509 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4510 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4512 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
4513 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
4515 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4516 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4517 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4518 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4519 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4520 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4521 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4522 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4524 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4525 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4526 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4527 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4528 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4529 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4531 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4532 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4533 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4534 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4536 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4537 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4538 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4540 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4542 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4543 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4545 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4547 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4550 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4553 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4554 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4555 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4556 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4557 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4558 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4559 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4561 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4562 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4563 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4564 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4566 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4567 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4568 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4569 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4571 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4572 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4574 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4576 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4577 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4579 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4581 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
4583 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4585 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4587 /* The E800 .. FFFF range is unconditionally redirected to the
4588 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4589 are processed via that table. Thus, we can never encounter a
4590 bare "second half of BL/BLX(1)" instruction here. */
4591 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
4592 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4595 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4596 We adopt the convention that hw1 is the high 16 bits of .value and
4597 .mask, hw2 the low 16 bits.
4599 print_insn_thumb32 recognizes the following format control codes:
4603 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4604 %M print a modified 12-bit immediate (same location)
4605 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4606 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4607 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4608 %S print a possibly-shifted Rm
4610 %L print address for a ldrd/strd instruction
4611 %a print the address of a plain load/store
4612 %w print the width and signedness of a core load/store
4613 %m print register mask for ldm/stm
4614 %n print register mask for clrm
4616 %E print the lsb and width fields of a bfc/bfi instruction
4617 %F print the lsb and width fields of a sbfx/ubfx instruction
4618 %G print a fallback offset for Branch Future instructions
4619 %W print an offset for BF instruction
4620 %Y print an offset for BFL instruction
4621 %Z print an offset for BFCSEL instruction
4622 %Q print an offset for Low Overhead Loop instructions
4623 %P print an offset for Low Overhead Loop end instructions
4624 %b print a conditional branch offset
4625 %B print an unconditional branch offset
4626 %s print the shift field of an SSAT instruction
4627 %R print the rotation field of an SXT instruction
4628 %U print barrier type.
4629 %P print address for pli instruction.
4630 %c print the condition code
4631 %x print warning if conditional an not at end of IT block"
4632 %X print "\t; unpredictable <IT:code>" if conditional
4634 %<bitfield>d print bitfield in decimal
4635 %<bitfield>D print bitfield plus one in decimal
4636 %<bitfield>W print bitfield*4 in decimal
4637 %<bitfield>r print bitfield as an ARM register
4638 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4639 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4640 %<bitfield>c print bitfield as a condition code
4642 %<bitfield>'c print specified char iff bitfield is all ones
4643 %<bitfield>`c print specified char iff bitfield is all zeroes
4644 %<bitfield>?ab... select from array of values in big endian order
4646 With one exception at the bottom (done because BL and BLX(1) need
4647 to come dead last), this table was machine-sorted first in
4648 decreasing order of number of bits set in the mask, then in
4649 increasing numeric order of mask, then in increasing numeric order
4650 of opcode. This order is not the clearest for a human reader, but
4651 is guaranteed never to catch a special-case bit pattern with a more
4652 general mask, which is important, because this instruction encoding
4653 makes heavy use of special-case bit patterns. */
4654 static const struct opcode32 thumb32_opcodes
[] =
4656 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4658 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4659 0xf00fe001, 0xffffffff, "lctp%c"},
4660 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4661 0xf02fc001, 0xfffff001, "le\t%P"},
4662 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4663 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4664 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4665 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4666 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4667 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4669 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4670 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4671 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4672 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4673 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4675 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4676 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4677 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4678 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4679 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4680 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4681 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4682 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4683 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4684 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4686 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4687 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4689 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4690 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
4691 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4692 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4693 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4694 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4695 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4696 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4697 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4698 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4700 /* ARM V8.2 RAS extension instructions. */
4701 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
4702 0xf3af8010, 0xffffffff, "esb"},
4704 /* V8 instructions. */
4705 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4706 0xf3af8005, 0xffffffff, "sevl%c.w"},
4707 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4708 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4709 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4710 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4711 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4712 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4713 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4714 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4715 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4716 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4717 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4718 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4719 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4720 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4721 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4722 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4723 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4724 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4725 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4726 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4727 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4728 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4729 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4730 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4731 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4732 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4733 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4734 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4735 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4736 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4738 /* CRC32 instructions. */
4739 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4740 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4741 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4742 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4743 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4744 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4745 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4746 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4747 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4748 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4749 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
4750 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4752 /* Speculation Barriers. */
4753 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
4755 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
4757 /* V7 instructions. */
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4759 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4761 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4763 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4765 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4766 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4767 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4768 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4770 /* Virtualization Extension instructions. */
4771 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4772 /* We skip ERET as that is SUBS pc, lr, #0. */
4774 /* MP Extension instructions. */
4775 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4777 /* Security extension instructions. */
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4780 /* ARMv8.5-A instructions. */
4781 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
4783 /* Instructions defined in the basic V6T2 set. */
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
4785 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4787 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
4789 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4790 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4791 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4793 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4794 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4795 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4796 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4797 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4798 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4799 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4800 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4801 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4802 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4803 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4804 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4805 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4806 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4807 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4808 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4809 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4810 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4811 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4812 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4813 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4814 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4815 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4816 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4817 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4818 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4819 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4820 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4821 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4822 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4823 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4824 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4825 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4826 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4827 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4828 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4829 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4830 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4831 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4832 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4833 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4834 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4835 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4836 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4837 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4838 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4839 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4840 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4841 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4842 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4843 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4844 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4845 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4846 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4847 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4848 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4849 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4850 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4851 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4852 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4853 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4854 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4855 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4856 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4857 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4858 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4859 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4860 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4861 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4862 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4863 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4864 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4865 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4866 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4867 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4868 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4869 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4870 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4871 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4872 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4873 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4874 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4875 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4876 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4877 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4878 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4879 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4880 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4881 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4882 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4883 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4884 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4885 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4886 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4887 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4888 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4889 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4890 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4891 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4892 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4893 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4894 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4895 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4896 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4897 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4898 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4899 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4900 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4901 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4902 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4903 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4904 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4905 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4906 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4907 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4908 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4909 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4910 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4911 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4912 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4913 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4914 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4915 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4916 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4917 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4918 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4919 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4920 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4921 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4922 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4923 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4924 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4925 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4926 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4928 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4929 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4930 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4931 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4932 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4933 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4934 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4935 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4936 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4937 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4938 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4939 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4940 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4941 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4942 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4943 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4944 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4945 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4946 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4947 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4948 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4949 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4950 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4951 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4952 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4953 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4954 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4955 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4956 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4958 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4960 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4962 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4963 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4964 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4966 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4968 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4970 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4972 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4974 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4976 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4978 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4979 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4980 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4981 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4982 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4983 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4984 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4986 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4988 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4990 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4992 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4993 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4994 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4995 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4996 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4997 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4998 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4999 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5000 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
5001 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5002 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5004 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5006 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5007 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5008 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5010 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5011 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5012 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5013 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5014 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5015 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5016 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5017 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5018 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
5019 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5020 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
5021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5022 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
5023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5024 0xf810f000, 0xff70f000, "pld%c\t%a"},
5025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5026 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5028 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5030 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5032 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5033 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5034 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
5035 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5036 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5037 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5038 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
5039 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5040 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
5041 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5042 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
5043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5044 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
5045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5046 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
5047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5048 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
5049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5050 0xfb100000, 0xfff000c0,
5051 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
5052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5053 0xfbc00080, 0xfff000c0,
5054 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
5055 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5056 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
5057 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5058 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
5059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5060 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
5061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5062 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
5063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5064 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
5065 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5066 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
5067 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5068 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
5069 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5070 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
5071 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5072 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
5073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5074 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
5075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5076 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
5077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5078 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
5079 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5080 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
5081 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5082 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
5083 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5084 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
5085 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5086 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
5087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5088 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
5089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5090 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
5091 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
5092 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
5093 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5094 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
5095 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5096 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
5097 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5098 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
5099 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5100 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
5101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5102 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
5103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5104 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
5105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5106 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
5107 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5108 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
5109 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5110 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
5111 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5112 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
5113 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5114 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
5115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5116 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
5117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5118 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
5119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5120 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
5121 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5122 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
5123 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5124 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5125 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5126 0xe9400000, 0xff500000,
5127 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5128 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5129 0xe9500000, 0xff500000,
5130 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5132 0xe8600000, 0xff700000,
5133 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5134 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5135 0xe8700000, 0xff700000,
5136 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5137 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5138 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5139 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5140 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5142 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
5143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5144 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5146 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5148 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5149 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5150 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5152 /* These have been 32-bit since the invention of Thumb. */
5153 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5154 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5155 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5156 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5159 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
5160 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
5161 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5164 static const char *const arm_conditional
[] =
5165 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5166 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5168 static const char *const arm_fp_const
[] =
5169 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5171 static const char *const arm_shift
[] =
5172 {"lsl", "lsr", "asr", "ror"};
5177 const char *description
;
5178 const char *reg_names
[16];
5182 static const arm_regname regnames
[] =
5184 { "reg-names-raw", N_("Select raw register names"),
5185 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5186 { "reg-names-gcc", N_("Select register names used by GCC"),
5187 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5188 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5189 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5190 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
5191 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
5192 { "reg-names-apcs", N_("Select register names used in the APCS"),
5193 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5194 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5195 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5196 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5197 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
5198 { "coproc<N>=(cde|generic)", N_("Enable CDE extensions for coprocessor N space"), { NULL
} }
5201 static const char *const iwmmxt_wwnames
[] =
5202 {"b", "h", "w", "d"};
5204 static const char *const iwmmxt_wwssnames
[] =
5205 {"b", "bus", "bc", "bss",
5206 "h", "hus", "hc", "hss",
5207 "w", "wus", "wc", "wss",
5208 "d", "dus", "dc", "dss"
5211 static const char *const iwmmxt_regnames
[] =
5212 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5213 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5216 static const char *const iwmmxt_cregnames
[] =
5217 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5218 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5221 static const char *const vec_condnames
[] =
5222 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5225 static const char *const mve_predicatenames
[] =
5226 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5227 "eee", "ee", "eet", "e", "ett", "et", "ete"
5230 /* Names for 2-bit size field for mve vector isntructions. */
5231 static const char *const mve_vec_sizename
[] =
5232 { "8", "16", "32", "64"};
5234 /* Indicates whether we are processing a then predicate,
5235 else predicate or none at all. */
5243 /* Information used to process a vpt block and subsequent instructions. */
5246 /* Are we in a vpt block. */
5247 bfd_boolean in_vpt_block
;
5249 /* Next predicate state if in vpt block. */
5250 enum vpt_pred_state next_pred_state
;
5252 /* Mask from vpt/vpst instruction. */
5253 long predicate_mask
;
5255 /* Instruction number in vpt block. */
5256 long current_insn_num
;
5258 /* Number of instructions in vpt block.. */
5262 static struct vpt_block vpt_block_state
=
5271 /* Default to GCC register name set. */
5272 static unsigned int regname_selected
= 1;
5274 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5275 #define arm_regnames regnames[regname_selected].reg_names
5277 static bfd_boolean force_thumb
= FALSE
;
5278 static uint16_t cde_coprocs
= 0;
5280 /* Current IT instruction state. This contains the same state as the IT
5281 bits in the CPSR. */
5282 static unsigned int ifthen_state
;
5283 /* IT state for the next instruction. */
5284 static unsigned int ifthen_next_state
;
5285 /* The address of the insn for which the IT state is valid. */
5286 static bfd_vma ifthen_address
;
5287 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5288 /* Indicates that the current Conditional state is unconditional or outside
5290 #define COND_UNCOND 16
5294 /* Extract the predicate mask for a VPT or VPST instruction.
5295 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5298 mve_extract_pred_mask (long given
)
5300 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
5303 /* Return the number of instructions in a MVE predicate block. */
5305 num_instructions_vpt_block (long given
)
5307 long mask
= mve_extract_pred_mask (given
);
5314 if ((mask
& 7) == 4)
5317 if ((mask
& 3) == 2)
5320 if ((mask
& 1) == 1)
5327 mark_outside_vpt_block (void)
5329 vpt_block_state
.in_vpt_block
= FALSE
;
5330 vpt_block_state
.next_pred_state
= PRED_NONE
;
5331 vpt_block_state
.predicate_mask
= 0;
5332 vpt_block_state
.current_insn_num
= 0;
5333 vpt_block_state
.num_pred_insn
= 0;
5337 mark_inside_vpt_block (long given
)
5339 vpt_block_state
.in_vpt_block
= TRUE
;
5340 vpt_block_state
.next_pred_state
= PRED_THEN
;
5341 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
5342 vpt_block_state
.current_insn_num
= 0;
5343 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
5344 assert (vpt_block_state
.num_pred_insn
>= 1);
5347 static enum vpt_pred_state
5348 invert_next_predicate_state (enum vpt_pred_state astate
)
5350 if (astate
== PRED_THEN
)
5352 else if (astate
== PRED_ELSE
)
5358 static enum vpt_pred_state
5359 update_next_predicate_state (void)
5361 long pred_mask
= vpt_block_state
.predicate_mask
;
5362 long mask_for_insn
= 0;
5364 switch (vpt_block_state
.current_insn_num
)
5382 if (pred_mask
& mask_for_insn
)
5383 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
5385 return vpt_block_state
.next_pred_state
;
5389 update_vpt_block_state (void)
5391 vpt_block_state
.current_insn_num
++;
5392 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
5394 /* No more instructions to process in vpt block. */
5395 mark_outside_vpt_block ();
5399 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
5402 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5403 Returns pointer to following character of the format string and
5404 fills in *VALUEP and *WIDTHP with the extracted value and number of
5405 bits extracted. WIDTHP can be NULL. */
5408 arm_decode_bitfield (const char *ptr
,
5410 unsigned long *valuep
,
5413 unsigned long value
= 0;
5421 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5422 start
= start
* 10 + *ptr
- '0';
5424 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5425 end
= end
* 10 + *ptr
- '0';
5431 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
5434 while (*ptr
++ == ',');
5442 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
5443 bfd_boolean print_shift
)
5445 func (stream
, "%s", arm_regnames
[given
& 0xf]);
5447 if ((given
& 0xff0) != 0)
5449 if ((given
& 0x10) == 0)
5451 int amount
= (given
& 0xf80) >> 7;
5452 int shift
= (given
& 0x60) >> 5;
5458 func (stream
, ", rrx");
5466 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
5468 func (stream
, ", #%d", amount
);
5470 else if ((given
& 0x80) == 0x80)
5471 func (stream
, "\t; <illegal shifter operand>");
5472 else if (print_shift
)
5473 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
5474 arm_regnames
[(given
& 0xf00) >> 8]);
5476 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
5480 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5483 is_mve_okay_in_it (enum mve_instructions matched_insn
)
5485 switch (matched_insn
)
5487 case MVE_VMOV_GP_TO_VEC_LANE
:
5488 case MVE_VMOV2_VEC_LANE_TO_GP
:
5489 case MVE_VMOV2_GP_TO_VEC_LANE
:
5490 case MVE_VMOV_VEC_LANE_TO_GP
:
5515 is_mve_architecture (struct disassemble_info
*info
)
5517 struct arm_private_data
*private_data
= info
->private_data
;
5518 arm_feature_set allowed_arches
= private_data
->features
;
5520 arm_feature_set arm_ext_v8_1m_main
5521 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
5523 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
5524 && !ARM_CPU_IS_ANY (allowed_arches
))
5531 is_vpt_instruction (long given
)
5534 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5535 if ((given
& 0x0040e000) == 0)
5538 /* VPT floating point T1 variant. */
5539 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
5540 /* VPT floating point T2 variant. */
5541 || ((given
& 0xefb10f50) == 0xee310f40)
5542 /* VPT vector T1 variant. */
5543 || ((given
& 0xff811f51) == 0xfe010f00)
5544 /* VPT vector T2 variant. */
5545 || ((given
& 0xff811f51) == 0xfe010f01
5546 && ((given
& 0x300000) != 0x300000))
5547 /* VPT vector T3 variant. */
5548 || ((given
& 0xff811f50) == 0xfe011f00)
5549 /* VPT vector T4 variant. */
5550 || ((given
& 0xff811f70) == 0xfe010f40)
5551 /* VPT vector T5 variant. */
5552 || ((given
& 0xff811f70) == 0xfe010f60)
5553 /* VPT vector T6 variant. */
5554 || ((given
& 0xff811f50) == 0xfe011f40)
5555 /* VPST vector T variant. */
5556 || ((given
& 0xffbf1fff) == 0xfe310f4d))
5562 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5563 and ending bitfield = END. END must be greater than START. */
5565 static unsigned long
5566 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
5568 int bits
= end
- start
;
5573 return ((given
>> start
) & ((2ul << bits
) - 1));
5576 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5577 START:END and START2:END2. END/END2 must be greater than
5580 static unsigned long
5581 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
5582 unsigned int end
, unsigned int start2
,
5585 int bits
= end
- start
;
5586 int bits2
= end2
- start2
;
5587 unsigned long value
= 0;
5593 value
= arm_decode_field (given
, start
, end
);
5596 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
5600 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5601 This helps us decode instructions that change mnemonic depending on specific
5602 operand values/encodings. */
5605 is_mve_encoding_conflict (unsigned long given
,
5606 enum mve_instructions matched_insn
)
5608 switch (matched_insn
)
5611 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5617 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5619 if ((arm_decode_field (given
, 12, 12) == 0)
5620 && (arm_decode_field (given
, 0, 0) == 1))
5625 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5627 if (arm_decode_field (given
, 0, 3) == 0xd)
5631 case MVE_VPT_VEC_T1
:
5632 case MVE_VPT_VEC_T2
:
5633 case MVE_VPT_VEC_T3
:
5634 case MVE_VPT_VEC_T4
:
5635 case MVE_VPT_VEC_T5
:
5636 case MVE_VPT_VEC_T6
:
5637 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5639 if (arm_decode_field (given
, 20, 21) == 3)
5643 case MVE_VCMP_FP_T1
:
5644 if ((arm_decode_field (given
, 12, 12) == 0)
5645 && (arm_decode_field (given
, 0, 0) == 1))
5650 case MVE_VCMP_FP_T2
:
5651 if (arm_decode_field (given
, 0, 3) == 0xd)
5658 case MVE_VMUL_VEC_T2
:
5665 case MVE_VADD_VEC_T2
:
5666 case MVE_VSUB_VEC_T2
:
5683 case MVE_VQDMULH_T3
:
5684 case MVE_VQRDMULH_T4
:
5690 case MVE_VCMP_VEC_T1
:
5691 case MVE_VCMP_VEC_T2
:
5692 case MVE_VCMP_VEC_T3
:
5693 case MVE_VCMP_VEC_T4
:
5694 case MVE_VCMP_VEC_T5
:
5695 case MVE_VCMP_VEC_T6
:
5696 if (arm_decode_field (given
, 20, 21) == 3)
5705 if (arm_decode_field (given
, 7, 8) == 3)
5712 if ((arm_decode_field (given
, 24, 24) == 0)
5713 && (arm_decode_field (given
, 21, 21) == 0))
5717 else if ((arm_decode_field (given
, 7, 8) == 3))
5725 if ((arm_decode_field (given
, 24, 24) == 0)
5726 && (arm_decode_field (given
, 21, 21) == 0))
5733 case MVE_VCVT_FP_FIX_VEC
:
5734 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
5739 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5741 if ((cmode
& 1) == 0)
5743 else if ((cmode
& 0xc) == 0xc)
5751 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5755 else if ((cmode
& 0x9) == 1)
5757 else if ((cmode
& 0xd) == 9)
5763 case MVE_VMOV_IMM_TO_VEC
:
5764 if ((arm_decode_field (given
, 5, 5) == 1)
5765 && (arm_decode_field (given
, 8, 11) != 0xe))
5772 unsigned long size
= arm_decode_field (given
, 19, 20);
5773 if ((size
== 0) || (size
== 3))
5794 if (arm_decode_field (given
, 18, 19) == 3)
5800 case MVE_VRMLSLDAVH
:
5803 if (arm_decode_field (given
, 20, 22) == 7)
5808 case MVE_VRMLALDAVH
:
5809 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
5816 if ((arm_decode_field (given
, 20, 21) == 3)
5817 || (arm_decode_field (given
, 1, 3) == 7))
5824 if (arm_decode_field (given
, 16, 18) == 0)
5826 unsigned long sz
= arm_decode_field (given
, 19, 20);
5828 if ((sz
== 1) || (sz
== 2))
5843 if (arm_decode_field (given
, 19, 21) == 0)
5849 if (arm_decode_field (given
, 16, 19) == 0xf)
5865 if (arm_decode_field (given
, 9, 11) == 0x7)
5873 unsigned long rm
, rn
;
5874 rm
= arm_decode_field (given
, 0, 3);
5875 rn
= arm_decode_field (given
, 16, 19);
5877 if (rm
== 0xf && rn
== 0xf)
5880 else if (rn
== rm
&& rn
!= 0xf)
5886 if (arm_decode_field (given
, 0, 3) == 0xd)
5889 else if (matched_insn
== MVE_CSNEG
)
5890 if (arm_decode_field (given
, 0, 3) == arm_decode_field (given
, 16, 19))
5895 case MVE_VADD_FP_T1
:
5896 case MVE_VADD_FP_T2
:
5897 case MVE_VADD_VEC_T1
:
5904 print_mve_vld_str_addr (struct disassemble_info
*info
,
5905 unsigned long given
,
5906 enum mve_instructions matched_insn
)
5908 void *stream
= info
->stream
;
5909 fprintf_ftype func
= info
->fprintf_func
;
5911 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
5913 imm
= arm_decode_field (given
, 0, 6);
5916 switch (matched_insn
)
5920 gpr
= arm_decode_field (given
, 16, 18);
5925 gpr
= arm_decode_field (given
, 16, 18);
5931 gpr
= arm_decode_field (given
, 16, 19);
5937 gpr
= arm_decode_field (given
, 16, 19);
5943 gpr
= arm_decode_field (given
, 16, 19);
5950 p
= arm_decode_field (given
, 24, 24);
5951 w
= arm_decode_field (given
, 21, 21);
5953 add
= arm_decode_field (given
, 23, 23);
5957 /* Don't print anything for '+' as it is implied. */
5967 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
5968 /* Pre-indexed mode. */
5970 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
5972 else if ((p
== 0) && (w
== 1))
5973 /* Post-index mode. */
5974 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
5977 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5978 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5979 this encoding is undefined. */
5982 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
5983 enum mve_undefined
*undefined_code
)
5985 *undefined_code
= UNDEF_NONE
;
5987 switch (matched_insn
)
5990 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
5992 *undefined_code
= UNDEF_SIZE_3
;
6000 case MVE_VMUL_VEC_T1
:
6002 case MVE_VADD_VEC_T1
:
6003 case MVE_VSUB_VEC_T1
:
6004 case MVE_VQDMULH_T1
:
6005 case MVE_VQRDMULH_T2
:
6009 if (arm_decode_field (given
, 20, 21) == 3)
6011 *undefined_code
= UNDEF_SIZE_3
;
6018 if (arm_decode_field (given
, 7, 8) == 3)
6020 *undefined_code
= UNDEF_SIZE_3
;
6027 if (arm_decode_field (given
, 7, 8) <= 1)
6029 *undefined_code
= UNDEF_SIZE_LE_1
;
6036 if ((arm_decode_field (given
, 7, 8) == 0))
6038 *undefined_code
= UNDEF_SIZE_0
;
6045 if ((arm_decode_field (given
, 7, 8) <= 1))
6047 *undefined_code
= UNDEF_SIZE_LE_1
;
6053 case MVE_VLDRB_GATHER_T1
:
6054 if (arm_decode_field (given
, 7, 8) == 3)
6056 *undefined_code
= UNDEF_SIZE_3
;
6059 else if ((arm_decode_field (given
, 28, 28) == 0)
6060 && (arm_decode_field (given
, 7, 8) == 0))
6062 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
6068 case MVE_VLDRH_GATHER_T2
:
6069 if (arm_decode_field (given
, 7, 8) == 3)
6071 *undefined_code
= UNDEF_SIZE_3
;
6074 else if ((arm_decode_field (given
, 28, 28) == 0)
6075 && (arm_decode_field (given
, 7, 8) == 1))
6077 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
6080 else if (arm_decode_field (given
, 7, 8) == 0)
6082 *undefined_code
= UNDEF_SIZE_0
;
6088 case MVE_VLDRW_GATHER_T3
:
6089 if (arm_decode_field (given
, 7, 8) != 2)
6091 *undefined_code
= UNDEF_SIZE_NOT_2
;
6094 else if (arm_decode_field (given
, 28, 28) == 0)
6096 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6102 case MVE_VLDRD_GATHER_T4
:
6103 if (arm_decode_field (given
, 7, 8) != 3)
6105 *undefined_code
= UNDEF_SIZE_NOT_3
;
6108 else if (arm_decode_field (given
, 28, 28) == 0)
6110 *undefined_code
= UNDEF_NOT_UNSIGNED
;
6116 case MVE_VSTRB_SCATTER_T1
:
6117 if (arm_decode_field (given
, 7, 8) == 3)
6119 *undefined_code
= UNDEF_SIZE_3
;
6125 case MVE_VSTRH_SCATTER_T2
:
6127 unsigned long size
= arm_decode_field (given
, 7, 8);
6130 *undefined_code
= UNDEF_SIZE_3
;
6135 *undefined_code
= UNDEF_SIZE_0
;
6142 case MVE_VSTRW_SCATTER_T3
:
6143 if (arm_decode_field (given
, 7, 8) != 2)
6145 *undefined_code
= UNDEF_SIZE_NOT_2
;
6151 case MVE_VSTRD_SCATTER_T4
:
6152 if (arm_decode_field (given
, 7, 8) != 3)
6154 *undefined_code
= UNDEF_SIZE_NOT_3
;
6160 case MVE_VCVT_FP_FIX_VEC
:
6162 unsigned long imm6
= arm_decode_field (given
, 16, 21);
6163 if ((imm6
& 0x20) == 0)
6165 *undefined_code
= UNDEF_VCVT_IMM6
;
6169 if ((arm_decode_field (given
, 9, 9) == 0)
6170 && ((imm6
& 0x30) == 0x20))
6172 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
6181 case MVE_VCVT_BETWEEN_FP_INT
:
6182 case MVE_VCVT_FROM_FP_TO_INT
:
6184 unsigned long size
= arm_decode_field (given
, 18, 19);
6187 *undefined_code
= UNDEF_SIZE_0
;
6192 *undefined_code
= UNDEF_SIZE_3
;
6199 case MVE_VMOV_VEC_LANE_TO_GP
:
6201 unsigned long op1
= arm_decode_field (given
, 21, 22);
6202 unsigned long op2
= arm_decode_field (given
, 5, 6);
6203 unsigned long u
= arm_decode_field (given
, 23, 23);
6205 if ((op2
== 0) && (u
== 1))
6207 if ((op1
== 0) || (op1
== 1))
6209 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
6217 if ((op1
== 0) || (op1
== 1))
6219 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6229 case MVE_VMOV_GP_TO_VEC_LANE
:
6230 if (arm_decode_field (given
, 5, 6) == 2)
6232 unsigned long op1
= arm_decode_field (given
, 21, 22);
6233 if ((op1
== 0) || (op1
== 1))
6235 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6244 case MVE_VMOV_VEC_TO_VEC
:
6245 if ((arm_decode_field (given
, 5, 5) == 1)
6246 || (arm_decode_field (given
, 22, 22) == 1))
6250 case MVE_VMOV_IMM_TO_VEC
:
6251 if (arm_decode_field (given
, 5, 5) == 0)
6253 unsigned long cmode
= arm_decode_field (given
, 8, 11);
6255 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
6257 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
6268 if (arm_decode_field (given
, 18, 19) == 2)
6270 *undefined_code
= UNDEF_SIZE_2
;
6276 case MVE_VRMLALDAVH
:
6277 case MVE_VMLADAV_T1
:
6278 case MVE_VMLADAV_T2
:
6280 if ((arm_decode_field (given
, 28, 28) == 1)
6281 && (arm_decode_field (given
, 12, 12) == 1))
6283 *undefined_code
= UNDEF_XCHG_UNS
;
6294 unsigned long sz
= arm_decode_field (given
, 19, 20);
6297 else if ((sz
& 2) == 2)
6301 *undefined_code
= UNDEF_SIZE
;
6315 unsigned long sz
= arm_decode_field (given
, 19, 21);
6318 else if ((sz
& 6) == 2)
6320 else if ((sz
& 4) == 4)
6324 *undefined_code
= UNDEF_SIZE
;
6331 if (arm_decode_field (given
, 19, 20) == 0)
6333 *undefined_code
= UNDEF_SIZE_0
;
6340 if (arm_decode_field (given
, 18, 19) == 3)
6342 *undefined_code
= UNDEF_SIZE_3
;
6353 if (arm_decode_field (given
, 18, 19) == 3)
6355 *undefined_code
= UNDEF_SIZE_3
;
6362 if (arm_decode_field (given
, 18, 19) == 0)
6366 *undefined_code
= UNDEF_SIZE_NOT_0
;
6372 unsigned long size
= arm_decode_field (given
, 18, 19);
6373 if ((size
& 2) == 2)
6375 *undefined_code
= UNDEF_SIZE_2
;
6383 if (arm_decode_field (given
, 18, 19) != 3)
6387 *undefined_code
= UNDEF_SIZE_3
;
6396 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6397 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6398 why this encoding is unpredictable. */
6401 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
6402 enum mve_unpredictable
*unpredictable_code
)
6404 *unpredictable_code
= UNPRED_NONE
;
6406 switch (matched_insn
)
6408 case MVE_VCMP_FP_T2
:
6410 if ((arm_decode_field (given
, 12, 12) == 0)
6411 && (arm_decode_field (given
, 5, 5) == 1))
6413 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
6419 case MVE_VPT_VEC_T4
:
6420 case MVE_VPT_VEC_T5
:
6421 case MVE_VPT_VEC_T6
:
6422 case MVE_VCMP_VEC_T4
:
6423 case MVE_VCMP_VEC_T5
:
6424 case MVE_VCMP_VEC_T6
:
6425 if (arm_decode_field (given
, 0, 3) == 0xd)
6427 *unpredictable_code
= UNPRED_R13
;
6435 unsigned long gpr
= arm_decode_field (given
, 12, 15);
6438 *unpredictable_code
= UNPRED_R13
;
6441 else if (gpr
== 0xf)
6443 *unpredictable_code
= UNPRED_R15
;
6452 case MVE_VMUL_FP_T2
:
6453 case MVE_VMUL_VEC_T2
:
6456 case MVE_VADD_FP_T2
:
6457 case MVE_VSUB_FP_T2
:
6458 case MVE_VADD_VEC_T2
:
6459 case MVE_VSUB_VEC_T2
:
6469 case MVE_VQDMULH_T3
:
6470 case MVE_VQRDMULH_T4
:
6472 case MVE_VFMA_FP_SCALAR
:
6473 case MVE_VFMAS_FP_SCALAR
:
6477 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6480 *unpredictable_code
= UNPRED_R13
;
6483 else if (gpr
== 0xf)
6485 *unpredictable_code
= UNPRED_R15
;
6495 unsigned long rn
= arm_decode_field (given
, 16, 19);
6497 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6499 *unpredictable_code
= UNPRED_R13_AND_WB
;
6505 *unpredictable_code
= UNPRED_R15
;
6509 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
6511 *unpredictable_code
= UNPRED_Q_GT_6
;
6521 unsigned long rn
= arm_decode_field (given
, 16, 19);
6523 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6525 *unpredictable_code
= UNPRED_R13_AND_WB
;
6531 *unpredictable_code
= UNPRED_R15
;
6535 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
6537 *unpredictable_code
= UNPRED_Q_GT_4
;
6551 unsigned long rn
= arm_decode_field (given
, 16, 19);
6553 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6555 *unpredictable_code
= UNPRED_R13_AND_WB
;
6560 *unpredictable_code
= UNPRED_R15
;
6567 case MVE_VLDRB_GATHER_T1
:
6568 if (arm_decode_field (given
, 0, 0) == 1)
6570 *unpredictable_code
= UNPRED_OS
;
6575 /* To handle common code with T2-T4 variants. */
6576 case MVE_VLDRH_GATHER_T2
:
6577 case MVE_VLDRW_GATHER_T3
:
6578 case MVE_VLDRD_GATHER_T4
:
6580 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6581 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6585 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6589 if (arm_decode_field (given
, 16, 19) == 0xf)
6591 *unpredictable_code
= UNPRED_R15
;
6598 case MVE_VLDRW_GATHER_T5
:
6599 case MVE_VLDRD_GATHER_T6
:
6601 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6602 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6606 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6613 case MVE_VSTRB_SCATTER_T1
:
6614 if (arm_decode_field (given
, 16, 19) == 0xf)
6616 *unpredictable_code
= UNPRED_R15
;
6619 else if (arm_decode_field (given
, 0, 0) == 1)
6621 *unpredictable_code
= UNPRED_OS
;
6627 case MVE_VSTRH_SCATTER_T2
:
6628 case MVE_VSTRW_SCATTER_T3
:
6629 case MVE_VSTRD_SCATTER_T4
:
6630 if (arm_decode_field (given
, 16, 19) == 0xf)
6632 *unpredictable_code
= UNPRED_R15
;
6638 case MVE_VMOV2_VEC_LANE_TO_GP
:
6639 case MVE_VMOV2_GP_TO_VEC_LANE
:
6640 case MVE_VCVT_BETWEEN_FP_INT
:
6641 case MVE_VCVT_FROM_FP_TO_INT
:
6643 unsigned long rt
= arm_decode_field (given
, 0, 3);
6644 unsigned long rt2
= arm_decode_field (given
, 16, 19);
6646 if ((rt
== 0xd) || (rt2
== 0xd))
6648 *unpredictable_code
= UNPRED_R13
;
6651 else if ((rt
== 0xf) || (rt2
== 0xf))
6653 *unpredictable_code
= UNPRED_R15
;
6658 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
6667 case MVE_VMAXNMV_FP
:
6668 case MVE_VMAXNMAV_FP
:
6669 case MVE_VMINNMV_FP
:
6670 case MVE_VMINNMAV_FP
:
6674 case MVE_VMOV_HFP_TO_GP
:
6675 case MVE_VMOV_GP_TO_VEC_LANE
:
6676 case MVE_VMOV_VEC_LANE_TO_GP
:
6678 unsigned long rda
= arm_decode_field (given
, 12, 15);
6681 *unpredictable_code
= UNPRED_R13
;
6684 else if (rda
== 0xf)
6686 *unpredictable_code
= UNPRED_R15
;
6699 if (arm_decode_field (given
, 20, 21) == 2)
6701 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6702 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6703 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6705 if ((Qd
== Qn
) || (Qd
== Qm
))
6707 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6718 case MVE_VQDMULL_T1
:
6724 if (arm_decode_field (given
, 28, 28) == 1)
6726 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6727 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6728 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6730 if ((Qd
== Qn
) || (Qd
== Qm
))
6732 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6742 case MVE_VQDMULL_T2
:
6744 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6747 *unpredictable_code
= UNPRED_R13
;
6750 else if (gpr
== 0xf)
6752 *unpredictable_code
= UNPRED_R15
;
6756 if (arm_decode_field (given
, 28, 28) == 1)
6759 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6760 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6764 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6775 case MVE_VRMLSLDAVH
:
6778 if (arm_decode_field (given
, 20, 22) == 6)
6780 *unpredictable_code
= UNPRED_R13
;
6788 if (arm_decode_field (given
, 1, 3) == 6)
6790 *unpredictable_code
= UNPRED_R13
;
6799 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6800 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6801 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
6803 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6812 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6813 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6814 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
6816 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6829 if (arm_decode_field (given
, 20, 20) == 1)
6831 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6832 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6833 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6835 if ((Qda
== Qn
) || (Qda
== Qm
))
6837 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6849 if (arm_decode_field (given
, 16, 19) == 0xd)
6851 *unpredictable_code
= UNPRED_R13
;
6859 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6860 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 6, 6);
6864 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6883 unsigned long gpr
= arm_decode_field (given
, 9, 11);
6884 gpr
= ((gpr
<< 1) | 1);
6887 *unpredictable_code
= UNPRED_R13
;
6890 else if (gpr
== 0xf)
6892 *unpredictable_code
= UNPRED_R15
;
6905 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
6907 unsigned long op1
= arm_decode_field (given
, 21, 22);
6908 unsigned long op2
= arm_decode_field (given
, 5, 6);
6909 unsigned long h
= arm_decode_field (given
, 16, 16);
6910 unsigned long index_operand
, esize
, targetBeat
, idx
;
6911 void *stream
= info
->stream
;
6912 fprintf_ftype func
= info
->fprintf_func
;
6914 if ((op1
& 0x2) == 0x2)
6916 index_operand
= op2
;
6919 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
6921 index_operand
= op2
>> 1;
6924 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
6931 func (stream
, "<undefined index>");
6935 targetBeat
= (op1
& 0x1) | (h
<< 1);
6936 idx
= index_operand
+ targetBeat
* (32/esize
);
6938 func (stream
, "%lu", idx
);
6941 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6942 in length and integer of floating-point type. */
6944 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
6945 unsigned int ibit_loc
, const struct mopcode32
*insn
)
6948 int cmode
= (given
>> 8) & 0xf;
6949 int op
= (given
>> 5) & 0x1;
6950 unsigned long value
= 0, hival
= 0;
6954 void *stream
= info
->stream
;
6955 fprintf_ftype func
= info
->fprintf_func
;
6957 /* On Neon the 'i' bit is at bit 24, on mve it is
6959 bits
|= ((given
>> ibit_loc
) & 1) << 7;
6960 bits
|= ((given
>> 16) & 7) << 4;
6961 bits
|= ((given
>> 0) & 15) << 0;
6965 shift
= (cmode
>> 1) & 3;
6966 value
= (unsigned long) bits
<< (8 * shift
);
6969 else if (cmode
< 12)
6971 shift
= (cmode
>> 1) & 1;
6972 value
= (unsigned long) bits
<< (8 * shift
);
6975 else if (cmode
< 14)
6977 shift
= (cmode
& 1) + 1;
6978 value
= (unsigned long) bits
<< (8 * shift
);
6979 value
|= (1ul << (8 * shift
)) - 1;
6982 else if (cmode
== 14)
6986 /* Bit replication into bytes. */
6992 for (ix
= 7; ix
>= 0; ix
--)
6994 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
6996 value
= (value
<< 8) | mask
;
6998 hival
= (hival
<< 8) | mask
;
7004 /* Byte replication. */
7005 value
= (unsigned long) bits
;
7011 /* Floating point encoding. */
7014 value
= (unsigned long) (bits
& 0x7f) << 19;
7015 value
|= (unsigned long) (bits
& 0x80) << 24;
7016 tmp
= bits
& 0x40 ? 0x3c : 0x40;
7017 value
|= (unsigned long) tmp
<< 24;
7023 func (stream
, "<illegal constant %.8x:%x:%x>",
7029 // printU determines whether the immediate value should be printed as
7031 unsigned printU
= 0;
7032 switch (insn
->mve_op
)
7036 // We want this for instructions that don't have a 'signed' type
7040 case MVE_VMOV_IMM_TO_VEC
:
7047 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
7054 : "#%ld\t; 0x%.4lx", value
, value
);
7060 unsigned char valbytes
[4];
7063 /* Do this a byte at a time so we don't have to
7064 worry about the host's endianness. */
7065 valbytes
[0] = value
& 0xff;
7066 valbytes
[1] = (value
>> 8) & 0xff;
7067 valbytes
[2] = (value
>> 16) & 0xff;
7068 valbytes
[3] = (value
>> 24) & 0xff;
7070 floatformat_to_double
7071 (& floatformat_ieee_single_little
, valbytes
,
7074 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
7081 : "#%ld\t; 0x%.8lx",
7082 (long) (((value
& 0x80000000L
) != 0)
7084 ? value
| ~0xffffffffL
: value
),
7089 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
7099 print_mve_undefined (struct disassemble_info
*info
,
7100 enum mve_undefined undefined_code
)
7102 void *stream
= info
->stream
;
7103 fprintf_ftype func
= info
->fprintf_func
;
7105 func (stream
, "\t\tundefined instruction: ");
7107 switch (undefined_code
)
7110 func (stream
, "illegal size");
7114 func (stream
, "size equals zero");
7118 func (stream
, "size equals two");
7122 func (stream
, "size equals three");
7125 case UNDEF_SIZE_LE_1
:
7126 func (stream
, "size <= 1");
7129 case UNDEF_SIZE_NOT_0
:
7130 func (stream
, "size not equal to 0");
7133 case UNDEF_SIZE_NOT_2
:
7134 func (stream
, "size not equal to 2");
7137 case UNDEF_SIZE_NOT_3
:
7138 func (stream
, "size not equal to 3");
7141 case UNDEF_NOT_UNS_SIZE_0
:
7142 func (stream
, "not unsigned and size = zero");
7145 case UNDEF_NOT_UNS_SIZE_1
:
7146 func (stream
, "not unsigned and size = one");
7149 case UNDEF_NOT_UNSIGNED
:
7150 func (stream
, "not unsigned");
7153 case UNDEF_VCVT_IMM6
:
7154 func (stream
, "invalid imm6");
7157 case UNDEF_VCVT_FSI_IMM6
:
7158 func (stream
, "fsi = 0 and invalid imm6");
7161 case UNDEF_BAD_OP1_OP2
:
7162 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
7165 case UNDEF_BAD_U_OP1_OP2
:
7166 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
7169 case UNDEF_OP_0_BAD_CMODE
:
7170 func (stream
, "op field equal 0 and bad cmode");
7173 case UNDEF_XCHG_UNS
:
7174 func (stream
, "exchange and unsigned together");
7184 print_mve_unpredictable (struct disassemble_info
*info
,
7185 enum mve_unpredictable unpredict_code
)
7187 void *stream
= info
->stream
;
7188 fprintf_ftype func
= info
->fprintf_func
;
7190 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
7192 switch (unpredict_code
)
7194 case UNPRED_IT_BLOCK
:
7195 func (stream
, "mve instruction in it block");
7198 case UNPRED_FCA_0_FCB_1
:
7199 func (stream
, "condition bits, fca = 0 and fcb = 1");
7203 func (stream
, "use of r13 (sp)");
7207 func (stream
, "use of r15 (pc)");
7211 func (stream
, "start register block > r4");
7215 func (stream
, "start register block > r6");
7218 case UNPRED_R13_AND_WB
:
7219 func (stream
, "use of r13 and write back");
7222 case UNPRED_Q_REGS_EQUAL
:
7224 "same vector register used for destination and other operand");
7228 func (stream
, "use of offset scaled");
7231 case UNPRED_GP_REGS_EQUAL
:
7232 func (stream
, "same general-purpose register used for both operands");
7235 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
7236 func (stream
, "use of identical q registers and size = 1");
7239 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
7240 func (stream
, "use of identical q registers and size = 1");
7248 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7251 print_mve_register_blocks (struct disassemble_info
*info
,
7252 unsigned long given
,
7253 enum mve_instructions matched_insn
)
7255 void *stream
= info
->stream
;
7256 fprintf_ftype func
= info
->fprintf_func
;
7258 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
7261 switch (matched_insn
)
7265 if (q_reg_start
<= 6)
7266 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
7268 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7273 if (q_reg_start
<= 4)
7274 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
7275 q_reg_start
+ 1, q_reg_start
+ 2,
7278 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7287 print_mve_rounding_mode (struct disassemble_info
*info
,
7288 unsigned long given
,
7289 enum mve_instructions matched_insn
)
7291 void *stream
= info
->stream
;
7292 fprintf_ftype func
= info
->fprintf_func
;
7294 switch (matched_insn
)
7296 case MVE_VCVT_FROM_FP_TO_INT
:
7298 switch (arm_decode_field (given
, 8, 9))
7324 switch (arm_decode_field (given
, 7, 9))
7363 print_mve_vcvt_size (struct disassemble_info
*info
,
7364 unsigned long given
,
7365 enum mve_instructions matched_insn
)
7367 unsigned long mode
= 0;
7368 void *stream
= info
->stream
;
7369 fprintf_ftype func
= info
->fprintf_func
;
7371 switch (matched_insn
)
7373 case MVE_VCVT_FP_FIX_VEC
:
7375 mode
= (((given
& 0x200) >> 7)
7376 | ((given
& 0x10000000) >> 27)
7377 | ((given
& 0x100) >> 8));
7382 func (stream
, "f16.s16");
7386 func (stream
, "s16.f16");
7390 func (stream
, "f16.u16");
7394 func (stream
, "u16.f16");
7398 func (stream
, "f32.s32");
7402 func (stream
, "s32.f32");
7406 func (stream
, "f32.u32");
7410 func (stream
, "u32.f32");
7418 case MVE_VCVT_BETWEEN_FP_INT
:
7420 unsigned long size
= arm_decode_field (given
, 18, 19);
7421 unsigned long op
= arm_decode_field (given
, 7, 8);
7428 func (stream
, "f16.s16");
7432 func (stream
, "f16.u16");
7436 func (stream
, "s16.f16");
7440 func (stream
, "u16.f16");
7452 func (stream
, "f32.s32");
7456 func (stream
, "f32.u32");
7460 func (stream
, "s32.f32");
7464 func (stream
, "u32.f32");
7471 case MVE_VCVT_FP_HALF_FP
:
7473 unsigned long op
= arm_decode_field (given
, 28, 28);
7475 func (stream
, "f16.f32");
7477 func (stream
, "f32.f16");
7481 case MVE_VCVT_FROM_FP_TO_INT
:
7483 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
7488 func (stream
, "s16.f16");
7492 func (stream
, "u16.f16");
7496 func (stream
, "s32.f32");
7500 func (stream
, "u32.f32");
7515 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
7516 unsigned long rot_width
)
7518 void *stream
= info
->stream
;
7519 fprintf_ftype func
= info
->fprintf_func
;
7526 func (stream
, "90");
7529 func (stream
, "270");
7535 else if (rot_width
== 2)
7543 func (stream
, "90");
7546 func (stream
, "180");
7549 func (stream
, "270");
7558 print_instruction_predicate (struct disassemble_info
*info
)
7560 void *stream
= info
->stream
;
7561 fprintf_ftype func
= info
->fprintf_func
;
7563 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
7565 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
7570 print_mve_size (struct disassemble_info
*info
,
7572 enum mve_instructions matched_insn
)
7574 void *stream
= info
->stream
;
7575 fprintf_ftype func
= info
->fprintf_func
;
7577 switch (matched_insn
)
7583 case MVE_VADD_VEC_T1
:
7584 case MVE_VADD_VEC_T2
:
7590 case MVE_VCMP_VEC_T1
:
7591 case MVE_VCMP_VEC_T2
:
7592 case MVE_VCMP_VEC_T3
:
7593 case MVE_VCMP_VEC_T4
:
7594 case MVE_VCMP_VEC_T5
:
7595 case MVE_VCMP_VEC_T6
:
7608 case MVE_VLDRB_GATHER_T1
:
7609 case MVE_VLDRH_GATHER_T2
:
7610 case MVE_VLDRW_GATHER_T3
:
7611 case MVE_VLDRD_GATHER_T4
:
7624 case MVE_VMUL_VEC_T1
:
7625 case MVE_VMUL_VEC_T2
:
7631 case MVE_VPT_VEC_T1
:
7632 case MVE_VPT_VEC_T2
:
7633 case MVE_VPT_VEC_T3
:
7634 case MVE_VPT_VEC_T4
:
7635 case MVE_VPT_VEC_T5
:
7636 case MVE_VPT_VEC_T6
:
7648 case MVE_VQDMULH_T1
:
7649 case MVE_VQRDMULH_T2
:
7650 case MVE_VQDMULH_T3
:
7651 case MVE_VQRDMULH_T4
:
7670 case MVE_VSTRB_SCATTER_T1
:
7671 case MVE_VSTRH_SCATTER_T2
:
7672 case MVE_VSTRW_SCATTER_T3
:
7675 case MVE_VSUB_VEC_T1
:
7676 case MVE_VSUB_VEC_T2
:
7678 func (stream
, "%s", mve_vec_sizename
[size
]);
7680 func (stream
, "<undef size>");
7684 case MVE_VADD_FP_T1
:
7685 case MVE_VADD_FP_T2
:
7686 case MVE_VSUB_FP_T1
:
7687 case MVE_VSUB_FP_T2
:
7688 case MVE_VCMP_FP_T1
:
7689 case MVE_VCMP_FP_T2
:
7690 case MVE_VFMA_FP_SCALAR
:
7693 case MVE_VFMAS_FP_SCALAR
:
7695 case MVE_VMAXNMA_FP
:
7696 case MVE_VMAXNMV_FP
:
7697 case MVE_VMAXNMAV_FP
:
7699 case MVE_VMINNMA_FP
:
7700 case MVE_VMINNMV_FP
:
7701 case MVE_VMINNMAV_FP
:
7702 case MVE_VMUL_FP_T1
:
7703 case MVE_VMUL_FP_T2
:
7707 func (stream
, "32");
7709 func (stream
, "16");
7715 case MVE_VMLADAV_T1
:
7717 case MVE_VMLSDAV_T1
:
7720 case MVE_VQDMULL_T1
:
7721 case MVE_VQDMULL_T2
:
7725 func (stream
, "16");
7727 func (stream
, "32");
7734 func (stream
, "16");
7741 func (stream
, "32");
7744 func (stream
, "16");
7754 case MVE_VMOV_GP_TO_VEC_LANE
:
7755 case MVE_VMOV_VEC_LANE_TO_GP
:
7759 func (stream
, "32");
7764 func (stream
, "16");
7767 case 8: case 9: case 10: case 11:
7768 case 12: case 13: case 14: case 15:
7777 case MVE_VMOV_IMM_TO_VEC
:
7780 case 0: case 4: case 8:
7781 case 12: case 24: case 26:
7782 func (stream
, "i32");
7785 func (stream
, "i16");
7788 func (stream
, "i8");
7791 func (stream
, "i64");
7794 func (stream
, "f32");
7801 case MVE_VMULL_POLY
:
7803 func (stream
, "p8");
7805 func (stream
, "p16");
7811 case 0: case 2: case 4:
7812 case 6: case 12: case 13:
7813 func (stream
, "32");
7817 func (stream
, "16");
7831 func (stream
, "32");
7835 func (stream
, "16");
7853 func (stream
, "16");
7857 func (stream
, "32");
7882 func (stream
, "16");
7885 case 4: case 5: case 6: case 7:
7886 func (stream
, "32");
7901 print_mve_shift_n (struct disassemble_info
*info
, long given
,
7902 enum mve_instructions matched_insn
)
7904 void *stream
= info
->stream
;
7905 fprintf_ftype func
= info
->fprintf_func
;
7908 = matched_insn
== MVE_VQSHL_T2
7909 || matched_insn
== MVE_VQSHLU_T3
7910 || matched_insn
== MVE_VSHL_T1
7911 || matched_insn
== MVE_VSHLL_T1
7912 || matched_insn
== MVE_VSLI
;
7914 unsigned imm6
= (given
& 0x3f0000) >> 16;
7916 if (matched_insn
== MVE_VSHLL_T1
)
7919 unsigned shiftAmount
= 0;
7920 if ((imm6
& 0x20) != 0)
7921 shiftAmount
= startAt0
? imm6
- 32 : 64 - imm6
;
7922 else if ((imm6
& 0x10) != 0)
7923 shiftAmount
= startAt0
? imm6
- 16 : 32 - imm6
;
7924 else if ((imm6
& 0x08) != 0)
7925 shiftAmount
= startAt0
? imm6
- 8 : 16 - imm6
;
7927 print_mve_undefined (info
, UNDEF_SIZE_0
);
7929 func (stream
, "%u", shiftAmount
);
7933 print_vec_condition (struct disassemble_info
*info
, long given
,
7934 enum mve_instructions matched_insn
)
7936 void *stream
= info
->stream
;
7937 fprintf_ftype func
= info
->fprintf_func
;
7940 switch (matched_insn
)
7943 case MVE_VCMP_FP_T1
:
7944 vec_cond
= (((given
& 0x1000) >> 10)
7945 | ((given
& 1) << 1)
7946 | ((given
& 0x0080) >> 7));
7947 func (stream
, "%s",vec_condnames
[vec_cond
]);
7951 case MVE_VCMP_FP_T2
:
7952 vec_cond
= (((given
& 0x1000) >> 10)
7953 | ((given
& 0x0020) >> 4)
7954 | ((given
& 0x0080) >> 7));
7955 func (stream
, "%s",vec_condnames
[vec_cond
]);
7958 case MVE_VPT_VEC_T1
:
7959 case MVE_VCMP_VEC_T1
:
7960 vec_cond
= (given
& 0x0080) >> 7;
7961 func (stream
, "%s",vec_condnames
[vec_cond
]);
7964 case MVE_VPT_VEC_T2
:
7965 case MVE_VCMP_VEC_T2
:
7966 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7967 func (stream
, "%s",vec_condnames
[vec_cond
]);
7970 case MVE_VPT_VEC_T3
:
7971 case MVE_VCMP_VEC_T3
:
7972 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
7973 func (stream
, "%s",vec_condnames
[vec_cond
]);
7976 case MVE_VPT_VEC_T4
:
7977 case MVE_VCMP_VEC_T4
:
7978 vec_cond
= (given
& 0x0080) >> 7;
7979 func (stream
, "%s",vec_condnames
[vec_cond
]);
7982 case MVE_VPT_VEC_T5
:
7983 case MVE_VCMP_VEC_T5
:
7984 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7985 func (stream
, "%s",vec_condnames
[vec_cond
]);
7988 case MVE_VPT_VEC_T6
:
7989 case MVE_VCMP_VEC_T6
:
7990 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
7991 func (stream
, "%s",vec_condnames
[vec_cond
]);
8006 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
8007 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
8008 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
8009 #define PRE_BIT_SET (given & (1 << P_BIT))
8012 /* Print one coprocessor instruction on INFO->STREAM.
8013 Return TRUE if the instuction matched, FALSE if this is not a
8014 recognised coprocessor instruction. */
8017 print_insn_coprocessor_1 (const struct sopcode32
*opcodes
,
8019 struct disassemble_info
*info
,
8023 const struct sopcode32
*insn
;
8024 void *stream
= info
->stream
;
8025 fprintf_ftype func
= info
->fprintf_func
;
8027 unsigned long value
= 0;
8030 struct arm_private_data
*private_data
= info
->private_data
;
8031 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
8032 arm_feature_set arm_ext_v8_1m_main
=
8033 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
8035 allowed_arches
= private_data
->features
;
8037 for (insn
= opcodes
; insn
->assembler
; insn
++)
8039 unsigned long u_reg
= 16;
8040 bfd_boolean is_unpredictable
= FALSE
;
8041 signed long value_in_comment
= 0;
8044 if (ARM_FEATURE_ZERO (insn
->arch
))
8045 switch (insn
->value
)
8047 case SENTINEL_IWMMXT_START
:
8048 if (info
->mach
!= bfd_mach_arm_XScale
8049 && info
->mach
!= bfd_mach_arm_iWMMXt
8050 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
8053 while ((! ARM_FEATURE_ZERO (insn
->arch
))
8054 && insn
->value
!= SENTINEL_IWMMXT_END
);
8057 case SENTINEL_IWMMXT_END
:
8060 case SENTINEL_GENERIC_START
:
8061 allowed_arches
= private_data
->features
;
8069 value
= insn
->value
;
8070 cp_num
= (given
>> 8) & 0xf;
8074 /* The high 4 bits are 0xe for Arm conditional instructions, and
8075 0xe for arm unconditional instructions. The rest of the
8076 encoding is the same. */
8078 value
|= 0xe0000000;
8086 /* Only match unconditional instuctions against unconditional
8088 if ((given
& 0xf0000000) == 0xf0000000)
8095 cond
= (given
>> 28) & 0xf;
8101 if ((insn
->isa
== T32
&& !thumb
)
8102 || (insn
->isa
== ARM
&& thumb
))
8105 if ((given
& mask
) != value
)
8108 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
8111 if (insn
->value
== 0xfe000010 /* mcr2 */
8112 || insn
->value
== 0xfe100010 /* mrc2 */
8113 || insn
->value
== 0xfc100000 /* ldc2 */
8114 || insn
->value
== 0xfc000000) /* stc2 */
8116 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8117 is_unpredictable
= TRUE
;
8119 /* Armv8.1-M Mainline FP & MVE instructions. */
8120 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8121 && !ARM_CPU_IS_ANY (allowed_arches
)
8122 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8126 else if (insn
->value
== 0x0e000000 /* cdp */
8127 || insn
->value
== 0xfe000000 /* cdp2 */
8128 || insn
->value
== 0x0e000010 /* mcr */
8129 || insn
->value
== 0x0e100010 /* mrc */
8130 || insn
->value
== 0x0c100000 /* ldc */
8131 || insn
->value
== 0x0c000000) /* stc */
8133 /* Floating-point instructions. */
8134 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8137 /* Armv8.1-M Mainline FP & MVE instructions. */
8138 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8139 && !ARM_CPU_IS_ANY (allowed_arches
)
8140 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8143 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
8144 || insn
->value
== 0xec000f80) /* vstr (system register) */
8145 && arm_decode_field (given
, 24, 24) == 0
8146 && arm_decode_field (given
, 21, 21) == 0)
8147 /* If the P and W bits are both 0 then these encodings match the MVE
8148 VLDR and VSTR instructions, these are in a different table, so we
8149 don't let it match here. */
8152 for (c
= insn
->assembler
; *c
; c
++)
8156 const char mod
= *++c
;
8160 func (stream
, "%%");
8166 int rn
= (given
>> 16) & 0xf;
8167 bfd_vma offset
= given
& 0xff;
8170 offset
= given
& 0x7f;
8172 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8174 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
8176 /* Not unindexed. The offset is scaled. */
8178 /* vldr.16/vstr.16 will shift the address
8179 left by 1 bit only. */
8180 offset
= offset
* 2;
8182 offset
= offset
* 4;
8184 if (NEGATIVE_BIT_SET
)
8187 value_in_comment
= offset
;
8193 func (stream
, ", #%d]%s",
8195 WRITEBACK_BIT_SET
? "!" : "");
8196 else if (NEGATIVE_BIT_SET
)
8197 func (stream
, ", #-0]");
8205 if (WRITEBACK_BIT_SET
)
8208 func (stream
, ", #%d", (int) offset
);
8209 else if (NEGATIVE_BIT_SET
)
8210 func (stream
, ", #-0");
8214 func (stream
, ", {%s%d}",
8215 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
8217 value_in_comment
= offset
;
8220 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
8222 func (stream
, "\t; ");
8223 /* For unaligned PCs, apply off-by-alignment
8225 info
->print_address_func (offset
+ pc
8226 + info
->bytes_per_chunk
* 2
8235 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
8236 int offset
= (given
>> 1) & 0x3f;
8239 func (stream
, "{d%d}", regno
);
8240 else if (regno
+ offset
> 32)
8241 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
8243 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
8249 bfd_boolean single
= ((given
>> 8) & 1) == 0;
8250 char reg_prefix
= single
? 's' : 'd';
8251 int Dreg
= (given
>> 22) & 0x1;
8252 int Vdreg
= (given
>> 12) & 0xf;
8253 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
8254 : ((Dreg
<< 4) | Vdreg
);
8255 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
8256 int maxreg
= single
? 31 : 15;
8257 int topreg
= reg
+ num
- 1;
8260 func (stream
, "{VPR}");
8262 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
8263 else if (topreg
> maxreg
)
8264 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
8265 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
8267 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
8268 reg_prefix
, topreg
);
8273 if (cond
!= COND_UNCOND
)
8274 is_unpredictable
= TRUE
;
8278 if (cond
!= COND_UNCOND
&& cp_num
== 9)
8279 is_unpredictable
= TRUE
;
8283 func (stream
, "%s", arm_conditional
[cond
]);
8287 /* Print a Cirrus/DSP shift immediate. */
8288 /* Immediates are 7bit signed ints with bits 0..3 in
8289 bits 0..3 of opcode and bits 4..6 in bits 5..7
8294 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
8296 /* Is ``imm'' a negative number? */
8300 func (stream
, "%d", imm
);
8308 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
8313 func (stream
, "FPSCR");
8316 func (stream
, "FPSCR_nzcvqc");
8319 func (stream
, "VPR");
8322 func (stream
, "P0");
8325 func (stream
, "FPCXTNS");
8328 func (stream
, "FPCXTS");
8331 func (stream
, "<invalid reg %lu>", regno
);
8338 switch (given
& 0x00408000)
8355 switch (given
& 0x00080080)
8367 func (stream
, _("<illegal precision>"));
8373 switch (given
& 0x00408000)
8391 switch (given
& 0x60)
8407 case '0': case '1': case '2': case '3': case '4':
8408 case '5': case '6': case '7': case '8': case '9':
8412 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8418 is_unpredictable
= TRUE
;
8423 /* Eat the 'u' character. */
8427 is_unpredictable
= TRUE
;
8430 func (stream
, "%s", arm_regnames
[value
]);
8433 if (given
& (1 << 6))
8437 func (stream
, "d%ld", value
);
8442 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
8444 func (stream
, "q%ld", value
>> 1);
8447 func (stream
, "%ld", value
);
8448 value_in_comment
= value
;
8452 /* Converts immediate 8 bit back to float value. */
8453 unsigned floatVal
= (value
& 0x80) << 24
8454 | (value
& 0x3F) << 19
8455 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
8457 /* Quarter float have a maximum value of 31.0.
8458 Get floating point value multiplied by 1e7.
8459 The maximum value stays in limit of a 32-bit int. */
8461 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
8462 (16 + (value
& 0xF));
8464 if (!(decVal
% 1000000))
8465 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
8466 floatVal
, value
& 0x80 ? '-' : ' ',
8468 decVal
% 10000000 / 1000000);
8469 else if (!(decVal
% 10000))
8470 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
8471 floatVal
, value
& 0x80 ? '-' : ' ',
8473 decVal
% 10000000 / 10000);
8475 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
8476 floatVal
, value
& 0x80 ? '-' : ' ',
8477 decVal
/ 10000000, decVal
% 10000000);
8482 int from
= (given
& (1 << 7)) ? 32 : 16;
8483 func (stream
, "%ld", from
- value
);
8489 func (stream
, "#%s", arm_fp_const
[value
& 7]);
8491 func (stream
, "f%ld", value
);
8496 func (stream
, "%s", iwmmxt_wwnames
[value
]);
8498 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
8502 func (stream
, "%s", iwmmxt_regnames
[value
]);
8505 func (stream
, "%s", iwmmxt_cregnames
[value
]);
8509 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
8516 func (stream
, "eq");
8520 func (stream
, "vs");
8524 func (stream
, "ge");
8528 func (stream
, "gt");
8532 func (stream
, "??");
8540 func (stream
, "%c", *c
);
8544 if (value
== ((1ul << width
) - 1))
8545 func (stream
, "%c", *c
);
8548 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8560 int single
= *c
++ == 'y';
8565 case '4': /* Sm pair */
8566 case '0': /* Sm, Dm */
8567 regno
= given
& 0x0000000f;
8571 regno
+= (given
>> 5) & 1;
8574 regno
+= ((given
>> 5) & 1) << 4;
8577 case '1': /* Sd, Dd */
8578 regno
= (given
>> 12) & 0x0000000f;
8582 regno
+= (given
>> 22) & 1;
8585 regno
+= ((given
>> 22) & 1) << 4;
8588 case '2': /* Sn, Dn */
8589 regno
= (given
>> 16) & 0x0000000f;
8593 regno
+= (given
>> 7) & 1;
8596 regno
+= ((given
>> 7) & 1) << 4;
8599 case '3': /* List */
8601 regno
= (given
>> 12) & 0x0000000f;
8605 regno
+= (given
>> 22) & 1;
8608 regno
+= ((given
>> 22) & 1) << 4;
8615 func (stream
, "%c%d", single
? 's' : 'd', regno
);
8619 int count
= given
& 0xff;
8626 func (stream
, "-%c%d",
8634 func (stream
, ", %c%d", single
? 's' : 'd',
8640 switch (given
& 0x00400100)
8642 case 0x00000000: func (stream
, "b"); break;
8643 case 0x00400000: func (stream
, "h"); break;
8644 case 0x00000100: func (stream
, "w"); break;
8645 case 0x00400100: func (stream
, "d"); break;
8653 /* given (20, 23) | given (0, 3) */
8654 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
8655 func (stream
, "%d", (int) value
);
8660 /* This is like the 'A' operator, except that if
8661 the width field "M" is zero, then the offset is
8662 *not* multiplied by four. */
8664 int offset
= given
& 0xff;
8665 int multiplier
= (given
& 0x00000100) ? 4 : 1;
8667 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8671 value_in_comment
= offset
* multiplier
;
8672 if (NEGATIVE_BIT_SET
)
8673 value_in_comment
= - value_in_comment
;
8679 func (stream
, ", #%s%d]%s",
8680 NEGATIVE_BIT_SET
? "-" : "",
8681 offset
* multiplier
,
8682 WRITEBACK_BIT_SET
? "!" : "");
8684 func (stream
, "], #%s%d",
8685 NEGATIVE_BIT_SET
? "-" : "",
8686 offset
* multiplier
);
8695 int imm4
= (given
>> 4) & 0xf;
8696 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
8697 int ubit
= ! NEGATIVE_BIT_SET
;
8698 const char *rm
= arm_regnames
[given
& 0xf];
8699 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
8705 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
8707 func (stream
, ", lsl #%d", imm4
);
8714 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
8716 func (stream
, ", lsl #%d", imm4
);
8718 if (puw_bits
== 5 || puw_bits
== 7)
8723 func (stream
, "INVALID");
8731 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
8732 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
8741 func (stream
, "%c", *c
);
8744 if (value_in_comment
> 32 || value_in_comment
< -16)
8745 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8747 if (is_unpredictable
)
8748 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8756 print_insn_coprocessor (bfd_vma pc
,
8757 struct disassemble_info
*info
,
8761 return print_insn_coprocessor_1 (coprocessor_opcodes
,
8762 pc
, info
, given
, thumb
);
8766 print_insn_generic_coprocessor (bfd_vma pc
,
8767 struct disassemble_info
*info
,
8771 return print_insn_coprocessor_1 (generic_coprocessor_opcodes
,
8772 pc
, info
, given
, thumb
);
8775 /* Decodes and prints ARM addressing modes. Returns the offset
8776 used in the address, if any, if it is worthwhile printing the
8777 offset as a hexadecimal value in a comment at the end of the
8778 line of disassembly. */
8781 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8783 void *stream
= info
->stream
;
8784 fprintf_ftype func
= info
->fprintf_func
;
8787 if (((given
& 0x000f0000) == 0x000f0000)
8788 && ((given
& 0x02000000) == 0))
8790 offset
= given
& 0xfff;
8792 func (stream
, "[pc");
8796 /* Pre-indexed. Elide offset of positive zero when
8798 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8799 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8801 if (NEGATIVE_BIT_SET
)
8806 /* Cope with the possibility of write-back
8807 being used. Probably a very dangerous thing
8808 for the programmer to do, but who are we to
8810 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
8812 else /* Post indexed. */
8814 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8816 /* Ie ignore the offset. */
8820 func (stream
, "\t; ");
8821 info
->print_address_func (offset
, info
);
8826 func (stream
, "[%s",
8827 arm_regnames
[(given
>> 16) & 0xf]);
8831 if ((given
& 0x02000000) == 0)
8833 /* Elide offset of positive zero when non-writeback. */
8834 offset
= given
& 0xfff;
8835 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8836 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8840 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
8841 arm_decode_shift (given
, func
, stream
, TRUE
);
8844 func (stream
, "]%s",
8845 WRITEBACK_BIT_SET
? "!" : "");
8849 if ((given
& 0x02000000) == 0)
8851 /* Always show offset. */
8852 offset
= given
& 0xfff;
8853 func (stream
, "], #%s%d",
8854 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8858 func (stream
, "], %s",
8859 NEGATIVE_BIT_SET
? "-" : "");
8860 arm_decode_shift (given
, func
, stream
, TRUE
);
8863 if (NEGATIVE_BIT_SET
)
8867 return (signed long) offset
;
8871 /* Print one cde instruction on INFO->STREAM.
8872 Return TRUE if the instuction matched, FALSE if this is not a
8873 recognised cde instruction. */
8875 print_insn_cde (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
8877 const struct cdeopcode32
*insn
;
8878 void *stream
= info
->stream
;
8879 fprintf_ftype func
= info
->fprintf_func
;
8883 /* Manually extract the coprocessor code from a known point.
8884 This position is the same across all CDE instructions. */
8885 for (insn
= cde_opcodes
; insn
->assembler
; insn
++)
8887 uint16_t coproc
= (given
>> insn
->coproc_shift
) & insn
->coproc_mask
;
8888 uint16_t coproc_mask
= 1 << coproc
;
8889 if (! (coproc_mask
& cde_coprocs
))
8892 if ((given
& insn
->mask
) == insn
->value
)
8894 bfd_boolean is_unpredictable
= FALSE
;
8897 for (c
= insn
->assembler
; *c
; c
++)
8904 func (stream
, "%%");
8907 case '0': case '1': case '2': case '3': case '4':
8908 case '5': case '6': case '7': case '8': case '9':
8911 unsigned long value
;
8913 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8919 is_unpredictable
= TRUE
;
8923 is_unpredictable
= TRUE
;
8926 func (stream
, "%s", arm_regnames
[value
]);
8931 func (stream
, "%s", "APSR_nzcv");
8933 func (stream
, "%s", arm_regnames
[value
]);
8937 func (stream
, "%s", arm_regnames
[value
+ 1]);
8941 func (stream
, "%ld", value
);
8945 if (given
& (1 << 6))
8946 func (stream
, "q%ld", value
>> 1);
8947 else if (given
& (1 << 24))
8948 func (stream
, "d%ld", value
);
8951 /* Encoding for S register is different than for D and
8952 Q registers. S registers are encoded using the top
8953 single bit in position 22 as the lowest bit of the
8954 register number, while for Q and D it represents the
8955 highest bit of the register number. */
8956 uint8_t top_bit
= (value
>> 4) & 1;
8957 uint8_t tmp
= (value
<< 1) & 0x1e;
8958 uint8_t res
= tmp
| top_bit
;
8959 func (stream
, "s%u", res
);
8971 uint8_t proc_number
= (given
>> 8) & 0x7;
8972 func (stream
, "p%u", proc_number
);
8978 uint8_t a_offset
= 28;
8979 if (given
& (1 << a_offset
))
8988 func (stream
, "%c", *c
);
8991 if (is_unpredictable
)
8992 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9004 /* Print one neon instruction on INFO->STREAM.
9005 Return TRUE if the instuction matched, FALSE if this is not a
9006 recognised neon instruction. */
9009 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
9011 const struct opcode32
*insn
;
9012 void *stream
= info
->stream
;
9013 fprintf_ftype func
= info
->fprintf_func
;
9017 if ((given
& 0xef000000) == 0xef000000)
9019 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
9020 unsigned long bit28
= given
& (1 << 28);
9022 given
&= 0x00ffffff;
9024 given
|= 0xf3000000;
9026 given
|= 0xf2000000;
9028 else if ((given
& 0xff000000) == 0xf9000000)
9029 given
^= 0xf9000000 ^ 0xf4000000;
9030 /* BFloat16 neon instructions without special top byte handling. */
9031 else if ((given
& 0xff000000) == 0xfe000000
9032 || (given
& 0xff000000) == 0xfc000000)
9034 /* vdup is also a valid neon instruction. */
9035 else if ((given
& 0xff900f5f) != 0xee800b10)
9039 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
9041 unsigned long cond_mask
= insn
->mask
;
9042 unsigned long cond_value
= insn
->value
;
9047 if ((cond_mask
& 0xf0000000) == 0) {
9048 /* For the entries in neon_opcodes, an opcode mask/value with
9049 the high 4 bits equal to 0 indicates a conditional
9050 instruction. For thumb however, we need to include those
9051 bits in the instruction matching. */
9052 cond_mask
|= 0xf0000000;
9053 /* Furthermore, the thumb encoding of a conditional instruction
9054 will have the high 4 bits equal to 0xe. */
9055 cond_value
|= 0xe0000000;
9064 if ((given
& 0xf0000000) == 0xf0000000)
9066 /* If the instruction is unconditional, update the mask to only
9067 match against unconditional opcode values. */
9068 cond_mask
|= 0xf0000000;
9073 cond
= (given
>> 28) & 0xf;
9079 if ((given
& cond_mask
) == cond_value
)
9081 signed long value_in_comment
= 0;
9082 bfd_boolean is_unpredictable
= FALSE
;
9085 for (c
= insn
->assembler
; *c
; c
++)
9092 func (stream
, "%%");
9096 if (thumb
&& ifthen_state
)
9097 is_unpredictable
= TRUE
;
9101 func (stream
, "%s", arm_conditional
[cond
]);
9106 static const unsigned char enc
[16] =
9108 0x4, 0x14, /* st4 0,1 */
9120 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9121 int rn
= ((given
>> 16) & 0xf);
9122 int rm
= ((given
>> 0) & 0xf);
9123 int align
= ((given
>> 4) & 0x3);
9124 int type
= ((given
>> 8) & 0xf);
9125 int n
= enc
[type
] & 0xf;
9126 int stride
= (enc
[type
] >> 4) + 1;
9131 for (ix
= 0; ix
!= n
; ix
++)
9132 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
9134 func (stream
, "d%d", rd
);
9136 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
9137 func (stream
, "}, [%s", arm_regnames
[rn
]);
9139 func (stream
, " :%d", 32 << align
);
9144 func (stream
, ", %s", arm_regnames
[rm
]);
9150 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9151 int rn
= ((given
>> 16) & 0xf);
9152 int rm
= ((given
>> 0) & 0xf);
9153 int idx_align
= ((given
>> 4) & 0xf);
9155 int size
= ((given
>> 10) & 0x3);
9156 int idx
= idx_align
>> (size
+ 1);
9157 int length
= ((given
>> 8) & 3) + 1;
9161 if (length
> 1 && size
> 0)
9162 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
9168 int amask
= (1 << size
) - 1;
9169 if ((idx_align
& (1 << size
)) != 0)
9173 if ((idx_align
& amask
) == amask
)
9175 else if ((idx_align
& amask
) != 0)
9182 if (size
== 2 && (idx_align
& 2) != 0)
9184 align
= (idx_align
& 1) ? 16 << size
: 0;
9188 if ((size
== 2 && (idx_align
& 3) != 0)
9189 || (idx_align
& 1) != 0)
9196 if ((idx_align
& 3) == 3)
9198 align
= (idx_align
& 3) * 64;
9201 align
= (idx_align
& 1) ? 32 << size
: 0;
9209 for (i
= 0; i
< length
; i
++)
9210 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
9211 rd
+ i
* stride
, idx
);
9212 func (stream
, "}, [%s", arm_regnames
[rn
]);
9214 func (stream
, " :%d", align
);
9219 func (stream
, ", %s", arm_regnames
[rm
]);
9225 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
9226 int rn
= ((given
>> 16) & 0xf);
9227 int rm
= ((given
>> 0) & 0xf);
9228 int align
= ((given
>> 4) & 0x1);
9229 int size
= ((given
>> 6) & 0x3);
9230 int type
= ((given
>> 8) & 0x3);
9232 int stride
= ((given
>> 5) & 0x1);
9235 if (stride
&& (n
== 1))
9242 for (ix
= 0; ix
!= n
; ix
++)
9243 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
9245 func (stream
, "d%d[]", rd
);
9247 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
9248 func (stream
, "}, [%s", arm_regnames
[rn
]);
9251 align
= (8 * (type
+ 1)) << size
;
9253 align
= (size
> 1) ? align
>> 1 : align
;
9254 if (type
== 2 || (type
== 0 && !size
))
9255 func (stream
, " :<bad align %d>", align
);
9257 func (stream
, " :%d", align
);
9263 func (stream
, ", %s", arm_regnames
[rm
]);
9269 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
9270 int size
= (given
>> 20) & 3;
9271 int reg
= raw_reg
& ((4 << size
) - 1);
9272 int ix
= raw_reg
>> size
>> 2;
9274 func (stream
, "d%d[%d]", reg
, ix
);
9279 /* Neon encoded constant for mov, mvn, vorr, vbic. */
9282 int cmode
= (given
>> 8) & 0xf;
9283 int op
= (given
>> 5) & 0x1;
9284 unsigned long value
= 0, hival
= 0;
9289 bits
|= ((given
>> 24) & 1) << 7;
9290 bits
|= ((given
>> 16) & 7) << 4;
9291 bits
|= ((given
>> 0) & 15) << 0;
9295 shift
= (cmode
>> 1) & 3;
9296 value
= (unsigned long) bits
<< (8 * shift
);
9299 else if (cmode
< 12)
9301 shift
= (cmode
>> 1) & 1;
9302 value
= (unsigned long) bits
<< (8 * shift
);
9305 else if (cmode
< 14)
9307 shift
= (cmode
& 1) + 1;
9308 value
= (unsigned long) bits
<< (8 * shift
);
9309 value
|= (1ul << (8 * shift
)) - 1;
9312 else if (cmode
== 14)
9316 /* Bit replication into bytes. */
9322 for (ix
= 7; ix
>= 0; ix
--)
9324 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
9326 value
= (value
<< 8) | mask
;
9328 hival
= (hival
<< 8) | mask
;
9334 /* Byte replication. */
9335 value
= (unsigned long) bits
;
9341 /* Floating point encoding. */
9344 value
= (unsigned long) (bits
& 0x7f) << 19;
9345 value
|= (unsigned long) (bits
& 0x80) << 24;
9346 tmp
= bits
& 0x40 ? 0x3c : 0x40;
9347 value
|= (unsigned long) tmp
<< 24;
9353 func (stream
, "<illegal constant %.8x:%x:%x>",
9361 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
9365 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
9371 unsigned char valbytes
[4];
9374 /* Do this a byte at a time so we don't have to
9375 worry about the host's endianness. */
9376 valbytes
[0] = value
& 0xff;
9377 valbytes
[1] = (value
>> 8) & 0xff;
9378 valbytes
[2] = (value
>> 16) & 0xff;
9379 valbytes
[3] = (value
>> 24) & 0xff;
9381 floatformat_to_double
9382 (& floatformat_ieee_single_little
, valbytes
,
9385 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
9389 func (stream
, "#%ld\t; 0x%.8lx",
9390 (long) (((value
& 0x80000000L
) != 0)
9391 ? value
| ~0xffffffffL
: value
),
9396 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
9407 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
9408 int num
= (given
>> 8) & 0x3;
9411 func (stream
, "{d%d}", regno
);
9412 else if (num
+ regno
>= 32)
9413 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
9415 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
9420 case '0': case '1': case '2': case '3': case '4':
9421 case '5': case '6': case '7': case '8': case '9':
9424 unsigned long value
;
9426 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9431 func (stream
, "%s", arm_regnames
[value
]);
9434 func (stream
, "%ld", value
);
9435 value_in_comment
= value
;
9438 func (stream
, "%ld", (1ul << width
) - value
);
9444 /* Various width encodings. */
9446 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
9451 if (*c
>= '0' && *c
<= '9')
9453 else if (*c
>= 'a' && *c
<= 'f')
9454 limit
= *c
- 'a' + 10;
9460 if (value
< low
|| value
> high
)
9461 func (stream
, "<illegal width %d>", base
<< value
);
9463 func (stream
, "%d", base
<< value
);
9467 if (given
& (1 << 6))
9471 func (stream
, "d%ld", value
);
9476 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
9478 func (stream
, "q%ld", value
>> 1);
9484 func (stream
, "%c", *c
);
9488 if (value
== ((1ul << width
) - 1))
9489 func (stream
, "%c", *c
);
9492 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
9506 func (stream
, "%c", *c
);
9509 if (value_in_comment
> 32 || value_in_comment
< -16)
9510 func (stream
, "\t; 0x%lx", value_in_comment
);
9512 if (is_unpredictable
)
9513 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9521 /* Print one mve instruction on INFO->STREAM.
9522 Return TRUE if the instuction matched, FALSE if this is not a
9523 recognised mve instruction. */
9526 print_insn_mve (struct disassemble_info
*info
, long given
)
9528 const struct mopcode32
*insn
;
9529 void *stream
= info
->stream
;
9530 fprintf_ftype func
= info
->fprintf_func
;
9532 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
9534 if (((given
& insn
->mask
) == insn
->value
)
9535 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
9537 signed long value_in_comment
= 0;
9538 bfd_boolean is_unpredictable
= FALSE
;
9539 bfd_boolean is_undefined
= FALSE
;
9541 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
9542 enum mve_undefined undefined_cond
= UNDEF_NONE
;
9544 /* Most vector mve instruction are illegal in a it block.
9545 There are a few exceptions; check for them. */
9546 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
9548 is_unpredictable
= TRUE
;
9549 unpredictable_cond
= UNPRED_IT_BLOCK
;
9551 else if (is_mve_unpredictable (given
, insn
->mve_op
,
9552 &unpredictable_cond
))
9553 is_unpredictable
= TRUE
;
9555 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
9556 is_undefined
= TRUE
;
9558 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9559 i.e "VMOV Qd, Qm". */
9560 if ((insn
->mve_op
== MVE_VORR_REG
)
9561 && (arm_decode_field (given
, 1, 3)
9562 == arm_decode_field (given
, 17, 19)))
9565 for (c
= insn
->assembler
; *c
; c
++)
9572 func (stream
, "%%");
9576 /* Don't print anything for '+' as it is implied. */
9577 if (arm_decode_field (given
, 23, 23) == 0)
9583 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9587 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
9592 long mve_mask
= mve_extract_pred_mask (given
);
9593 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
9599 unsigned int imm5
= 0;
9600 imm5
|= arm_decode_field (given
, 6, 7);
9601 imm5
|= (arm_decode_field (given
, 12, 14) << 2);
9602 func (stream
, "#%u", (imm5
== 0) ? 32 : imm5
);
9607 func (stream
, "#%u",
9608 (arm_decode_field (given
, 7, 7) == 0) ? 64 : 48);
9612 print_vec_condition (info
, given
, insn
->mve_op
);
9616 if (arm_decode_field (given
, 0, 0) == 1)
9619 = arm_decode_field (given
, 4, 4)
9620 | (arm_decode_field (given
, 6, 6) << 1);
9622 func (stream
, ", uxtw #%lu", size
);
9627 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
9631 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
9636 unsigned long op1
= arm_decode_field (given
, 21, 22);
9638 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
9640 /* Check for signed. */
9641 if (arm_decode_field (given
, 23, 23) == 0)
9643 /* We don't print 's' for S32. */
9644 if ((arm_decode_field (given
, 5, 6) == 0)
9645 && ((op1
== 0) || (op1
== 1)))
9655 if (arm_decode_field (given
, 28, 28) == 0)
9664 print_instruction_predicate (info
);
9668 if (arm_decode_field (given
, 21, 21) == 1)
9673 print_mve_register_blocks (info
, given
, insn
->mve_op
);
9677 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9679 print_simd_imm8 (info
, given
, 28, insn
);
9683 print_mve_vmov_index (info
, given
);
9687 if (arm_decode_field (given
, 12, 12) == 0)
9694 if (arm_decode_field (given
, 12, 12) == 1)
9698 case '0': case '1': case '2': case '3': case '4':
9699 case '5': case '6': case '7': case '8': case '9':
9702 unsigned long value
;
9704 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9710 is_unpredictable
= TRUE
;
9711 else if (value
== 15)
9712 func (stream
, "zr");
9714 func (stream
, "%s", arm_regnames
[value
]);
9718 func (stream
, "%s", arm_conditional
[value
]);
9723 func (stream
, "%s", arm_conditional
[value
]);
9727 if (value
== 13 || value
== 15)
9728 is_unpredictable
= TRUE
;
9730 func (stream
, "%s", arm_regnames
[value
]);
9734 print_mve_size (info
,
9748 unsigned int odd_reg
= (value
<< 1) | 1;
9749 func (stream
, "%s", arm_regnames
[odd_reg
]);
9755 = arm_decode_field (given
, 0, 6);
9756 unsigned long mod_imm
= imm
;
9758 switch (insn
->mve_op
)
9760 case MVE_VLDRW_GATHER_T5
:
9761 case MVE_VSTRW_SCATTER_T5
:
9762 mod_imm
= mod_imm
<< 2;
9764 case MVE_VSTRD_SCATTER_T6
:
9765 case MVE_VLDRD_GATHER_T6
:
9766 mod_imm
= mod_imm
<< 3;
9773 func (stream
, "%lu", mod_imm
);
9777 func (stream
, "%lu", 64 - value
);
9781 unsigned int even_reg
= value
<< 1;
9782 func (stream
, "%s", arm_regnames
[even_reg
]);
9805 print_mve_rotate (info
, value
, width
);
9808 func (stream
, "%s", arm_regnames
[value
]);
9811 if (insn
->mve_op
== MVE_VQSHL_T2
9812 || insn
->mve_op
== MVE_VQSHLU_T3
9813 || insn
->mve_op
== MVE_VRSHR
9814 || insn
->mve_op
== MVE_VRSHRN
9815 || insn
->mve_op
== MVE_VSHL_T1
9816 || insn
->mve_op
== MVE_VSHLL_T1
9817 || insn
->mve_op
== MVE_VSHR
9818 || insn
->mve_op
== MVE_VSHRN
9819 || insn
->mve_op
== MVE_VSLI
9820 || insn
->mve_op
== MVE_VSRI
)
9821 print_mve_shift_n (info
, given
, insn
->mve_op
);
9822 else if (insn
->mve_op
== MVE_VSHLL_T2
)
9830 func (stream
, "16");
9833 print_mve_undefined (info
, UNDEF_SIZE_0
);
9842 if (insn
->mve_op
== MVE_VSHLC
&& value
== 0)
9844 func (stream
, "%ld", value
);
9845 value_in_comment
= value
;
9849 func (stream
, "s%ld", value
);
9853 func (stream
, "<illegal reg q%ld.5>", value
);
9855 func (stream
, "q%ld", value
);
9858 func (stream
, "0x%08lx", value
);
9870 func (stream
, "%c", *c
);
9873 if (value_in_comment
> 32 || value_in_comment
< -16)
9874 func (stream
, "\t; 0x%lx", value_in_comment
);
9876 if (is_unpredictable
)
9877 print_mve_unpredictable (info
, unpredictable_cond
);
9880 print_mve_undefined (info
, undefined_cond
);
9882 if ((vpt_block_state
.in_vpt_block
== FALSE
)
9884 && (is_vpt_instruction (given
) == TRUE
))
9885 mark_inside_vpt_block (given
);
9886 else if (vpt_block_state
.in_vpt_block
== TRUE
)
9887 update_vpt_block_state ();
9896 /* Return the name of a v7A special register. */
9899 banked_regname (unsigned reg
)
9903 case 15: return "CPSR";
9904 case 32: return "R8_usr";
9905 case 33: return "R9_usr";
9906 case 34: return "R10_usr";
9907 case 35: return "R11_usr";
9908 case 36: return "R12_usr";
9909 case 37: return "SP_usr";
9910 case 38: return "LR_usr";
9911 case 40: return "R8_fiq";
9912 case 41: return "R9_fiq";
9913 case 42: return "R10_fiq";
9914 case 43: return "R11_fiq";
9915 case 44: return "R12_fiq";
9916 case 45: return "SP_fiq";
9917 case 46: return "LR_fiq";
9918 case 48: return "LR_irq";
9919 case 49: return "SP_irq";
9920 case 50: return "LR_svc";
9921 case 51: return "SP_svc";
9922 case 52: return "LR_abt";
9923 case 53: return "SP_abt";
9924 case 54: return "LR_und";
9925 case 55: return "SP_und";
9926 case 60: return "LR_mon";
9927 case 61: return "SP_mon";
9928 case 62: return "ELR_hyp";
9929 case 63: return "SP_hyp";
9930 case 79: return "SPSR";
9931 case 110: return "SPSR_fiq";
9932 case 112: return "SPSR_irq";
9933 case 114: return "SPSR_svc";
9934 case 116: return "SPSR_abt";
9935 case 118: return "SPSR_und";
9936 case 124: return "SPSR_mon";
9937 case 126: return "SPSR_hyp";
9938 default: return NULL
;
9942 /* Return the name of the DMB/DSB option. */
9944 data_barrier_option (unsigned option
)
9946 switch (option
& 0xf)
9948 case 0xf: return "sy";
9949 case 0xe: return "st";
9950 case 0xd: return "ld";
9951 case 0xb: return "ish";
9952 case 0xa: return "ishst";
9953 case 0x9: return "ishld";
9954 case 0x7: return "un";
9955 case 0x6: return "unst";
9956 case 0x5: return "nshld";
9957 case 0x3: return "osh";
9958 case 0x2: return "oshst";
9959 case 0x1: return "oshld";
9960 default: return NULL
;
9964 /* Print one ARM instruction from PC on INFO->STREAM. */
9967 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9969 const struct opcode32
*insn
;
9970 void *stream
= info
->stream
;
9971 fprintf_ftype func
= info
->fprintf_func
;
9972 struct arm_private_data
*private_data
= info
->private_data
;
9974 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
9977 if (print_insn_neon (info
, given
, FALSE
))
9980 if (print_insn_generic_coprocessor (pc
, info
, given
, FALSE
))
9983 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
9985 if ((given
& insn
->mask
) != insn
->value
)
9988 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
9991 /* Special case: an instruction with all bits set in the condition field
9992 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9993 or by the catchall at the end of the table. */
9994 if ((given
& 0xF0000000) != 0xF0000000
9995 || (insn
->mask
& 0xF0000000) == 0xF0000000
9996 || (insn
->mask
== 0 && insn
->value
== 0))
9998 unsigned long u_reg
= 16;
9999 unsigned long U_reg
= 16;
10000 bfd_boolean is_unpredictable
= FALSE
;
10001 signed long value_in_comment
= 0;
10004 for (c
= insn
->assembler
; *c
; c
++)
10008 bfd_boolean allow_unpredictable
= FALSE
;
10013 func (stream
, "%%");
10017 value_in_comment
= print_arm_address (pc
, info
, given
);
10021 /* Set P address bit and use normal address
10022 printing routine. */
10023 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
10027 allow_unpredictable
= TRUE
;
10028 /* Fall through. */
10030 if ((given
& 0x004f0000) == 0x004f0000)
10032 /* PC relative with immediate offset. */
10033 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
10037 /* Elide positive zero offset. */
10038 if (offset
|| NEGATIVE_BIT_SET
)
10039 func (stream
, "[pc, #%s%d]\t; ",
10040 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
10042 func (stream
, "[pc]\t; ");
10043 if (NEGATIVE_BIT_SET
)
10045 info
->print_address_func (offset
+ pc
+ 8, info
);
10049 /* Always show the offset. */
10050 func (stream
, "[pc], #%s%d",
10051 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
10052 if (! allow_unpredictable
)
10053 is_unpredictable
= TRUE
;
10058 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
10060 func (stream
, "[%s",
10061 arm_regnames
[(given
>> 16) & 0xf]);
10065 if (IMMEDIATE_BIT_SET
)
10067 /* Elide offset for non-writeback
10069 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
10071 func (stream
, ", #%s%d",
10072 NEGATIVE_BIT_SET
? "-" : "", offset
);
10074 if (NEGATIVE_BIT_SET
)
10077 value_in_comment
= offset
;
10081 /* Register Offset or Register Pre-Indexed. */
10082 func (stream
, ", %s%s",
10083 NEGATIVE_BIT_SET
? "-" : "",
10084 arm_regnames
[given
& 0xf]);
10086 /* Writing back to the register that is the source/
10087 destination of the load/store is unpredictable. */
10088 if (! allow_unpredictable
10089 && WRITEBACK_BIT_SET
10090 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
10091 is_unpredictable
= TRUE
;
10094 func (stream
, "]%s",
10095 WRITEBACK_BIT_SET
? "!" : "");
10099 if (IMMEDIATE_BIT_SET
)
10101 /* Immediate Post-indexed. */
10102 /* PR 10924: Offset must be printed, even if it is zero. */
10103 func (stream
, "], #%s%d",
10104 NEGATIVE_BIT_SET
? "-" : "", offset
);
10105 if (NEGATIVE_BIT_SET
)
10107 value_in_comment
= offset
;
10111 /* Register Post-indexed. */
10112 func (stream
, "], %s%s",
10113 NEGATIVE_BIT_SET
? "-" : "",
10114 arm_regnames
[given
& 0xf]);
10116 /* Writing back to the register that is the source/
10117 destination of the load/store is unpredictable. */
10118 if (! allow_unpredictable
10119 && (given
& 0xf) == ((given
>> 12) & 0xf))
10120 is_unpredictable
= TRUE
;
10123 if (! allow_unpredictable
)
10125 /* Writeback is automatically implied by post- addressing.
10126 Setting the W bit is unnecessary and ARM specify it as
10127 being unpredictable. */
10128 if (WRITEBACK_BIT_SET
10129 /* Specifying the PC register as the post-indexed
10130 registers is also unpredictable. */
10131 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
10132 is_unpredictable
= TRUE
;
10140 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
10141 bfd_vma target
= disp
* 4 + pc
+ 8;
10142 info
->print_address_func (target
, info
);
10144 /* Fill in instruction information. */
10145 info
->insn_info_valid
= 1;
10146 info
->insn_type
= dis_branch
;
10147 info
->target
= target
;
10152 if (((given
>> 28) & 0xf) != 0xe)
10153 func (stream
, "%s",
10154 arm_conditional
[(given
>> 28) & 0xf]);
10162 func (stream
, "{");
10163 for (reg
= 0; reg
< 16; reg
++)
10164 if ((given
& (1 << reg
)) != 0)
10167 func (stream
, ", ");
10169 func (stream
, "%s", arm_regnames
[reg
]);
10171 func (stream
, "}");
10173 is_unpredictable
= TRUE
;
10178 arm_decode_shift (given
, func
, stream
, FALSE
);
10182 if ((given
& 0x02000000) != 0)
10184 unsigned int rotate
= (given
& 0xf00) >> 7;
10185 unsigned int immed
= (given
& 0xff);
10188 a
= (immed
<< ((32 - rotate
) & 31)
10189 | immed
>> rotate
) & 0xffffffff;
10190 /* If there is another encoding with smaller rotate,
10191 the rotate should be specified directly. */
10192 for (i
= 0; i
< 32; i
+= 2)
10193 if ((a
<< i
| a
>> ((32 - i
) & 31)) <= 0xff)
10197 func (stream
, "#%d, %d", immed
, rotate
);
10199 func (stream
, "#%d", a
);
10200 value_in_comment
= a
;
10203 arm_decode_shift (given
, func
, stream
, TRUE
);
10207 if ((given
& 0x0000f000) == 0x0000f000)
10209 arm_feature_set arm_ext_v6
=
10210 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
10212 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
10213 mechanism for setting PSR flag bits. They are
10214 obsolete in V6 onwards. */
10215 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
10217 func (stream
, "p");
10219 is_unpredictable
= TRUE
;
10224 if ((given
& 0x01200000) == 0x00200000)
10225 func (stream
, "t");
10230 int offset
= given
& 0xff;
10232 value_in_comment
= offset
* 4;
10233 if (NEGATIVE_BIT_SET
)
10234 value_in_comment
= - value_in_comment
;
10236 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
10241 func (stream
, ", #%d]%s",
10242 (int) value_in_comment
,
10243 WRITEBACK_BIT_SET
? "!" : "");
10245 func (stream
, "]");
10249 func (stream
, "]");
10251 if (WRITEBACK_BIT_SET
)
10254 func (stream
, ", #%d", (int) value_in_comment
);
10258 func (stream
, ", {%d}", (int) offset
);
10259 value_in_comment
= offset
;
10266 /* Print ARM V5 BLX(1) address: pc+25 bits. */
10269 bfd_vma offset
= 0;
10271 if (! NEGATIVE_BIT_SET
)
10272 /* Is signed, hi bits should be ones. */
10273 offset
= (-1) ^ 0x00ffffff;
10275 /* Offset is (SignExtend(offset field)<<2). */
10276 offset
+= given
& 0x00ffffff;
10278 address
= offset
+ pc
+ 8;
10280 if (given
& 0x01000000)
10281 /* H bit allows addressing to 2-byte boundaries. */
10284 info
->print_address_func (address
, info
);
10286 /* Fill in instruction information. */
10287 info
->insn_info_valid
= 1;
10288 info
->insn_type
= dis_branch
;
10289 info
->target
= address
;
10294 if ((given
& 0x02000200) == 0x200)
10297 unsigned sysm
= (given
& 0x004f0000) >> 16;
10299 sysm
|= (given
& 0x300) >> 4;
10300 name
= banked_regname (sysm
);
10303 func (stream
, "%s", name
);
10305 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10309 func (stream
, "%cPSR_",
10310 (given
& 0x00400000) ? 'S' : 'C');
10311 if (given
& 0x80000)
10312 func (stream
, "f");
10313 if (given
& 0x40000)
10314 func (stream
, "s");
10315 if (given
& 0x20000)
10316 func (stream
, "x");
10317 if (given
& 0x10000)
10318 func (stream
, "c");
10323 if ((given
& 0xf0) == 0x60)
10325 switch (given
& 0xf)
10327 case 0xf: func (stream
, "sy"); break;
10329 func (stream
, "#%d", (int) given
& 0xf);
10335 const char * opt
= data_barrier_option (given
& 0xf);
10337 func (stream
, "%s", opt
);
10339 func (stream
, "#%d", (int) given
& 0xf);
10343 case '0': case '1': case '2': case '3': case '4':
10344 case '5': case '6': case '7': case '8': case '9':
10347 unsigned long value
;
10349 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
10355 is_unpredictable
= TRUE
;
10356 /* Fall through. */
10359 /* We want register + 1 when decoding T. */
10361 value
= (value
+ 1) & 0xf;
10365 /* Eat the 'u' character. */
10368 if (u_reg
== value
)
10369 is_unpredictable
= TRUE
;
10374 /* Eat the 'U' character. */
10377 if (U_reg
== value
)
10378 is_unpredictable
= TRUE
;
10381 func (stream
, "%s", arm_regnames
[value
]);
10384 func (stream
, "%ld", value
);
10385 value_in_comment
= value
;
10388 func (stream
, "%ld", value
* 8);
10389 value_in_comment
= value
* 8;
10392 func (stream
, "%ld", value
+ 1);
10393 value_in_comment
= value
+ 1;
10396 func (stream
, "0x%08lx", value
);
10398 /* Some SWI instructions have special
10400 if ((given
& 0x0fffffff) == 0x0FF00000)
10401 func (stream
, "\t; IMB");
10402 else if ((given
& 0x0fffffff) == 0x0FF00001)
10403 func (stream
, "\t; IMBRange");
10406 func (stream
, "%01lx", value
& 0xf);
10407 value_in_comment
= value
;
10412 func (stream
, "%c", *c
);
10416 if (value
== ((1ul << width
) - 1))
10417 func (stream
, "%c", *c
);
10420 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
10433 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
10434 func (stream
, "%d", imm
);
10435 value_in_comment
= imm
;
10440 /* LSB and WIDTH fields of BFI or BFC. The machine-
10441 language instruction encodes LSB and MSB. */
10443 long msb
= (given
& 0x001f0000) >> 16;
10444 long lsb
= (given
& 0x00000f80) >> 7;
10445 long w
= msb
- lsb
+ 1;
10448 func (stream
, "#%lu, #%lu", lsb
, w
);
10450 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
10455 /* Get the PSR/banked register name. */
10458 unsigned sysm
= (given
& 0x004f0000) >> 16;
10460 sysm
|= (given
& 0x300) >> 4;
10461 name
= banked_regname (sysm
);
10464 func (stream
, "%s", name
);
10466 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10471 /* 16-bit unsigned immediate from a MOVT or MOVW
10472 instruction, encoded in bits 0:11 and 15:19. */
10474 long hi
= (given
& 0x000f0000) >> 4;
10475 long lo
= (given
& 0x00000fff);
10476 long imm16
= hi
| lo
;
10478 func (stream
, "#%lu", imm16
);
10479 value_in_comment
= imm16
;
10488 func (stream
, "%c", *c
);
10491 if (value_in_comment
> 32 || value_in_comment
< -16)
10492 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
10494 if (is_unpredictable
)
10495 func (stream
, UNPREDICTABLE_INSTRUCTION
);
10500 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
10504 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10507 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10509 const struct opcode16
*insn
;
10510 void *stream
= info
->stream
;
10511 fprintf_ftype func
= info
->fprintf_func
;
10513 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
10514 if ((given
& insn
->mask
) == insn
->value
)
10516 signed long value_in_comment
= 0;
10517 const char *c
= insn
->assembler
;
10526 func (stream
, "%c", *c
);
10533 func (stream
, "%%");
10538 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10543 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10545 func (stream
, "s");
10552 ifthen_next_state
= given
& 0xff;
10553 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
10554 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
10555 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
10560 if (ifthen_next_state
)
10561 func (stream
, "\t; unpredictable branch in IT block\n");
10566 func (stream
, "\t; unpredictable <IT:%s>",
10567 arm_conditional
[IFTHEN_COND
]);
10574 reg
= (given
>> 3) & 0x7;
10575 if (given
& (1 << 6))
10578 func (stream
, "%s", arm_regnames
[reg
]);
10587 if (given
& (1 << 7))
10590 func (stream
, "%s", arm_regnames
[reg
]);
10595 if (given
& (1 << 8))
10597 /* Fall through. */
10599 if (*c
== 'O' && (given
& (1 << 8)))
10601 /* Fall through. */
10607 func (stream
, "{");
10609 /* It would be nice if we could spot
10610 ranges, and generate the rS-rE format: */
10611 for (reg
= 0; (reg
< 8); reg
++)
10612 if ((given
& (1 << reg
)) != 0)
10615 func (stream
, ", ");
10617 func (stream
, "%s", arm_regnames
[reg
]);
10623 func (stream
, ", ");
10625 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
10631 func (stream
, ", ");
10632 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
10635 func (stream
, "}");
10640 /* Print writeback indicator for a LDMIA. We are doing a
10641 writeback if the base register is not in the register
10643 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
10644 func (stream
, "!");
10648 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10650 bfd_vma address
= (pc
+ 4
10651 + ((given
& 0x00f8) >> 2)
10652 + ((given
& 0x0200) >> 3));
10653 info
->print_address_func (address
, info
);
10655 /* Fill in instruction information. */
10656 info
->insn_info_valid
= 1;
10657 info
->insn_type
= dis_branch
;
10658 info
->target
= address
;
10663 /* Right shift immediate -- bits 6..10; 1-31 print
10664 as themselves, 0 prints as 32. */
10666 long imm
= (given
& 0x07c0) >> 6;
10669 func (stream
, "#%ld", imm
);
10673 case '0': case '1': case '2': case '3': case '4':
10674 case '5': case '6': case '7': case '8': case '9':
10676 int bitstart
= *c
++ - '0';
10679 while (*c
>= '0' && *c
<= '9')
10680 bitstart
= (bitstart
* 10) + *c
++ - '0';
10689 while (*c
>= '0' && *c
<= '9')
10690 bitend
= (bitend
* 10) + *c
++ - '0';
10693 reg
= given
>> bitstart
;
10694 reg
&= (2 << (bitend
- bitstart
)) - 1;
10699 func (stream
, "%s", arm_regnames
[reg
]);
10703 func (stream
, "%ld", (long) reg
);
10704 value_in_comment
= reg
;
10708 func (stream
, "%ld", (long) (reg
<< 1));
10709 value_in_comment
= reg
<< 1;
10713 func (stream
, "%ld", (long) (reg
<< 2));
10714 value_in_comment
= reg
<< 2;
10718 /* PC-relative address -- the bottom two
10719 bits of the address are dropped
10720 before the calculation. */
10721 info
->print_address_func
10722 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
10723 value_in_comment
= 0;
10727 func (stream
, "0x%04lx", (long) reg
);
10731 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
10732 bfd_vma target
= reg
* 2 + pc
+ 4;
10733 info
->print_address_func (target
, info
);
10734 value_in_comment
= 0;
10736 /* Fill in instruction information. */
10737 info
->insn_info_valid
= 1;
10738 info
->insn_type
= dis_branch
;
10739 info
->target
= target
;
10743 func (stream
, "%s", arm_conditional
[reg
]);
10754 if ((given
& (1 << bitstart
)) != 0)
10755 func (stream
, "%c", *c
);
10760 if ((given
& (1 << bitstart
)) != 0)
10761 func (stream
, "%c", *c
++);
10763 func (stream
, "%c", *++c
);
10777 if (value_in_comment
> 32 || value_in_comment
< -16)
10778 func (stream
, "\t; 0x%lx", value_in_comment
);
10783 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
10787 /* Return the name of an V7M special register. */
10789 static const char *
10790 psr_name (int regno
)
10794 case 0x0: return "APSR";
10795 case 0x1: return "IAPSR";
10796 case 0x2: return "EAPSR";
10797 case 0x3: return "PSR";
10798 case 0x5: return "IPSR";
10799 case 0x6: return "EPSR";
10800 case 0x7: return "IEPSR";
10801 case 0x8: return "MSP";
10802 case 0x9: return "PSP";
10803 case 0xa: return "MSPLIM";
10804 case 0xb: return "PSPLIM";
10805 case 0x10: return "PRIMASK";
10806 case 0x11: return "BASEPRI";
10807 case 0x12: return "BASEPRI_MAX";
10808 case 0x13: return "FAULTMASK";
10809 case 0x14: return "CONTROL";
10810 case 0x88: return "MSP_NS";
10811 case 0x89: return "PSP_NS";
10812 case 0x8a: return "MSPLIM_NS";
10813 case 0x8b: return "PSPLIM_NS";
10814 case 0x90: return "PRIMASK_NS";
10815 case 0x91: return "BASEPRI_NS";
10816 case 0x93: return "FAULTMASK_NS";
10817 case 0x94: return "CONTROL_NS";
10818 case 0x98: return "SP_NS";
10819 default: return "<unknown>";
10823 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10826 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10828 const struct opcode32
*insn
;
10829 void *stream
= info
->stream
;
10830 fprintf_ftype func
= info
->fprintf_func
;
10831 bfd_boolean is_mve
= is_mve_architecture (info
);
10833 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
10836 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
10839 if (is_mve
&& print_insn_mve (info
, given
))
10842 if (print_insn_cde (info
, given
, TRUE
))
10845 if (print_insn_generic_coprocessor (pc
, info
, given
, TRUE
))
10848 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
10849 if ((given
& insn
->mask
) == insn
->value
)
10851 bfd_boolean is_clrm
= FALSE
;
10852 bfd_boolean is_unpredictable
= FALSE
;
10853 signed long value_in_comment
= 0;
10854 const char *c
= insn
->assembler
;
10860 func (stream
, "%c", *c
);
10867 func (stream
, "%%");
10872 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10876 if (ifthen_next_state
)
10877 func (stream
, "\t; unpredictable branch in IT block\n");
10882 func (stream
, "\t; unpredictable <IT:%s>",
10883 arm_conditional
[IFTHEN_COND
]);
10888 unsigned int imm12
= 0;
10890 imm12
|= (given
& 0x000000ffu
);
10891 imm12
|= (given
& 0x00007000u
) >> 4;
10892 imm12
|= (given
& 0x04000000u
) >> 15;
10893 func (stream
, "#%u", imm12
);
10894 value_in_comment
= imm12
;
10900 unsigned int bits
= 0, imm
, imm8
, mod
;
10902 bits
|= (given
& 0x000000ffu
);
10903 bits
|= (given
& 0x00007000u
) >> 4;
10904 bits
|= (given
& 0x04000000u
) >> 15;
10905 imm8
= (bits
& 0x0ff);
10906 mod
= (bits
& 0xf00) >> 8;
10909 case 0: imm
= imm8
; break;
10910 case 1: imm
= ((imm8
<< 16) | imm8
); break;
10911 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
10912 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
10914 mod
= (bits
& 0xf80) >> 7;
10915 imm8
= (bits
& 0x07f) | 0x80;
10916 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
10918 func (stream
, "#%u", imm
);
10919 value_in_comment
= imm
;
10925 unsigned int imm
= 0;
10927 imm
|= (given
& 0x000000ffu
);
10928 imm
|= (given
& 0x00007000u
) >> 4;
10929 imm
|= (given
& 0x04000000u
) >> 15;
10930 imm
|= (given
& 0x000f0000u
) >> 4;
10931 func (stream
, "#%u", imm
);
10932 value_in_comment
= imm
;
10938 unsigned int imm
= 0;
10940 imm
|= (given
& 0x000f0000u
) >> 16;
10941 imm
|= (given
& 0x00000ff0u
) >> 0;
10942 imm
|= (given
& 0x0000000fu
) << 12;
10943 func (stream
, "#%u", imm
);
10944 value_in_comment
= imm
;
10950 unsigned int imm
= 0;
10952 imm
|= (given
& 0x000f0000u
) >> 4;
10953 imm
|= (given
& 0x00000fffu
) >> 0;
10954 func (stream
, "#%u", imm
);
10955 value_in_comment
= imm
;
10961 unsigned int imm
= 0;
10963 imm
|= (given
& 0x00000fffu
);
10964 imm
|= (given
& 0x000f0000u
) >> 4;
10965 func (stream
, "#%u", imm
);
10966 value_in_comment
= imm
;
10972 unsigned int reg
= (given
& 0x0000000fu
);
10973 unsigned int stp
= (given
& 0x00000030u
) >> 4;
10974 unsigned int imm
= 0;
10975 imm
|= (given
& 0x000000c0u
) >> 6;
10976 imm
|= (given
& 0x00007000u
) >> 10;
10978 func (stream
, "%s", arm_regnames
[reg
]);
10983 func (stream
, ", lsl #%u", imm
);
10989 func (stream
, ", lsr #%u", imm
);
10995 func (stream
, ", asr #%u", imm
);
11000 func (stream
, ", rrx");
11002 func (stream
, ", ror #%u", imm
);
11009 unsigned int Rn
= (given
& 0x000f0000) >> 16;
11010 unsigned int U
= ! NEGATIVE_BIT_SET
;
11011 unsigned int op
= (given
& 0x00000f00) >> 8;
11012 unsigned int i12
= (given
& 0x00000fff);
11013 unsigned int i8
= (given
& 0x000000ff);
11014 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
11015 bfd_vma offset
= 0;
11017 func (stream
, "[%s", arm_regnames
[Rn
]);
11018 if (U
) /* 12-bit positive immediate offset. */
11022 value_in_comment
= offset
;
11024 else if (Rn
== 15) /* 12-bit negative immediate offset. */
11025 offset
= - (int) i12
;
11026 else if (op
== 0x0) /* Shifted register offset. */
11028 unsigned int Rm
= (i8
& 0x0f);
11029 unsigned int sh
= (i8
& 0x30) >> 4;
11031 func (stream
, ", %s", arm_regnames
[Rm
]);
11033 func (stream
, ", lsl #%u", sh
);
11034 func (stream
, "]");
11039 case 0xE: /* 8-bit positive immediate offset. */
11043 case 0xC: /* 8-bit negative immediate offset. */
11047 case 0xF: /* 8-bit + preindex with wb. */
11052 case 0xD: /* 8-bit - preindex with wb. */
11057 case 0xB: /* 8-bit + postindex. */
11062 case 0x9: /* 8-bit - postindex. */
11068 func (stream
, ", <undefined>]");
11073 func (stream
, "], #%d", (int) offset
);
11077 func (stream
, ", #%d", (int) offset
);
11078 func (stream
, writeback
? "]!" : "]");
11083 func (stream
, "\t; ");
11084 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
11092 unsigned int U
= ! NEGATIVE_BIT_SET
;
11093 unsigned int W
= WRITEBACK_BIT_SET
;
11094 unsigned int Rn
= (given
& 0x000f0000) >> 16;
11095 unsigned int off
= (given
& 0x000000ff);
11097 func (stream
, "[%s", arm_regnames
[Rn
]);
11103 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
11104 value_in_comment
= off
* 4 * (U
? 1 : -1);
11106 func (stream
, "]");
11108 func (stream
, "!");
11112 func (stream
, "], ");
11115 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
11116 value_in_comment
= off
* 4 * (U
? 1 : -1);
11120 func (stream
, "{%u}", off
);
11121 value_in_comment
= off
;
11129 unsigned int Sbit
= (given
& 0x01000000) >> 24;
11130 unsigned int type
= (given
& 0x00600000) >> 21;
11134 case 0: func (stream
, Sbit
? "sb" : "b"); break;
11135 case 1: func (stream
, Sbit
? "sh" : "h"); break;
11138 func (stream
, "??");
11141 func (stream
, "??");
11149 /* Fall through. */
11155 func (stream
, "{");
11156 for (reg
= 0; reg
< 16; reg
++)
11157 if ((given
& (1 << reg
)) != 0)
11160 func (stream
, ", ");
11162 if (is_clrm
&& reg
== 13)
11163 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
11164 else if (is_clrm
&& reg
== 15)
11165 func (stream
, "%s", "APSR");
11167 func (stream
, "%s", arm_regnames
[reg
]);
11169 func (stream
, "}");
11175 unsigned int msb
= (given
& 0x0000001f);
11176 unsigned int lsb
= 0;
11178 lsb
|= (given
& 0x000000c0u
) >> 6;
11179 lsb
|= (given
& 0x00007000u
) >> 10;
11180 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
11186 unsigned int width
= (given
& 0x0000001f) + 1;
11187 unsigned int lsb
= 0;
11189 lsb
|= (given
& 0x000000c0u
) >> 6;
11190 lsb
|= (given
& 0x00007000u
) >> 10;
11191 func (stream
, "#%u, #%u", lsb
, width
);
11197 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
11198 func (stream
, "%x", boff
);
11204 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
11205 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11206 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11207 bfd_vma offset
= 0;
11209 offset
|= immA
<< 12;
11210 offset
|= immB
<< 2;
11211 offset
|= immC
<< 1;
11213 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
11215 info
->print_address_func (pc
+ 4 + offset
, info
);
11221 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
11222 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11223 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11224 bfd_vma offset
= 0;
11226 offset
|= immA
<< 12;
11227 offset
|= immB
<< 2;
11228 offset
|= immC
<< 1;
11230 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
11232 info
->print_address_func (pc
+ 4 + offset
, info
);
11238 unsigned int immA
= (given
& 0x00010000u
) >> 16;
11239 unsigned int immB
= (given
& 0x000007feu
) >> 1;
11240 unsigned int immC
= (given
& 0x00000800u
) >> 11;
11241 bfd_vma offset
= 0;
11243 offset
|= immA
<< 12;
11244 offset
|= immB
<< 2;
11245 offset
|= immC
<< 1;
11247 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
11249 info
->print_address_func (pc
+ 4 + offset
, info
);
11251 unsigned int T
= (given
& 0x00020000u
) >> 17;
11252 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
11253 unsigned int boffset
= (T
== 1) ? 4 : 2;
11254 func (stream
, ", ");
11255 func (stream
, "%x", endoffset
+ boffset
);
11261 unsigned int immh
= (given
& 0x000007feu
) >> 1;
11262 unsigned int imml
= (given
& 0x00000800u
) >> 11;
11265 imm32
|= immh
<< 2;
11266 imm32
|= imml
<< 1;
11268 info
->print_address_func (pc
+ 4 + imm32
, info
);
11274 unsigned int immh
= (given
& 0x000007feu
) >> 1;
11275 unsigned int imml
= (given
& 0x00000800u
) >> 11;
11278 imm32
|= immh
<< 2;
11279 imm32
|= imml
<< 1;
11281 info
->print_address_func (pc
+ 4 - imm32
, info
);
11287 unsigned int S
= (given
& 0x04000000u
) >> 26;
11288 unsigned int J1
= (given
& 0x00002000u
) >> 13;
11289 unsigned int J2
= (given
& 0x00000800u
) >> 11;
11290 bfd_vma offset
= 0;
11292 offset
|= !S
<< 20;
11293 offset
|= J2
<< 19;
11294 offset
|= J1
<< 18;
11295 offset
|= (given
& 0x003f0000) >> 4;
11296 offset
|= (given
& 0x000007ff) << 1;
11297 offset
-= (1 << 20);
11299 bfd_vma target
= pc
+ 4 + offset
;
11300 info
->print_address_func (target
, info
);
11302 /* Fill in instruction information. */
11303 info
->insn_info_valid
= 1;
11304 info
->insn_type
= dis_branch
;
11305 info
->target
= target
;
11311 unsigned int S
= (given
& 0x04000000u
) >> 26;
11312 unsigned int I1
= (given
& 0x00002000u
) >> 13;
11313 unsigned int I2
= (given
& 0x00000800u
) >> 11;
11314 bfd_vma offset
= 0;
11316 offset
|= !S
<< 24;
11317 offset
|= !(I1
^ S
) << 23;
11318 offset
|= !(I2
^ S
) << 22;
11319 offset
|= (given
& 0x03ff0000u
) >> 4;
11320 offset
|= (given
& 0x000007ffu
) << 1;
11321 offset
-= (1 << 24);
11324 /* BLX target addresses are always word aligned. */
11325 if ((given
& 0x00001000u
) == 0)
11328 info
->print_address_func (offset
, info
);
11330 /* Fill in instruction information. */
11331 info
->insn_info_valid
= 1;
11332 info
->insn_type
= dis_branch
;
11333 info
->target
= offset
;
11339 unsigned int shift
= 0;
11341 shift
|= (given
& 0x000000c0u
) >> 6;
11342 shift
|= (given
& 0x00007000u
) >> 10;
11343 if (WRITEBACK_BIT_SET
)
11344 func (stream
, ", asr #%u", shift
);
11346 func (stream
, ", lsl #%u", shift
);
11347 /* else print nothing - lsl #0 */
11353 unsigned int rot
= (given
& 0x00000030) >> 4;
11356 func (stream
, ", ror #%u", rot
* 8);
11361 if ((given
& 0xf0) == 0x60)
11363 switch (given
& 0xf)
11365 case 0xf: func (stream
, "sy"); break;
11367 func (stream
, "#%d", (int) given
& 0xf);
11373 const char * opt
= data_barrier_option (given
& 0xf);
11375 func (stream
, "%s", opt
);
11377 func (stream
, "#%d", (int) given
& 0xf);
11382 if ((given
& 0xff) == 0)
11384 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
11386 func (stream
, "f");
11388 func (stream
, "s");
11390 func (stream
, "x");
11392 func (stream
, "c");
11394 else if ((given
& 0x20) == 0x20)
11397 unsigned sysm
= (given
& 0xf00) >> 8;
11399 sysm
|= (given
& 0x30);
11400 sysm
|= (given
& 0x00100000) >> 14;
11401 name
= banked_regname (sysm
);
11404 func (stream
, "%s", name
);
11406 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
11410 func (stream
, "%s", psr_name (given
& 0xff));
11415 if (((given
& 0xff) == 0)
11416 || ((given
& 0x20) == 0x20))
11419 unsigned sm
= (given
& 0xf0000) >> 16;
11421 sm
|= (given
& 0x30);
11422 sm
|= (given
& 0x00100000) >> 14;
11423 name
= banked_regname (sm
);
11426 func (stream
, "%s", name
);
11428 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
11431 func (stream
, "%s", psr_name (given
& 0xff));
11434 case '0': case '1': case '2': case '3': case '4':
11435 case '5': case '6': case '7': case '8': case '9':
11440 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
11446 func (stream
, "%s", mve_vec_sizename
[val
]);
11448 func (stream
, "<undef size>");
11452 func (stream
, "%lu", val
);
11453 value_in_comment
= val
;
11457 func (stream
, "%lu", val
+ 1);
11458 value_in_comment
= val
+ 1;
11462 func (stream
, "%lu", val
* 4);
11463 value_in_comment
= val
* 4;
11468 is_unpredictable
= TRUE
;
11469 /* Fall through. */
11472 is_unpredictable
= TRUE
;
11473 /* Fall through. */
11475 func (stream
, "%s", arm_regnames
[val
]);
11479 func (stream
, "%s", arm_conditional
[val
]);
11484 if (val
== ((1ul << width
) - 1))
11485 func (stream
, "%c", *c
);
11491 func (stream
, "%c", *c
);
11495 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
11500 func (stream
, "0x%lx", val
& 0xffffffffUL
);
11510 /* PR binutils/12534
11511 If we have a PC relative offset in an LDRD or STRD
11512 instructions then display the decoded address. */
11513 if (((given
>> 16) & 0xf) == 0xf)
11515 bfd_vma offset
= (given
& 0xff) * 4;
11517 if ((given
& (1 << 23)) == 0)
11519 func (stream
, "\t; ");
11520 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
11529 if (value_in_comment
> 32 || value_in_comment
< -16)
11530 func (stream
, "\t; 0x%lx", value_in_comment
);
11532 if (is_unpredictable
)
11533 func (stream
, UNPREDICTABLE_INSTRUCTION
);
11539 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
11543 /* Print data bytes on INFO->STREAM. */
11546 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
11547 struct disassemble_info
*info
,
11550 switch (info
->bytes_per_chunk
)
11553 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
11556 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
11559 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
11566 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11567 being displayed in symbol relative addresses.
11569 Also disallow private symbol, with __tagsym$$ prefix,
11570 from ARM RVCT toolchain being displayed. */
11573 arm_symbol_is_valid (asymbol
* sym
,
11574 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
11581 name
= bfd_asymbol_name (sym
);
11583 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
11586 /* Parse the string of disassembler options. */
11589 parse_arm_disassembler_options (const char *options
)
11593 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
11595 if (CONST_STRNEQ (opt
, "reg-names-"))
11598 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11599 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
11601 regname_selected
= i
;
11605 if (i
>= NUM_ARM_OPTIONS
)
11606 /* xgettext: c-format */
11607 opcodes_error_handler (_("unrecognised register name set: %s"),
11610 else if (CONST_STRNEQ (opt
, "force-thumb"))
11612 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
11614 else if (CONST_STRNEQ (opt
, "coproc"))
11616 const char *procptr
= opt
+ sizeof ("coproc") - 1;
11618 uint8_t coproc_number
= strtol (procptr
, &endptr
, 10);
11619 if (endptr
!= procptr
+ 1 || coproc_number
> 7)
11621 opcodes_error_handler (_("cde coprocessor not between 0-7: %s"),
11625 if (*endptr
!= '=')
11627 opcodes_error_handler (_("coproc must have an argument: %s"),
11632 if (CONST_STRNEQ (endptr
, "generic"))
11633 cde_coprocs
&= ~(1 << coproc_number
);
11634 else if (CONST_STRNEQ (endptr
, "cde")
11635 || CONST_STRNEQ (endptr
, "CDE"))
11636 cde_coprocs
|= (1 << coproc_number
);
11639 opcodes_error_handler (
11640 _("coprocN argument takes options \"generic\","
11641 " \"cde\", or \"CDE\": %s"), opt
);
11645 /* xgettext: c-format */
11646 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
11653 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11654 enum map_type
*map_symbol
);
11656 /* Search back through the insn stream to determine if this instruction is
11657 conditionally executed. */
11660 find_ifthen_state (bfd_vma pc
,
11661 struct disassemble_info
*info
,
11662 bfd_boolean little
)
11664 unsigned char b
[2];
11667 /* COUNT is twice the number of instructions seen. It will be odd if we
11668 just crossed an instruction boundary. */
11671 unsigned int seen_it
;
11674 ifthen_address
= pc
;
11681 /* Scan backwards looking for IT instructions, keeping track of where
11682 instruction boundaries are. We don't know if something is actually an
11683 IT instruction until we find a definite instruction boundary. */
11686 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
11688 /* A symbol must be on an instruction boundary, and will not
11689 be within an IT block. */
11690 if (seen_it
&& (count
& 1))
11696 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
11701 insn
= (b
[0]) | (b
[1] << 8);
11703 insn
= (b
[1]) | (b
[0] << 8);
11706 if ((insn
& 0xf800) < 0xe800)
11708 /* Addr + 2 is an instruction boundary. See if this matches
11709 the expected boundary based on the position of the last
11716 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
11718 enum map_type type
= MAP_ARM
;
11719 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
11721 if (!found
|| (found
&& type
== MAP_THUMB
))
11723 /* This could be an IT instruction. */
11725 it_count
= count
>> 1;
11728 if ((insn
& 0xf800) >= 0xe800)
11731 count
= (count
+ 2) | 1;
11732 /* IT blocks contain at most 4 instructions. */
11733 if (count
>= 8 && !seen_it
)
11736 /* We found an IT instruction. */
11737 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
11738 if ((ifthen_state
& 0xf) == 0)
11742 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11746 is_mapping_symbol (struct disassemble_info
*info
, int n
,
11747 enum map_type
*map_type
)
11751 name
= bfd_asymbol_name (info
->symtab
[n
]);
11752 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
11753 && (name
[2] == 0 || name
[2] == '.'))
11755 *map_type
= ((name
[1] == 'a') ? MAP_ARM
11756 : (name
[1] == 't') ? MAP_THUMB
11764 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11765 Returns nonzero if *MAP_TYPE was set. */
11768 get_map_sym_type (struct disassemble_info
*info
,
11770 enum map_type
*map_type
)
11772 /* If the symbol is in a different section, ignore it. */
11773 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11776 return is_mapping_symbol (info
, n
, map_type
);
11779 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11780 Returns nonzero if *MAP_TYPE was set. */
11783 get_sym_code_type (struct disassemble_info
*info
,
11785 enum map_type
*map_type
)
11787 elf_symbol_type
*es
;
11790 /* If the symbol is in a different section, ignore it. */
11791 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11794 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
11795 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11797 /* If the symbol has function type then use that. */
11798 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
11800 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11801 == ST_BRANCH_TO_THUMB
)
11802 *map_type
= MAP_THUMB
;
11804 *map_type
= MAP_ARM
;
11811 /* Search the mapping symbol state for instruction at pc. This is only
11812 applicable for elf target.
11814 There is an assumption Here, info->private_data contains the correct AND
11815 up-to-date information about current scan process. The information will be
11816 used to speed this search process.
11818 Return TRUE if the mapping state can be determined, and map_symbol
11819 will be updated accordingly. Otherwise, return FALSE. */
11822 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11823 enum map_type
*map_symbol
)
11825 bfd_vma addr
, section_vma
= 0;
11826 int n
, last_sym
= -1;
11827 bfd_boolean found
= FALSE
;
11828 bfd_boolean can_use_search_opt_p
= FALSE
;
11830 /* Default to DATA. A text section is required by the ABI to contain an
11831 INSN mapping symbol at the start. A data section has no such
11832 requirement, hence if no mapping symbol is found the section must
11833 contain only data. This however isn't very useful if the user has
11834 fully stripped the binaries. If this is the case use the section
11835 attributes to determine the default. If we have no section default to
11836 INSN as well, as we may be disassembling some raw bytes on a baremetal
11837 HEX file or similar. */
11838 enum map_type type
= MAP_DATA
;
11839 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
11841 struct arm_private_data
*private_data
;
11843 if (info
->private_data
== NULL
11844 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
11847 private_data
= info
->private_data
;
11849 /* First, look for mapping symbols. */
11850 if (info
->symtab_size
!= 0)
11852 if (pc
<= private_data
->last_mapping_addr
)
11853 private_data
->last_mapping_sym
= -1;
11855 /* Start scanning at the start of the function, or wherever
11856 we finished last time. */
11857 n
= info
->symtab_pos
+ 1;
11859 /* If the last stop offset is different from the current one it means we
11860 are disassembling a different glob of bytes. As such the optimization
11861 would not be safe and we should start over. */
11862 can_use_search_opt_p
11863 = private_data
->last_mapping_sym
>= 0
11864 && info
->stop_offset
== private_data
->last_stop_offset
;
11866 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11867 n
= private_data
->last_mapping_sym
;
11869 /* Look down while we haven't passed the location being disassembled.
11870 The reason for this is that there's no defined order between a symbol
11871 and an mapping symbol that may be at the same address. We may have to
11872 look at least one position ahead. */
11873 for (; n
< info
->symtab_size
; n
++)
11875 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11878 if (get_map_sym_type (info
, n
, &type
))
11887 n
= info
->symtab_pos
;
11888 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11889 n
= private_data
->last_mapping_sym
;
11891 /* No mapping symbol found at this address. Look backwards
11892 for a preceeding one, but don't go pass the section start
11893 otherwise a data section with no mapping symbol can pick up
11894 a text mapping symbol of a preceeding section. The documentation
11895 says section can be NULL, in which case we will seek up all the
11898 section_vma
= info
->section
->vma
;
11900 for (; n
>= 0; n
--)
11902 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11903 if (addr
< section_vma
)
11906 if (get_map_sym_type (info
, n
, &type
))
11916 /* If no mapping symbol was found, try looking up without a mapping
11917 symbol. This is done by walking up from the current PC to the nearest
11918 symbol. We don't actually have to loop here since symtab_pos will
11919 contain the nearest symbol already. */
11922 n
= info
->symtab_pos
;
11923 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
11930 private_data
->last_mapping_sym
= last_sym
;
11931 private_data
->last_type
= type
;
11932 private_data
->last_stop_offset
= info
->stop_offset
;
11934 *map_symbol
= type
;
11938 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11939 of the supplied arm_feature_set structure with bitmasks indicating
11940 the supported base architectures and coprocessor extensions.
11942 FIXME: This could more efficiently implemented as a constant array,
11943 although it would also be less robust. */
11946 select_arm_features (unsigned long mach
,
11947 arm_feature_set
* features
)
11949 arm_feature_set arch_fset
;
11950 const arm_feature_set fpu_any
= FPU_ANY
;
11952 #undef ARM_SET_FEATURES
11953 #define ARM_SET_FEATURES(FSET) \
11955 const arm_feature_set fset = FSET; \
11956 arch_fset = fset; \
11959 /* When several architecture versions share the same bfd_mach_arm_XXX value
11960 the most featureful is chosen. */
11963 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
11964 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
11965 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
11966 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
11967 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
11968 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
11969 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
11970 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
11971 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
11972 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
11973 case bfd_mach_arm_ep9312
:
11974 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
11975 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
11977 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
11978 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
11979 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
11980 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
11981 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
11982 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
11983 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
11984 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
11985 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
11986 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
11987 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
11988 case bfd_mach_arm_8
:
11990 /* Add bits for extensions that Armv8.6-A recognizes. */
11991 arm_feature_set armv8_6_ext_fset
11992 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
11993 ARM_SET_FEATURES (ARM_ARCH_V8_6A
);
11994 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_6_ext_fset
);
11997 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
11998 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
11999 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
12000 case bfd_mach_arm_8_1M_MAIN
:
12001 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
12002 arm_feature_set mve_all
12003 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
);
12004 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, mve_all
);
12007 /* If the machine type is unknown allow all architecture types and all
12008 extensions, with the exception of MVE as that clashes with NEON. */
12009 case bfd_mach_arm_unknown
:
12010 ARM_SET_FEATURES (ARM_FEATURE (-1,
12011 -1 & ~(ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
),
12017 #undef ARM_SET_FEATURES
12019 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
12020 and thus on bfd_mach_arm_XXX value. Therefore for a given
12021 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
12022 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
12026 /* NOTE: There are no checks in these routines that
12027 the relevant number of data bytes exist. */
12030 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
12032 unsigned char b
[4];
12033 unsigned long given
;
12035 int is_thumb
= FALSE
;
12036 int is_data
= FALSE
;
12038 unsigned int size
= 4;
12039 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
12040 bfd_boolean found
= FALSE
;
12041 struct arm_private_data
*private_data
;
12043 /* Clear instruction information field. */
12044 info
->insn_info_valid
= 0;
12045 info
->branch_delay_insns
= 0;
12046 info
->data_size
= 0;
12047 info
->insn_type
= dis_noninsn
;
12051 if (info
->disassembler_options
)
12053 parse_arm_disassembler_options (info
->disassembler_options
);
12055 /* To avoid repeated parsing of these options, we remove them here. */
12056 info
->disassembler_options
= NULL
;
12059 /* PR 10288: Control which instructions will be disassembled. */
12060 if (info
->private_data
== NULL
)
12062 static struct arm_private_data
private;
12064 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
12065 /* If the user did not use the -m command line switch then default to
12066 disassembling all types of ARM instruction.
12068 The info->mach value has to be ignored as this will be based on
12069 the default archictecture for the target and/or hints in the notes
12070 section, but it will never be greater than the current largest arm
12071 machine value (iWMMXt2), which is only equivalent to the V5TE
12072 architecture. ARM architectures have advanced beyond the machine
12073 value encoding, and these newer architectures would be ignored if
12074 the machine value was used.
12076 Ie the -m switch is used to restrict which instructions will be
12077 disassembled. If it is necessary to use the -m switch to tell
12078 objdump that an ARM binary is being disassembled, eg because the
12079 input is a raw binary file, but it is also desired to disassemble
12080 all ARM instructions then use "-marm". This will select the
12081 "unknown" arm architecture which is compatible with any ARM
12083 info
->mach
= bfd_mach_arm_unknown
;
12085 /* Compute the architecture bitmask from the machine number.
12086 Note: This assumes that the machine number will not change
12087 during disassembly.... */
12088 select_arm_features (info
->mach
, & private.features
);
12090 private.last_mapping_sym
= -1;
12091 private.last_mapping_addr
= 0;
12092 private.last_stop_offset
= 0;
12094 info
->private_data
= & private;
12097 private_data
= info
->private_data
;
12099 /* Decide if our code is going to be little-endian, despite what the
12100 function argument might say. */
12101 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
12103 /* For ELF, consult the symbol table to determine what kind of code
12104 or data we have. */
12105 if (info
->symtab_size
!= 0
12106 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
12111 enum map_type type
= MAP_ARM
;
12113 found
= mapping_symbol_for_insn (pc
, info
, &type
);
12114 last_sym
= private_data
->last_mapping_sym
;
12116 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
12117 is_data
= (private_data
->last_type
== MAP_DATA
);
12119 /* Look a little bit ahead to see if we should print out
12120 two or four bytes of data. If there's a symbol,
12121 mapping or otherwise, after two bytes then don't
12125 size
= 4 - (pc
& 3);
12126 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
12128 addr
= bfd_asymbol_value (info
->symtab
[n
]);
12130 && (info
->section
== NULL
12131 || info
->section
== info
->symtab
[n
]->section
))
12133 if (addr
- pc
< size
)
12138 /* If the next symbol is after three bytes, we need to
12139 print only part of the data, so that we can use either
12140 .byte or .short. */
12142 size
= (pc
& 1) ? 1 : 2;
12146 if (info
->symbols
!= NULL
)
12148 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
12150 coff_symbol_type
* cs
;
12152 cs
= coffsymbol (*info
->symbols
);
12153 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
12154 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
12155 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
12156 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
12157 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
12159 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
12162 /* If no mapping symbol has been found then fall back to the type
12163 of the function symbol. */
12164 elf_symbol_type
* es
;
12167 es
= *(elf_symbol_type
**)(info
->symbols
);
12168 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
12171 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
12172 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
12174 else if (bfd_asymbol_flavour (*info
->symbols
)
12175 == bfd_target_mach_o_flavour
)
12177 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
12179 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
12187 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
12189 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
12191 info
->bytes_per_line
= 4;
12193 /* PR 10263: Disassemble data if requested to do so by the user. */
12194 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
12198 /* Size was already set above. */
12199 info
->bytes_per_chunk
= size
;
12200 printer
= print_insn_data
;
12202 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
12205 for (i
= size
- 1; i
>= 0; i
--)
12206 given
= b
[i
] | (given
<< 8);
12208 for (i
= 0; i
< (int) size
; i
++)
12209 given
= b
[i
] | (given
<< 8);
12211 else if (!is_thumb
)
12213 /* In ARM mode endianness is a straightforward issue: the instruction
12214 is four bytes long and is either ordered 0123 or 3210. */
12215 printer
= print_insn_arm
;
12216 info
->bytes_per_chunk
= 4;
12219 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
12221 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | ((unsigned) b
[3] << 24);
12223 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | ((unsigned) b
[0] << 24);
12227 /* In Thumb mode we have the additional wrinkle of two
12228 instruction lengths. Fortunately, the bits that determine
12229 the length of the current instruction are always to be found
12230 in the first two bytes. */
12231 printer
= print_insn_thumb16
;
12232 info
->bytes_per_chunk
= 2;
12235 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
12237 given
= (b
[0]) | (b
[1] << 8);
12239 given
= (b
[1]) | (b
[0] << 8);
12243 /* These bit patterns signal a four-byte Thumb
12245 if ((given
& 0xF800) == 0xF800
12246 || (given
& 0xF800) == 0xF000
12247 || (given
& 0xF800) == 0xE800)
12249 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
12251 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
12253 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
12255 printer
= print_insn_thumb32
;
12260 if (ifthen_address
!= pc
)
12261 find_ifthen_state (pc
, info
, little_code
);
12265 if ((ifthen_state
& 0xf) == 0x8)
12266 ifthen_next_state
= 0;
12268 ifthen_next_state
= (ifthen_state
& 0xe0)
12269 | ((ifthen_state
& 0xf) << 1);
12275 info
->memory_error_func (status
, pc
, info
);
12278 if (info
->flags
& INSN_HAS_RELOC
)
12279 /* If the instruction has a reloc associated with it, then
12280 the offset field in the instruction will actually be the
12281 addend for the reloc. (We are using REL type relocs).
12282 In such cases, we can ignore the pc when computing
12283 addresses, since the addend is not currently pc-relative. */
12286 printer (pc
, info
, given
);
12290 ifthen_state
= ifthen_next_state
;
12291 ifthen_address
+= size
;
12297 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
12299 /* Detect BE8-ness and record it in the disassembler info. */
12300 if (info
->flavour
== bfd_target_elf_flavour
12301 && info
->section
!= NULL
12302 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
12303 info
->endian_code
= BFD_ENDIAN_LITTLE
;
12305 return print_insn (pc
, info
, FALSE
);
12309 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
12311 return print_insn (pc
, info
, TRUE
);
12314 const disasm_options_and_args_t
*
12315 disassembler_options_arm (void)
12317 static disasm_options_and_args_t
*opts_and_args
;
12319 if (opts_and_args
== NULL
)
12321 disasm_options_t
*opts
;
12324 opts_and_args
= XNEW (disasm_options_and_args_t
);
12325 opts_and_args
->args
= NULL
;
12327 opts
= &opts_and_args
->options
;
12328 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
12329 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
12331 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
12333 opts
->name
[i
] = regnames
[i
].name
;
12334 if (regnames
[i
].description
!= NULL
)
12335 opts
->description
[i
] = _(regnames
[i
].description
);
12337 opts
->description
[i
] = NULL
;
12339 /* The array we return must be NULL terminated. */
12340 opts
->name
[i
] = NULL
;
12341 opts
->description
[i
] = NULL
;
12344 return opts_and_args
;
12348 print_arm_disassembler_options (FILE *stream
)
12350 unsigned int i
, max_len
= 0;
12351 fprintf (stream
, _("\n\
12352 The following ARM specific disassembler options are supported for use with\n\
12353 the -M switch:\n"));
12355 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
12357 unsigned int len
= strlen (regnames
[i
].name
);
12362 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
12363 fprintf (stream
, " %s%*c %s\n",
12365 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
12366 _(regnames
[i
].description
));