1 /* Instruction printing code for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
6 This file is part of libopcodes.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
26 #include "disassemble.h"
27 #include "opcode/arm.h"
29 #include "safe-ctype.h"
30 #include "libiberty.h"
31 #include "floatformat.h"
33 /* FIXME: This shouldn't be done here. */
34 #include "coff/internal.h"
38 #include "elf/internal.h"
42 /* FIXME: Belongs in global header. */
44 #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
47 /* Cached mapping symbol state. */
55 struct arm_private_data
57 /* The features to use when disassembling optional instructions. */
58 arm_feature_set features
;
60 /* Track the last type (although this doesn't seem to be useful) */
61 enum map_type last_type
;
63 /* Tracking symbol table information */
66 /* The end range of the current range being disassembled. */
67 bfd_vma last_stop_offset
;
68 bfd_vma last_mapping_addr
;
121 MVE_VSTRB_SCATTER_T1
,
122 MVE_VSTRH_SCATTER_T2
,
123 MVE_VSTRW_SCATTER_T3
,
124 MVE_VSTRD_SCATTER_T4
,
125 MVE_VSTRW_SCATTER_T5
,
126 MVE_VSTRD_SCATTER_T6
,
128 MVE_VCVT_BETWEEN_FP_INT
,
130 MVE_VCVT_FROM_FP_TO_INT
,
133 MVE_VMOV_GP_TO_VEC_LANE
,
136 MVE_VMOV2_VEC_LANE_TO_GP
,
137 MVE_VMOV2_GP_TO_VEC_LANE
,
138 MVE_VMOV_VEC_LANE_TO_GP
,
296 enum mve_unpredictable
298 UNPRED_IT_BLOCK
, /* Unpredictable because mve insn in it block.
300 UNPRED_FCA_0_FCB_1
, /* Unpredictable because fcA = 0 and
302 UNPRED_R13
, /* Unpredictable because r13 (sp) or
304 UNPRED_R15
, /* Unpredictable because r15 (pc) is used. */
305 UNPRED_Q_GT_4
, /* Unpredictable because
306 vec reg start > 4 (vld4/st4). */
307 UNPRED_Q_GT_6
, /* Unpredictable because
308 vec reg start > 6 (vld2/st2). */
309 UNPRED_R13_AND_WB
, /* Unpredictable becase gp reg = r13
311 UNPRED_Q_REGS_EQUAL
, /* Unpredictable because vector registers are
313 UNPRED_OS
, /* Unpredictable because offset scaled == 1. */
314 UNPRED_GP_REGS_EQUAL
, /* Unpredictable because gp registers are the
316 UNPRED_Q_REGS_EQ_AND_SIZE_1
, /* Unpredictable because q regs equal and
318 UNPRED_Q_REGS_EQ_AND_SIZE_2
, /* Unpredictable because q regs equal and
320 UNPRED_NONE
/* No unpredictable behavior. */
325 UNDEF_SIZE
, /* undefined size. */
326 UNDEF_SIZE_0
, /* undefined because size == 0. */
327 UNDEF_SIZE_2
, /* undefined because size == 2. */
328 UNDEF_SIZE_3
, /* undefined because size == 3. */
329 UNDEF_SIZE_LE_1
, /* undefined because size <= 1. */
330 UNDEF_SIZE_NOT_0
, /* undefined because size != 0. */
331 UNDEF_SIZE_NOT_2
, /* undefined because size != 2. */
332 UNDEF_SIZE_NOT_3
, /* undefined because size != 3. */
333 UNDEF_NOT_UNS_SIZE_0
, /* undefined because U == 0 and
335 UNDEF_NOT_UNS_SIZE_1
, /* undefined because U == 0 and
337 UNDEF_NOT_UNSIGNED
, /* undefined because U == 0. */
338 UNDEF_VCVT_IMM6
, /* imm6 < 32. */
339 UNDEF_VCVT_FSI_IMM6
, /* fsi = 0 and 32 >= imm6 <= 47. */
340 UNDEF_BAD_OP1_OP2
, /* undefined with op2 = 2 and
342 UNDEF_BAD_U_OP1_OP2
, /* undefined with U = 1 and
343 op2 == 0 and op1 == (0 or 1). */
344 UNDEF_OP_0_BAD_CMODE
, /* undefined because op == 0 and cmode
346 UNDEF_XCHG_UNS
, /* undefined because X == 1 and U == 1. */
347 UNDEF_NONE
/* no undefined behavior. */
352 arm_feature_set arch
; /* Architecture defining this insn. */
353 unsigned long value
; /* If arch is 0 then value is a sentinel. */
354 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
355 const char * assembler
; /* How to disassemble this insn. */
362 arm_feature_set arch
; /* Architecture defining this insn. */
363 enum mve_instructions mve_op
; /* Specific mve instruction for faster
365 unsigned long value
; /* If arch is 0 then value is a sentinel. */
366 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
367 const char * assembler
; /* How to disassemble this insn. */
377 /* Shared (between Arm and Thumb mode) opcode. */
380 enum isa isa
; /* Execution mode instruction availability. */
381 arm_feature_set arch
; /* Architecture defining this insn. */
382 unsigned long value
; /* If arch is 0 then value is a sentinel. */
383 unsigned long mask
; /* Recognise insn if (op & mask) == value. */
384 const char * assembler
; /* How to disassemble this insn. */
389 arm_feature_set arch
; /* Architecture defining this insn. */
390 unsigned short value
, mask
; /* Recognise insn if (op & mask) == value. */
391 const char *assembler
; /* How to disassemble this insn. */
394 /* print_insn_coprocessor recognizes the following format control codes:
398 %c print condition code (always bits 28-31 in ARM mode)
399 %q print shifter argument
400 %u print condition code (unconditional in ARM mode,
401 UNPREDICTABLE if not AL in Thumb)
402 %A print address for ldc/stc/ldf/stf instruction
403 %B print vstm/vldm register list
404 %C print vscclrm register list
405 %I print cirrus signed shift immediate: bits 0..3|4..6
406 %J print register for VLDR instruction
407 %K print address for VLDR instruction
408 %F print the COUNT field of a LFM/SFM instruction.
409 %P print floating point precision in arithmetic insn
410 %Q print floating point precision in ldf/stf insn
411 %R print floating point rounding mode
413 %<bitfield>c print as a condition code (for vsel)
414 %<bitfield>r print as an ARM register
415 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
416 %<bitfield>ru as %<>r but each u register must be unique.
417 %<bitfield>d print the bitfield in decimal
418 %<bitfield>k print immediate for VFPv3 conversion instruction
419 %<bitfield>x print the bitfield in hex
420 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
421 %<bitfield>f print a floating point constant if >7 else a
422 floating point register
423 %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
424 %<bitfield>g print as an iWMMXt 64-bit register
425 %<bitfield>G print as an iWMMXt general purpose or control register
426 %<bitfield>D print as a NEON D register
427 %<bitfield>Q print as a NEON Q register
428 %<bitfield>V print as a NEON D or Q register
429 %<bitfield>E print a quarter-float immediate value
431 %y<code> print a single precision VFP reg.
432 Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
433 %z<code> print a double precision VFP reg
434 Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
436 %<bitfield>'c print specified char iff bitfield is all ones
437 %<bitfield>`c print specified char iff bitfield is all zeroes
438 %<bitfield>?ab... select from array of values in big endian order
440 %L print as an iWMMXt N/M width field.
441 %Z print the Immediate of a WSHUFH instruction.
442 %l like 'A' except use byte offsets for 'B' & 'H'
444 %i print 5-bit immediate in bits 8,3..0
446 %r print register offset address for wldt/wstr instruction. */
448 enum opcode_sentinel_enum
450 SENTINEL_IWMMXT_START
= 1,
452 SENTINEL_GENERIC_START
455 #define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
456 #define UNKNOWN_INSTRUCTION_32BIT "\t\t; <UNDEFINED> instruction: %08x"
457 #define UNKNOWN_INSTRUCTION_16BIT "\t\t; <UNDEFINED> instruction: %04x"
458 #define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
460 /* Common coprocessor opcodes shared between Arm and Thumb-2. */
462 static const struct sopcode32 coprocessor_opcodes
[] =
464 /* XScale instructions. */
465 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
466 0x0e200010, 0x0fff0ff0,
467 "mia%c\tacc0, %0-3r, %12-15r"},
468 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
469 0x0e280010, 0x0fff0ff0,
470 "miaph%c\tacc0, %0-3r, %12-15r"},
471 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
472 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
473 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
474 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
475 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
476 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
478 /* Intel Wireless MMX technology instructions. */
479 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START
, 0, "" },
480 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
481 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
482 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
483 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
484 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
485 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
486 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
487 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
488 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
489 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
490 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
491 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
492 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
493 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
494 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
495 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
496 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
497 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
498 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
499 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
500 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
501 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
502 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
503 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
504 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
505 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
506 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
507 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
508 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
509 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
510 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
511 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
512 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
513 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
514 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
515 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
516 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
517 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
518 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
519 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
520 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
521 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
522 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
523 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
524 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
525 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
526 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
527 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
528 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
529 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
530 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
531 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
532 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
533 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
534 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
535 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
536 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
537 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
538 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
539 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
540 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
541 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
542 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
543 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
544 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
545 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
546 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
547 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
548 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
549 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
550 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
551 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
552 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
553 0x0e800120, 0x0f800ff0,
554 "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
555 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
556 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
557 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
558 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
559 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
560 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
561 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
562 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
563 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
564 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
565 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
566 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
567 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
568 0x0e8000a0, 0x0f800ff0,
569 "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
570 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
571 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
572 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
573 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
574 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
575 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
576 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
577 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
578 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
579 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
580 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
581 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
582 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
583 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
584 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
585 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
586 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
587 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
588 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
589 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
590 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
591 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
592 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
593 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
594 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
595 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
596 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
597 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
598 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
599 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
600 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
601 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
602 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
603 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
604 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
605 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
606 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
607 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
608 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
609 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
610 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
611 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
612 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
613 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
614 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
615 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
616 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
617 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
618 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
619 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
620 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
621 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
622 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
623 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
624 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
625 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
626 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
627 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
628 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
629 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
630 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
631 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
632 {ANY
, ARM_FEATURE_CORE_LOW (0),
633 SENTINEL_IWMMXT_END
, 0, "" },
635 /* Floating point coprocessor (FPA) instructions. */
636 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
637 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
638 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
639 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
640 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
641 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
642 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
643 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
644 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
645 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
646 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
647 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
648 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
649 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
650 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
651 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
652 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
653 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
654 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
655 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
656 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
657 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
658 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
659 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
660 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
661 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
662 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
663 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
664 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
665 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
666 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
667 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
668 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
669 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
670 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
671 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
672 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
673 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
674 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
675 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
676 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
677 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
678 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
679 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
680 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
681 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
682 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
683 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
684 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
685 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
686 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
687 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
688 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
689 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
690 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
691 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
692 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
693 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
694 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
695 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
696 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
697 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
698 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
699 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
700 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
701 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
702 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
703 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
704 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
705 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
706 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
707 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
708 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
709 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
710 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
711 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
712 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
713 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
714 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
715 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
716 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
),
717 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
718 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
719 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
720 {ANY
, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
),
721 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
723 /* Armv8.1-M Mainline instructions. */
724 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
725 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
726 {T32
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
727 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
729 /* ARMv8-M Mainline Security Extensions instructions. */
730 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
731 0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
732 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
),
733 0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
735 /* Register load/store. */
736 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
737 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
738 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
739 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
740 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
741 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
742 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
743 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
744 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
745 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
746 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
747 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
748 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
749 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
750 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_NEON_EXT_V1
),
751 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
752 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
753 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
754 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
755 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
756 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
757 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
758 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
759 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
760 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
761 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
762 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
763 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
764 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
765 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
766 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
767 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
768 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
769 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
770 {ANY
, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN
),
771 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
773 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
774 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
775 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
776 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
777 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
778 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
779 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
780 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
782 /* Data transfer between ARM and NEON registers. */
783 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
784 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
785 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
786 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
787 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
788 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
789 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
790 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
791 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
792 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
793 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
794 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
795 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
796 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
797 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
798 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
799 /* Half-precision conversion instructions. */
800 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
801 0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
802 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
803 0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
804 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
805 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
806 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
807 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
809 /* Floating point coprocessor (VFP) instructions. */
810 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
811 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
812 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_MVE
),
813 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
814 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
815 0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
816 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
817 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
818 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
819 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
820 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
821 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
822 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
823 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
824 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
825 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
826 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
827 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
828 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
829 0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
830 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
831 0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
832 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
833 0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
834 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
835 0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
836 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
837 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
838 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
839 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
840 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
| FPU_MVE
),
841 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
842 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
843 0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
844 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
845 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
846 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
847 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
848 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
849 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
850 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
851 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
852 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
853 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
854 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
855 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
856 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
857 0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
858 {ANY
, ARM_FEATURE_COPROC (FPU_MVE
),
859 0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
860 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
861 0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
862 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
863 0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
864 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
865 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
866 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
867 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
868 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
869 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
870 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
871 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
872 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
873 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
874 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
875 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
876 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
877 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
878 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
879 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
880 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
881 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
882 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
883 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
884 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
885 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
886 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
887 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
888 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
889 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
890 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
891 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
892 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
893 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
894 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
895 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
896 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
897 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
898 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
899 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
900 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
901 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
902 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
903 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
904 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
905 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
906 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
907 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
908 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
909 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
910 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
911 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
912 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
913 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
914 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
915 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
916 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
917 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
918 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
919 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
920 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
921 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
922 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
),
923 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
924 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
),
925 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
926 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
927 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
928 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
929 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
930 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
),
931 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
932 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
933 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
934 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
935 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
936 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
937 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
938 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
939 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
940 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
941 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
942 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
943 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
944 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
945 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
946 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
947 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
948 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
949 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
950 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
951 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
952 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
953 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
954 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
955 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
956 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
957 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
958 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
959 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
960 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
961 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
962 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
963 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
964 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
),
965 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
966 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
),
967 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
969 /* Cirrus coprocessor instructions. */
970 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
971 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
972 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
973 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
974 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
975 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
976 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
977 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
978 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
979 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
980 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
981 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
982 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
983 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
984 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
985 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
986 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
987 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
988 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
989 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
990 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
991 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
992 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
993 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
994 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
995 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
996 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
997 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
998 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
999 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1000 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1001 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
1002 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1003 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
1004 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1005 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
1006 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1007 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
1008 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1009 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
1010 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1011 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
1012 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1013 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
1014 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1015 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
1016 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1017 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
1018 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1019 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
1020 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1021 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
1022 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1023 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
1024 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1025 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
1026 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1027 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
1028 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1029 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
1030 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1031 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
1032 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1033 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
1034 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1035 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
1036 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1037 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
1038 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1039 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
1040 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1041 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
1042 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1043 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
1044 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1045 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
1046 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1047 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
1048 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1049 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
1050 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1051 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
1052 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1053 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
1054 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1055 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
1056 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1057 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
1058 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1059 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
1060 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1061 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
1062 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1063 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
1064 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1065 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
1066 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1067 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
1068 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1069 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
1070 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1071 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
1072 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1073 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
1074 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1075 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
1076 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1077 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
1078 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1079 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
1080 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1081 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
1082 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1083 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
1084 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1085 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
1086 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1087 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
1088 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1089 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
1090 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1091 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
1092 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1093 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
1094 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1095 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1096 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1097 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1098 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1099 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1100 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1101 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1102 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1103 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
1104 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1105 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
1106 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1107 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
1108 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1109 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
1110 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1111 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
1112 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1113 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
1114 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1115 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1116 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1117 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1118 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1119 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1120 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1121 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1122 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1123 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1124 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1125 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
1126 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1127 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1128 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1129 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1130 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1131 0x0e000600, 0x0ff00f10,
1132 "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1133 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1134 0x0e100600, 0x0ff00f10,
1135 "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
1136 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1137 0x0e200600, 0x0ff00f10,
1138 "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1139 {ANY
, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
1140 0x0e300600, 0x0ff00f10,
1141 "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
1143 /* VFP Fused multiply add instructions. */
1144 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1145 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
1146 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1147 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
1148 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1149 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
1150 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1151 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
1152 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1153 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
1154 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1155 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
1156 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1157 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
1158 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
),
1159 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
1162 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1163 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
1164 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1165 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
1166 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1167 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
1168 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1169 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
1170 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1171 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
1172 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1173 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
1174 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1175 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
1176 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1177 0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
1178 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1179 0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
1180 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1181 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
1182 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1183 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
1184 {ANY
, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
),
1185 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
1187 /* Generic coprocessor instructions. */
1188 {ANY
, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START
, 0, "" },
1189 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1190 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
1191 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
1192 0x0c500000, 0x0ff00000,
1193 "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1194 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1195 0x0e000000, 0x0f000010,
1196 "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1197 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1198 0x0e10f010, 0x0f10f010,
1199 "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
1200 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1201 0x0e100010, 0x0f100010,
1202 "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1203 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1204 0x0e000010, 0x0f100010,
1205 "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1206 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1207 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
1208 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
1209 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
1211 /* V6 coprocessor instructions. */
1212 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1213 0xfc500000, 0xfff00000,
1214 "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
1215 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
1216 0xfc400000, 0xfff00000,
1217 "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
1219 /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
1220 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1221 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1222 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1223 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
1224 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1225 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1226 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1227 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1228 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1229 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
1230 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1231 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
1232 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1233 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
1234 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1235 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
1236 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1237 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
1238 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1239 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
1241 /* Dot Product instructions in the space of coprocessor 13. */
1242 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1243 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
1244 {ANY
, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
1245 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
1247 /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
1248 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1249 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1250 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1251 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
1252 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1253 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1254 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1255 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
1256 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1257 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1258 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1259 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
1260 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1261 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1262 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
| ARM_EXT2_V8_2A
),
1263 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
1265 /* V5 coprocessor instructions. */
1266 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1267 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1268 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1269 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
1270 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1271 0xfe000000, 0xff000010,
1272 "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
1273 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1274 0xfe000010, 0xff100010,
1275 "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
1276 {ANY
, ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
1277 0xfe100010, 0xff100010,
1278 "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
1280 /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
1281 cp_num: bit <11:8> == 0b1001.
1282 cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
1283 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1284 0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
1285 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1286 0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
1287 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1288 0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
1289 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1290 0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
1291 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1292 0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
1293 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1294 0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
1295 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1296 0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
1297 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1298 0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
1299 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1300 0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
1301 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1302 0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
1303 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1304 0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
1305 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1306 0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
1307 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1308 0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
1309 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1310 0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
1311 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1312 0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
1313 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1314 0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
1315 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1316 0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
1317 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1318 0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
1319 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1320 0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
1321 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1322 0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
1323 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1324 0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
1325 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1326 0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
1327 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1328 0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
1329 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1330 0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
1331 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1332 0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
1333 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1334 0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
1335 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1336 0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
1337 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1338 0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
1339 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1340 0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
1341 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1342 0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
1343 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1344 0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
1345 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1346 0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
1347 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1348 0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
1349 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1350 0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
1351 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1352 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
1354 /* ARMv8.3 javascript conversion instruction. */
1355 {ANY
, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
),
1356 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1358 {ANY
, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1361 /* Neon opcode table: This does not encode the top byte -- that is
1362 checked by the print_insn_neon routine, as it depends on whether we are
1363 doing thumb32 or arm32 disassembly. */
1365 /* print_insn_neon recognizes the following format control codes:
1369 %c print condition code
1370 %u print condition code (unconditional in ARM mode,
1371 UNPREDICTABLE if not AL in Thumb)
1372 %A print v{st,ld}[1234] operands
1373 %B print v{st,ld}[1234] any one operands
1374 %C print v{st,ld}[1234] single->all operands
1376 %E print vmov, vmvn, vorr, vbic encoded constant
1377 %F print vtbl,vtbx register list
1379 %<bitfield>r print as an ARM register
1380 %<bitfield>d print the bitfield in decimal
1381 %<bitfield>e print the 2^N - bitfield in decimal
1382 %<bitfield>D print as a NEON D register
1383 %<bitfield>Q print as a NEON Q register
1384 %<bitfield>R print as a NEON D or Q register
1385 %<bitfield>Sn print byte scaled width limited by n
1386 %<bitfield>Tn print short scaled width limited by n
1387 %<bitfield>Un print long scaled width limited by n
1389 %<bitfield>'c print specified char iff bitfield is all ones
1390 %<bitfield>`c print specified char iff bitfield is all zeroes
1391 %<bitfield>?ab... select from array of values in big endian order. */
1393 static const struct opcode32 neon_opcodes
[] =
1396 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1397 0xf2b00840, 0xffb00850,
1398 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1399 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1400 0xf2b00000, 0xffb00810,
1401 "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1403 /* Data transfer between ARM and NEON registers. */
1404 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1405 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
1406 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1407 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
1408 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1409 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
1410 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1411 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
1412 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1413 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
1414 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1415 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
1417 /* Move data element to all lanes. */
1418 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1419 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1420 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1421 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1422 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1423 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1426 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1427 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1428 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1429 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1431 /* Half-precision conversions. */
1432 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1433 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1434 {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
),
1435 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1437 /* NEON fused multiply add instructions. */
1438 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1439 0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1440 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1441 0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1442 {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
),
1443 0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1444 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1445 0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1447 /* Two registers, miscellaneous. */
1448 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1449 0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1451 0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1452 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1453 0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1454 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1455 0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1456 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1457 0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1458 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1459 0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1460 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1461 0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1462 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1463 0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1464 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1465 0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1466 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1467 0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1468 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1469 0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1470 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1471 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1472 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1473 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1474 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1475 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1476 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1477 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1478 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1479 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1480 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1481 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1482 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1483 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1484 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1485 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1486 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1487 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1488 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1489 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1490 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1491 0xf3b20300, 0xffb30fd0,
1492 "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1493 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1494 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1495 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1496 0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1497 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1498 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1499 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1500 0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1501 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1502 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1503 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1504 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1505 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1506 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1507 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1508 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1509 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1510 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1511 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1512 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1513 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1514 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1515 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1516 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1517 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1518 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1519 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1520 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1521 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1522 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1523 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1524 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1525 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1526 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1527 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1528 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1529 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1530 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1531 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1532 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1533 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1534 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1535 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1536 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1537 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1538 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1539 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1540 0xf3bb0600, 0xffbf0e10,
1541 "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1542 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1543 0xf3b70600, 0xffbf0e10,
1544 "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1546 /* Three registers of the same length. */
1547 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1548 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1549 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1550 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1551 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1552 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1553 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1554 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1555 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1556 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1557 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1558 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1559 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1560 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1561 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1562 0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1563 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1564 0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1565 {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
),
1566 0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1567 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1568 0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1569 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1570 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1571 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1572 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1573 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1574 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1575 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1576 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1577 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1578 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1579 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1580 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1581 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1582 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1583 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1584 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1585 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1586 0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1587 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1588 0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1589 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1590 0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1591 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1592 0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1593 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1594 0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1595 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1596 0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1597 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1598 0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1599 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1600 0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1601 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1602 0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1603 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1604 0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1605 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1606 0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1607 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1608 0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1609 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1610 0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1611 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1612 0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1613 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1614 0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1615 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1616 0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1617 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1618 0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1619 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1620 0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1621 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1622 0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1623 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1624 0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1625 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1626 0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1627 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1628 0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1629 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1630 0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1631 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1632 0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1633 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1634 0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1635 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1636 0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1637 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1638 0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1639 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1640 0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1641 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1642 0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1643 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1644 0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1645 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1646 0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1647 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1648 0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1649 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1650 0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1651 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1652 0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1653 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1654 0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1655 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1656 0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1657 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1658 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1659 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1660 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1661 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1662 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1663 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1664 0xf2000b00, 0xff800f10,
1665 "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1666 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1667 0xf2000b10, 0xff800f10,
1668 "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1669 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1670 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1671 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1672 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1673 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1674 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1675 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1676 0xf3000b00, 0xff800f10,
1677 "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1678 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1679 0xf2000000, 0xfe800f10,
1680 "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1681 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1682 0xf2000010, 0xfe800f10,
1683 "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1684 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1685 0xf2000100, 0xfe800f10,
1686 "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1687 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1688 0xf2000200, 0xfe800f10,
1689 "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1690 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1691 0xf2000210, 0xfe800f10,
1692 "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1693 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1694 0xf2000300, 0xfe800f10,
1695 "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1696 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1697 0xf2000310, 0xfe800f10,
1698 "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1699 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1700 0xf2000400, 0xfe800f10,
1701 "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1702 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1703 0xf2000410, 0xfe800f10,
1704 "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1705 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1706 0xf2000500, 0xfe800f10,
1707 "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1708 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1709 0xf2000510, 0xfe800f10,
1710 "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1711 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1712 0xf2000600, 0xfe800f10,
1713 "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1714 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1715 0xf2000610, 0xfe800f10,
1716 "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1717 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1718 0xf2000700, 0xfe800f10,
1719 "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1720 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1721 0xf2000710, 0xfe800f10,
1722 "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1723 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1724 0xf2000910, 0xfe800f10,
1725 "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1726 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1727 0xf2000a00, 0xfe800f10,
1728 "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1729 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1730 0xf2000a10, 0xfe800f10,
1731 "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1732 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1733 0xf3000b10, 0xff800f10,
1734 "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1735 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
1736 0xf3000c10, 0xff800f10,
1737 "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1739 /* One register and an immediate value. */
1740 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1741 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1742 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1743 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1744 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1745 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1746 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1747 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1748 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1749 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1750 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1751 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1752 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1753 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1754 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1755 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1756 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1757 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1758 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1759 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1760 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1761 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1762 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1763 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1764 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1765 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1767 /* Two registers and a shift amount. */
1768 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1769 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1770 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1771 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1772 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1773 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1774 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1775 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1776 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1777 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1778 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1779 0xf2880950, 0xfeb80fd0,
1780 "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1781 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1782 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1783 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1784 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1785 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1786 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1787 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1788 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1789 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1790 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1791 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1792 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1793 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1794 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1795 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1796 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1797 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1798 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1799 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1800 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1801 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1802 0xf2900950, 0xfeb00fd0,
1803 "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1804 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1805 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1806 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1807 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1808 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1809 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1810 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1811 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1812 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1813 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1814 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1815 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1816 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1817 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1818 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1819 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1820 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1821 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1822 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1823 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1824 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1825 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1826 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1827 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1828 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1829 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1830 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1831 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1832 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1833 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1834 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1835 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1836 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1837 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1838 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1839 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1840 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1841 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1842 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1843 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1844 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1845 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1846 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1847 0xf2a00950, 0xfea00fd0,
1848 "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1849 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1850 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1851 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1852 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1853 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1854 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1855 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1856 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1857 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1858 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1859 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1860 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1861 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1862 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1863 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1864 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1865 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1866 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1867 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1868 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1869 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1870 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1871 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1872 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1873 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1874 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1875 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1876 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1877 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1878 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1879 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1880 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1881 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1882 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1883 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1884 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1885 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1886 0xf2a00e10, 0xfea00e90,
1887 "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1888 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
1889 0xf2a00c10, 0xfea00e90,
1890 "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1892 /* Three registers of different lengths. */
1893 {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
),
1894 0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1895 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1896 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1897 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1898 0xf2800400, 0xff800f50,
1899 "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1900 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1901 0xf2800600, 0xff800f50,
1902 "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1903 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1904 0xf2800900, 0xff800f50,
1905 "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1906 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1907 0xf2800b00, 0xff800f50,
1908 "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1909 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1910 0xf2800d00, 0xff800f50,
1911 "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1912 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1913 0xf3800400, 0xff800f50,
1914 "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1915 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1916 0xf3800600, 0xff800f50,
1917 "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1918 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1919 0xf2800000, 0xfe800f50,
1920 "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1921 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1922 0xf2800100, 0xfe800f50,
1923 "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1924 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1925 0xf2800200, 0xfe800f50,
1926 "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1927 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1928 0xf2800300, 0xfe800f50,
1929 "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1930 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1931 0xf2800500, 0xfe800f50,
1932 "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1933 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1934 0xf2800700, 0xfe800f50,
1935 "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1936 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1937 0xf2800800, 0xfe800f50,
1938 "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1939 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1940 0xf2800a00, 0xfe800f50,
1941 "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1942 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1943 0xf2800c00, 0xfe800f50,
1944 "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1946 /* Two registers and a scalar. */
1947 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1948 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1949 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1950 0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1951 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1952 0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1953 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1954 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1955 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1956 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1957 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1958 0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1959 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1960 0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1961 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1962 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1963 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1964 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1965 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1966 0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1967 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1968 0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1969 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1970 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1971 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1972 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1973 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1974 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1975 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1976 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1977 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1978 0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1979 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1980 0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1981 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1982 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1983 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1984 0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1985 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1986 0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1987 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1988 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1989 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1990 0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1991 {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST
),
1992 0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1993 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1994 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1995 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1996 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1997 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
1998 0xf2800240, 0xfe800f50,
1999 "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2000 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2001 0xf2800640, 0xfe800f50,
2002 "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2003 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2004 0xf2800a40, 0xfe800f50,
2005 "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
2006 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2007 0xf2800e40, 0xff800f50,
2008 "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2009 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2010 0xf2800f40, 0xff800f50,
2011 "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
2012 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2013 0xf3800e40, 0xff800f50,
2014 "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
2015 {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
),
2016 0xf3800f40, 0xff800f50,
2017 "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
2020 /* Element and structure load/store. */
2021 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2022 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
2023 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2024 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
2025 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2026 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
2027 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2028 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
2029 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2030 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
2031 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2032 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2033 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2034 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2035 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2036 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2037 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2038 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
2039 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2040 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2041 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2042 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2043 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2044 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2045 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2046 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
2047 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2048 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
2049 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2050 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
2051 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2052 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
2053 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2054 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
2055 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2056 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
2057 {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
),
2058 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
2060 {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
2063 /* mve opcode table. */
2065 /* print_insn_mve recognizes the following format control codes:
2069 %a print '+' or '-' or imm offset in vldr[bhwd] and
2071 %c print condition code
2072 %d print addr mode of MVE vldr[bhw] and vstr[bhw]
2073 %u print 'U' (unsigned) or 'S' for various mve instructions
2074 %i print MVE predicate(s) for vpt and vpst
2075 %j print a 5-bit immediate from hw2[14:12,7:6]
2076 %k print 48 if the 7th position bit is set else print 64.
2077 %m print rounding mode for vcvt and vrint
2078 %n print vector comparison code for predicated instruction
2079 %s print size for various vcvt instructions
2080 %v print vector predicate for instruction in predicated
2082 %o print offset scaled for vldr[hwd] and vstr[hwd]
2083 %w print writeback mode for MVE v{st,ld}[24]
2084 %B print v{st,ld}[24] any one operands
2085 %E print vmov, vmvn, vorr, vbic encoded constant
2086 %N print generic index for vmov
2087 %T print bottom ('b') or top ('t') of source register
2088 %X print exchange field in vmla* instructions
2090 %<bitfield>r print as an ARM register
2091 %<bitfield>d print the bitfield in decimal
2092 %<bitfield>A print accumulate or not
2093 %<bitfield>c print bitfield as a condition code
2094 %<bitfield>C print bitfield as an inverted condition code
2095 %<bitfield>Q print as a MVE Q register
2096 %<bitfield>F print as a MVE S register
2097 %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
2100 %<bitfield>S as %<>r but r15 or r13 is UNPREDICTABLE
2101 %<bitfield>s print size for vector predicate & non VMOV instructions
2102 %<bitfield>I print carry flag or not
2103 %<bitfield>i print immediate for vstr/vldr reg +/- imm
2104 %<bitfield>h print high half of 64-bit destination reg
2105 %<bitfield>k print immediate for vector conversion instruction
2106 %<bitfield>l print low half of 64-bit destination reg
2107 %<bitfield>o print rotate value for vcmul
2108 %<bitfield>u print immediate value for vddup/vdwdup
2109 %<bitfield>x print the bitfield in hex.
2112 static const struct mopcode32 mve_opcodes
[] =
2116 {ARM_FEATURE_COPROC (FPU_MVE
),
2118 0xfe310f4d, 0xffbf1fff,
2122 /* Floating point VPT T1. */
2123 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2125 0xee310f00, 0xefb10f50,
2126 "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
2127 /* Floating point VPT T2. */
2128 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2130 0xee310f40, 0xefb10f50,
2131 "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
2133 /* Vector VPT T1. */
2134 {ARM_FEATURE_COPROC (FPU_MVE
),
2136 0xfe010f00, 0xff811f51,
2137 "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2138 /* Vector VPT T2. */
2139 {ARM_FEATURE_COPROC (FPU_MVE
),
2141 0xfe010f01, 0xff811f51,
2142 "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2143 /* Vector VPT T3. */
2144 {ARM_FEATURE_COPROC (FPU_MVE
),
2146 0xfe011f00, 0xff811f50,
2147 "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2148 /* Vector VPT T4. */
2149 {ARM_FEATURE_COPROC (FPU_MVE
),
2151 0xfe010f40, 0xff811f70,
2152 "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
2153 /* Vector VPT T5. */
2154 {ARM_FEATURE_COPROC (FPU_MVE
),
2156 0xfe010f60, 0xff811f70,
2157 "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
2158 /* Vector VPT T6. */
2159 {ARM_FEATURE_COPROC (FPU_MVE
),
2161 0xfe011f40, 0xff811f50,
2162 "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
2164 /* Vector VBIC immediate. */
2165 {ARM_FEATURE_COPROC (FPU_MVE
),
2167 0xef800070, 0xefb81070,
2168 "vbic%v.i%8-11s\t%13-15,22Q, %E"},
2170 /* Vector VBIC register. */
2171 {ARM_FEATURE_COPROC (FPU_MVE
),
2173 0xef100150, 0xffb11f51,
2174 "vbic%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2177 {ARM_FEATURE_COPROC (FPU_MVE
),
2179 0xee800f01, 0xefc10f51,
2180 "vabav%v.%u%20-21s\t%12-15r, %17-19,7Q, %1-3,5Q"},
2182 /* Vector VABD floating point. */
2183 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2185 0xff200d40, 0xffa11f51,
2186 "vabd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2189 {ARM_FEATURE_COPROC (FPU_MVE
),
2191 0xef000740, 0xef811f51,
2192 "vabd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2194 /* Vector VABS floating point. */
2195 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2197 0xFFB10740, 0xFFB31FD1,
2198 "vabs%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2200 {ARM_FEATURE_COPROC (FPU_MVE
),
2202 0xffb10340, 0xffb31fd1,
2203 "vabs%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2205 /* Vector VADD floating point T1. */
2206 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2208 0xef000d40, 0xffa11f51,
2209 "vadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2210 /* Vector VADD floating point T2. */
2211 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2213 0xee300f40, 0xefb11f70,
2214 "vadd%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2215 /* Vector VADD T1. */
2216 {ARM_FEATURE_COPROC (FPU_MVE
),
2218 0xef000840, 0xff811f51,
2219 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2220 /* Vector VADD T2. */
2221 {ARM_FEATURE_COPROC (FPU_MVE
),
2223 0xee010f40, 0xff811f70,
2224 "vadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2226 /* Vector VADDLV. */
2227 {ARM_FEATURE_COPROC (FPU_MVE
),
2229 0xee890f00, 0xef8f1fd1,
2230 "vaddlv%5A%v.%u32\t%13-15l, %20-22h, %1-3Q"},
2233 {ARM_FEATURE_COPROC (FPU_MVE
),
2235 0xeef10f00, 0xeff31fd1,
2236 "vaddv%5A%v.%u%18-19s\t%13-15l, %1-3Q"},
2239 {ARM_FEATURE_COPROC (FPU_MVE
),
2241 0xee300f00, 0xffb10f51,
2242 "vadc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2245 {ARM_FEATURE_COPROC (FPU_MVE
),
2247 0xef000150, 0xffb11f51,
2248 "vand%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2250 /* Vector VBRSR register. */
2251 {ARM_FEATURE_COPROC (FPU_MVE
),
2253 0xfe011e60, 0xff811f70,
2254 "vbrsr%v.%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2256 /* Vector VCADD floating point. */
2257 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2259 0xfc800840, 0xfea11f51,
2260 "vcadd%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%24o"},
2263 {ARM_FEATURE_COPROC (FPU_MVE
),
2265 0xfe000f00, 0xff810f51,
2266 "vcadd%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2269 {ARM_FEATURE_COPROC (FPU_MVE
),
2271 0xffb00440, 0xffb31fd1,
2272 "vcls%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2275 {ARM_FEATURE_COPROC (FPU_MVE
),
2277 0xffb004c0, 0xffb31fd1,
2278 "vclz%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2281 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2283 0xfc200840, 0xfe211f51,
2284 "vcmla%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%23-24o"},
2286 /* Vector VCMP floating point T1. */
2287 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2289 0xee310f00, 0xeff1ef50,
2290 "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
2292 /* Vector VCMP floating point T2. */
2293 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2295 0xee310f40, 0xeff1ef50,
2296 "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
2298 /* Vector VCMP T1. */
2299 {ARM_FEATURE_COPROC (FPU_MVE
),
2301 0xfe010f00, 0xffc1ff51,
2302 "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
2303 /* Vector VCMP T2. */
2304 {ARM_FEATURE_COPROC (FPU_MVE
),
2306 0xfe010f01, 0xffc1ff51,
2307 "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
2308 /* Vector VCMP T3. */
2309 {ARM_FEATURE_COPROC (FPU_MVE
),
2311 0xfe011f00, 0xffc1ff50,
2312 "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
2313 /* Vector VCMP T4. */
2314 {ARM_FEATURE_COPROC (FPU_MVE
),
2316 0xfe010f40, 0xffc1ff70,
2317 "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
2318 /* Vector VCMP T5. */
2319 {ARM_FEATURE_COPROC (FPU_MVE
),
2321 0xfe010f60, 0xffc1ff70,
2322 "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
2323 /* Vector VCMP T6. */
2324 {ARM_FEATURE_COPROC (FPU_MVE
),
2326 0xfe011f40, 0xffc1ff50,
2327 "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
2330 {ARM_FEATURE_COPROC (FPU_MVE
),
2332 0xeea00b10, 0xffb10f5f,
2333 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2336 {ARM_FEATURE_COPROC (FPU_MVE
),
2338 0xff000150, 0xffd11f51,
2339 "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2341 /* Vector VFMA, vector * scalar. */
2342 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2344 0xee310e40, 0xefb11f70,
2345 "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2347 /* Vector VFMA floating point. */
2348 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2350 0xef000c50, 0xffa11f51,
2351 "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2353 /* Vector VFMS floating point. */
2354 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2356 0xef200c50, 0xffa11f51,
2357 "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2359 /* Vector VFMAS, vector * scalar. */
2360 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2361 MVE_VFMAS_FP_SCALAR
,
2362 0xee311e40, 0xefb11f70,
2363 "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2365 /* Vector VHADD T1. */
2366 {ARM_FEATURE_COPROC (FPU_MVE
),
2368 0xef000040, 0xef811f51,
2369 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2371 /* Vector VHADD T2. */
2372 {ARM_FEATURE_COPROC (FPU_MVE
),
2374 0xee000f40, 0xef811f70,
2375 "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2377 /* Vector VHSUB T1. */
2378 {ARM_FEATURE_COPROC (FPU_MVE
),
2380 0xef000240, 0xef811f51,
2381 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2383 /* Vector VHSUB T2. */
2384 {ARM_FEATURE_COPROC (FPU_MVE
),
2386 0xee001f40, 0xef811f70,
2387 "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2390 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2392 0xee300e00, 0xefb10f50,
2393 "vcmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%0,12o"},
2396 {ARM_FEATURE_COPROC (FPU_MVE
),
2398 0xf000e801, 0xffc0ffff,
2399 "vctp%v.%20-21s\t%16-19r"},
2402 {ARM_FEATURE_COPROC (FPU_MVE
),
2404 0xeea00b10, 0xffb10f5f,
2405 "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
2407 /* Vector VRHADD. */
2408 {ARM_FEATURE_COPROC (FPU_MVE
),
2410 0xef000140, 0xef811f51,
2411 "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2414 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2415 MVE_VCVT_FP_FIX_VEC
,
2416 0xef800c50, 0xef801cd1,
2417 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q, #%16-21k"},
2420 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2421 MVE_VCVT_BETWEEN_FP_INT
,
2422 0xffb30640, 0xffb31e51,
2423 "vcvt%v.%s\t%13-15,22Q, %1-3,5Q"},
2425 /* Vector VCVT between single and half-precision float, bottom half. */
2426 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2427 MVE_VCVT_FP_HALF_FP
,
2428 0xee3f0e01, 0xefbf1fd1,
2429 "vcvtb%v.%s\t%13-15,22Q, %1-3,5Q"},
2431 /* Vector VCVT between single and half-precision float, top half. */
2432 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2433 MVE_VCVT_FP_HALF_FP
,
2434 0xee3f1e01, 0xefbf1fd1,
2435 "vcvtt%v.%s\t%13-15,22Q, %1-3,5Q"},
2438 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2439 MVE_VCVT_FROM_FP_TO_INT
,
2440 0xffb30040, 0xffb31c51,
2441 "vcvt%m%v.%s\t%13-15,22Q, %1-3,5Q"},
2444 {ARM_FEATURE_COPROC (FPU_MVE
),
2446 0xee011f6e, 0xff811f7e,
2447 "vddup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2449 /* Vector VDWDUP. */
2450 {ARM_FEATURE_COPROC (FPU_MVE
),
2452 0xee011f60, 0xff811f70,
2453 "vdwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2455 /* Vector VHCADD. */
2456 {ARM_FEATURE_COPROC (FPU_MVE
),
2458 0xee000f00, 0xff810f51,
2459 "vhcadd%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q, #%12o"},
2461 /* Vector VIWDUP. */
2462 {ARM_FEATURE_COPROC (FPU_MVE
),
2464 0xee010f60, 0xff811f70,
2465 "viwdup%v.u%20-21s\t%13-15,22Q, %17-19l, %1-3h, #%0,7u"},
2468 {ARM_FEATURE_COPROC (FPU_MVE
),
2470 0xee010f6e, 0xff811f7e,
2471 "vidup%v.u%20-21s\t%13-15,22Q, %17-19l, #%0,7u"},
2474 {ARM_FEATURE_COPROC (FPU_MVE
),
2476 0xfc901e00, 0xff901e5f,
2477 "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
2480 {ARM_FEATURE_COPROC (FPU_MVE
),
2482 0xfc901e01, 0xff901e1f,
2483 "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
2485 /* Vector VLDRB gather load. */
2486 {ARM_FEATURE_COPROC (FPU_MVE
),
2487 MVE_VLDRB_GATHER_T1
,
2488 0xec900e00, 0xefb01e50,
2489 "vldrb%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
2491 /* Vector VLDRH gather load. */
2492 {ARM_FEATURE_COPROC (FPU_MVE
),
2493 MVE_VLDRH_GATHER_T2
,
2494 0xec900e10, 0xefb01e50,
2495 "vldrh%v.%u%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2497 /* Vector VLDRW gather load. */
2498 {ARM_FEATURE_COPROC (FPU_MVE
),
2499 MVE_VLDRW_GATHER_T3
,
2500 0xfc900f40, 0xffb01fd0,
2501 "vldrw%v.u32\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2503 /* Vector VLDRD gather load. */
2504 {ARM_FEATURE_COPROC (FPU_MVE
),
2505 MVE_VLDRD_GATHER_T4
,
2506 0xec900fd0, 0xefb01fd0,
2507 "vldrd%v.u64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
2509 /* Vector VLDRW gather load. */
2510 {ARM_FEATURE_COPROC (FPU_MVE
),
2511 MVE_VLDRW_GATHER_T5
,
2512 0xfd101e00, 0xff111f00,
2513 "vldrw%v.u32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2515 /* Vector VLDRD gather load, variant T6. */
2516 {ARM_FEATURE_COPROC (FPU_MVE
),
2517 MVE_VLDRD_GATHER_T6
,
2518 0xfd101f00, 0xff111f00,
2519 "vldrd%v.u64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
2522 {ARM_FEATURE_COPROC (FPU_MVE
),
2524 0xec100e00, 0xee581e00,
2525 "vldrb%v.%u%7-8s\t%13-15Q, %d"},
2528 {ARM_FEATURE_COPROC (FPU_MVE
),
2530 0xec180e00, 0xee581e00,
2531 "vldrh%v.%u%7-8s\t%13-15Q, %d"},
2533 /* Vector VLDRB unsigned, variant T5. */
2534 {ARM_FEATURE_COPROC (FPU_MVE
),
2536 0xec101e00, 0xfe101f80,
2537 "vldrb%v.u8\t%13-15,22Q, %d"},
2539 /* Vector VLDRH unsigned, variant T6. */
2540 {ARM_FEATURE_COPROC (FPU_MVE
),
2542 0xec101e80, 0xfe101f80,
2543 "vldrh%v.u16\t%13-15,22Q, %d"},
2545 /* Vector VLDRW unsigned, variant T7. */
2546 {ARM_FEATURE_COPROC (FPU_MVE
),
2548 0xec101f00, 0xfe101f80,
2549 "vldrw%v.u32\t%13-15,22Q, %d"},
2552 {ARM_FEATURE_COPROC (FPU_MVE
),
2554 0xef000640, 0xef811f51,
2555 "vmax%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2558 {ARM_FEATURE_COPROC (FPU_MVE
),
2560 0xee330e81, 0xffb31fd1,
2561 "vmaxa%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2563 /* Vector VMAXNM floating point. */
2564 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2566 0xff000f50, 0xffa11f51,
2567 "vmaxnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2569 /* Vector VMAXNMA floating point. */
2570 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2572 0xee3f0e81, 0xefbf1fd1,
2573 "vmaxnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2575 /* Vector VMAXNMV floating point. */
2576 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2578 0xeeee0f00, 0xefff0fd1,
2579 "vmaxnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2581 /* Vector VMAXNMAV floating point. */
2582 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2584 0xeeec0f00, 0xefff0fd1,
2585 "vmaxnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2588 {ARM_FEATURE_COPROC (FPU_MVE
),
2590 0xeee20f00, 0xeff30fd1,
2591 "vmaxv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2593 /* Vector VMAXAV. */
2594 {ARM_FEATURE_COPROC (FPU_MVE
),
2596 0xeee00f00, 0xfff30fd1,
2597 "vmaxav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2600 {ARM_FEATURE_COPROC (FPU_MVE
),
2602 0xef000650, 0xef811f51,
2603 "vmin%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2606 {ARM_FEATURE_COPROC (FPU_MVE
),
2608 0xee331e81, 0xffb31fd1,
2609 "vmina%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2611 /* Vector VMINNM floating point. */
2612 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2614 0xff200f50, 0xffa11f51,
2615 "vminnm%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2617 /* Vector VMINNMA floating point. */
2618 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2620 0xee3f1e81, 0xefbf1fd1,
2621 "vminnma%v.f%28s\t%13-15,22Q, %1-3,5Q"},
2623 /* Vector VMINNMV floating point. */
2624 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2626 0xeeee0f80, 0xefff0fd1,
2627 "vminnmv%v.f%28s\t%12-15r, %1-3,5Q"},
2629 /* Vector VMINNMAV floating point. */
2630 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2632 0xeeec0f80, 0xefff0fd1,
2633 "vminnmav%v.f%28s\t%12-15r, %1-3,5Q"},
2636 {ARM_FEATURE_COPROC (FPU_MVE
),
2638 0xeee20f80, 0xeff30fd1,
2639 "vminv%v.%u%18-19s\t%12-15r, %1-3,5Q"},
2641 /* Vector VMINAV. */
2642 {ARM_FEATURE_COPROC (FPU_MVE
),
2644 0xeee00f80, 0xfff30fd1,
2645 "vminav%v.s%18-19s\t%12-15r, %1-3,5Q"},
2648 {ARM_FEATURE_COPROC (FPU_MVE
),
2650 0xee010e40, 0xef811f70,
2651 "vmla%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2653 /* Vector VMLALDAV. Note must appear before VMLADAV due to instruction
2655 {ARM_FEATURE_COPROC (FPU_MVE
),
2657 0xee801e00, 0xef801f51,
2658 "vmlaldav%5Ax%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2660 {ARM_FEATURE_COPROC (FPU_MVE
),
2662 0xee800e00, 0xef801f51,
2663 "vmlalv%5A%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2665 /* Vector VMLAV T1 variant, same as VMLADAV but with X == 0. */
2666 {ARM_FEATURE_COPROC (FPU_MVE
),
2668 0xeef00e00, 0xeff01f51,
2669 "vmlav%5A%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2671 /* Vector VMLAV T2 variant, same as VMLADAV but with X == 0. */
2672 {ARM_FEATURE_COPROC (FPU_MVE
),
2674 0xeef00f00, 0xeff11f51,
2675 "vmlav%5A%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2677 /* Vector VMLADAV T1 variant. */
2678 {ARM_FEATURE_COPROC (FPU_MVE
),
2680 0xeef01e00, 0xeff01f51,
2681 "vmladav%5Ax%v.%u%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2683 /* Vector VMLADAV T2 variant. */
2684 {ARM_FEATURE_COPROC (FPU_MVE
),
2686 0xeef01f00, 0xeff11f51,
2687 "vmladav%5Ax%v.%u8\t%13-15l, %17-19,7Q, %1-3Q"},
2690 {ARM_FEATURE_COPROC (FPU_MVE
),
2692 0xee011e40, 0xef811f70,
2693 "vmlas%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2695 /* Vector VRMLSLDAVH. Note must appear before VMLSDAV due to instruction
2697 {ARM_FEATURE_COPROC (FPU_MVE
),
2699 0xfe800e01, 0xff810f51,
2700 "vrmlsldavh%5A%X%v.s32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2702 /* Vector VMLSLDAV. Note must appear before VMLSDAV due to instruction
2704 {ARM_FEATURE_COPROC (FPU_MVE
),
2706 0xee800e01, 0xff800f51,
2707 "vmlsldav%5A%X%v.%u%16s\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
2709 /* Vector VMLSDAV T1 Variant. */
2710 {ARM_FEATURE_COPROC (FPU_MVE
),
2712 0xeef00e01, 0xfff00f51,
2713 "vmlsdav%5A%X%v.s%16s\t%13-15l, %17-19,7Q, %1-3Q"},
2715 /* Vector VMLSDAV T2 Variant. */
2716 {ARM_FEATURE_COPROC (FPU_MVE
),
2718 0xfef00e01, 0xfff10f51,
2719 "vmlsdav%5A%X%v.s8\t%13-15l, %17-19,7Q, %1-3Q"},
2721 /* Vector VMOV between gpr and half precision register, op == 0. */
2722 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2724 0xee000910, 0xfff00f7f,
2725 "vmov.f16\t%7,16-19F, %12-15r"},
2727 /* Vector VMOV between gpr and half precision register, op == 1. */
2728 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2730 0xee100910, 0xfff00f7f,
2731 "vmov.f16\t%12-15r, %7,16-19F"},
2733 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2734 MVE_VMOV_GP_TO_VEC_LANE
,
2735 0xee000b10, 0xff900f1f,
2736 "vmov%c.%5-6,21-22s\t%17-19,7Q[%N], %12-15r"},
2738 /* Vector VORR immediate to vector.
2739 NOTE: MVE_VORR_IMM must appear in the table
2740 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2741 {ARM_FEATURE_COPROC (FPU_MVE
),
2743 0xef800050, 0xefb810f0,
2744 "vorr%v.i%8-11s\t%13-15,22Q, %E"},
2746 /* Vector VQSHL T2 Variant.
2747 NOTE: MVE_VQSHL_T2 must appear in the table before
2748 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2749 {ARM_FEATURE_COPROC (FPU_MVE
),
2751 0xef800750, 0xef801fd1,
2752 "vqshl%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2754 /* Vector VQSHLU T3 Variant
2755 NOTE: MVE_VQSHL_T2 must appear in the table before
2756 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2758 {ARM_FEATURE_COPROC (FPU_MVE
),
2760 0xff800650, 0xff801fd1,
2761 "vqshlu%v.s%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2764 NOTE: MVE_VRSHR must appear in the table before
2765 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2766 {ARM_FEATURE_COPROC (FPU_MVE
),
2768 0xef800250, 0xef801fd1,
2769 "vrshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2772 NOTE: MVE_VSHL must appear in the table before
2773 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2774 {ARM_FEATURE_COPROC (FPU_MVE
),
2776 0xef800550, 0xff801fd1,
2777 "vshl%v.i%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2780 NOTE: MVE_VSHR must appear in the table before
2781 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2782 {ARM_FEATURE_COPROC (FPU_MVE
),
2784 0xef800050, 0xef801fd1,
2785 "vshr%v.%u%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2788 NOTE: MVE_VSLI must appear in the table before
2789 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2790 {ARM_FEATURE_COPROC (FPU_MVE
),
2792 0xff800550, 0xff801fd1,
2793 "vsli%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2796 NOTE: MVE_VSRI must appear in the table before
2797 before MVE_VMOV_IMM_TO_VEC due to opcode aliasing. */
2798 {ARM_FEATURE_COPROC (FPU_MVE
),
2800 0xff800450, 0xff801fd1,
2801 "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2803 /* Vector VMOV immediate to vector,
2804 cmode == 11x1 -> VMVN which is UNDEFINED
2805 for such a cmode. */
2806 {ARM_FEATURE_COPROC (FPU_MVE
),
2807 MVE_VMVN_IMM
, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION
},
2809 /* Vector VMOV immediate to vector. */
2810 {ARM_FEATURE_COPROC (FPU_MVE
),
2811 MVE_VMOV_IMM_TO_VEC
,
2812 0xef800050, 0xefb810d0,
2813 "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
2815 /* Vector VMOV two 32-bit lanes to two gprs, idx = 0. */
2816 {ARM_FEATURE_COPROC (FPU_MVE
),
2817 MVE_VMOV2_VEC_LANE_TO_GP
,
2818 0xec000f00, 0xffb01ff0,
2819 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[2], %13-15,22Q[0]"},
2821 /* Vector VMOV two 32-bit lanes to two gprs, idx = 1. */
2822 {ARM_FEATURE_COPROC (FPU_MVE
),
2823 MVE_VMOV2_VEC_LANE_TO_GP
,
2824 0xec000f10, 0xffb01ff0,
2825 "vmov%c\t%0-3r, %16-19r, %13-15,22Q[3], %13-15,22Q[1]"},
2827 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 0. */
2828 {ARM_FEATURE_COPROC (FPU_MVE
),
2829 MVE_VMOV2_GP_TO_VEC_LANE
,
2830 0xec100f00, 0xffb01ff0,
2831 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2833 /* Vector VMOV Two gprs to two 32-bit lanes, idx = 1. */
2834 {ARM_FEATURE_COPROC (FPU_MVE
),
2835 MVE_VMOV2_GP_TO_VEC_LANE
,
2836 0xec100f10, 0xffb01ff0,
2837 "vmov%c\t%13-15,22Q[2], %13-15,22Q[0], %0-3r, %16-19r"},
2839 /* Vector VMOV Vector lane to gpr. */
2840 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2841 MVE_VMOV_VEC_LANE_TO_GP
,
2842 0xee100b10, 0xff100f1f,
2843 "vmov%c.%u%5-6,21-22s\t%12-15r, %17-19,7Q[%N]"},
2845 /* Vector VSHLL T1 Variant. Note: VSHLL T1 must appear before MVE_VMOVL due
2846 to instruction opcode aliasing. */
2847 {ARM_FEATURE_COPROC (FPU_MVE
),
2849 0xeea00f40, 0xefa00fd1,
2850 "vshll%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
2852 /* Vector VMOVL long. */
2853 {ARM_FEATURE_COPROC (FPU_MVE
),
2855 0xeea00f40, 0xefa70fd1,
2856 "vmovl%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q"},
2858 /* Vector VMOV and narrow. */
2859 {ARM_FEATURE_COPROC (FPU_MVE
),
2861 0xfe310e81, 0xffb30fd1,
2862 "vmovn%T%v.i%18-19s\t%13-15,22Q, %1-3,5Q"},
2864 /* Floating point move extract. */
2865 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2867 0xfeb00a40, 0xffbf0fd0,
2868 "vmovx.f16\t%22,12-15F, %5,0-3F"},
2870 /* Vector VMUL floating-point T1 variant. */
2871 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2873 0xff000d50, 0xffa11f51,
2874 "vmul%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2876 /* Vector VMUL floating-point T2 variant. */
2877 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2879 0xee310e60, 0xefb11f70,
2880 "vmul%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2882 /* Vector VMUL T1 variant. */
2883 {ARM_FEATURE_COPROC (FPU_MVE
),
2885 0xef000950, 0xff811f51,
2886 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2888 /* Vector VMUL T2 variant. */
2889 {ARM_FEATURE_COPROC (FPU_MVE
),
2891 0xee011e60, 0xff811f70,
2892 "vmul%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
2895 {ARM_FEATURE_COPROC (FPU_MVE
),
2897 0xee010e01, 0xef811f51,
2898 "vmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2900 /* Vector VRMULH. */
2901 {ARM_FEATURE_COPROC (FPU_MVE
),
2903 0xee011e01, 0xef811f51,
2904 "vrmulh%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2906 /* Vector VMULL integer. */
2907 {ARM_FEATURE_COPROC (FPU_MVE
),
2909 0xee010e00, 0xef810f51,
2910 "vmull%T%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2912 /* Vector VMULL polynomial. */
2913 {ARM_FEATURE_COPROC (FPU_MVE
),
2915 0xee310e00, 0xefb10f51,
2916 "vmull%T%v.%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2918 /* Vector VMVN immediate to vector. */
2919 {ARM_FEATURE_COPROC (FPU_MVE
),
2921 0xef800070, 0xefb810f0,
2922 "vmvn%v.i%8-11s\t%13-15,22Q, %E"},
2924 /* Vector VMVN register. */
2925 {ARM_FEATURE_COPROC (FPU_MVE
),
2927 0xffb005c0, 0xffbf1fd1,
2928 "vmvn%v\t%13-15,22Q, %1-3,5Q"},
2930 /* Vector VNEG floating point. */
2931 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
2933 0xffb107c0, 0xffb31fd1,
2934 "vneg%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
2937 {ARM_FEATURE_COPROC (FPU_MVE
),
2939 0xffb103c0, 0xffb31fd1,
2940 "vneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
2942 /* Vector VORN, vector bitwise or not. */
2943 {ARM_FEATURE_COPROC (FPU_MVE
),
2945 0xef300150, 0xffb11f51,
2946 "vorn%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2948 /* Vector VORR register. */
2949 {ARM_FEATURE_COPROC (FPU_MVE
),
2951 0xef200150, 0xffb11f51,
2952 "vorr%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2954 /* Vector VMOV, vector to vector move. While decoding MVE_VORR_REG if
2955 "Qm==Qn", VORR should replaced by its alias VMOV. For that to happen
2956 MVE_VMOV_VEC_TO_VEC need to placed after MVE_VORR_REG in this mve_opcodes
2959 {ARM_FEATURE_COPROC (FPU_MVE
),
2960 MVE_VMOV_VEC_TO_VEC
,
2961 0xef200150, 0xffb11f51,
2962 "vmov%v\t%13-15,22Q, %17-19,7Q"},
2964 /* Vector VQDMULL T1 variant. */
2965 {ARM_FEATURE_COPROC (FPU_MVE
),
2967 0xee300f01, 0xefb10f51,
2968 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2971 {ARM_FEATURE_COPROC (FPU_MVE
),
2973 0xfe310f4d, 0xffffffff,
2977 {ARM_FEATURE_COPROC (FPU_MVE
),
2979 0xfe310f01, 0xffb11f51,
2980 "vpsel%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2983 {ARM_FEATURE_COPROC (FPU_MVE
),
2985 0xffb00740, 0xffb31fd1,
2986 "vqabs%v.s%18-19s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2988 /* Vector VQADD T1 variant. */
2989 {ARM_FEATURE_COPROC (FPU_MVE
),
2991 0xef000050, 0xef811f51,
2992 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
2994 /* Vector VQADD T2 variant. */
2995 {ARM_FEATURE_COPROC (FPU_MVE
),
2997 0xee000f60, 0xef811f70,
2998 "vqadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3000 /* Vector VQDMULL T2 variant. */
3001 {ARM_FEATURE_COPROC (FPU_MVE
),
3003 0xee300f60, 0xefb10f70,
3004 "vqdmull%T%v.s%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3006 /* Vector VQMOVN. */
3007 {ARM_FEATURE_COPROC (FPU_MVE
),
3009 0xee330e01, 0xefb30fd1,
3010 "vqmovn%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q"},
3012 /* Vector VQMOVUN. */
3013 {ARM_FEATURE_COPROC (FPU_MVE
),
3015 0xee310e81, 0xffb30fd1,
3016 "vqmovun%T%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3018 /* Vector VQDMLADH. */
3019 {ARM_FEATURE_COPROC (FPU_MVE
),
3021 0xee000e00, 0xff810f51,
3022 "vqdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3024 /* Vector VQRDMLADH. */
3025 {ARM_FEATURE_COPROC (FPU_MVE
),
3027 0xee000e01, 0xff810f51,
3028 "vqrdmladh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3030 /* Vector VQDMLAH. */
3031 {ARM_FEATURE_COPROC (FPU_MVE
),
3033 0xee000e60, 0xff811f70,
3034 "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3036 /* Vector VQRDMLAH. */
3037 {ARM_FEATURE_COPROC (FPU_MVE
),
3039 0xee000e40, 0xff811f70,
3040 "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3042 /* Vector VQDMLASH. */
3043 {ARM_FEATURE_COPROC (FPU_MVE
),
3045 0xee001e60, 0xff811f70,
3046 "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3048 /* Vector VQRDMLASH. */
3049 {ARM_FEATURE_COPROC (FPU_MVE
),
3051 0xee001e40, 0xff811f70,
3052 "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3054 /* Vector VQDMLSDH. */
3055 {ARM_FEATURE_COPROC (FPU_MVE
),
3057 0xfe000e00, 0xff810f51,
3058 "vqdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3060 /* Vector VQRDMLSDH. */
3061 {ARM_FEATURE_COPROC (FPU_MVE
),
3063 0xfe000e01, 0xff810f51,
3064 "vqrdmlsdh%X%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3066 /* Vector VQDMULH T1 variant. */
3067 {ARM_FEATURE_COPROC (FPU_MVE
),
3069 0xef000b40, 0xff811f51,
3070 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3072 /* Vector VQRDMULH T2 variant. */
3073 {ARM_FEATURE_COPROC (FPU_MVE
),
3075 0xff000b40, 0xff811f51,
3076 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3078 /* Vector VQDMULH T3 variant. */
3079 {ARM_FEATURE_COPROC (FPU_MVE
),
3081 0xee010e60, 0xff811f70,
3082 "vqdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3084 /* Vector VQRDMULH T4 variant. */
3085 {ARM_FEATURE_COPROC (FPU_MVE
),
3087 0xfe010e60, 0xff811f70,
3088 "vqrdmulh%v.s%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3091 {ARM_FEATURE_COPROC (FPU_MVE
),
3093 0xffb007c0, 0xffb31fd1,
3094 "vqneg%v.s%18-19s\t%13-15,22Q, %1-3,5Q"},
3096 /* Vector VQRSHL T1 variant. */
3097 {ARM_FEATURE_COPROC (FPU_MVE
),
3099 0xef000550, 0xef811f51,
3100 "vqrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3102 /* Vector VQRSHL T2 variant. */
3103 {ARM_FEATURE_COPROC (FPU_MVE
),
3105 0xee331ee0, 0xefb31ff0,
3106 "vqrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3108 /* Vector VQRSHRN. */
3109 {ARM_FEATURE_COPROC (FPU_MVE
),
3111 0xee800f41, 0xefa00fd1,
3112 "vqrshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3114 /* Vector VQRSHRUN. */
3115 {ARM_FEATURE_COPROC (FPU_MVE
),
3117 0xfe800fc0, 0xffa00fd1,
3118 "vqrshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3120 /* Vector VQSHL T1 Variant. */
3121 {ARM_FEATURE_COPROC (FPU_MVE
),
3123 0xee311ee0, 0xefb31ff0,
3124 "vqshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3126 /* Vector VQSHL T4 Variant. */
3127 {ARM_FEATURE_COPROC (FPU_MVE
),
3129 0xef000450, 0xef811f51,
3130 "vqshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3132 /* Vector VQSHRN. */
3133 {ARM_FEATURE_COPROC (FPU_MVE
),
3135 0xee800f40, 0xefa00fd1,
3136 "vqshrn%T%v.%u%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3138 /* Vector VQSHRUN. */
3139 {ARM_FEATURE_COPROC (FPU_MVE
),
3141 0xee800fc0, 0xffa00fd1,
3142 "vqshrun%T%v.s%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3144 /* Vector VQSUB T1 Variant. */
3145 {ARM_FEATURE_COPROC (FPU_MVE
),
3147 0xef000250, 0xef811f51,
3148 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3150 /* Vector VQSUB T2 Variant. */
3151 {ARM_FEATURE_COPROC (FPU_MVE
),
3153 0xee001f60, 0xef811f70,
3154 "vqsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3156 /* Vector VREV16. */
3157 {ARM_FEATURE_COPROC (FPU_MVE
),
3159 0xffb00140, 0xffb31fd1,
3160 "vrev16%v.8\t%13-15,22Q, %1-3,5Q"},
3162 /* Vector VREV32. */
3163 {ARM_FEATURE_COPROC (FPU_MVE
),
3165 0xffb000c0, 0xffb31fd1,
3166 "vrev32%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3168 /* Vector VREV64. */
3169 {ARM_FEATURE_COPROC (FPU_MVE
),
3171 0xffb00040, 0xffb31fd1,
3172 "vrev64%v.%18-19s\t%13-15,22Q, %1-3,5Q"},
3174 /* Vector VRINT floating point. */
3175 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
3177 0xffb20440, 0xffb31c51,
3178 "vrint%m%v.f%18-19s\t%13-15,22Q, %1-3,5Q"},
3180 /* Vector VRMLALDAVH. */
3181 {ARM_FEATURE_COPROC (FPU_MVE
),
3183 0xee800f00, 0xef811f51,
3184 "vrmlalvh%5A%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3186 /* Vector VRMLALDAVH. */
3187 {ARM_FEATURE_COPROC (FPU_MVE
),
3189 0xee801f00, 0xef811f51,
3190 "vrmlaldavh%5Ax%v.%u32\t%13-15l, %20-22h, %17-19,7Q, %1-3Q"},
3192 /* Vector VRSHL T1 Variant. */
3193 {ARM_FEATURE_COPROC (FPU_MVE
),
3195 0xef000540, 0xef811f51,
3196 "vrshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3198 /* Vector VRSHL T2 Variant. */
3199 {ARM_FEATURE_COPROC (FPU_MVE
),
3201 0xee331e60, 0xefb31ff0,
3202 "vrshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3204 /* Vector VRSHRN. */
3205 {ARM_FEATURE_COPROC (FPU_MVE
),
3207 0xfe800fc1, 0xffa00fd1,
3208 "vrshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3211 {ARM_FEATURE_COPROC (FPU_MVE
),
3213 0xfe300f00, 0xffb10f51,
3214 "vsbc%12I%v.i32\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3216 /* Vector VSHL T2 Variant. */
3217 {ARM_FEATURE_COPROC (FPU_MVE
),
3219 0xee311e60, 0xefb31ff0,
3220 "vshl%v.%u%18-19s\t%13-15,22Q, %0-3r"},
3222 /* Vector VSHL T3 Variant. */
3223 {ARM_FEATURE_COPROC (FPU_MVE
),
3225 0xef000440, 0xef811f51,
3226 "vshl%v.%u%20-21s\t%13-15,22Q, %1-3,5Q, %17-19,7Q"},
3229 {ARM_FEATURE_COPROC (FPU_MVE
),
3231 0xeea00fc0, 0xffa01ff0,
3232 "vshlc%v\t%13-15,22Q, %0-3r, #%16-20d"},
3234 /* Vector VSHLL T2 Variant. */
3235 {ARM_FEATURE_COPROC (FPU_MVE
),
3237 0xee310e01, 0xefb30fd1,
3238 "vshll%T%v.%u%18-19s\t%13-15,22Q, %1-3,5Q, #%18-19d"},
3241 {ARM_FEATURE_COPROC (FPU_MVE
),
3243 0xee800fc1, 0xffa00fd1,
3244 "vshrn%T%v.i%19-20s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
3246 /* Vector VST2 no writeback. */
3247 {ARM_FEATURE_COPROC (FPU_MVE
),
3249 0xfc801e00, 0xffb01e5f,
3250 "vst2%5d.%7-8s\t%B, [%16-19r]"},
3252 /* Vector VST2 writeback. */
3253 {ARM_FEATURE_COPROC (FPU_MVE
),
3255 0xfca01e00, 0xffb01e5f,
3256 "vst2%5d.%7-8s\t%B, [%16-19r]!"},
3258 /* Vector VST4 no writeback. */
3259 {ARM_FEATURE_COPROC (FPU_MVE
),
3261 0xfc801e01, 0xffb01e1f,
3262 "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
3264 /* Vector VST4 writeback. */
3265 {ARM_FEATURE_COPROC (FPU_MVE
),
3267 0xfca01e01, 0xffb01e1f,
3268 "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
3270 /* Vector VSTRB scatter store, T1 variant. */
3271 {ARM_FEATURE_COPROC (FPU_MVE
),
3272 MVE_VSTRB_SCATTER_T1
,
3273 0xec800e00, 0xffb01e50,
3274 "vstrb%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q]"},
3276 /* Vector VSTRH scatter store, T2 variant. */
3277 {ARM_FEATURE_COPROC (FPU_MVE
),
3278 MVE_VSTRH_SCATTER_T2
,
3279 0xec800e10, 0xffb01e50,
3280 "vstrh%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3282 /* Vector VSTRW scatter store, T3 variant. */
3283 {ARM_FEATURE_COPROC (FPU_MVE
),
3284 MVE_VSTRW_SCATTER_T3
,
3285 0xec800e40, 0xffb01e50,
3286 "vstrw%v.%7-8s\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3288 /* Vector VSTRD scatter store, T4 variant. */
3289 {ARM_FEATURE_COPROC (FPU_MVE
),
3290 MVE_VSTRD_SCATTER_T4
,
3291 0xec800fd0, 0xffb01fd0,
3292 "vstrd%v.64\t%13-15,22Q, [%16-19r, %1-3,5Q%o]"},
3294 /* Vector VSTRW scatter store, T5 variant. */
3295 {ARM_FEATURE_COPROC (FPU_MVE
),
3296 MVE_VSTRW_SCATTER_T5
,
3297 0xfd001e00, 0xff111f00,
3298 "vstrw%v.32\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3300 /* Vector VSTRD scatter store, T6 variant. */
3301 {ARM_FEATURE_COPROC (FPU_MVE
),
3302 MVE_VSTRD_SCATTER_T6
,
3303 0xfd001f00, 0xff111f00,
3304 "vstrd%v.64\t%13-15,22Q, [%17-19,7Q, #%a%0-6i]%w"},
3307 {ARM_FEATURE_COPROC (FPU_MVE
),
3309 0xec000e00, 0xfe581e00,
3310 "vstrb%v.%7-8s\t%13-15Q, %d"},
3313 {ARM_FEATURE_COPROC (FPU_MVE
),
3315 0xec080e00, 0xfe581e00,
3316 "vstrh%v.%7-8s\t%13-15Q, %d"},
3318 /* Vector VSTRB variant T5. */
3319 {ARM_FEATURE_COPROC (FPU_MVE
),
3321 0xec001e00, 0xfe101f80,
3322 "vstrb%v.8\t%13-15,22Q, %d"},
3324 /* Vector VSTRH variant T6. */
3325 {ARM_FEATURE_COPROC (FPU_MVE
),
3327 0xec001e80, 0xfe101f80,
3328 "vstrh%v.16\t%13-15,22Q, %d"},
3330 /* Vector VSTRW variant T7. */
3331 {ARM_FEATURE_COPROC (FPU_MVE
),
3333 0xec001f00, 0xfe101f80,
3334 "vstrw%v.32\t%13-15,22Q, %d"},
3336 /* Vector VSUB floating point T1 variant. */
3337 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
3339 0xef200d40, 0xffa11f51,
3340 "vsub%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3342 /* Vector VSUB floating point T2 variant. */
3343 {ARM_FEATURE_COPROC (FPU_MVE_FP
),
3345 0xee301f40, 0xefb11f70,
3346 "vsub%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3348 /* Vector VSUB T1 variant. */
3349 {ARM_FEATURE_COPROC (FPU_MVE
),
3351 0xff000840, 0xff811f51,
3352 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
3354 /* Vector VSUB T2 variant. */
3355 {ARM_FEATURE_COPROC (FPU_MVE
),
3357 0xee011f40, 0xff811f70,
3358 "vsub%v.i%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
3360 {ARM_FEATURE_COPROC (FPU_MVE
),
3362 0xea50012f, 0xfff1813f,
3363 "asrl%c\t%17-19l, %9-11h, %j"},
3365 {ARM_FEATURE_COPROC (FPU_MVE
),
3367 0xea50012d, 0xfff101ff,
3368 "asrl%c\t%17-19l, %9-11h, %12-15S"},
3370 {ARM_FEATURE_COPROC (FPU_MVE
),
3372 0xea50010f, 0xfff1813f,
3373 "lsll%c\t%17-19l, %9-11h, %j"},
3375 {ARM_FEATURE_COPROC (FPU_MVE
),
3377 0xea50010d, 0xfff101ff,
3378 "lsll%c\t%17-19l, %9-11h, %12-15S"},
3380 {ARM_FEATURE_COPROC (FPU_MVE
),
3382 0xea50011f, 0xfff1813f,
3383 "lsrl%c\t%17-19l, %9-11h, %j"},
3385 {ARM_FEATURE_COPROC (FPU_MVE
),
3387 0xea51012d, 0xfff1017f,
3388 "sqrshrl%c\t%17-19l, %9-11h, %k, %12-15S"},
3390 {ARM_FEATURE_COPROC (FPU_MVE
),
3392 0xea500f2d, 0xfff00fff,
3393 "sqrshr%c\t%16-19S, %12-15S"},
3395 {ARM_FEATURE_COPROC (FPU_MVE
),
3397 0xea51013f, 0xfff1813f,
3398 "sqshll%c\t%17-19l, %9-11h, %j"},
3400 {ARM_FEATURE_COPROC (FPU_MVE
),
3402 0xea500f3f, 0xfff08f3f,
3403 "sqshl%c\t%16-19S, %j"},
3405 {ARM_FEATURE_COPROC (FPU_MVE
),
3407 0xea51012f, 0xfff1813f,
3408 "srshrl%c\t%17-19l, %9-11h, %j"},
3410 {ARM_FEATURE_COPROC (FPU_MVE
),
3412 0xea500f2f, 0xfff08f3f,
3413 "srshr%c\t%16-19S, %j"},
3415 {ARM_FEATURE_COPROC (FPU_MVE
),
3417 0xea51010d, 0xfff1017f,
3418 "uqrshll%c\t%17-19l, %9-11h, %k, %12-15S"},
3420 {ARM_FEATURE_COPROC (FPU_MVE
),
3422 0xea500f0d, 0xfff00fff,
3423 "uqrshl%c\t%16-19S, %12-15S"},
3425 {ARM_FEATURE_COPROC (FPU_MVE
),
3427 0xea51010f, 0xfff1813f,
3428 "uqshll%c\t%17-19l, %9-11h, %j"},
3430 {ARM_FEATURE_COPROC (FPU_MVE
),
3432 0xea500f0f, 0xfff08f3f,
3433 "uqshl%c\t%16-19S, %j"},
3435 {ARM_FEATURE_COPROC (FPU_MVE
),
3437 0xea51011f, 0xfff1813f,
3438 "urshrl%c\t%17-19l, %9-11h, %j"},
3440 {ARM_FEATURE_COPROC (FPU_MVE
),
3442 0xea500f1f, 0xfff08f3f,
3443 "urshr%c\t%16-19S, %j"},
3445 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3447 0xea509000, 0xfff0f000,
3448 "csinc\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3450 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3452 0xea50a000, 0xfff0f000,
3453 "csinv\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3455 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3457 0xea5f900f, 0xfffff00f,
3458 "cset\t%8-11S, %4-7C"},
3460 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3462 0xea5fa00f, 0xfffff00f,
3463 "csetm\t%8-11S, %4-7C"},
3465 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3467 0xea508000, 0xfff0f000,
3468 "csel\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3470 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3472 0xea50b000, 0xfff0f000,
3473 "csneg\t%8-11S, %16-19Z, %0-3Z, %4-7c"},
3475 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3477 0xea509000, 0xfff0f000,
3478 "cinc\t%8-11S, %16-19Z, %4-7C"},
3480 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3482 0xea50a000, 0xfff0f000,
3483 "cinv\t%8-11S, %16-19Z, %4-7C"},
3485 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
3487 0xea50b000, 0xfff0f000,
3488 "cneg\t%8-11S, %16-19Z, %4-7C"},
3490 {ARM_FEATURE_CORE_LOW (0),
3492 0x00000000, 0x00000000, 0}
3495 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3496 ordered: they must be searched linearly from the top to obtain a correct
3499 /* print_insn_arm recognizes the following format control codes:
3503 %a print address for ldr/str instruction
3504 %s print address for ldr/str halfword/signextend instruction
3505 %S like %s but allow UNPREDICTABLE addressing
3506 %b print branch destination
3507 %c print condition code (always bits 28-31)
3508 %m print register mask for ldm/stm instruction
3509 %o print operand2 (immediate or register + shift)
3510 %p print 'p' iff bits 12-15 are 15
3511 %t print 't' iff bit 21 set and bit 24 clear
3512 %B print arm BLX(1) destination
3513 %C print the PSR sub type.
3514 %U print barrier type.
3515 %P print address for pli instruction.
3517 %<bitfield>r print as an ARM register
3518 %<bitfield>T print as an ARM register + 1
3519 %<bitfield>R as %r but r15 is UNPREDICTABLE
3520 %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3521 %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3522 %<bitfield>d print the bitfield in decimal
3523 %<bitfield>W print the bitfield plus one in decimal
3524 %<bitfield>x print the bitfield in hex
3525 %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3527 %<bitfield>'c print specified char iff bitfield is all ones
3528 %<bitfield>`c print specified char iff bitfield is all zeroes
3529 %<bitfield>?ab... select from array of values in big endian order
3531 %e print arm SMI operand (bits 0..7,8..19).
3532 %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3533 %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3534 %R print the SPSR/CPSR or banked register of an MRS. */
3536 static const struct opcode32 arm_opcodes
[] =
3538 /* ARM instructions. */
3539 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3540 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3541 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3542 0xe7f000f0, 0xfff000f0, "udf\t#%e"},
3544 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
),
3545 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3546 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3547 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3548 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2
),
3549 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3550 {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
),
3551 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3552 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3553 0x00800090, 0x0fa000f0,
3554 "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3555 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
),
3556 0x00a00090, 0x0fa000f0,
3557 "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3559 /* V8.2 RAS extension instructions. */
3560 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
3561 0xe320f010, 0xffffffff, "esb"},
3563 /* V8 instructions. */
3564 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3565 0x0320f005, 0x0fffffff, "sevl"},
3566 /* Defined in V8 but is in NOP space so available to all arch. */
3567 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
3568 0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
3569 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
),
3570 0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
3571 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3572 0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
3573 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3574 0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
3575 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
3576 0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
3577 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3578 0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
3579 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3580 0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
3581 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3582 0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
3583 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3584 0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
3585 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3586 0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
3587 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3588 0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
3589 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3590 0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
3591 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3592 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
3593 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3594 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
3595 {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS
),
3596 0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
3597 /* CRC32 instructions. */
3598 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3599 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
3600 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3601 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
3602 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3603 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
3604 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3605 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
3606 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3607 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
3608 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
3609 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
3611 /* Privileged Access Never extension instructions. */
3612 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
3613 0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
3615 /* Virtualization Extension instructions. */
3616 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x0160006e, 0x0fffffff, "eret%c"},
3617 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3619 /* Integer Divide Extension instructions. */
3620 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3621 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3622 {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
3623 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3625 /* MP Extension instructions. */
3626 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf410f000, 0xfc70f000, "pldw\t%a"},
3628 /* Speculation Barriers. */
3629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xe320f014, 0xffffffff, "csdb"},
3630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff040, 0xffffffff, "ssbb"},
3631 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
), 0xf57ff044, 0xffffffff, "pssbb"},
3633 /* V7 instructions. */
3634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf450f000, 0xfd70f000, "pli\t%P"},
3635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
3637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
3638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3640 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf57ff060, 0xfffffff0, "isb\t%U"},
3641 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
3642 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
3644 /* ARM V6T2 instructions. */
3645 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3646 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3647 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3648 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3649 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3650 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3651 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3652 0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
3654 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3655 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION
},
3656 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3657 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3659 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3660 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3661 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
3662 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3664 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3665 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
3666 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3668 /* ARM Security extension instructions. */
3669 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
3670 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3672 /* ARM V6K instructions. */
3673 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3674 0xf57ff01f, 0xffffffff, "clrex"},
3675 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3676 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3677 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3678 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3679 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3680 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3681 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3682 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3683 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3684 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3685 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3686 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3688 /* ARMv8.5-A instructions. */
3689 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf57ff070, 0xffffffff, "sb"},
3691 /* ARM V6K NOP hints. */
3692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3693 0x0320f001, 0x0fffffff, "yield%c"},
3694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3695 0x0320f002, 0x0fffffff, "wfe%c"},
3696 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3697 0x0320f003, 0x0fffffff, "wfi%c"},
3698 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3699 0x0320f004, 0x0fffffff, "sev%c"},
3700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
3701 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3703 /* ARM V6 instructions. */
3704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3705 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3707 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3709 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3711 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3713 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3715 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3716 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3717 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3719 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3721 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3723 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3725 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3727 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3729 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3731 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3733 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3735 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3737 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3739 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3741 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3743 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3745 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3747 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3749 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3751 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3753 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3755 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3757 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3759 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3761 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3763 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3765 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3767 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3769 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3771 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3773 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3775 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3777 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3779 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3781 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3783 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3785 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3787 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3789 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3791 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3793 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3795 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3797 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3799 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3801 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3803 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3805 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3807 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3809 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3811 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3813 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3815 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3817 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3819 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3821 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3823 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3824 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3825 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3827 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3829 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3831 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3833 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3835 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3837 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3839 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3841 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3843 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3845 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3847 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3849 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3851 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3853 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3855 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3857 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3859 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3861 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3863 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3865 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3867 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3869 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3871 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3873 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3875 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3877 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3879 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3881 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3883 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3885 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3887 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3889 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3891 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3892 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3893 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3895 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3897 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3899 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3901 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3903 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3905 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3907 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3909 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3911 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3913 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3915 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3917 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3919 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3921 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3923 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3925 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3926 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3927 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3928 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3929 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3931 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3933 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3935 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3937 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3939 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3940 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3941 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3943 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3944 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3945 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
),
3947 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3949 /* V5J instruction. */
3950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
),
3951 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3953 /* V5 Instructions. */
3954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3955 0xe1200070, 0xfff000f0,
3956 "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3957 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3958 0xfa000000, 0xfe000000, "blx\t%B"},
3959 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3960 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3961 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5
),
3962 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3964 /* V5E "El Segundo" Instructions. */
3965 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3966 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3967 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3968 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3969 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
),
3970 0xf450f000, 0xfc70f000, "pld\t%a"},
3971 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3972 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3973 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3974 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3975 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3976 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3977 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3978 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3981 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3983 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3985 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3986 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3987 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3988 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3989 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3990 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3991 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3992 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3995 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3997 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
3999 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
4000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4001 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
4003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4004 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
4005 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4006 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
4008 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4009 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
4010 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4011 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
4012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4013 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
4014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
),
4015 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
4017 /* ARM Instructions. */
4018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4019 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
4021 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4022 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
4023 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4024 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
4025 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4026 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
4027 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4028 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
4029 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4030 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
4031 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4032 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
4034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4035 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
4036 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4037 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
4038 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4039 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
4040 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4041 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
4043 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4044 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION
},
4045 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4046 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
4047 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4048 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION
},
4049 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4050 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
4052 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4053 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
4054 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4055 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
4056 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4057 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
4059 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4060 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
4061 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4062 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
4063 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4064 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
4066 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4067 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
4068 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4069 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
4070 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4071 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
4073 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4074 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4075 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4076 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
4077 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4078 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
4080 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4081 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
4082 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4083 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
4084 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4085 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
4087 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4088 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
4089 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4090 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
4091 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4092 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
4094 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4095 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4096 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4097 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
4098 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4099 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
4101 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4102 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4103 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4104 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
4105 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4106 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
4108 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
4109 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
4110 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4111 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
4112 {ARM_FEATURE_CORE_LOW (ARM_EXT_V3
),
4113 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
4115 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4116 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
4117 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4118 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
4119 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4120 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
4122 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4123 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
4124 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4125 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
4126 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4127 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
4129 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4130 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
4131 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4132 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
4133 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4134 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
4136 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4137 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
4138 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4139 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
4140 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4141 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
4143 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4144 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
4145 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4146 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
4147 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4148 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
4150 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4151 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
4152 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4153 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
4154 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4155 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
4156 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4157 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
4158 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4159 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
4160 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4161 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
4162 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4163 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
4165 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4166 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
4167 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4168 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
4169 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4170 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
4172 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4173 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
4174 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4175 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
4176 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4177 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
4179 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4180 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION
},
4181 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4182 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
4184 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4185 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
4187 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4188 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
4189 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4190 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
4192 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4193 0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4194 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4195 0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4196 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4197 0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4198 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4199 0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4200 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4201 0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4202 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4203 0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4204 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4205 0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4206 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4207 0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4208 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4209 0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4210 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4211 0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4212 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4213 0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4214 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4215 0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4216 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4217 0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4218 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4219 0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4220 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4221 0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4222 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4223 0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
4224 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4225 0x092d0000, 0x0fff0000, "push%c\t%m"},
4226 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4227 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
4228 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4229 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4231 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4232 0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4233 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4234 0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4235 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4236 0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4237 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4238 0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4239 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4240 0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4241 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4242 0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4243 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4244 0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4245 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4246 0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4247 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4248 0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4249 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4250 0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4251 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4252 0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4253 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4254 0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4255 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4256 0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4257 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4258 0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4259 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4260 0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4261 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4262 0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
4263 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4264 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
4265 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4266 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
4267 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4268 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
4270 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4271 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
4272 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4273 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
4276 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
),
4277 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION
},
4278 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
4279 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
4280 {ARM_FEATURE_CORE_LOW (0),
4281 0x00000000, 0x00000000, 0}
4284 /* print_insn_thumb16 recognizes the following format control codes:
4286 %S print Thumb register (bits 3..5 as high number if bit 6 set)
4287 %D print Thumb register (bits 0..2 as high number if bit 7 set)
4288 %<bitfield>I print bitfield as a signed decimal
4289 (top bit of range being the sign bit)
4290 %N print Thumb register mask (with LR)
4291 %O print Thumb register mask (with PC)
4292 %M print Thumb register mask
4293 %b print CZB's 6-bit unsigned branch destination
4294 %s print Thumb right-shift immediate (6..10; 0 == 32).
4295 %c print the condition code
4296 %C print the condition code, or "s" if not conditional
4297 %x print warning if conditional an not at end of IT block"
4298 %X print "\t; unpredictable <IT:code>" if conditional
4299 %I print IT instruction suffix and operands
4300 %W print Thumb Writeback indicator for LDMIA
4301 %<bitfield>r print bitfield as an ARM register
4302 %<bitfield>d print bitfield as a decimal
4303 %<bitfield>H print (bitfield * 2) as a decimal
4304 %<bitfield>W print (bitfield * 4) as a decimal
4305 %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
4306 %<bitfield>B print Thumb branch destination (signed displacement)
4307 %<bitfield>c print bitfield as a condition code
4308 %<bitnum>'c print specified char iff bit is one
4309 %<bitnum>?ab print a if bit is one else print b. */
4311 static const struct opcode16 thumb_opcodes
[] =
4313 /* Thumb instructions. */
4315 /* ARMv8-M Security Extensions instructions. */
4316 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4784, 0xff87, "blxns\t%3-6r"},
4317 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0x4704, 0xff87, "bxns\t%3-6r"},
4319 /* ARM V8 instructions. */
4320 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xbf50, 0xffff, "sevl%c"},
4321 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xba80, 0xffc0, "hlt\t%0-5x"},
4322 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
), 0xb610, 0xfff7, "setpan\t#%3-3d"},
4324 /* ARM V6K no-argument instructions. */
4325 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xffff, "nop%c"},
4326 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf10, 0xffff, "yield%c"},
4327 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf20, 0xffff, "wfe%c"},
4328 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf30, 0xffff, "wfi%c"},
4329 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf40, 0xffff, "sev%c"},
4330 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
4332 /* ARM V6T2 instructions. */
4333 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4334 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
4335 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4336 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
4337 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xbf00, 0xff00, "it%I%X"},
4340 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
4341 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
4342 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
4343 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
4344 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
4345 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
4346 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb650, 0xfff7, "setend\t%3?ble%X"},
4347 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
4348 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
4349 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
4350 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6
), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
4352 /* ARM V5 ISA extends Thumb. */
4353 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4354 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
4355 /* This is BLX(2). BLX(1) is a 32-bit instruction. */
4356 {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
),
4357 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
4358 /* ARM V4T ISA (Thumb v1). */
4359 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4360 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
4362 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
4363 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
4364 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
4365 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
4366 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
4367 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
4368 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
4369 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
4370 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
4371 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
4372 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
4373 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
4374 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
4375 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
4376 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
4377 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
4379 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
4380 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
4382 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4700, 0xFF80, "bx%c\t%S%x"},
4383 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4400, 0xFF00, "add%c\t%D, %S"},
4384 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
4385 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x4600, 0xFF00, "mov%c\t%D, %S"},
4387 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xB400, 0xFE00, "push%c\t%N"},
4388 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xBC00, 0xFE00, "pop%c\t%O"},
4390 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4391 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
4392 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4393 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
4394 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4395 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
4396 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4397 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
4399 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4400 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
4401 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4402 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
4403 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4404 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
4406 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4407 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4408 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4409 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
4411 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
4412 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4413 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
4414 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
4415 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
4417 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
4418 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
4419 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
4420 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
4422 /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
4423 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4425 "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
4427 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4428 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
4429 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4430 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
4431 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4432 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
4433 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4434 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
4436 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4437 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
4438 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4439 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
4441 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4442 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
4443 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4444 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
4446 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4447 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
4448 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
4449 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
4451 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
4452 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
4454 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
4456 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
4457 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION
},
4458 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
4460 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
4462 /* The E800 .. FFFF range is unconditionally redirected to the
4463 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
4464 are processed via that table. Thus, we can never encounter a
4465 bare "second half of BL/BLX(1)" instruction here. */
4466 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
), 0x0000, 0x0000, UNDEFINED_INSTRUCTION
},
4467 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
4470 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
4471 We adopt the convention that hw1 is the high 16 bits of .value and
4472 .mask, hw2 the low 16 bits.
4474 print_insn_thumb32 recognizes the following format control codes:
4478 %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
4479 %M print a modified 12-bit immediate (same location)
4480 %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
4481 %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
4482 %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
4483 %S print a possibly-shifted Rm
4485 %L print address for a ldrd/strd instruction
4486 %a print the address of a plain load/store
4487 %w print the width and signedness of a core load/store
4488 %m print register mask for ldm/stm
4489 %n print register mask for clrm
4491 %E print the lsb and width fields of a bfc/bfi instruction
4492 %F print the lsb and width fields of a sbfx/ubfx instruction
4493 %G print a fallback offset for Branch Future instructions
4494 %W print an offset for BF instruction
4495 %Y print an offset for BFL instruction
4496 %Z print an offset for BFCSEL instruction
4497 %Q print an offset for Low Overhead Loop instructions
4498 %P print an offset for Low Overhead Loop end instructions
4499 %b print a conditional branch offset
4500 %B print an unconditional branch offset
4501 %s print the shift field of an SSAT instruction
4502 %R print the rotation field of an SXT instruction
4503 %U print barrier type.
4504 %P print address for pli instruction.
4505 %c print the condition code
4506 %x print warning if conditional an not at end of IT block"
4507 %X print "\t; unpredictable <IT:code>" if conditional
4509 %<bitfield>d print bitfield in decimal
4510 %<bitfield>D print bitfield plus one in decimal
4511 %<bitfield>W print bitfield*4 in decimal
4512 %<bitfield>r print bitfield as an ARM register
4513 %<bitfield>R as %<>r but r15 is UNPREDICTABLE
4514 %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
4515 %<bitfield>c print bitfield as a condition code
4517 %<bitfield>'c print specified char iff bitfield is all ones
4518 %<bitfield>`c print specified char iff bitfield is all zeroes
4519 %<bitfield>?ab... select from array of values in big endian order
4521 With one exception at the bottom (done because BL and BLX(1) need
4522 to come dead last), this table was machine-sorted first in
4523 decreasing order of number of bits set in the mask, then in
4524 increasing numeric order of mask, then in increasing numeric order
4525 of opcode. This order is not the clearest for a human reader, but
4526 is guaranteed never to catch a special-case bit pattern with a more
4527 general mask, which is important, because this instruction encoding
4528 makes heavy use of special-case bit patterns. */
4529 static const struct opcode32 thumb32_opcodes
[] =
4531 /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
4533 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4534 0xf00fe001, 0xffffffff, "lctp%c"},
4535 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4536 0xf02fc001, 0xfffff001, "le\t%P"},
4537 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4538 0xf00fc001, 0xfffff001, "le\tlr, %P"},
4539 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4540 0xf01fc001, 0xfffff001, "letp\tlr, %P"},
4541 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4542 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
4543 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4544 0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
4545 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4546 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
4547 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4548 0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
4550 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4551 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
4552 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4553 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
4554 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4555 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
4556 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4557 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
4558 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4559 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
4561 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
),
4562 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
4564 /* ARMv8-M and ARMv8-M Security Extensions instructions. */
4565 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
), 0xe97fe97f, 0xffffffff, "sg"},
4566 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4567 0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
4568 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4569 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
4570 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4571 0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
4572 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
),
4573 0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
4575 /* ARM V8.2 RAS extension instructions. */
4576 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
4577 0xf3af8010, 0xffffffff, "esb"},
4579 /* V8 instructions. */
4580 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4581 0xf3af8005, 0xffffffff, "sevl%c.w"},
4582 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4583 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
4584 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4585 0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
4586 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4587 0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
4588 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4589 0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
4590 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4591 0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
4592 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4593 0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
4594 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4595 0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
4596 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4597 0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
4598 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4599 0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
4600 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4601 0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
4602 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4603 0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
4604 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4605 0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
4606 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4607 0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
4608 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4609 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
4610 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
),
4611 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
4613 /* CRC32 instructions. */
4614 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4615 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
4616 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4617 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
4618 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4619 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
4620 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4621 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
4622 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4623 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
4624 {ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
4625 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
4627 /* Speculation Barriers. */
4628 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8014, 0xffffffff, "csdb"},
4629 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f40, 0xffffffff, "ssbb"},
4630 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3bf8f44, 0xffffffff, "pssbb"},
4632 /* V7 instructions. */
4633 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf910f000, 0xff70f000, "pli%c\t%a"},
4634 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
4635 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
4636 {ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
4637 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
4638 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
4639 {ARM_FEATURE_CORE_LOW (ARM_EXT_V7
), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
4640 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4641 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
4642 {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
4643 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
4645 /* Virtualization Extension instructions. */
4646 {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
4647 /* We skip ERET as that is SUBS pc, lr, #0. */
4649 /* MP Extension instructions. */
4650 {ARM_FEATURE_CORE_LOW (ARM_EXT_MP
), 0xf830f000, 0xff70f000, "pldw%c\t%a"},
4652 /* Security extension instructions. */
4653 {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
), 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
4655 /* ARMv8.5-A instructions. */
4656 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
), 0xf3bf8f70, 0xffffffff, "sb"},
4658 /* Instructions defined in the basic V6T2 set. */
4659 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8000, 0xffffffff, "nop%c.w"},
4660 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8001, 0xffffffff, "yield%c.w"},
4661 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8002, 0xffffffff, "wfe%c.w"},
4662 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8003, 0xffffffff, "wfi%c.w"},
4663 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf3af8004, 0xffffffff, "sev%c.w"},
4664 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4665 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
4666 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
4668 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4669 0xf3bf8f2f, 0xffffffff, "clrex%c"},
4670 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4671 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
4672 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4673 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
4674 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4675 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
4676 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4677 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
4678 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4679 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
4680 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4681 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
4682 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4683 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
4684 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4685 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
4686 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4687 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
4688 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4689 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
4690 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4691 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
4692 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4693 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
4694 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4695 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
4696 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4697 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
4698 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4699 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
4700 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4701 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
4702 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4703 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
4704 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4705 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
4706 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4707 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
4708 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4709 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
4710 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4711 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
4712 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4713 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
4714 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4715 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
4716 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4717 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
4718 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4719 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
4720 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4721 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
4722 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4723 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
4724 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4725 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
4726 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4727 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
4728 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4729 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
4730 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4731 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
4732 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4733 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
4734 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4735 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
4736 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4737 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
4738 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4739 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
4740 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4741 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
4742 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4743 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
4744 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4745 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
4746 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4747 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
4748 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4749 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
4750 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4751 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
4752 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4753 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
4754 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4755 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
4756 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4757 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
4758 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4759 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
4760 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4761 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
4762 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4763 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
4764 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4765 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
4766 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4767 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
4768 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4769 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
4770 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4771 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
4772 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4773 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
4774 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4775 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
4776 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4777 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
4778 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4779 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
4780 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4781 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
4782 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4783 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
4784 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4785 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
4786 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4787 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
4788 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4789 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
4790 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4791 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
4792 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4793 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
4794 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4795 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
4796 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4797 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
4798 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4799 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
4800 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4801 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
4802 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4803 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
4804 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4805 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
4806 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4807 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
4808 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4809 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
4810 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4811 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
4812 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4813 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
4814 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4815 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
4816 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4817 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4818 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4819 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4820 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4821 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
4822 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4823 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
4824 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4825 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
4826 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4827 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
4828 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4829 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
4830 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4831 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
4832 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4833 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4834 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4835 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
4836 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4837 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
4838 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4839 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4840 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4841 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
4842 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4843 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4844 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4845 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
4846 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4847 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4848 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4849 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
4850 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4851 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
4852 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4853 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
4854 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4855 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
4856 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4857 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
4858 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4859 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
4860 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4861 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
4862 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4863 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
4864 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4865 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
4866 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4867 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
4868 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4869 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
4870 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4871 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
4872 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4873 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
4874 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4875 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
4876 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4877 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4878 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4879 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4880 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4881 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4882 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4883 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4884 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4885 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4886 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4887 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4888 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4889 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4890 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4891 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4892 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4893 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
4894 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4895 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
4896 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4897 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
4898 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4899 0xf810f000, 0xff70f000, "pld%c\t%a"},
4900 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4901 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4902 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4903 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4904 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4905 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4906 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4907 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4908 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4909 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
4910 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4911 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4912 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4913 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
4914 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4915 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
4916 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4917 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
4918 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4919 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
4920 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4921 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
4922 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4923 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
4924 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4925 0xfb100000, 0xfff000c0,
4926 "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
4927 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4928 0xfbc00080, 0xfff000c0,
4929 "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
4930 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4931 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
4932 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4933 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
4934 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4935 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
4936 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4937 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
4938 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4939 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
4940 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4941 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
4942 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4943 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
4944 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4945 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
4946 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4947 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
4948 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4949 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
4950 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4951 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
4952 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4953 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
4954 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4955 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
4956 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4957 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
4958 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4959 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
4960 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4961 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
4962 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4963 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
4964 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4965 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
4966 {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
),
4967 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
4968 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4969 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
4970 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4971 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
4972 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4973 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
4974 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4975 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
4976 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4977 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
4978 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4979 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
4980 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4981 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
4982 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4983 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
4984 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4985 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
4986 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4987 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
4988 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4989 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
4990 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4991 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
4992 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4993 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
4994 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4995 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
4996 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4997 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
4998 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
4999 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
5000 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5001 0xe9400000, 0xff500000,
5002 "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5003 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5004 0xe9500000, 0xff500000,
5005 "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
5006 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5007 0xe8600000, 0xff700000,
5008 "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5009 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5010 0xe8700000, 0xff700000,
5011 "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
5012 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5013 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
5014 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5015 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
5017 /* Filter out Bcc with cond=E or F, which are used for other instructions. */
5018 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5019 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
5020 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5021 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
5022 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5023 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
5024 {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
),
5025 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
5027 /* These have been 32-bit since the invention of Thumb. */
5028 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5029 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
5030 {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
),
5031 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
5034 {ARM_FEATURE_CORE_LOW (ARM_EXT_V1
),
5035 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION
},
5036 {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
5039 static const char *const arm_conditional
[] =
5040 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
5041 "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
5043 static const char *const arm_fp_const
[] =
5044 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
5046 static const char *const arm_shift
[] =
5047 {"lsl", "lsr", "asr", "ror"};
5052 const char *description
;
5053 const char *reg_names
[16];
5057 static const arm_regname regnames
[] =
5059 { "reg-names-raw", N_("Select raw register names"),
5060 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
5061 { "reg-names-gcc", N_("Select register names used by GCC"),
5062 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
5063 { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
5064 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
5065 { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL
} },
5066 { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL
} },
5067 { "reg-names-apcs", N_("Select register names used in the APCS"),
5068 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
5069 { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
5070 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
5071 { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
5072 { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
5075 static const char *const iwmmxt_wwnames
[] =
5076 {"b", "h", "w", "d"};
5078 static const char *const iwmmxt_wwssnames
[] =
5079 {"b", "bus", "bc", "bss",
5080 "h", "hus", "hc", "hss",
5081 "w", "wus", "wc", "wss",
5082 "d", "dus", "dc", "dss"
5085 static const char *const iwmmxt_regnames
[] =
5086 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
5087 "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
5090 static const char *const iwmmxt_cregnames
[] =
5091 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
5092 "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
5095 static const char *const vec_condnames
[] =
5096 { "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
5099 static const char *const mve_predicatenames
[] =
5100 { "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
5101 "eee", "ee", "eet", "e", "ett", "et", "ete"
5104 /* Names for 2-bit size field for mve vector isntructions. */
5105 static const char *const mve_vec_sizename
[] =
5106 { "8", "16", "32", "64"};
5108 /* Indicates whether we are processing a then predicate,
5109 else predicate or none at all. */
5117 /* Information used to process a vpt block and subsequent instructions. */
5120 /* Are we in a vpt block. */
5121 bfd_boolean in_vpt_block
;
5123 /* Next predicate state if in vpt block. */
5124 enum vpt_pred_state next_pred_state
;
5126 /* Mask from vpt/vpst instruction. */
5127 long predicate_mask
;
5129 /* Instruction number in vpt block. */
5130 long current_insn_num
;
5132 /* Number of instructions in vpt block.. */
5136 static struct vpt_block vpt_block_state
=
5145 /* Default to GCC register name set. */
5146 static unsigned int regname_selected
= 1;
5148 #define NUM_ARM_OPTIONS ARRAY_SIZE (regnames)
5149 #define arm_regnames regnames[regname_selected].reg_names
5151 static bfd_boolean force_thumb
= FALSE
;
5153 /* Current IT instruction state. This contains the same state as the IT
5154 bits in the CPSR. */
5155 static unsigned int ifthen_state
;
5156 /* IT state for the next instruction. */
5157 static unsigned int ifthen_next_state
;
5158 /* The address of the insn for which the IT state is valid. */
5159 static bfd_vma ifthen_address
;
5160 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
5161 /* Indicates that the current Conditional state is unconditional or outside
5163 #define COND_UNCOND 16
5167 /* Extract the predicate mask for a VPT or VPST instruction.
5168 The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
5171 mve_extract_pred_mask (long given
)
5173 return ((given
& 0x00400000) >> 19) | ((given
& 0xe000) >> 13);
5176 /* Return the number of instructions in a MVE predicate block. */
5178 num_instructions_vpt_block (long given
)
5180 long mask
= mve_extract_pred_mask (given
);
5187 if ((mask
& 7) == 4)
5190 if ((mask
& 3) == 2)
5193 if ((mask
& 1) == 1)
5200 mark_outside_vpt_block (void)
5202 vpt_block_state
.in_vpt_block
= FALSE
;
5203 vpt_block_state
.next_pred_state
= PRED_NONE
;
5204 vpt_block_state
.predicate_mask
= 0;
5205 vpt_block_state
.current_insn_num
= 0;
5206 vpt_block_state
.num_pred_insn
= 0;
5210 mark_inside_vpt_block (long given
)
5212 vpt_block_state
.in_vpt_block
= TRUE
;
5213 vpt_block_state
.next_pred_state
= PRED_THEN
;
5214 vpt_block_state
.predicate_mask
= mve_extract_pred_mask (given
);
5215 vpt_block_state
.current_insn_num
= 0;
5216 vpt_block_state
.num_pred_insn
= num_instructions_vpt_block (given
);
5217 assert (vpt_block_state
.num_pred_insn
>= 1);
5220 static enum vpt_pred_state
5221 invert_next_predicate_state (enum vpt_pred_state astate
)
5223 if (astate
== PRED_THEN
)
5225 else if (astate
== PRED_ELSE
)
5231 static enum vpt_pred_state
5232 update_next_predicate_state (void)
5234 long pred_mask
= vpt_block_state
.predicate_mask
;
5235 long mask_for_insn
= 0;
5237 switch (vpt_block_state
.current_insn_num
)
5255 if (pred_mask
& mask_for_insn
)
5256 return invert_next_predicate_state (vpt_block_state
.next_pred_state
);
5258 return vpt_block_state
.next_pred_state
;
5262 update_vpt_block_state (void)
5264 vpt_block_state
.current_insn_num
++;
5265 if (vpt_block_state
.current_insn_num
== vpt_block_state
.num_pred_insn
)
5267 /* No more instructions to process in vpt block. */
5268 mark_outside_vpt_block ();
5272 vpt_block_state
.next_pred_state
= update_next_predicate_state ();
5275 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
5276 Returns pointer to following character of the format string and
5277 fills in *VALUEP and *WIDTHP with the extracted value and number of
5278 bits extracted. WIDTHP can be NULL. */
5281 arm_decode_bitfield (const char *ptr
,
5283 unsigned long *valuep
,
5286 unsigned long value
= 0;
5294 for (start
= 0; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5295 start
= start
* 10 + *ptr
- '0';
5297 for (end
= 0, ptr
++; *ptr
>= '0' && *ptr
<= '9'; ptr
++)
5298 end
= end
* 10 + *ptr
- '0';
5304 value
|= ((insn
>> start
) & ((2ul << bits
) - 1)) << width
;
5307 while (*ptr
++ == ',');
5315 arm_decode_shift (long given
, fprintf_ftype func
, void *stream
,
5316 bfd_boolean print_shift
)
5318 func (stream
, "%s", arm_regnames
[given
& 0xf]);
5320 if ((given
& 0xff0) != 0)
5322 if ((given
& 0x10) == 0)
5324 int amount
= (given
& 0xf80) >> 7;
5325 int shift
= (given
& 0x60) >> 5;
5331 func (stream
, ", rrx");
5339 func (stream
, ", %s #%d", arm_shift
[shift
], amount
);
5341 func (stream
, ", #%d", amount
);
5343 else if ((given
& 0x80) == 0x80)
5344 func (stream
, "\t; <illegal shifter operand>");
5345 else if (print_shift
)
5346 func (stream
, ", %s %s", arm_shift
[(given
& 0x60) >> 5],
5347 arm_regnames
[(given
& 0xf00) >> 8]);
5349 func (stream
, ", %s", arm_regnames
[(given
& 0xf00) >> 8]);
5353 /* Return TRUE if the MATCHED_INSN can be inside an IT block. */
5356 is_mve_okay_in_it (enum mve_instructions matched_insn
)
5358 switch (matched_insn
)
5360 case MVE_VMOV_GP_TO_VEC_LANE
:
5361 case MVE_VMOV2_VEC_LANE_TO_GP
:
5362 case MVE_VMOV2_GP_TO_VEC_LANE
:
5363 case MVE_VMOV_VEC_LANE_TO_GP
:
5388 is_mve_architecture (struct disassemble_info
*info
)
5390 struct arm_private_data
*private_data
= info
->private_data
;
5391 arm_feature_set allowed_arches
= private_data
->features
;
5393 arm_feature_set arm_ext_v8_1m_main
5394 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
5396 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
5397 && !ARM_CPU_IS_ANY (allowed_arches
))
5404 is_vpt_instruction (long given
)
5407 /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
5408 if ((given
& 0x0040e000) == 0)
5411 /* VPT floating point T1 variant. */
5412 if (((given
& 0xefb10f50) == 0xee310f00 && ((given
& 0x1001) != 0x1))
5413 /* VPT floating point T2 variant. */
5414 || ((given
& 0xefb10f50) == 0xee310f40)
5415 /* VPT vector T1 variant. */
5416 || ((given
& 0xff811f51) == 0xfe010f00)
5417 /* VPT vector T2 variant. */
5418 || ((given
& 0xff811f51) == 0xfe010f01
5419 && ((given
& 0x300000) != 0x300000))
5420 /* VPT vector T3 variant. */
5421 || ((given
& 0xff811f50) == 0xfe011f00)
5422 /* VPT vector T4 variant. */
5423 || ((given
& 0xff811f70) == 0xfe010f40)
5424 /* VPT vector T5 variant. */
5425 || ((given
& 0xff811f70) == 0xfe010f60)
5426 /* VPT vector T6 variant. */
5427 || ((given
& 0xff811f50) == 0xfe011f40)
5428 /* VPST vector T variant. */
5429 || ((given
& 0xffbf1fff) == 0xfe310f4d))
5435 /* Decode a bitfield from opcode GIVEN, with starting bitfield = START
5436 and ending bitfield = END. END must be greater than START. */
5438 static unsigned long
5439 arm_decode_field (unsigned long given
, unsigned int start
, unsigned int end
)
5441 int bits
= end
- start
;
5446 return ((given
>> start
) & ((2ul << bits
) - 1));
5449 /* Decode a bitfield from opcode GIVEN, with multiple bitfields:
5450 START:END and START2:END2. END/END2 must be greater than
5453 static unsigned long
5454 arm_decode_field_multiple (unsigned long given
, unsigned int start
,
5455 unsigned int end
, unsigned int start2
,
5458 int bits
= end
- start
;
5459 int bits2
= end2
- start2
;
5460 unsigned long value
= 0;
5466 value
= arm_decode_field (given
, start
, end
);
5469 value
|= ((given
>> start2
) & ((2ul << bits2
) - 1)) << width
;
5473 /* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
5474 This helps us decode instructions that change mnemonic depending on specific
5475 operand values/encodings. */
5478 is_mve_encoding_conflict (unsigned long given
,
5479 enum mve_instructions matched_insn
)
5481 switch (matched_insn
)
5484 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5490 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5492 if ((arm_decode_field (given
, 12, 12) == 0)
5493 && (arm_decode_field (given
, 0, 0) == 1))
5498 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5500 if (arm_decode_field (given
, 0, 3) == 0xd)
5504 case MVE_VPT_VEC_T1
:
5505 case MVE_VPT_VEC_T2
:
5506 case MVE_VPT_VEC_T3
:
5507 case MVE_VPT_VEC_T4
:
5508 case MVE_VPT_VEC_T5
:
5509 case MVE_VPT_VEC_T6
:
5510 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) == 0)
5512 if (arm_decode_field (given
, 20, 21) == 3)
5516 case MVE_VCMP_FP_T1
:
5517 if ((arm_decode_field (given
, 12, 12) == 0)
5518 && (arm_decode_field (given
, 0, 0) == 1))
5523 case MVE_VCMP_FP_T2
:
5524 if (arm_decode_field (given
, 0, 3) == 0xd)
5531 case MVE_VMUL_VEC_T2
:
5538 case MVE_VADD_VEC_T2
:
5539 case MVE_VSUB_VEC_T2
:
5556 case MVE_VQDMULH_T3
:
5557 case MVE_VQRDMULH_T4
:
5563 case MVE_VCMP_VEC_T1
:
5564 case MVE_VCMP_VEC_T2
:
5565 case MVE_VCMP_VEC_T3
:
5566 case MVE_VCMP_VEC_T4
:
5567 case MVE_VCMP_VEC_T5
:
5568 case MVE_VCMP_VEC_T6
:
5569 if (arm_decode_field (given
, 20, 21) == 3)
5578 if (arm_decode_field (given
, 7, 8) == 3)
5585 if ((arm_decode_field (given
, 24, 24) == 0)
5586 && (arm_decode_field (given
, 21, 21) == 0))
5590 else if ((arm_decode_field (given
, 7, 8) == 3))
5598 if ((arm_decode_field (given
, 24, 24) == 0)
5599 && (arm_decode_field (given
, 21, 21) == 0))
5606 case MVE_VCVT_FP_FIX_VEC
:
5607 return (arm_decode_field (given
, 16, 21) & 0x38) == 0;
5612 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5614 if ((cmode
& 1) == 0)
5616 else if ((cmode
& 0xc) == 0xc)
5624 unsigned long cmode
= arm_decode_field (given
, 8, 11);
5626 if ((cmode
& 9) == 1)
5628 else if ((cmode
& 5) == 1)
5630 else if ((cmode
& 0xe) == 0xe)
5636 case MVE_VMOV_IMM_TO_VEC
:
5637 if ((arm_decode_field (given
, 5, 5) == 1)
5638 && (arm_decode_field (given
, 8, 11) != 0xe))
5645 unsigned long size
= arm_decode_field (given
, 19, 20);
5646 if ((size
== 0) || (size
== 3))
5667 if (arm_decode_field (given
, 18, 19) == 3)
5673 case MVE_VRMLSLDAVH
:
5676 if (arm_decode_field (given
, 20, 22) == 7)
5681 case MVE_VRMLALDAVH
:
5682 if ((arm_decode_field (given
, 20, 22) & 6) == 6)
5689 if ((arm_decode_field (given
, 20, 21) == 3)
5690 || (arm_decode_field (given
, 1, 3) == 7))
5697 if (arm_decode_field (given
, 16, 18) == 0)
5699 unsigned long sz
= arm_decode_field (given
, 19, 20);
5701 if ((sz
== 1) || (sz
== 2))
5716 if (arm_decode_field (given
, 19, 21) == 0)
5722 if (arm_decode_field (given
, 16, 19) == 0xf)
5738 if (arm_decode_field (given
, 9, 11) == 0x7)
5746 unsigned long rm
, rn
;
5747 rm
= arm_decode_field (given
, 0, 3);
5748 rn
= arm_decode_field (given
, 16, 19);
5750 if (rm
== 0xf && rn
== 0xf)
5753 else if (rn
== rm
&& rn
!= 0xf)
5759 if (arm_decode_field (given
, 0, 3) == 0xd)
5762 else if (matched_insn
== MVE_CSNEG
)
5763 if (arm_decode_field (given
, 0, 3) == arm_decode_field (given
, 16, 19))
5768 case MVE_VADD_FP_T1
:
5769 case MVE_VADD_FP_T2
:
5770 case MVE_VADD_VEC_T1
:
5777 print_mve_vld_str_addr (struct disassemble_info
*info
,
5778 unsigned long given
,
5779 enum mve_instructions matched_insn
)
5781 void *stream
= info
->stream
;
5782 fprintf_ftype func
= info
->fprintf_func
;
5784 unsigned long p
, w
, gpr
, imm
, add
, mod_imm
;
5786 imm
= arm_decode_field (given
, 0, 6);
5789 switch (matched_insn
)
5793 gpr
= arm_decode_field (given
, 16, 18);
5798 gpr
= arm_decode_field (given
, 16, 18);
5804 gpr
= arm_decode_field (given
, 16, 19);
5810 gpr
= arm_decode_field (given
, 16, 19);
5816 gpr
= arm_decode_field (given
, 16, 19);
5823 p
= arm_decode_field (given
, 24, 24);
5824 w
= arm_decode_field (given
, 21, 21);
5826 add
= arm_decode_field (given
, 23, 23);
5830 /* Don't print anything for '+' as it is implied. */
5840 func (stream
, "[%s, #%s%lu]", arm_regnames
[gpr
], add_sub
, mod_imm
);
5841 /* Pre-indexed mode. */
5843 func (stream
, "[%s, #%s%lu]!", arm_regnames
[gpr
], add_sub
, mod_imm
);
5845 else if ((p
== 0) && (w
== 1))
5846 /* Post-index mode. */
5847 func (stream
, "[%s], #%s%lu", arm_regnames
[gpr
], add_sub
, mod_imm
);
5850 /* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
5851 Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
5852 this encoding is undefined. */
5855 is_mve_undefined (unsigned long given
, enum mve_instructions matched_insn
,
5856 enum mve_undefined
*undefined_code
)
5858 *undefined_code
= UNDEF_NONE
;
5860 switch (matched_insn
)
5863 if (arm_decode_field_multiple (given
, 5, 5, 22, 22) == 3)
5865 *undefined_code
= UNDEF_SIZE_3
;
5873 case MVE_VMUL_VEC_T1
:
5875 case MVE_VADD_VEC_T1
:
5876 case MVE_VSUB_VEC_T1
:
5877 case MVE_VQDMULH_T1
:
5878 case MVE_VQRDMULH_T2
:
5882 if (arm_decode_field (given
, 20, 21) == 3)
5884 *undefined_code
= UNDEF_SIZE_3
;
5891 if (arm_decode_field (given
, 7, 8) == 3)
5893 *undefined_code
= UNDEF_SIZE_3
;
5900 if (arm_decode_field (given
, 7, 8) <= 1)
5902 *undefined_code
= UNDEF_SIZE_LE_1
;
5909 if ((arm_decode_field (given
, 7, 8) == 0))
5911 *undefined_code
= UNDEF_SIZE_0
;
5918 if ((arm_decode_field (given
, 7, 8) <= 1))
5920 *undefined_code
= UNDEF_SIZE_LE_1
;
5926 case MVE_VLDRB_GATHER_T1
:
5927 if (arm_decode_field (given
, 7, 8) == 3)
5929 *undefined_code
= UNDEF_SIZE_3
;
5932 else if ((arm_decode_field (given
, 28, 28) == 0)
5933 && (arm_decode_field (given
, 7, 8) == 0))
5935 *undefined_code
= UNDEF_NOT_UNS_SIZE_0
;
5941 case MVE_VLDRH_GATHER_T2
:
5942 if (arm_decode_field (given
, 7, 8) == 3)
5944 *undefined_code
= UNDEF_SIZE_3
;
5947 else if ((arm_decode_field (given
, 28, 28) == 0)
5948 && (arm_decode_field (given
, 7, 8) == 1))
5950 *undefined_code
= UNDEF_NOT_UNS_SIZE_1
;
5953 else if (arm_decode_field (given
, 7, 8) == 0)
5955 *undefined_code
= UNDEF_SIZE_0
;
5961 case MVE_VLDRW_GATHER_T3
:
5962 if (arm_decode_field (given
, 7, 8) != 2)
5964 *undefined_code
= UNDEF_SIZE_NOT_2
;
5967 else if (arm_decode_field (given
, 28, 28) == 0)
5969 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5975 case MVE_VLDRD_GATHER_T4
:
5976 if (arm_decode_field (given
, 7, 8) != 3)
5978 *undefined_code
= UNDEF_SIZE_NOT_3
;
5981 else if (arm_decode_field (given
, 28, 28) == 0)
5983 *undefined_code
= UNDEF_NOT_UNSIGNED
;
5989 case MVE_VSTRB_SCATTER_T1
:
5990 if (arm_decode_field (given
, 7, 8) == 3)
5992 *undefined_code
= UNDEF_SIZE_3
;
5998 case MVE_VSTRH_SCATTER_T2
:
6000 unsigned long size
= arm_decode_field (given
, 7, 8);
6003 *undefined_code
= UNDEF_SIZE_3
;
6008 *undefined_code
= UNDEF_SIZE_0
;
6015 case MVE_VSTRW_SCATTER_T3
:
6016 if (arm_decode_field (given
, 7, 8) != 2)
6018 *undefined_code
= UNDEF_SIZE_NOT_2
;
6024 case MVE_VSTRD_SCATTER_T4
:
6025 if (arm_decode_field (given
, 7, 8) != 3)
6027 *undefined_code
= UNDEF_SIZE_NOT_3
;
6033 case MVE_VCVT_FP_FIX_VEC
:
6035 unsigned long imm6
= arm_decode_field (given
, 16, 21);
6036 if ((imm6
& 0x20) == 0)
6038 *undefined_code
= UNDEF_VCVT_IMM6
;
6042 if ((arm_decode_field (given
, 9, 9) == 0)
6043 && ((imm6
& 0x30) == 0x20))
6045 *undefined_code
= UNDEF_VCVT_FSI_IMM6
;
6054 case MVE_VCVT_BETWEEN_FP_INT
:
6055 case MVE_VCVT_FROM_FP_TO_INT
:
6057 unsigned long size
= arm_decode_field (given
, 18, 19);
6060 *undefined_code
= UNDEF_SIZE_0
;
6065 *undefined_code
= UNDEF_SIZE_3
;
6072 case MVE_VMOV_VEC_LANE_TO_GP
:
6074 unsigned long op1
= arm_decode_field (given
, 21, 22);
6075 unsigned long op2
= arm_decode_field (given
, 5, 6);
6076 unsigned long u
= arm_decode_field (given
, 23, 23);
6078 if ((op2
== 0) && (u
== 1))
6080 if ((op1
== 0) || (op1
== 1))
6082 *undefined_code
= UNDEF_BAD_U_OP1_OP2
;
6090 if ((op1
== 0) || (op1
== 1))
6092 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6102 case MVE_VMOV_GP_TO_VEC_LANE
:
6103 if (arm_decode_field (given
, 5, 6) == 2)
6105 unsigned long op1
= arm_decode_field (given
, 21, 22);
6106 if ((op1
== 0) || (op1
== 1))
6108 *undefined_code
= UNDEF_BAD_OP1_OP2
;
6117 case MVE_VMOV_VEC_TO_VEC
:
6118 if ((arm_decode_field (given
, 5, 5) == 1)
6119 || (arm_decode_field (given
, 22, 22) == 1))
6123 case MVE_VMOV_IMM_TO_VEC
:
6124 if (arm_decode_field (given
, 5, 5) == 0)
6126 unsigned long cmode
= arm_decode_field (given
, 8, 11);
6128 if (((cmode
& 9) == 1) || ((cmode
& 5) == 1))
6130 *undefined_code
= UNDEF_OP_0_BAD_CMODE
;
6141 if (arm_decode_field (given
, 18, 19) == 2)
6143 *undefined_code
= UNDEF_SIZE_2
;
6149 case MVE_VRMLALDAVH
:
6150 case MVE_VMLADAV_T1
:
6151 case MVE_VMLADAV_T2
:
6153 if ((arm_decode_field (given
, 28, 28) == 1)
6154 && (arm_decode_field (given
, 12, 12) == 1))
6156 *undefined_code
= UNDEF_XCHG_UNS
;
6167 unsigned long sz
= arm_decode_field (given
, 19, 20);
6170 else if ((sz
& 2) == 2)
6174 *undefined_code
= UNDEF_SIZE
;
6188 unsigned long sz
= arm_decode_field (given
, 19, 21);
6191 else if ((sz
& 6) == 2)
6193 else if ((sz
& 4) == 4)
6197 *undefined_code
= UNDEF_SIZE
;
6204 if (arm_decode_field (given
, 19, 20) == 0)
6206 *undefined_code
= UNDEF_SIZE_0
;
6213 if (arm_decode_field (given
, 18, 19) == 3)
6215 *undefined_code
= UNDEF_SIZE_3
;
6226 if (arm_decode_field (given
, 18, 19) == 3)
6228 *undefined_code
= UNDEF_SIZE_3
;
6235 if (arm_decode_field (given
, 18, 19) == 0)
6239 *undefined_code
= UNDEF_SIZE_NOT_0
;
6245 unsigned long size
= arm_decode_field (given
, 18, 19);
6246 if ((size
& 2) == 2)
6248 *undefined_code
= UNDEF_SIZE_2
;
6256 if (arm_decode_field (given
, 18, 19) != 3)
6260 *undefined_code
= UNDEF_SIZE_3
;
6269 /* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
6270 Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
6271 why this encoding is unpredictable. */
6274 is_mve_unpredictable (unsigned long given
, enum mve_instructions matched_insn
,
6275 enum mve_unpredictable
*unpredictable_code
)
6277 *unpredictable_code
= UNPRED_NONE
;
6279 switch (matched_insn
)
6281 case MVE_VCMP_FP_T2
:
6283 if ((arm_decode_field (given
, 12, 12) == 0)
6284 && (arm_decode_field (given
, 5, 5) == 1))
6286 *unpredictable_code
= UNPRED_FCA_0_FCB_1
;
6292 case MVE_VPT_VEC_T4
:
6293 case MVE_VPT_VEC_T5
:
6294 case MVE_VPT_VEC_T6
:
6295 case MVE_VCMP_VEC_T4
:
6296 case MVE_VCMP_VEC_T5
:
6297 case MVE_VCMP_VEC_T6
:
6298 if (arm_decode_field (given
, 0, 3) == 0xd)
6300 *unpredictable_code
= UNPRED_R13
;
6308 unsigned long gpr
= arm_decode_field (given
, 12, 15);
6311 *unpredictable_code
= UNPRED_R13
;
6314 else if (gpr
== 0xf)
6316 *unpredictable_code
= UNPRED_R15
;
6325 case MVE_VMUL_FP_T2
:
6326 case MVE_VMUL_VEC_T2
:
6329 case MVE_VADD_FP_T2
:
6330 case MVE_VSUB_FP_T2
:
6331 case MVE_VADD_VEC_T2
:
6332 case MVE_VSUB_VEC_T2
:
6342 case MVE_VQDMULH_T3
:
6343 case MVE_VQRDMULH_T4
:
6345 case MVE_VFMA_FP_SCALAR
:
6346 case MVE_VFMAS_FP_SCALAR
:
6350 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6353 *unpredictable_code
= UNPRED_R13
;
6356 else if (gpr
== 0xf)
6358 *unpredictable_code
= UNPRED_R15
;
6368 unsigned long rn
= arm_decode_field (given
, 16, 19);
6370 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6372 *unpredictable_code
= UNPRED_R13_AND_WB
;
6378 *unpredictable_code
= UNPRED_R15
;
6382 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 6)
6384 *unpredictable_code
= UNPRED_Q_GT_6
;
6394 unsigned long rn
= arm_decode_field (given
, 16, 19);
6396 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6398 *unpredictable_code
= UNPRED_R13_AND_WB
;
6404 *unpredictable_code
= UNPRED_R15
;
6408 if (arm_decode_field_multiple (given
, 13, 15, 22, 22) > 4)
6410 *unpredictable_code
= UNPRED_Q_GT_4
;
6424 unsigned long rn
= arm_decode_field (given
, 16, 19);
6426 if ((rn
== 0xd) && (arm_decode_field (given
, 21, 21) == 1))
6428 *unpredictable_code
= UNPRED_R13_AND_WB
;
6433 *unpredictable_code
= UNPRED_R15
;
6440 case MVE_VLDRB_GATHER_T1
:
6441 if (arm_decode_field (given
, 0, 0) == 1)
6443 *unpredictable_code
= UNPRED_OS
;
6448 /* To handle common code with T2-T4 variants. */
6449 case MVE_VLDRH_GATHER_T2
:
6450 case MVE_VLDRW_GATHER_T3
:
6451 case MVE_VLDRD_GATHER_T4
:
6453 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6454 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6458 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6462 if (arm_decode_field (given
, 16, 19) == 0xf)
6464 *unpredictable_code
= UNPRED_R15
;
6471 case MVE_VLDRW_GATHER_T5
:
6472 case MVE_VLDRD_GATHER_T6
:
6474 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6475 unsigned long qm
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6479 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6486 case MVE_VSTRB_SCATTER_T1
:
6487 if (arm_decode_field (given
, 16, 19) == 0xf)
6489 *unpredictable_code
= UNPRED_R15
;
6492 else if (arm_decode_field (given
, 0, 0) == 1)
6494 *unpredictable_code
= UNPRED_OS
;
6500 case MVE_VSTRH_SCATTER_T2
:
6501 case MVE_VSTRW_SCATTER_T3
:
6502 case MVE_VSTRD_SCATTER_T4
:
6503 if (arm_decode_field (given
, 16, 19) == 0xf)
6505 *unpredictable_code
= UNPRED_R15
;
6511 case MVE_VMOV2_VEC_LANE_TO_GP
:
6512 case MVE_VMOV2_GP_TO_VEC_LANE
:
6513 case MVE_VCVT_BETWEEN_FP_INT
:
6514 case MVE_VCVT_FROM_FP_TO_INT
:
6516 unsigned long rt
= arm_decode_field (given
, 0, 3);
6517 unsigned long rt2
= arm_decode_field (given
, 16, 19);
6519 if ((rt
== 0xd) || (rt2
== 0xd))
6521 *unpredictable_code
= UNPRED_R13
;
6524 else if ((rt
== 0xf) || (rt2
== 0xf))
6526 *unpredictable_code
= UNPRED_R15
;
6531 *unpredictable_code
= UNPRED_GP_REGS_EQUAL
;
6540 case MVE_VMAXNMV_FP
:
6541 case MVE_VMAXNMAV_FP
:
6542 case MVE_VMINNMV_FP
:
6543 case MVE_VMINNMAV_FP
:
6547 case MVE_VMOV_HFP_TO_GP
:
6548 case MVE_VMOV_GP_TO_VEC_LANE
:
6549 case MVE_VMOV_VEC_LANE_TO_GP
:
6551 unsigned long rda
= arm_decode_field (given
, 12, 15);
6554 *unpredictable_code
= UNPRED_R13
;
6557 else if (rda
== 0xf)
6559 *unpredictable_code
= UNPRED_R15
;
6572 if (arm_decode_field (given
, 20, 21) == 2)
6574 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6575 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6576 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6578 if ((Qd
== Qn
) || (Qd
== Qm
))
6580 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6591 case MVE_VQDMULL_T1
:
6597 if (arm_decode_field (given
, 28, 28) == 1)
6599 Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6600 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6601 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6603 if ((Qd
== Qn
) || (Qd
== Qm
))
6605 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6615 case MVE_VQDMULL_T2
:
6617 unsigned long gpr
= arm_decode_field (given
, 0, 3);
6620 *unpredictable_code
= UNPRED_R13
;
6623 else if (gpr
== 0xf)
6625 *unpredictable_code
= UNPRED_R15
;
6629 if (arm_decode_field (given
, 28, 28) == 1)
6632 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
6633 unsigned long Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6637 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6648 case MVE_VRMLSLDAVH
:
6651 if (arm_decode_field (given
, 20, 22) == 6)
6653 *unpredictable_code
= UNPRED_R13
;
6661 if (arm_decode_field (given
, 1, 3) == 6)
6663 *unpredictable_code
= UNPRED_R13
;
6672 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6673 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6674 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 21) == 2)
6676 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_2
;
6685 unsigned long Qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6686 unsigned long Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6687 if ((Qd
== Qm
) && arm_decode_field (given
, 20, 20) == 1)
6689 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6702 if (arm_decode_field (given
, 20, 20) == 1)
6704 Qda
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6705 Qm
= arm_decode_field_multiple (given
, 1, 3, 5, 5);
6706 Qn
= arm_decode_field_multiple (given
, 17, 19, 7, 7);
6708 if ((Qda
== Qn
) || (Qda
== Qm
))
6710 *unpredictable_code
= UNPRED_Q_REGS_EQ_AND_SIZE_1
;
6722 if (arm_decode_field (given
, 16, 19) == 0xd)
6724 *unpredictable_code
= UNPRED_R13
;
6732 unsigned long qd
= arm_decode_field_multiple (given
, 13, 15, 22, 22);
6733 unsigned long qm
= arm_decode_field_multiple (given
, 1, 3, 6, 6);
6737 *unpredictable_code
= UNPRED_Q_REGS_EQUAL
;
6756 unsigned long gpr
= arm_decode_field (given
, 9, 11);
6757 gpr
= ((gpr
<< 1) | 1);
6760 *unpredictable_code
= UNPRED_R13
;
6763 else if (gpr
== 0xf)
6765 *unpredictable_code
= UNPRED_R15
;
6778 print_mve_vmov_index (struct disassemble_info
*info
, unsigned long given
)
6780 unsigned long op1
= arm_decode_field (given
, 21, 22);
6781 unsigned long op2
= arm_decode_field (given
, 5, 6);
6782 unsigned long h
= arm_decode_field (given
, 16, 16);
6783 unsigned long index_operand
, esize
, targetBeat
, idx
;
6784 void *stream
= info
->stream
;
6785 fprintf_ftype func
= info
->fprintf_func
;
6787 if ((op1
& 0x2) == 0x2)
6789 index_operand
= op2
;
6792 else if (((op1
& 0x2) == 0x0) && ((op2
& 0x1) == 0x1))
6794 index_operand
= op2
>> 1;
6797 else if (((op1
& 0x2) == 0) && ((op2
& 0x3) == 0))
6804 func (stream
, "<undefined index>");
6808 targetBeat
= (op1
& 0x1) | (h
<< 1);
6809 idx
= index_operand
+ targetBeat
* (32/esize
);
6811 func (stream
, "%lu", idx
);
6814 /* Print neon and mve 8-bit immediate that can be a 8, 16, 32, or 64-bits
6815 in length and integer of floating-point type. */
6817 print_simd_imm8 (struct disassemble_info
*info
, unsigned long given
,
6818 unsigned int ibit_loc
, const struct mopcode32
*insn
)
6821 int cmode
= (given
>> 8) & 0xf;
6822 int op
= (given
>> 5) & 0x1;
6823 unsigned long value
= 0, hival
= 0;
6827 void *stream
= info
->stream
;
6828 fprintf_ftype func
= info
->fprintf_func
;
6830 /* On Neon the 'i' bit is at bit 24, on mve it is
6832 bits
|= ((given
>> ibit_loc
) & 1) << 7;
6833 bits
|= ((given
>> 16) & 7) << 4;
6834 bits
|= ((given
>> 0) & 15) << 0;
6838 shift
= (cmode
>> 1) & 3;
6839 value
= (unsigned long) bits
<< (8 * shift
);
6842 else if (cmode
< 12)
6844 shift
= (cmode
>> 1) & 1;
6845 value
= (unsigned long) bits
<< (8 * shift
);
6848 else if (cmode
< 14)
6850 shift
= (cmode
& 1) + 1;
6851 value
= (unsigned long) bits
<< (8 * shift
);
6852 value
|= (1ul << (8 * shift
)) - 1;
6855 else if (cmode
== 14)
6859 /* Bit replication into bytes. */
6865 for (ix
= 7; ix
>= 0; ix
--)
6867 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
6869 value
= (value
<< 8) | mask
;
6871 hival
= (hival
<< 8) | mask
;
6877 /* Byte replication. */
6878 value
= (unsigned long) bits
;
6884 /* Floating point encoding. */
6887 value
= (unsigned long) (bits
& 0x7f) << 19;
6888 value
|= (unsigned long) (bits
& 0x80) << 24;
6889 tmp
= bits
& 0x40 ? 0x3c : 0x40;
6890 value
|= (unsigned long) tmp
<< 24;
6896 func (stream
, "<illegal constant %.8x:%x:%x>",
6902 // printU determines whether the immediate value should be printed as
6904 unsigned printU
= 0;
6905 switch (insn
->mve_op
)
6909 // We want this for instructions that don't have a 'signed' type
6913 case MVE_VMOV_IMM_TO_VEC
:
6920 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
6927 : "#%ld\t; 0x%.4lx", value
, value
);
6933 unsigned char valbytes
[4];
6936 /* Do this a byte at a time so we don't have to
6937 worry about the host's endianness. */
6938 valbytes
[0] = value
& 0xff;
6939 valbytes
[1] = (value
>> 8) & 0xff;
6940 valbytes
[2] = (value
>> 16) & 0xff;
6941 valbytes
[3] = (value
>> 24) & 0xff;
6943 floatformat_to_double
6944 (& floatformat_ieee_single_little
, valbytes
,
6947 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
6954 : "#%ld\t; 0x%.8lx",
6955 (long) (((value
& 0x80000000L
) != 0)
6957 ? value
| ~0xffffffffL
: value
),
6962 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
6972 print_mve_undefined (struct disassemble_info
*info
,
6973 enum mve_undefined undefined_code
)
6975 void *stream
= info
->stream
;
6976 fprintf_ftype func
= info
->fprintf_func
;
6978 func (stream
, "\t\tundefined instruction: ");
6980 switch (undefined_code
)
6983 func (stream
, "illegal size");
6987 func (stream
, "size equals zero");
6991 func (stream
, "size equals two");
6995 func (stream
, "size equals three");
6998 case UNDEF_SIZE_LE_1
:
6999 func (stream
, "size <= 1");
7002 case UNDEF_SIZE_NOT_0
:
7003 func (stream
, "size not equal to 0");
7006 case UNDEF_SIZE_NOT_2
:
7007 func (stream
, "size not equal to 2");
7010 case UNDEF_SIZE_NOT_3
:
7011 func (stream
, "size not equal to 3");
7014 case UNDEF_NOT_UNS_SIZE_0
:
7015 func (stream
, "not unsigned and size = zero");
7018 case UNDEF_NOT_UNS_SIZE_1
:
7019 func (stream
, "not unsigned and size = one");
7022 case UNDEF_NOT_UNSIGNED
:
7023 func (stream
, "not unsigned");
7026 case UNDEF_VCVT_IMM6
:
7027 func (stream
, "invalid imm6");
7030 case UNDEF_VCVT_FSI_IMM6
:
7031 func (stream
, "fsi = 0 and invalid imm6");
7034 case UNDEF_BAD_OP1_OP2
:
7035 func (stream
, "bad size with op2 = 2 and op1 = 0 or 1");
7038 case UNDEF_BAD_U_OP1_OP2
:
7039 func (stream
, "unsigned with op2 = 0 and op1 = 0 or 1");
7042 case UNDEF_OP_0_BAD_CMODE
:
7043 func (stream
, "op field equal 0 and bad cmode");
7046 case UNDEF_XCHG_UNS
:
7047 func (stream
, "exchange and unsigned together");
7057 print_mve_unpredictable (struct disassemble_info
*info
,
7058 enum mve_unpredictable unpredict_code
)
7060 void *stream
= info
->stream
;
7061 fprintf_ftype func
= info
->fprintf_func
;
7063 func (stream
, "%s: ", UNPREDICTABLE_INSTRUCTION
);
7065 switch (unpredict_code
)
7067 case UNPRED_IT_BLOCK
:
7068 func (stream
, "mve instruction in it block");
7071 case UNPRED_FCA_0_FCB_1
:
7072 func (stream
, "condition bits, fca = 0 and fcb = 1");
7076 func (stream
, "use of r13 (sp)");
7080 func (stream
, "use of r15 (pc)");
7084 func (stream
, "start register block > r4");
7088 func (stream
, "start register block > r6");
7091 case UNPRED_R13_AND_WB
:
7092 func (stream
, "use of r13 and write back");
7095 case UNPRED_Q_REGS_EQUAL
:
7097 "same vector register used for destination and other operand");
7101 func (stream
, "use of offset scaled");
7104 case UNPRED_GP_REGS_EQUAL
:
7105 func (stream
, "same general-purpose register used for both operands");
7108 case UNPRED_Q_REGS_EQ_AND_SIZE_1
:
7109 func (stream
, "use of identical q registers and size = 1");
7112 case UNPRED_Q_REGS_EQ_AND_SIZE_2
:
7113 func (stream
, "use of identical q registers and size = 1");
7121 /* Print register block operand for mve vld2/vld4/vst2/vld4. */
7124 print_mve_register_blocks (struct disassemble_info
*info
,
7125 unsigned long given
,
7126 enum mve_instructions matched_insn
)
7128 void *stream
= info
->stream
;
7129 fprintf_ftype func
= info
->fprintf_func
;
7131 unsigned long q_reg_start
= arm_decode_field_multiple (given
,
7134 switch (matched_insn
)
7138 if (q_reg_start
<= 6)
7139 func (stream
, "{q%ld, q%ld}", q_reg_start
, q_reg_start
+ 1);
7141 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7146 if (q_reg_start
<= 4)
7147 func (stream
, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start
,
7148 q_reg_start
+ 1, q_reg_start
+ 2,
7151 func (stream
, "<illegal reg q%ld>", q_reg_start
);
7160 print_mve_rounding_mode (struct disassemble_info
*info
,
7161 unsigned long given
,
7162 enum mve_instructions matched_insn
)
7164 void *stream
= info
->stream
;
7165 fprintf_ftype func
= info
->fprintf_func
;
7167 switch (matched_insn
)
7169 case MVE_VCVT_FROM_FP_TO_INT
:
7171 switch (arm_decode_field (given
, 8, 9))
7197 switch (arm_decode_field (given
, 7, 9))
7236 print_mve_vcvt_size (struct disassemble_info
*info
,
7237 unsigned long given
,
7238 enum mve_instructions matched_insn
)
7240 unsigned long mode
= 0;
7241 void *stream
= info
->stream
;
7242 fprintf_ftype func
= info
->fprintf_func
;
7244 switch (matched_insn
)
7246 case MVE_VCVT_FP_FIX_VEC
:
7248 mode
= (((given
& 0x200) >> 7)
7249 | ((given
& 0x10000000) >> 27)
7250 | ((given
& 0x100) >> 8));
7255 func (stream
, "f16.s16");
7259 func (stream
, "s16.f16");
7263 func (stream
, "f16.u16");
7267 func (stream
, "u16.f16");
7271 func (stream
, "f32.s32");
7275 func (stream
, "s32.f32");
7279 func (stream
, "f32.u32");
7283 func (stream
, "u32.f32");
7291 case MVE_VCVT_BETWEEN_FP_INT
:
7293 unsigned long size
= arm_decode_field (given
, 18, 19);
7294 unsigned long op
= arm_decode_field (given
, 7, 8);
7301 func (stream
, "f16.s16");
7305 func (stream
, "f16.u16");
7309 func (stream
, "s16.f16");
7313 func (stream
, "u16.f16");
7325 func (stream
, "f32.s32");
7329 func (stream
, "f32.u32");
7333 func (stream
, "s32.f32");
7337 func (stream
, "u32.f32");
7344 case MVE_VCVT_FP_HALF_FP
:
7346 unsigned long op
= arm_decode_field (given
, 28, 28);
7348 func (stream
, "f16.f32");
7350 func (stream
, "f32.f16");
7354 case MVE_VCVT_FROM_FP_TO_INT
:
7356 unsigned long size
= arm_decode_field_multiple (given
, 7, 7, 18, 19);
7361 func (stream
, "s16.f16");
7365 func (stream
, "u16.f16");
7369 func (stream
, "s32.f32");
7373 func (stream
, "u32.f32");
7388 print_mve_rotate (struct disassemble_info
*info
, unsigned long rot
,
7389 unsigned long rot_width
)
7391 void *stream
= info
->stream
;
7392 fprintf_ftype func
= info
->fprintf_func
;
7399 func (stream
, "90");
7402 func (stream
, "270");
7408 else if (rot_width
== 2)
7416 func (stream
, "90");
7419 func (stream
, "180");
7422 func (stream
, "270");
7431 print_instruction_predicate (struct disassemble_info
*info
)
7433 void *stream
= info
->stream
;
7434 fprintf_ftype func
= info
->fprintf_func
;
7436 if (vpt_block_state
.next_pred_state
== PRED_THEN
)
7438 else if (vpt_block_state
.next_pred_state
== PRED_ELSE
)
7443 print_mve_size (struct disassemble_info
*info
,
7445 enum mve_instructions matched_insn
)
7447 void *stream
= info
->stream
;
7448 fprintf_ftype func
= info
->fprintf_func
;
7450 switch (matched_insn
)
7456 case MVE_VADD_VEC_T1
:
7457 case MVE_VADD_VEC_T2
:
7463 case MVE_VCMP_VEC_T1
:
7464 case MVE_VCMP_VEC_T2
:
7465 case MVE_VCMP_VEC_T3
:
7466 case MVE_VCMP_VEC_T4
:
7467 case MVE_VCMP_VEC_T5
:
7468 case MVE_VCMP_VEC_T6
:
7481 case MVE_VLDRB_GATHER_T1
:
7482 case MVE_VLDRH_GATHER_T2
:
7483 case MVE_VLDRW_GATHER_T3
:
7484 case MVE_VLDRD_GATHER_T4
:
7497 case MVE_VMUL_VEC_T1
:
7498 case MVE_VMUL_VEC_T2
:
7504 case MVE_VPT_VEC_T1
:
7505 case MVE_VPT_VEC_T2
:
7506 case MVE_VPT_VEC_T3
:
7507 case MVE_VPT_VEC_T4
:
7508 case MVE_VPT_VEC_T5
:
7509 case MVE_VPT_VEC_T6
:
7521 case MVE_VQDMULH_T1
:
7522 case MVE_VQRDMULH_T2
:
7523 case MVE_VQDMULH_T3
:
7524 case MVE_VQRDMULH_T4
:
7543 case MVE_VSTRB_SCATTER_T1
:
7544 case MVE_VSTRH_SCATTER_T2
:
7545 case MVE_VSTRW_SCATTER_T3
:
7548 case MVE_VSUB_VEC_T1
:
7549 case MVE_VSUB_VEC_T2
:
7551 func (stream
, "%s", mve_vec_sizename
[size
]);
7553 func (stream
, "<undef size>");
7557 case MVE_VADD_FP_T1
:
7558 case MVE_VADD_FP_T2
:
7559 case MVE_VSUB_FP_T1
:
7560 case MVE_VSUB_FP_T2
:
7561 case MVE_VCMP_FP_T1
:
7562 case MVE_VCMP_FP_T2
:
7563 case MVE_VFMA_FP_SCALAR
:
7566 case MVE_VFMAS_FP_SCALAR
:
7568 case MVE_VMAXNMA_FP
:
7569 case MVE_VMAXNMV_FP
:
7570 case MVE_VMAXNMAV_FP
:
7572 case MVE_VMINNMA_FP
:
7573 case MVE_VMINNMV_FP
:
7574 case MVE_VMINNMAV_FP
:
7575 case MVE_VMUL_FP_T1
:
7576 case MVE_VMUL_FP_T2
:
7580 func (stream
, "32");
7582 func (stream
, "16");
7588 case MVE_VMLADAV_T1
:
7590 case MVE_VMLSDAV_T1
:
7593 case MVE_VQDMULL_T1
:
7594 case MVE_VQDMULL_T2
:
7598 func (stream
, "16");
7600 func (stream
, "32");
7607 func (stream
, "16");
7614 func (stream
, "32");
7617 func (stream
, "16");
7627 case MVE_VMOV_GP_TO_VEC_LANE
:
7628 case MVE_VMOV_VEC_LANE_TO_GP
:
7632 func (stream
, "32");
7637 func (stream
, "16");
7640 case 8: case 9: case 10: case 11:
7641 case 12: case 13: case 14: case 15:
7650 case MVE_VMOV_IMM_TO_VEC
:
7653 case 0: case 4: case 8:
7654 case 12: case 24: case 26:
7655 func (stream
, "i32");
7658 func (stream
, "i16");
7661 func (stream
, "i8");
7664 func (stream
, "i64");
7667 func (stream
, "f32");
7674 case MVE_VMULL_POLY
:
7676 func (stream
, "p8");
7678 func (stream
, "p16");
7684 case 0: case 2: case 4:
7685 case 6: case 12: case 13:
7686 func (stream
, "32");
7690 func (stream
, "16");
7704 func (stream
, "32");
7708 func (stream
, "16");
7726 func (stream
, "16");
7730 func (stream
, "32");
7755 func (stream
, "16");
7758 case 4: case 5: case 6: case 7:
7759 func (stream
, "32");
7774 print_mve_shift_n (struct disassemble_info
*info
, long given
,
7775 enum mve_instructions matched_insn
)
7777 void *stream
= info
->stream
;
7778 fprintf_ftype func
= info
->fprintf_func
;
7781 = matched_insn
== MVE_VQSHL_T2
7782 || matched_insn
== MVE_VQSHLU_T3
7783 || matched_insn
== MVE_VSHL_T1
7784 || matched_insn
== MVE_VSHLL_T1
7785 || matched_insn
== MVE_VSLI
;
7787 unsigned imm6
= (given
& 0x3f0000) >> 16;
7789 if (matched_insn
== MVE_VSHLL_T1
)
7792 unsigned shiftAmount
= 0;
7793 if ((imm6
& 0x20) != 0)
7794 shiftAmount
= startAt0
? imm6
- 32 : 64 - imm6
;
7795 else if ((imm6
& 0x10) != 0)
7796 shiftAmount
= startAt0
? imm6
- 16 : 32 - imm6
;
7797 else if ((imm6
& 0x08) != 0)
7798 shiftAmount
= startAt0
? imm6
- 8 : 16 - imm6
;
7800 print_mve_undefined (info
, UNDEF_SIZE_0
);
7802 func (stream
, "%u", shiftAmount
);
7806 print_vec_condition (struct disassemble_info
*info
, long given
,
7807 enum mve_instructions matched_insn
)
7809 void *stream
= info
->stream
;
7810 fprintf_ftype func
= info
->fprintf_func
;
7813 switch (matched_insn
)
7816 case MVE_VCMP_FP_T1
:
7817 vec_cond
= (((given
& 0x1000) >> 10)
7818 | ((given
& 1) << 1)
7819 | ((given
& 0x0080) >> 7));
7820 func (stream
, "%s",vec_condnames
[vec_cond
]);
7824 case MVE_VCMP_FP_T2
:
7825 vec_cond
= (((given
& 0x1000) >> 10)
7826 | ((given
& 0x0020) >> 4)
7827 | ((given
& 0x0080) >> 7));
7828 func (stream
, "%s",vec_condnames
[vec_cond
]);
7831 case MVE_VPT_VEC_T1
:
7832 case MVE_VCMP_VEC_T1
:
7833 vec_cond
= (given
& 0x0080) >> 7;
7834 func (stream
, "%s",vec_condnames
[vec_cond
]);
7837 case MVE_VPT_VEC_T2
:
7838 case MVE_VCMP_VEC_T2
:
7839 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7840 func (stream
, "%s",vec_condnames
[vec_cond
]);
7843 case MVE_VPT_VEC_T3
:
7844 case MVE_VCMP_VEC_T3
:
7845 vec_cond
= 4 | ((given
& 1) << 1) | ((given
& 0x0080) >> 7);
7846 func (stream
, "%s",vec_condnames
[vec_cond
]);
7849 case MVE_VPT_VEC_T4
:
7850 case MVE_VCMP_VEC_T4
:
7851 vec_cond
= (given
& 0x0080) >> 7;
7852 func (stream
, "%s",vec_condnames
[vec_cond
]);
7855 case MVE_VPT_VEC_T5
:
7856 case MVE_VCMP_VEC_T5
:
7857 vec_cond
= 2 | ((given
& 0x0080) >> 7);
7858 func (stream
, "%s",vec_condnames
[vec_cond
]);
7861 case MVE_VPT_VEC_T6
:
7862 case MVE_VCMP_VEC_T6
:
7863 vec_cond
= 4 | ((given
& 0x0020) >> 4) | ((given
& 0x0080) >> 7);
7864 func (stream
, "%s",vec_condnames
[vec_cond
]);
7879 #define WRITEBACK_BIT_SET (given & (1 << W_BIT))
7880 #define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
7881 #define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
7882 #define PRE_BIT_SET (given & (1 << P_BIT))
7885 /* Print one coprocessor instruction on INFO->STREAM.
7886 Return TRUE if the instuction matched, FALSE if this is not a
7887 recognised coprocessor instruction. */
7890 print_insn_coprocessor (bfd_vma pc
,
7891 struct disassemble_info
*info
,
7895 const struct sopcode32
*insn
;
7896 void *stream
= info
->stream
;
7897 fprintf_ftype func
= info
->fprintf_func
;
7899 unsigned long value
= 0;
7902 struct arm_private_data
*private_data
= info
->private_data
;
7903 arm_feature_set allowed_arches
= ARM_ARCH_NONE
;
7904 arm_feature_set arm_ext_v8_1m_main
=
7905 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
7907 allowed_arches
= private_data
->features
;
7909 for (insn
= coprocessor_opcodes
; insn
->assembler
; insn
++)
7911 unsigned long u_reg
= 16;
7912 bfd_boolean is_unpredictable
= FALSE
;
7913 signed long value_in_comment
= 0;
7916 if (ARM_FEATURE_ZERO (insn
->arch
))
7917 switch (insn
->value
)
7919 case SENTINEL_IWMMXT_START
:
7920 if (info
->mach
!= bfd_mach_arm_XScale
7921 && info
->mach
!= bfd_mach_arm_iWMMXt
7922 && info
->mach
!= bfd_mach_arm_iWMMXt2
)
7925 while ((! ARM_FEATURE_ZERO (insn
->arch
))
7926 && insn
->value
!= SENTINEL_IWMMXT_END
);
7929 case SENTINEL_IWMMXT_END
:
7932 case SENTINEL_GENERIC_START
:
7933 allowed_arches
= private_data
->features
;
7941 value
= insn
->value
;
7942 cp_num
= (given
>> 8) & 0xf;
7946 /* The high 4 bits are 0xe for Arm conditional instructions, and
7947 0xe for arm unconditional instructions. The rest of the
7948 encoding is the same. */
7950 value
|= 0xe0000000;
7958 /* Only match unconditional instuctions against unconditional
7960 if ((given
& 0xf0000000) == 0xf0000000)
7967 cond
= (given
>> 28) & 0xf;
7973 if ((insn
->isa
== T32
&& !thumb
)
7974 || (insn
->isa
== ARM
&& thumb
))
7977 if ((given
& mask
) != value
)
7980 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, allowed_arches
))
7983 if (insn
->value
== 0xfe000010 /* mcr2 */
7984 || insn
->value
== 0xfe100010 /* mrc2 */
7985 || insn
->value
== 0xfc100000 /* ldc2 */
7986 || insn
->value
== 0xfc000000) /* stc2 */
7988 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
7989 is_unpredictable
= TRUE
;
7991 /* Armv8.1-M Mainline FP & MVE instructions. */
7992 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
7993 && !ARM_CPU_IS_ANY (allowed_arches
)
7994 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
7998 else if (insn
->value
== 0x0e000000 /* cdp */
7999 || insn
->value
== 0xfe000000 /* cdp2 */
8000 || insn
->value
== 0x0e000010 /* mcr */
8001 || insn
->value
== 0x0e100010 /* mrc */
8002 || insn
->value
== 0x0c100000 /* ldc */
8003 || insn
->value
== 0x0c000000) /* stc */
8005 /* Floating-point instructions. */
8006 if (cp_num
== 9 || cp_num
== 10 || cp_num
== 11)
8009 /* Armv8.1-M Mainline FP & MVE instructions. */
8010 if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main
, allowed_arches
)
8011 && !ARM_CPU_IS_ANY (allowed_arches
)
8012 && (cp_num
== 8 || cp_num
== 14 || cp_num
== 15))
8015 else if ((insn
->value
== 0xec100f80 /* vldr (system register) */
8016 || insn
->value
== 0xec000f80) /* vstr (system register) */
8017 && arm_decode_field (given
, 24, 24) == 0
8018 && arm_decode_field (given
, 21, 21) == 0)
8019 /* If the P and W bits are both 0 then these encodings match the MVE
8020 VLDR and VSTR instructions, these are in a different table, so we
8021 don't let it match here. */
8024 for (c
= insn
->assembler
; *c
; c
++)
8028 const char mod
= *++c
;
8032 func (stream
, "%%");
8038 int rn
= (given
>> 16) & 0xf;
8039 bfd_vma offset
= given
& 0xff;
8042 offset
= given
& 0x7f;
8044 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8046 if (PRE_BIT_SET
|| WRITEBACK_BIT_SET
)
8048 /* Not unindexed. The offset is scaled. */
8050 /* vldr.16/vstr.16 will shift the address
8051 left by 1 bit only. */
8052 offset
= offset
* 2;
8054 offset
= offset
* 4;
8056 if (NEGATIVE_BIT_SET
)
8059 value_in_comment
= offset
;
8065 func (stream
, ", #%d]%s",
8067 WRITEBACK_BIT_SET
? "!" : "");
8068 else if (NEGATIVE_BIT_SET
)
8069 func (stream
, ", #-0]");
8077 if (WRITEBACK_BIT_SET
)
8080 func (stream
, ", #%d", (int) offset
);
8081 else if (NEGATIVE_BIT_SET
)
8082 func (stream
, ", #-0");
8086 func (stream
, ", {%s%d}",
8087 (NEGATIVE_BIT_SET
&& !offset
) ? "-" : "",
8089 value_in_comment
= offset
;
8092 if (rn
== 15 && (PRE_BIT_SET
|| WRITEBACK_BIT_SET
))
8094 func (stream
, "\t; ");
8095 /* For unaligned PCs, apply off-by-alignment
8097 info
->print_address_func (offset
+ pc
8098 + info
->bytes_per_chunk
* 2
8107 int regno
= ((given
>> 12) & 0xf) | ((given
>> (22 - 4)) & 0x10);
8108 int offset
= (given
>> 1) & 0x3f;
8111 func (stream
, "{d%d}", regno
);
8112 else if (regno
+ offset
> 32)
8113 func (stream
, "{d%d-<overflow reg d%d>}", regno
, regno
+ offset
- 1);
8115 func (stream
, "{d%d-d%d}", regno
, regno
+ offset
- 1);
8121 bfd_boolean single
= ((given
>> 8) & 1) == 0;
8122 char reg_prefix
= single
? 's' : 'd';
8123 int Dreg
= (given
>> 22) & 0x1;
8124 int Vdreg
= (given
>> 12) & 0xf;
8125 int reg
= single
? ((Vdreg
<< 1) | Dreg
)
8126 : ((Dreg
<< 4) | Vdreg
);
8127 int num
= (given
>> (single
? 0 : 1)) & 0x7f;
8128 int maxreg
= single
? 31 : 15;
8129 int topreg
= reg
+ num
- 1;
8132 func (stream
, "{VPR}");
8134 func (stream
, "{%c%d, VPR}", reg_prefix
, reg
);
8135 else if (topreg
> maxreg
)
8136 func (stream
, "{%c%d-<overflow reg d%d, VPR}",
8137 reg_prefix
, reg
, single
? topreg
>> 1 : topreg
);
8139 func (stream
, "{%c%d-%c%d, VPR}", reg_prefix
, reg
,
8140 reg_prefix
, topreg
);
8145 if (cond
!= COND_UNCOND
)
8146 is_unpredictable
= TRUE
;
8150 if (cond
!= COND_UNCOND
&& cp_num
== 9)
8151 is_unpredictable
= TRUE
;
8153 func (stream
, "%s", arm_conditional
[cond
]);
8157 /* Print a Cirrus/DSP shift immediate. */
8158 /* Immediates are 7bit signed ints with bits 0..3 in
8159 bits 0..3 of opcode and bits 4..6 in bits 5..7
8164 imm
= (given
& 0xf) | ((given
& 0xe0) >> 1);
8166 /* Is ``imm'' a negative number? */
8170 func (stream
, "%d", imm
);
8178 = arm_decode_field_multiple (given
, 13, 15, 22, 22);
8183 func (stream
, "FPSCR");
8186 func (stream
, "FPSCR_nzcvqc");
8189 func (stream
, "VPR");
8192 func (stream
, "P0");
8195 func (stream
, "FPCXTNS");
8198 func (stream
, "FPCXTS");
8201 func (stream
, "<invalid reg %lu>", regno
);
8208 switch (given
& 0x00408000)
8225 switch (given
& 0x00080080)
8237 func (stream
, _("<illegal precision>"));
8243 switch (given
& 0x00408000)
8261 switch (given
& 0x60)
8277 case '0': case '1': case '2': case '3': case '4':
8278 case '5': case '6': case '7': case '8': case '9':
8282 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
8288 is_unpredictable
= TRUE
;
8293 /* Eat the 'u' character. */
8297 is_unpredictable
= TRUE
;
8300 func (stream
, "%s", arm_regnames
[value
]);
8303 if (given
& (1 << 6))
8307 func (stream
, "d%ld", value
);
8312 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
8314 func (stream
, "q%ld", value
>> 1);
8317 func (stream
, "%ld", value
);
8318 value_in_comment
= value
;
8322 /* Converts immediate 8 bit back to float value. */
8323 unsigned floatVal
= (value
& 0x80) << 24
8324 | (value
& 0x3F) << 19
8325 | ((value
& 0x40) ? (0xF8 << 22) : (1 << 30));
8327 /* Quarter float have a maximum value of 31.0.
8328 Get floating point value multiplied by 1e7.
8329 The maximum value stays in limit of a 32-bit int. */
8331 (78125 << (((floatVal
>> 23) & 0xFF) - 124)) *
8332 (16 + (value
& 0xF));
8334 if (!(decVal
% 1000000))
8335 func (stream
, "%ld\t; 0x%08x %c%u.%01u", value
,
8336 floatVal
, value
& 0x80 ? '-' : ' ',
8338 decVal
% 10000000 / 1000000);
8339 else if (!(decVal
% 10000))
8340 func (stream
, "%ld\t; 0x%08x %c%u.%03u", value
,
8341 floatVal
, value
& 0x80 ? '-' : ' ',
8343 decVal
% 10000000 / 10000);
8345 func (stream
, "%ld\t; 0x%08x %c%u.%07u", value
,
8346 floatVal
, value
& 0x80 ? '-' : ' ',
8347 decVal
/ 10000000, decVal
% 10000000);
8352 int from
= (given
& (1 << 7)) ? 32 : 16;
8353 func (stream
, "%ld", from
- value
);
8359 func (stream
, "#%s", arm_fp_const
[value
& 7]);
8361 func (stream
, "f%ld", value
);
8366 func (stream
, "%s", iwmmxt_wwnames
[value
]);
8368 func (stream
, "%s", iwmmxt_wwssnames
[value
]);
8372 func (stream
, "%s", iwmmxt_regnames
[value
]);
8375 func (stream
, "%s", iwmmxt_cregnames
[value
]);
8379 func (stream
, "0x%lx", (value
& 0xffffffffUL
));
8386 func (stream
, "eq");
8390 func (stream
, "vs");
8394 func (stream
, "ge");
8398 func (stream
, "gt");
8402 func (stream
, "??");
8410 func (stream
, "%c", *c
);
8414 if (value
== ((1ul << width
) - 1))
8415 func (stream
, "%c", *c
);
8418 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
8430 int single
= *c
++ == 'y';
8435 case '4': /* Sm pair */
8436 case '0': /* Sm, Dm */
8437 regno
= given
& 0x0000000f;
8441 regno
+= (given
>> 5) & 1;
8444 regno
+= ((given
>> 5) & 1) << 4;
8447 case '1': /* Sd, Dd */
8448 regno
= (given
>> 12) & 0x0000000f;
8452 regno
+= (given
>> 22) & 1;
8455 regno
+= ((given
>> 22) & 1) << 4;
8458 case '2': /* Sn, Dn */
8459 regno
= (given
>> 16) & 0x0000000f;
8463 regno
+= (given
>> 7) & 1;
8466 regno
+= ((given
>> 7) & 1) << 4;
8469 case '3': /* List */
8471 regno
= (given
>> 12) & 0x0000000f;
8475 regno
+= (given
>> 22) & 1;
8478 regno
+= ((given
>> 22) & 1) << 4;
8485 func (stream
, "%c%d", single
? 's' : 'd', regno
);
8489 int count
= given
& 0xff;
8496 func (stream
, "-%c%d",
8504 func (stream
, ", %c%d", single
? 's' : 'd',
8510 switch (given
& 0x00400100)
8512 case 0x00000000: func (stream
, "b"); break;
8513 case 0x00400000: func (stream
, "h"); break;
8514 case 0x00000100: func (stream
, "w"); break;
8515 case 0x00400100: func (stream
, "d"); break;
8523 /* given (20, 23) | given (0, 3) */
8524 value
= ((given
>> 16) & 0xf0) | (given
& 0xf);
8525 func (stream
, "%d", (int) value
);
8530 /* This is like the 'A' operator, except that if
8531 the width field "M" is zero, then the offset is
8532 *not* multiplied by four. */
8534 int offset
= given
& 0xff;
8535 int multiplier
= (given
& 0x00000100) ? 4 : 1;
8537 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
8541 value_in_comment
= offset
* multiplier
;
8542 if (NEGATIVE_BIT_SET
)
8543 value_in_comment
= - value_in_comment
;
8549 func (stream
, ", #%s%d]%s",
8550 NEGATIVE_BIT_SET
? "-" : "",
8551 offset
* multiplier
,
8552 WRITEBACK_BIT_SET
? "!" : "");
8554 func (stream
, "], #%s%d",
8555 NEGATIVE_BIT_SET
? "-" : "",
8556 offset
* multiplier
);
8565 int imm4
= (given
>> 4) & 0xf;
8566 int puw_bits
= ((given
>> 22) & 6) | ((given
>> W_BIT
) & 1);
8567 int ubit
= ! NEGATIVE_BIT_SET
;
8568 const char *rm
= arm_regnames
[given
& 0xf];
8569 const char *rn
= arm_regnames
[(given
>> 16) & 0xf];
8575 func (stream
, "[%s], %c%s", rn
, ubit
? '+' : '-', rm
);
8577 func (stream
, ", lsl #%d", imm4
);
8584 func (stream
, "[%s, %c%s", rn
, ubit
? '+' : '-', rm
);
8586 func (stream
, ", lsl #%d", imm4
);
8588 if (puw_bits
== 5 || puw_bits
== 7)
8593 func (stream
, "INVALID");
8601 imm5
= ((given
& 0x100) >> 4) | (given
& 0xf);
8602 func (stream
, "%ld", (imm5
== 0) ? 32 : imm5
);
8611 func (stream
, "%c", *c
);
8614 if (value_in_comment
> 32 || value_in_comment
< -16)
8615 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
8617 if (is_unpredictable
)
8618 func (stream
, UNPREDICTABLE_INSTRUCTION
);
8625 /* Decodes and prints ARM addressing modes. Returns the offset
8626 used in the address, if any, if it is worthwhile printing the
8627 offset as a hexadecimal value in a comment at the end of the
8628 line of disassembly. */
8631 print_arm_address (bfd_vma pc
, struct disassemble_info
*info
, long given
)
8633 void *stream
= info
->stream
;
8634 fprintf_ftype func
= info
->fprintf_func
;
8637 if (((given
& 0x000f0000) == 0x000f0000)
8638 && ((given
& 0x02000000) == 0))
8640 offset
= given
& 0xfff;
8642 func (stream
, "[pc");
8646 /* Pre-indexed. Elide offset of positive zero when
8648 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8649 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8651 if (NEGATIVE_BIT_SET
)
8656 /* Cope with the possibility of write-back
8657 being used. Probably a very dangerous thing
8658 for the programmer to do, but who are we to
8660 func (stream
, "]%s", WRITEBACK_BIT_SET
? "!" : "");
8662 else /* Post indexed. */
8664 func (stream
, "], #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8666 /* Ie ignore the offset. */
8670 func (stream
, "\t; ");
8671 info
->print_address_func (offset
, info
);
8676 func (stream
, "[%s",
8677 arm_regnames
[(given
>> 16) & 0xf]);
8681 if ((given
& 0x02000000) == 0)
8683 /* Elide offset of positive zero when non-writeback. */
8684 offset
= given
& 0xfff;
8685 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
|| offset
)
8686 func (stream
, ", #%s%d", NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8690 func (stream
, ", %s", NEGATIVE_BIT_SET
? "-" : "");
8691 arm_decode_shift (given
, func
, stream
, TRUE
);
8694 func (stream
, "]%s",
8695 WRITEBACK_BIT_SET
? "!" : "");
8699 if ((given
& 0x02000000) == 0)
8701 /* Always show offset. */
8702 offset
= given
& 0xfff;
8703 func (stream
, "], #%s%d",
8704 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
8708 func (stream
, "], %s",
8709 NEGATIVE_BIT_SET
? "-" : "");
8710 arm_decode_shift (given
, func
, stream
, TRUE
);
8713 if (NEGATIVE_BIT_SET
)
8717 return (signed long) offset
;
8720 /* Print one neon instruction on INFO->STREAM.
8721 Return TRUE if the instuction matched, FALSE if this is not a
8722 recognised neon instruction. */
8725 print_insn_neon (struct disassemble_info
*info
, long given
, bfd_boolean thumb
)
8727 const struct opcode32
*insn
;
8728 void *stream
= info
->stream
;
8729 fprintf_ftype func
= info
->fprintf_func
;
8733 if ((given
& 0xef000000) == 0xef000000)
8735 /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
8736 unsigned long bit28
= given
& (1 << 28);
8738 given
&= 0x00ffffff;
8740 given
|= 0xf3000000;
8742 given
|= 0xf2000000;
8744 else if ((given
& 0xff000000) == 0xf9000000)
8745 given
^= 0xf9000000 ^ 0xf4000000;
8746 /* vdup is also a valid neon instruction. */
8747 else if ((given
& 0xff910f5f) != 0xee800b10)
8751 for (insn
= neon_opcodes
; insn
->assembler
; insn
++)
8753 if ((given
& insn
->mask
) == insn
->value
)
8755 signed long value_in_comment
= 0;
8756 bfd_boolean is_unpredictable
= FALSE
;
8759 for (c
= insn
->assembler
; *c
; c
++)
8766 func (stream
, "%%");
8770 if (thumb
&& ifthen_state
)
8771 is_unpredictable
= TRUE
;
8775 if (thumb
&& ifthen_state
)
8776 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
8781 static const unsigned char enc
[16] =
8783 0x4, 0x14, /* st4 0,1 */
8795 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8796 int rn
= ((given
>> 16) & 0xf);
8797 int rm
= ((given
>> 0) & 0xf);
8798 int align
= ((given
>> 4) & 0x3);
8799 int type
= ((given
>> 8) & 0xf);
8800 int n
= enc
[type
] & 0xf;
8801 int stride
= (enc
[type
] >> 4) + 1;
8806 for (ix
= 0; ix
!= n
; ix
++)
8807 func (stream
, "%sd%d", ix
? "," : "", rd
+ ix
* stride
);
8809 func (stream
, "d%d", rd
);
8811 func (stream
, "d%d-d%d", rd
, rd
+ n
- 1);
8812 func (stream
, "}, [%s", arm_regnames
[rn
]);
8814 func (stream
, " :%d", 32 << align
);
8819 func (stream
, ", %s", arm_regnames
[rm
]);
8825 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8826 int rn
= ((given
>> 16) & 0xf);
8827 int rm
= ((given
>> 0) & 0xf);
8828 int idx_align
= ((given
>> 4) & 0xf);
8830 int size
= ((given
>> 10) & 0x3);
8831 int idx
= idx_align
>> (size
+ 1);
8832 int length
= ((given
>> 8) & 3) + 1;
8836 if (length
> 1 && size
> 0)
8837 stride
= (idx_align
& (1 << size
)) ? 2 : 1;
8843 int amask
= (1 << size
) - 1;
8844 if ((idx_align
& (1 << size
)) != 0)
8848 if ((idx_align
& amask
) == amask
)
8850 else if ((idx_align
& amask
) != 0)
8857 if (size
== 2 && (idx_align
& 2) != 0)
8859 align
= (idx_align
& 1) ? 16 << size
: 0;
8863 if ((size
== 2 && (idx_align
& 3) != 0)
8864 || (idx_align
& 1) != 0)
8871 if ((idx_align
& 3) == 3)
8873 align
= (idx_align
& 3) * 64;
8876 align
= (idx_align
& 1) ? 32 << size
: 0;
8884 for (i
= 0; i
< length
; i
++)
8885 func (stream
, "%sd%d[%d]", (i
== 0) ? "" : ",",
8886 rd
+ i
* stride
, idx
);
8887 func (stream
, "}, [%s", arm_regnames
[rn
]);
8889 func (stream
, " :%d", align
);
8894 func (stream
, ", %s", arm_regnames
[rm
]);
8900 int rd
= ((given
>> 12) & 0xf) | (((given
>> 22) & 1) << 4);
8901 int rn
= ((given
>> 16) & 0xf);
8902 int rm
= ((given
>> 0) & 0xf);
8903 int align
= ((given
>> 4) & 0x1);
8904 int size
= ((given
>> 6) & 0x3);
8905 int type
= ((given
>> 8) & 0x3);
8907 int stride
= ((given
>> 5) & 0x1);
8910 if (stride
&& (n
== 1))
8917 for (ix
= 0; ix
!= n
; ix
++)
8918 func (stream
, "%sd%d[]", ix
? "," : "", rd
+ ix
* stride
);
8920 func (stream
, "d%d[]", rd
);
8922 func (stream
, "d%d[]-d%d[]", rd
, rd
+ n
- 1);
8923 func (stream
, "}, [%s", arm_regnames
[rn
]);
8926 align
= (8 * (type
+ 1)) << size
;
8928 align
= (size
> 1) ? align
>> 1 : align
;
8929 if (type
== 2 || (type
== 0 && !size
))
8930 func (stream
, " :<bad align %d>", align
);
8932 func (stream
, " :%d", align
);
8938 func (stream
, ", %s", arm_regnames
[rm
]);
8944 int raw_reg
= (given
& 0xf) | ((given
>> 1) & 0x10);
8945 int size
= (given
>> 20) & 3;
8946 int reg
= raw_reg
& ((4 << size
) - 1);
8947 int ix
= raw_reg
>> size
>> 2;
8949 func (stream
, "d%d[%d]", reg
, ix
);
8954 /* Neon encoded constant for mov, mvn, vorr, vbic. */
8957 int cmode
= (given
>> 8) & 0xf;
8958 int op
= (given
>> 5) & 0x1;
8959 unsigned long value
= 0, hival
= 0;
8964 bits
|= ((given
>> 24) & 1) << 7;
8965 bits
|= ((given
>> 16) & 7) << 4;
8966 bits
|= ((given
>> 0) & 15) << 0;
8970 shift
= (cmode
>> 1) & 3;
8971 value
= (unsigned long) bits
<< (8 * shift
);
8974 else if (cmode
< 12)
8976 shift
= (cmode
>> 1) & 1;
8977 value
= (unsigned long) bits
<< (8 * shift
);
8980 else if (cmode
< 14)
8982 shift
= (cmode
& 1) + 1;
8983 value
= (unsigned long) bits
<< (8 * shift
);
8984 value
|= (1ul << (8 * shift
)) - 1;
8987 else if (cmode
== 14)
8991 /* Bit replication into bytes. */
8997 for (ix
= 7; ix
>= 0; ix
--)
8999 mask
= ((bits
>> ix
) & 1) ? 0xff : 0;
9001 value
= (value
<< 8) | mask
;
9003 hival
= (hival
<< 8) | mask
;
9009 /* Byte replication. */
9010 value
= (unsigned long) bits
;
9016 /* Floating point encoding. */
9019 value
= (unsigned long) (bits
& 0x7f) << 19;
9020 value
|= (unsigned long) (bits
& 0x80) << 24;
9021 tmp
= bits
& 0x40 ? 0x3c : 0x40;
9022 value
|= (unsigned long) tmp
<< 24;
9028 func (stream
, "<illegal constant %.8x:%x:%x>",
9036 func (stream
, "#%ld\t; 0x%.2lx", value
, value
);
9040 func (stream
, "#%ld\t; 0x%.4lx", value
, value
);
9046 unsigned char valbytes
[4];
9049 /* Do this a byte at a time so we don't have to
9050 worry about the host's endianness. */
9051 valbytes
[0] = value
& 0xff;
9052 valbytes
[1] = (value
>> 8) & 0xff;
9053 valbytes
[2] = (value
>> 16) & 0xff;
9054 valbytes
[3] = (value
>> 24) & 0xff;
9056 floatformat_to_double
9057 (& floatformat_ieee_single_little
, valbytes
,
9060 func (stream
, "#%.7g\t; 0x%.8lx", fvalue
,
9064 func (stream
, "#%ld\t; 0x%.8lx",
9065 (long) (((value
& 0x80000000L
) != 0)
9066 ? value
| ~0xffffffffL
: value
),
9071 func (stream
, "#0x%.8lx%.8lx", hival
, value
);
9082 int regno
= ((given
>> 16) & 0xf) | ((given
>> (7 - 4)) & 0x10);
9083 int num
= (given
>> 8) & 0x3;
9086 func (stream
, "{d%d}", regno
);
9087 else if (num
+ regno
>= 32)
9088 func (stream
, "{d%d-<overflow reg d%d}", regno
, regno
+ num
);
9090 func (stream
, "{d%d-d%d}", regno
, regno
+ num
);
9095 case '0': case '1': case '2': case '3': case '4':
9096 case '5': case '6': case '7': case '8': case '9':
9099 unsigned long value
;
9101 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9106 func (stream
, "%s", arm_regnames
[value
]);
9109 func (stream
, "%ld", value
);
9110 value_in_comment
= value
;
9113 func (stream
, "%ld", (1ul << width
) - value
);
9119 /* Various width encodings. */
9121 int base
= 8 << (*c
- 'S'); /* 8,16 or 32 */
9126 if (*c
>= '0' && *c
<= '9')
9128 else if (*c
>= 'a' && *c
<= 'f')
9129 limit
= *c
- 'a' + 10;
9135 if (value
< low
|| value
> high
)
9136 func (stream
, "<illegal width %d>", base
<< value
);
9138 func (stream
, "%d", base
<< value
);
9142 if (given
& (1 << 6))
9146 func (stream
, "d%ld", value
);
9151 func (stream
, "<illegal reg q%ld.5>", value
>> 1);
9153 func (stream
, "q%ld", value
>> 1);
9159 func (stream
, "%c", *c
);
9163 if (value
== ((1ul << width
) - 1))
9164 func (stream
, "%c", *c
);
9167 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
9181 func (stream
, "%c", *c
);
9184 if (value_in_comment
> 32 || value_in_comment
< -16)
9185 func (stream
, "\t; 0x%lx", value_in_comment
);
9187 if (is_unpredictable
)
9188 func (stream
, UNPREDICTABLE_INSTRUCTION
);
9196 /* Print one mve instruction on INFO->STREAM.
9197 Return TRUE if the instuction matched, FALSE if this is not a
9198 recognised mve instruction. */
9201 print_insn_mve (struct disassemble_info
*info
, long given
)
9203 const struct mopcode32
*insn
;
9204 void *stream
= info
->stream
;
9205 fprintf_ftype func
= info
->fprintf_func
;
9207 for (insn
= mve_opcodes
; insn
->assembler
; insn
++)
9209 if (((given
& insn
->mask
) == insn
->value
)
9210 && !is_mve_encoding_conflict (given
, insn
->mve_op
))
9212 signed long value_in_comment
= 0;
9213 bfd_boolean is_unpredictable
= FALSE
;
9214 bfd_boolean is_undefined
= FALSE
;
9216 enum mve_unpredictable unpredictable_cond
= UNPRED_NONE
;
9217 enum mve_undefined undefined_cond
= UNDEF_NONE
;
9219 /* Most vector mve instruction are illegal in a it block.
9220 There are a few exceptions; check for them. */
9221 if (ifthen_state
&& !is_mve_okay_in_it (insn
->mve_op
))
9223 is_unpredictable
= TRUE
;
9224 unpredictable_cond
= UNPRED_IT_BLOCK
;
9226 else if (is_mve_unpredictable (given
, insn
->mve_op
,
9227 &unpredictable_cond
))
9228 is_unpredictable
= TRUE
;
9230 if (is_mve_undefined (given
, insn
->mve_op
, &undefined_cond
))
9231 is_undefined
= TRUE
;
9233 /* In "VORR Qd, Qm, Qn", if Qm==Qn, VORR is nothing but VMOV,
9234 i.e "VMOV Qd, Qm". */
9235 if ((insn
->mve_op
== MVE_VORR_REG
)
9236 && (arm_decode_field (given
, 1, 3)
9237 == arm_decode_field (given
, 17, 19)))
9240 for (c
= insn
->assembler
; *c
; c
++)
9247 func (stream
, "%%");
9251 /* Don't print anything for '+' as it is implied. */
9252 if (arm_decode_field (given
, 23, 23) == 0)
9258 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
9262 print_mve_vld_str_addr (info
, given
, insn
->mve_op
);
9267 long mve_mask
= mve_extract_pred_mask (given
);
9268 func (stream
, "%s", mve_predicatenames
[mve_mask
]);
9274 unsigned int imm5
= 0;
9275 imm5
|= arm_decode_field (given
, 6, 7);
9276 imm5
|= (arm_decode_field (given
, 12, 14) << 2);
9277 func (stream
, "#%u", (imm5
== 0) ? 32 : imm5
);
9282 func (stream
, "#%u",
9283 (arm_decode_field (given
, 7, 7) == 0) ? 64 : 48);
9287 print_vec_condition (info
, given
, insn
->mve_op
);
9291 if (arm_decode_field (given
, 0, 0) == 1)
9294 = arm_decode_field (given
, 4, 4)
9295 | (arm_decode_field (given
, 6, 6) << 1);
9297 func (stream
, ", uxtw #%lu", size
);
9302 print_mve_rounding_mode (info
, given
, insn
->mve_op
);
9306 print_mve_vcvt_size (info
, given
, insn
->mve_op
);
9311 unsigned long op1
= arm_decode_field (given
, 21, 22);
9313 if ((insn
->mve_op
== MVE_VMOV_VEC_LANE_TO_GP
))
9315 /* Check for signed. */
9316 if (arm_decode_field (given
, 23, 23) == 0)
9318 /* We don't print 's' for S32. */
9319 if ((arm_decode_field (given
, 5, 6) == 0)
9320 && ((op1
== 0) || (op1
== 1)))
9330 if (arm_decode_field (given
, 28, 28) == 0)
9339 print_instruction_predicate (info
);
9343 if (arm_decode_field (given
, 21, 21) == 1)
9348 print_mve_register_blocks (info
, given
, insn
->mve_op
);
9352 /* SIMD encoded constant for mov, mvn, vorr, vbic. */
9354 print_simd_imm8 (info
, given
, 28, insn
);
9358 print_mve_vmov_index (info
, given
);
9362 if (arm_decode_field (given
, 12, 12) == 0)
9369 if (arm_decode_field (given
, 12, 12) == 1)
9373 case '0': case '1': case '2': case '3': case '4':
9374 case '5': case '6': case '7': case '8': case '9':
9377 unsigned long value
;
9379 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
9385 is_unpredictable
= TRUE
;
9386 else if (value
== 15)
9387 func (stream
, "zr");
9389 func (stream
, "%s", arm_regnames
[value
]);
9393 func (stream
, "%s", arm_conditional
[value
]);
9398 func (stream
, "%s", arm_conditional
[value
]);
9402 if (value
== 13 || value
== 15)
9403 is_unpredictable
= TRUE
;
9405 func (stream
, "%s", arm_regnames
[value
]);
9409 print_mve_size (info
,
9423 unsigned int odd_reg
= (value
<< 1) | 1;
9424 func (stream
, "%s", arm_regnames
[odd_reg
]);
9430 = arm_decode_field (given
, 0, 6);
9431 unsigned long mod_imm
= imm
;
9433 switch (insn
->mve_op
)
9435 case MVE_VLDRW_GATHER_T5
:
9436 case MVE_VSTRW_SCATTER_T5
:
9437 mod_imm
= mod_imm
<< 2;
9439 case MVE_VSTRD_SCATTER_T6
:
9440 case MVE_VLDRD_GATHER_T6
:
9441 mod_imm
= mod_imm
<< 3;
9448 func (stream
, "%lu", mod_imm
);
9452 func (stream
, "%lu", 64 - value
);
9456 unsigned int even_reg
= value
<< 1;
9457 func (stream
, "%s", arm_regnames
[even_reg
]);
9480 print_mve_rotate (info
, value
, width
);
9483 func (stream
, "%s", arm_regnames
[value
]);
9486 if (insn
->mve_op
== MVE_VQSHL_T2
9487 || insn
->mve_op
== MVE_VQSHLU_T3
9488 || insn
->mve_op
== MVE_VRSHR
9489 || insn
->mve_op
== MVE_VRSHRN
9490 || insn
->mve_op
== MVE_VSHL_T1
9491 || insn
->mve_op
== MVE_VSHLL_T1
9492 || insn
->mve_op
== MVE_VSHR
9493 || insn
->mve_op
== MVE_VSHRN
9494 || insn
->mve_op
== MVE_VSLI
9495 || insn
->mve_op
== MVE_VSRI
)
9496 print_mve_shift_n (info
, given
, insn
->mve_op
);
9497 else if (insn
->mve_op
== MVE_VSHLL_T2
)
9505 func (stream
, "16");
9508 print_mve_undefined (info
, UNDEF_SIZE_0
);
9517 if (insn
->mve_op
== MVE_VSHLC
&& value
== 0)
9519 func (stream
, "%ld", value
);
9520 value_in_comment
= value
;
9524 func (stream
, "s%ld", value
);
9528 func (stream
, "<illegal reg q%ld.5>", value
);
9530 func (stream
, "q%ld", value
);
9533 func (stream
, "0x%08lx", value
);
9545 func (stream
, "%c", *c
);
9548 if (value_in_comment
> 32 || value_in_comment
< -16)
9549 func (stream
, "\t; 0x%lx", value_in_comment
);
9551 if (is_unpredictable
)
9552 print_mve_unpredictable (info
, unpredictable_cond
);
9555 print_mve_undefined (info
, undefined_cond
);
9557 if ((vpt_block_state
.in_vpt_block
== FALSE
)
9559 && (is_vpt_instruction (given
) == TRUE
))
9560 mark_inside_vpt_block (given
);
9561 else if (vpt_block_state
.in_vpt_block
== TRUE
)
9562 update_vpt_block_state ();
9571 /* Return the name of a v7A special register. */
9574 banked_regname (unsigned reg
)
9578 case 15: return "CPSR";
9579 case 32: return "R8_usr";
9580 case 33: return "R9_usr";
9581 case 34: return "R10_usr";
9582 case 35: return "R11_usr";
9583 case 36: return "R12_usr";
9584 case 37: return "SP_usr";
9585 case 38: return "LR_usr";
9586 case 40: return "R8_fiq";
9587 case 41: return "R9_fiq";
9588 case 42: return "R10_fiq";
9589 case 43: return "R11_fiq";
9590 case 44: return "R12_fiq";
9591 case 45: return "SP_fiq";
9592 case 46: return "LR_fiq";
9593 case 48: return "LR_irq";
9594 case 49: return "SP_irq";
9595 case 50: return "LR_svc";
9596 case 51: return "SP_svc";
9597 case 52: return "LR_abt";
9598 case 53: return "SP_abt";
9599 case 54: return "LR_und";
9600 case 55: return "SP_und";
9601 case 60: return "LR_mon";
9602 case 61: return "SP_mon";
9603 case 62: return "ELR_hyp";
9604 case 63: return "SP_hyp";
9605 case 79: return "SPSR";
9606 case 110: return "SPSR_fiq";
9607 case 112: return "SPSR_irq";
9608 case 114: return "SPSR_svc";
9609 case 116: return "SPSR_abt";
9610 case 118: return "SPSR_und";
9611 case 124: return "SPSR_mon";
9612 case 126: return "SPSR_hyp";
9613 default: return NULL
;
9617 /* Return the name of the DMB/DSB option. */
9619 data_barrier_option (unsigned option
)
9621 switch (option
& 0xf)
9623 case 0xf: return "sy";
9624 case 0xe: return "st";
9625 case 0xd: return "ld";
9626 case 0xb: return "ish";
9627 case 0xa: return "ishst";
9628 case 0x9: return "ishld";
9629 case 0x7: return "un";
9630 case 0x6: return "unst";
9631 case 0x5: return "nshld";
9632 case 0x3: return "osh";
9633 case 0x2: return "oshst";
9634 case 0x1: return "oshld";
9635 default: return NULL
;
9639 /* Print one ARM instruction from PC on INFO->STREAM. */
9642 print_insn_arm (bfd_vma pc
, struct disassemble_info
*info
, long given
)
9644 const struct opcode32
*insn
;
9645 void *stream
= info
->stream
;
9646 fprintf_ftype func
= info
->fprintf_func
;
9647 struct arm_private_data
*private_data
= info
->private_data
;
9649 if (print_insn_coprocessor (pc
, info
, given
, FALSE
))
9652 if (print_insn_neon (info
, given
, FALSE
))
9655 for (insn
= arm_opcodes
; insn
->assembler
; insn
++)
9657 if ((given
& insn
->mask
) != insn
->value
)
9660 if (! ARM_CPU_HAS_FEATURE (insn
->arch
, private_data
->features
))
9663 /* Special case: an instruction with all bits set in the condition field
9664 (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
9665 or by the catchall at the end of the table. */
9666 if ((given
& 0xF0000000) != 0xF0000000
9667 || (insn
->mask
& 0xF0000000) == 0xF0000000
9668 || (insn
->mask
== 0 && insn
->value
== 0))
9670 unsigned long u_reg
= 16;
9671 unsigned long U_reg
= 16;
9672 bfd_boolean is_unpredictable
= FALSE
;
9673 signed long value_in_comment
= 0;
9676 for (c
= insn
->assembler
; *c
; c
++)
9680 bfd_boolean allow_unpredictable
= FALSE
;
9685 func (stream
, "%%");
9689 value_in_comment
= print_arm_address (pc
, info
, given
);
9693 /* Set P address bit and use normal address
9694 printing routine. */
9695 value_in_comment
= print_arm_address (pc
, info
, given
| (1 << P_BIT
));
9699 allow_unpredictable
= TRUE
;
9702 if ((given
& 0x004f0000) == 0x004f0000)
9704 /* PC relative with immediate offset. */
9705 bfd_vma offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
9709 /* Elide positive zero offset. */
9710 if (offset
|| NEGATIVE_BIT_SET
)
9711 func (stream
, "[pc, #%s%d]\t; ",
9712 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
9714 func (stream
, "[pc]\t; ");
9715 if (NEGATIVE_BIT_SET
)
9717 info
->print_address_func (offset
+ pc
+ 8, info
);
9721 /* Always show the offset. */
9722 func (stream
, "[pc], #%s%d",
9723 NEGATIVE_BIT_SET
? "-" : "", (int) offset
);
9724 if (! allow_unpredictable
)
9725 is_unpredictable
= TRUE
;
9730 int offset
= ((given
& 0xf00) >> 4) | (given
& 0xf);
9732 func (stream
, "[%s",
9733 arm_regnames
[(given
>> 16) & 0xf]);
9737 if (IMMEDIATE_BIT_SET
)
9739 /* Elide offset for non-writeback
9741 if (WRITEBACK_BIT_SET
|| NEGATIVE_BIT_SET
9743 func (stream
, ", #%s%d",
9744 NEGATIVE_BIT_SET
? "-" : "", offset
);
9746 if (NEGATIVE_BIT_SET
)
9749 value_in_comment
= offset
;
9753 /* Register Offset or Register Pre-Indexed. */
9754 func (stream
, ", %s%s",
9755 NEGATIVE_BIT_SET
? "-" : "",
9756 arm_regnames
[given
& 0xf]);
9758 /* Writing back to the register that is the source/
9759 destination of the load/store is unpredictable. */
9760 if (! allow_unpredictable
9761 && WRITEBACK_BIT_SET
9762 && ((given
& 0xf) == ((given
>> 12) & 0xf)))
9763 is_unpredictable
= TRUE
;
9766 func (stream
, "]%s",
9767 WRITEBACK_BIT_SET
? "!" : "");
9771 if (IMMEDIATE_BIT_SET
)
9773 /* Immediate Post-indexed. */
9774 /* PR 10924: Offset must be printed, even if it is zero. */
9775 func (stream
, "], #%s%d",
9776 NEGATIVE_BIT_SET
? "-" : "", offset
);
9777 if (NEGATIVE_BIT_SET
)
9779 value_in_comment
= offset
;
9783 /* Register Post-indexed. */
9784 func (stream
, "], %s%s",
9785 NEGATIVE_BIT_SET
? "-" : "",
9786 arm_regnames
[given
& 0xf]);
9788 /* Writing back to the register that is the source/
9789 destination of the load/store is unpredictable. */
9790 if (! allow_unpredictable
9791 && (given
& 0xf) == ((given
>> 12) & 0xf))
9792 is_unpredictable
= TRUE
;
9795 if (! allow_unpredictable
)
9797 /* Writeback is automatically implied by post- addressing.
9798 Setting the W bit is unnecessary and ARM specify it as
9799 being unpredictable. */
9800 if (WRITEBACK_BIT_SET
9801 /* Specifying the PC register as the post-indexed
9802 registers is also unpredictable. */
9803 || (! IMMEDIATE_BIT_SET
&& ((given
& 0xf) == 0xf)))
9804 is_unpredictable
= TRUE
;
9812 bfd_vma disp
= (((given
& 0xffffff) ^ 0x800000) - 0x800000);
9813 info
->print_address_func (disp
* 4 + pc
+ 8, info
);
9818 if (((given
>> 28) & 0xf) != 0xe)
9820 arm_conditional
[(given
>> 28) & 0xf]);
9829 for (reg
= 0; reg
< 16; reg
++)
9830 if ((given
& (1 << reg
)) != 0)
9833 func (stream
, ", ");
9835 func (stream
, "%s", arm_regnames
[reg
]);
9839 is_unpredictable
= TRUE
;
9844 arm_decode_shift (given
, func
, stream
, FALSE
);
9848 if ((given
& 0x02000000) != 0)
9850 unsigned int rotate
= (given
& 0xf00) >> 7;
9851 unsigned int immed
= (given
& 0xff);
9854 a
= (((immed
<< (32 - rotate
))
9855 | (immed
>> rotate
)) & 0xffffffff);
9856 /* If there is another encoding with smaller rotate,
9857 the rotate should be specified directly. */
9858 for (i
= 0; i
< 32; i
+= 2)
9859 if ((a
<< i
| a
>> (32 - i
)) <= 0xff)
9863 func (stream
, "#%d, %d", immed
, rotate
);
9865 func (stream
, "#%d", a
);
9866 value_in_comment
= a
;
9869 arm_decode_shift (given
, func
, stream
, TRUE
);
9873 if ((given
& 0x0000f000) == 0x0000f000)
9875 arm_feature_set arm_ext_v6
=
9876 ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
9878 /* The p-variants of tst/cmp/cmn/teq are the pre-V6
9879 mechanism for setting PSR flag bits. They are
9880 obsolete in V6 onwards. */
9881 if (! ARM_CPU_HAS_FEATURE (private_data
->features
, \
9885 is_unpredictable
= TRUE
;
9890 if ((given
& 0x01200000) == 0x00200000)
9896 int offset
= given
& 0xff;
9898 value_in_comment
= offset
* 4;
9899 if (NEGATIVE_BIT_SET
)
9900 value_in_comment
= - value_in_comment
;
9902 func (stream
, "[%s", arm_regnames
[(given
>> 16) & 0xf]);
9907 func (stream
, ", #%d]%s",
9908 (int) value_in_comment
,
9909 WRITEBACK_BIT_SET
? "!" : "");
9917 if (WRITEBACK_BIT_SET
)
9920 func (stream
, ", #%d", (int) value_in_comment
);
9924 func (stream
, ", {%d}", (int) offset
);
9925 value_in_comment
= offset
;
9932 /* Print ARM V5 BLX(1) address: pc+25 bits. */
9937 if (! NEGATIVE_BIT_SET
)
9938 /* Is signed, hi bits should be ones. */
9939 offset
= (-1) ^ 0x00ffffff;
9941 /* Offset is (SignExtend(offset field)<<2). */
9942 offset
+= given
& 0x00ffffff;
9944 address
= offset
+ pc
+ 8;
9946 if (given
& 0x01000000)
9947 /* H bit allows addressing to 2-byte boundaries. */
9950 info
->print_address_func (address
, info
);
9955 if ((given
& 0x02000200) == 0x200)
9958 unsigned sysm
= (given
& 0x004f0000) >> 16;
9960 sysm
|= (given
& 0x300) >> 4;
9961 name
= banked_regname (sysm
);
9964 func (stream
, "%s", name
);
9966 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
9970 func (stream
, "%cPSR_",
9971 (given
& 0x00400000) ? 'S' : 'C');
9972 if (given
& 0x80000)
9974 if (given
& 0x40000)
9976 if (given
& 0x20000)
9978 if (given
& 0x10000)
9984 if ((given
& 0xf0) == 0x60)
9986 switch (given
& 0xf)
9988 case 0xf: func (stream
, "sy"); break;
9990 func (stream
, "#%d", (int) given
& 0xf);
9996 const char * opt
= data_barrier_option (given
& 0xf);
9998 func (stream
, "%s", opt
);
10000 func (stream
, "#%d", (int) given
& 0xf);
10004 case '0': case '1': case '2': case '3': case '4':
10005 case '5': case '6': case '7': case '8': case '9':
10008 unsigned long value
;
10010 c
= arm_decode_bitfield (c
, given
, &value
, &width
);
10016 is_unpredictable
= TRUE
;
10017 /* Fall through. */
10020 /* We want register + 1 when decoding T. */
10026 /* Eat the 'u' character. */
10029 if (u_reg
== value
)
10030 is_unpredictable
= TRUE
;
10035 /* Eat the 'U' character. */
10038 if (U_reg
== value
)
10039 is_unpredictable
= TRUE
;
10042 func (stream
, "%s", arm_regnames
[value
]);
10045 func (stream
, "%ld", value
);
10046 value_in_comment
= value
;
10049 func (stream
, "%ld", value
* 8);
10050 value_in_comment
= value
* 8;
10053 func (stream
, "%ld", value
+ 1);
10054 value_in_comment
= value
+ 1;
10057 func (stream
, "0x%08lx", value
);
10059 /* Some SWI instructions have special
10061 if ((given
& 0x0fffffff) == 0x0FF00000)
10062 func (stream
, "\t; IMB");
10063 else if ((given
& 0x0fffffff) == 0x0FF00001)
10064 func (stream
, "\t; IMBRange");
10067 func (stream
, "%01lx", value
& 0xf);
10068 value_in_comment
= value
;
10073 func (stream
, "%c", *c
);
10077 if (value
== ((1ul << width
) - 1))
10078 func (stream
, "%c", *c
);
10081 func (stream
, "%c", c
[(1 << width
) - (int) value
]);
10094 imm
= (given
& 0xf) | ((given
& 0xfff00) >> 4);
10095 func (stream
, "%d", imm
);
10096 value_in_comment
= imm
;
10101 /* LSB and WIDTH fields of BFI or BFC. The machine-
10102 language instruction encodes LSB and MSB. */
10104 long msb
= (given
& 0x001f0000) >> 16;
10105 long lsb
= (given
& 0x00000f80) >> 7;
10106 long w
= msb
- lsb
+ 1;
10109 func (stream
, "#%lu, #%lu", lsb
, w
);
10111 func (stream
, "(invalid: %lu:%lu)", lsb
, msb
);
10116 /* Get the PSR/banked register name. */
10119 unsigned sysm
= (given
& 0x004f0000) >> 16;
10121 sysm
|= (given
& 0x300) >> 4;
10122 name
= banked_regname (sysm
);
10125 func (stream
, "%s", name
);
10127 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
10132 /* 16-bit unsigned immediate from a MOVT or MOVW
10133 instruction, encoded in bits 0:11 and 15:19. */
10135 long hi
= (given
& 0x000f0000) >> 4;
10136 long lo
= (given
& 0x00000fff);
10137 long imm16
= hi
| lo
;
10139 func (stream
, "#%lu", imm16
);
10140 value_in_comment
= imm16
;
10149 func (stream
, "%c", *c
);
10152 if (value_in_comment
> 32 || value_in_comment
< -16)
10153 func (stream
, "\t; 0x%lx", (value_in_comment
& 0xffffffffUL
));
10155 if (is_unpredictable
)
10156 func (stream
, UNPREDICTABLE_INSTRUCTION
);
10161 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
10165 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
10168 print_insn_thumb16 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10170 const struct opcode16
*insn
;
10171 void *stream
= info
->stream
;
10172 fprintf_ftype func
= info
->fprintf_func
;
10174 for (insn
= thumb_opcodes
; insn
->assembler
; insn
++)
10175 if ((given
& insn
->mask
) == insn
->value
)
10177 signed long value_in_comment
= 0;
10178 const char *c
= insn
->assembler
;
10187 func (stream
, "%c", *c
);
10194 func (stream
, "%%");
10199 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10204 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10206 func (stream
, "s");
10213 ifthen_next_state
= given
& 0xff;
10214 for (tmp
= given
<< 1; tmp
& 0xf; tmp
<<= 1)
10215 func (stream
, ((given
^ tmp
) & 0x10) ? "e" : "t");
10216 func (stream
, "\t%s", arm_conditional
[(given
>> 4) & 0xf]);
10221 if (ifthen_next_state
)
10222 func (stream
, "\t; unpredictable branch in IT block\n");
10227 func (stream
, "\t; unpredictable <IT:%s>",
10228 arm_conditional
[IFTHEN_COND
]);
10235 reg
= (given
>> 3) & 0x7;
10236 if (given
& (1 << 6))
10239 func (stream
, "%s", arm_regnames
[reg
]);
10248 if (given
& (1 << 7))
10251 func (stream
, "%s", arm_regnames
[reg
]);
10256 if (given
& (1 << 8))
10258 /* Fall through. */
10260 if (*c
== 'O' && (given
& (1 << 8)))
10262 /* Fall through. */
10268 func (stream
, "{");
10270 /* It would be nice if we could spot
10271 ranges, and generate the rS-rE format: */
10272 for (reg
= 0; (reg
< 8); reg
++)
10273 if ((given
& (1 << reg
)) != 0)
10276 func (stream
, ", ");
10278 func (stream
, "%s", arm_regnames
[reg
]);
10284 func (stream
, ", ");
10286 func (stream
, "%s", arm_regnames
[14] /* "lr" */);
10292 func (stream
, ", ");
10293 func (stream
, "%s", arm_regnames
[15] /* "pc" */);
10296 func (stream
, "}");
10301 /* Print writeback indicator for a LDMIA. We are doing a
10302 writeback if the base register is not in the register
10304 if ((given
& (1 << ((given
& 0x0700) >> 8))) == 0)
10305 func (stream
, "!");
10309 /* Print ARM V6T2 CZB address: pc+4+6 bits. */
10311 bfd_vma address
= (pc
+ 4
10312 + ((given
& 0x00f8) >> 2)
10313 + ((given
& 0x0200) >> 3));
10314 info
->print_address_func (address
, info
);
10319 /* Right shift immediate -- bits 6..10; 1-31 print
10320 as themselves, 0 prints as 32. */
10322 long imm
= (given
& 0x07c0) >> 6;
10325 func (stream
, "#%ld", imm
);
10329 case '0': case '1': case '2': case '3': case '4':
10330 case '5': case '6': case '7': case '8': case '9':
10332 int bitstart
= *c
++ - '0';
10335 while (*c
>= '0' && *c
<= '9')
10336 bitstart
= (bitstart
* 10) + *c
++ - '0';
10345 while (*c
>= '0' && *c
<= '9')
10346 bitend
= (bitend
* 10) + *c
++ - '0';
10349 reg
= given
>> bitstart
;
10350 reg
&= (2 << (bitend
- bitstart
)) - 1;
10355 func (stream
, "%s", arm_regnames
[reg
]);
10359 func (stream
, "%ld", (long) reg
);
10360 value_in_comment
= reg
;
10364 func (stream
, "%ld", (long) (reg
<< 1));
10365 value_in_comment
= reg
<< 1;
10369 func (stream
, "%ld", (long) (reg
<< 2));
10370 value_in_comment
= reg
<< 2;
10374 /* PC-relative address -- the bottom two
10375 bits of the address are dropped
10376 before the calculation. */
10377 info
->print_address_func
10378 (((pc
+ 4) & ~3) + (reg
<< 2), info
);
10379 value_in_comment
= 0;
10383 func (stream
, "0x%04lx", (long) reg
);
10387 reg
= ((reg
^ (1 << bitend
)) - (1 << bitend
));
10388 info
->print_address_func (reg
* 2 + pc
+ 4, info
);
10389 value_in_comment
= 0;
10393 func (stream
, "%s", arm_conditional
[reg
]);
10404 if ((given
& (1 << bitstart
)) != 0)
10405 func (stream
, "%c", *c
);
10410 if ((given
& (1 << bitstart
)) != 0)
10411 func (stream
, "%c", *c
++);
10413 func (stream
, "%c", *++c
);
10427 if (value_in_comment
> 32 || value_in_comment
< -16)
10428 func (stream
, "\t; 0x%lx", value_in_comment
);
10433 func (stream
, UNKNOWN_INSTRUCTION_16BIT
, (unsigned)given
);
10437 /* Return the name of an V7M special register. */
10439 static const char *
10440 psr_name (int regno
)
10444 case 0x0: return "APSR";
10445 case 0x1: return "IAPSR";
10446 case 0x2: return "EAPSR";
10447 case 0x3: return "PSR";
10448 case 0x5: return "IPSR";
10449 case 0x6: return "EPSR";
10450 case 0x7: return "IEPSR";
10451 case 0x8: return "MSP";
10452 case 0x9: return "PSP";
10453 case 0xa: return "MSPLIM";
10454 case 0xb: return "PSPLIM";
10455 case 0x10: return "PRIMASK";
10456 case 0x11: return "BASEPRI";
10457 case 0x12: return "BASEPRI_MAX";
10458 case 0x13: return "FAULTMASK";
10459 case 0x14: return "CONTROL";
10460 case 0x88: return "MSP_NS";
10461 case 0x89: return "PSP_NS";
10462 case 0x8a: return "MSPLIM_NS";
10463 case 0x8b: return "PSPLIM_NS";
10464 case 0x90: return "PRIMASK_NS";
10465 case 0x91: return "BASEPRI_NS";
10466 case 0x93: return "FAULTMASK_NS";
10467 case 0x94: return "CONTROL_NS";
10468 case 0x98: return "SP_NS";
10469 default: return "<unknown>";
10473 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
10476 print_insn_thumb32 (bfd_vma pc
, struct disassemble_info
*info
, long given
)
10478 const struct opcode32
*insn
;
10479 void *stream
= info
->stream
;
10480 fprintf_ftype func
= info
->fprintf_func
;
10481 bfd_boolean is_mve
= is_mve_architecture (info
);
10483 if (print_insn_coprocessor (pc
, info
, given
, TRUE
))
10486 if ((is_mve
== FALSE
) && print_insn_neon (info
, given
, TRUE
))
10489 if (is_mve
&& print_insn_mve (info
, given
))
10492 for (insn
= thumb32_opcodes
; insn
->assembler
; insn
++)
10493 if ((given
& insn
->mask
) == insn
->value
)
10495 bfd_boolean is_clrm
= FALSE
;
10496 bfd_boolean is_unpredictable
= FALSE
;
10497 signed long value_in_comment
= 0;
10498 const char *c
= insn
->assembler
;
10504 func (stream
, "%c", *c
);
10511 func (stream
, "%%");
10516 func (stream
, "%s", arm_conditional
[IFTHEN_COND
]);
10520 if (ifthen_next_state
)
10521 func (stream
, "\t; unpredictable branch in IT block\n");
10526 func (stream
, "\t; unpredictable <IT:%s>",
10527 arm_conditional
[IFTHEN_COND
]);
10532 unsigned int imm12
= 0;
10534 imm12
|= (given
& 0x000000ffu
);
10535 imm12
|= (given
& 0x00007000u
) >> 4;
10536 imm12
|= (given
& 0x04000000u
) >> 15;
10537 func (stream
, "#%u", imm12
);
10538 value_in_comment
= imm12
;
10544 unsigned int bits
= 0, imm
, imm8
, mod
;
10546 bits
|= (given
& 0x000000ffu
);
10547 bits
|= (given
& 0x00007000u
) >> 4;
10548 bits
|= (given
& 0x04000000u
) >> 15;
10549 imm8
= (bits
& 0x0ff);
10550 mod
= (bits
& 0xf00) >> 8;
10553 case 0: imm
= imm8
; break;
10554 case 1: imm
= ((imm8
<< 16) | imm8
); break;
10555 case 2: imm
= ((imm8
<< 24) | (imm8
<< 8)); break;
10556 case 3: imm
= ((imm8
<< 24) | (imm8
<< 16) | (imm8
<< 8) | imm8
); break;
10558 mod
= (bits
& 0xf80) >> 7;
10559 imm8
= (bits
& 0x07f) | 0x80;
10560 imm
= (((imm8
<< (32 - mod
)) | (imm8
>> mod
)) & 0xffffffff);
10562 func (stream
, "#%u", imm
);
10563 value_in_comment
= imm
;
10569 unsigned int imm
= 0;
10571 imm
|= (given
& 0x000000ffu
);
10572 imm
|= (given
& 0x00007000u
) >> 4;
10573 imm
|= (given
& 0x04000000u
) >> 15;
10574 imm
|= (given
& 0x000f0000u
) >> 4;
10575 func (stream
, "#%u", imm
);
10576 value_in_comment
= imm
;
10582 unsigned int imm
= 0;
10584 imm
|= (given
& 0x000f0000u
) >> 16;
10585 imm
|= (given
& 0x00000ff0u
) >> 0;
10586 imm
|= (given
& 0x0000000fu
) << 12;
10587 func (stream
, "#%u", imm
);
10588 value_in_comment
= imm
;
10594 unsigned int imm
= 0;
10596 imm
|= (given
& 0x000f0000u
) >> 4;
10597 imm
|= (given
& 0x00000fffu
) >> 0;
10598 func (stream
, "#%u", imm
);
10599 value_in_comment
= imm
;
10605 unsigned int imm
= 0;
10607 imm
|= (given
& 0x00000fffu
);
10608 imm
|= (given
& 0x000f0000u
) >> 4;
10609 func (stream
, "#%u", imm
);
10610 value_in_comment
= imm
;
10616 unsigned int reg
= (given
& 0x0000000fu
);
10617 unsigned int stp
= (given
& 0x00000030u
) >> 4;
10618 unsigned int imm
= 0;
10619 imm
|= (given
& 0x000000c0u
) >> 6;
10620 imm
|= (given
& 0x00007000u
) >> 10;
10622 func (stream
, "%s", arm_regnames
[reg
]);
10627 func (stream
, ", lsl #%u", imm
);
10633 func (stream
, ", lsr #%u", imm
);
10639 func (stream
, ", asr #%u", imm
);
10644 func (stream
, ", rrx");
10646 func (stream
, ", ror #%u", imm
);
10653 unsigned int Rn
= (given
& 0x000f0000) >> 16;
10654 unsigned int U
= ! NEGATIVE_BIT_SET
;
10655 unsigned int op
= (given
& 0x00000f00) >> 8;
10656 unsigned int i12
= (given
& 0x00000fff);
10657 unsigned int i8
= (given
& 0x000000ff);
10658 bfd_boolean writeback
= FALSE
, postind
= FALSE
;
10659 bfd_vma offset
= 0;
10661 func (stream
, "[%s", arm_regnames
[Rn
]);
10662 if (U
) /* 12-bit positive immediate offset. */
10666 value_in_comment
= offset
;
10668 else if (Rn
== 15) /* 12-bit negative immediate offset. */
10669 offset
= - (int) i12
;
10670 else if (op
== 0x0) /* Shifted register offset. */
10672 unsigned int Rm
= (i8
& 0x0f);
10673 unsigned int sh
= (i8
& 0x30) >> 4;
10675 func (stream
, ", %s", arm_regnames
[Rm
]);
10677 func (stream
, ", lsl #%u", sh
);
10678 func (stream
, "]");
10683 case 0xE: /* 8-bit positive immediate offset. */
10687 case 0xC: /* 8-bit negative immediate offset. */
10691 case 0xF: /* 8-bit + preindex with wb. */
10696 case 0xD: /* 8-bit - preindex with wb. */
10701 case 0xB: /* 8-bit + postindex. */
10706 case 0x9: /* 8-bit - postindex. */
10712 func (stream
, ", <undefined>]");
10717 func (stream
, "], #%d", (int) offset
);
10721 func (stream
, ", #%d", (int) offset
);
10722 func (stream
, writeback
? "]!" : "]");
10727 func (stream
, "\t; ");
10728 info
->print_address_func (((pc
+ 4) & ~3) + offset
, info
);
10736 unsigned int U
= ! NEGATIVE_BIT_SET
;
10737 unsigned int W
= WRITEBACK_BIT_SET
;
10738 unsigned int Rn
= (given
& 0x000f0000) >> 16;
10739 unsigned int off
= (given
& 0x000000ff);
10741 func (stream
, "[%s", arm_regnames
[Rn
]);
10747 func (stream
, ", #%c%u", U
? '+' : '-', off
* 4);
10748 value_in_comment
= off
* 4 * (U
? 1 : -1);
10750 func (stream
, "]");
10752 func (stream
, "!");
10756 func (stream
, "], ");
10759 func (stream
, "#%c%u", U
? '+' : '-', off
* 4);
10760 value_in_comment
= off
* 4 * (U
? 1 : -1);
10764 func (stream
, "{%u}", off
);
10765 value_in_comment
= off
;
10773 unsigned int Sbit
= (given
& 0x01000000) >> 24;
10774 unsigned int type
= (given
& 0x00600000) >> 21;
10778 case 0: func (stream
, Sbit
? "sb" : "b"); break;
10779 case 1: func (stream
, Sbit
? "sh" : "h"); break;
10782 func (stream
, "??");
10785 func (stream
, "??");
10793 /* Fall through. */
10799 func (stream
, "{");
10800 for (reg
= 0; reg
< 16; reg
++)
10801 if ((given
& (1 << reg
)) != 0)
10804 func (stream
, ", ");
10806 if (is_clrm
&& reg
== 13)
10807 func (stream
, "(invalid: %s)", arm_regnames
[reg
]);
10808 else if (is_clrm
&& reg
== 15)
10809 func (stream
, "%s", "APSR");
10811 func (stream
, "%s", arm_regnames
[reg
]);
10813 func (stream
, "}");
10819 unsigned int msb
= (given
& 0x0000001f);
10820 unsigned int lsb
= 0;
10822 lsb
|= (given
& 0x000000c0u
) >> 6;
10823 lsb
|= (given
& 0x00007000u
) >> 10;
10824 func (stream
, "#%u, #%u", lsb
, msb
- lsb
+ 1);
10830 unsigned int width
= (given
& 0x0000001f) + 1;
10831 unsigned int lsb
= 0;
10833 lsb
|= (given
& 0x000000c0u
) >> 6;
10834 lsb
|= (given
& 0x00007000u
) >> 10;
10835 func (stream
, "#%u, #%u", lsb
, width
);
10841 unsigned int boff
= (((given
& 0x07800000) >> 23) << 1);
10842 func (stream
, "%x", boff
);
10848 unsigned int immA
= (given
& 0x001f0000u
) >> 16;
10849 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10850 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10851 bfd_vma offset
= 0;
10853 offset
|= immA
<< 12;
10854 offset
|= immB
<< 2;
10855 offset
|= immC
<< 1;
10857 offset
= (offset
& 0x10000) ? offset
- (1 << 17) : offset
;
10859 info
->print_address_func (pc
+ 4 + offset
, info
);
10865 unsigned int immA
= (given
& 0x007f0000u
) >> 16;
10866 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10867 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10868 bfd_vma offset
= 0;
10870 offset
|= immA
<< 12;
10871 offset
|= immB
<< 2;
10872 offset
|= immC
<< 1;
10874 offset
= (offset
& 0x40000) ? offset
- (1 << 19) : offset
;
10876 info
->print_address_func (pc
+ 4 + offset
, info
);
10882 unsigned int immA
= (given
& 0x00010000u
) >> 16;
10883 unsigned int immB
= (given
& 0x000007feu
) >> 1;
10884 unsigned int immC
= (given
& 0x00000800u
) >> 11;
10885 bfd_vma offset
= 0;
10887 offset
|= immA
<< 12;
10888 offset
|= immB
<< 2;
10889 offset
|= immC
<< 1;
10891 offset
= (offset
& 0x1000) ? offset
- (1 << 13) : offset
;
10893 info
->print_address_func (pc
+ 4 + offset
, info
);
10895 unsigned int T
= (given
& 0x00020000u
) >> 17;
10896 unsigned int endoffset
= (((given
& 0x07800000) >> 23) << 1);
10897 unsigned int boffset
= (T
== 1) ? 4 : 2;
10898 func (stream
, ", ");
10899 func (stream
, "%x", endoffset
+ boffset
);
10905 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10906 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10909 imm32
|= immh
<< 2;
10910 imm32
|= imml
<< 1;
10912 info
->print_address_func (pc
+ 4 + imm32
, info
);
10918 unsigned int immh
= (given
& 0x000007feu
) >> 1;
10919 unsigned int imml
= (given
& 0x00000800u
) >> 11;
10922 imm32
|= immh
<< 2;
10923 imm32
|= imml
<< 1;
10925 info
->print_address_func (pc
+ 4 - imm32
, info
);
10931 unsigned int S
= (given
& 0x04000000u
) >> 26;
10932 unsigned int J1
= (given
& 0x00002000u
) >> 13;
10933 unsigned int J2
= (given
& 0x00000800u
) >> 11;
10934 bfd_vma offset
= 0;
10936 offset
|= !S
<< 20;
10937 offset
|= J2
<< 19;
10938 offset
|= J1
<< 18;
10939 offset
|= (given
& 0x003f0000) >> 4;
10940 offset
|= (given
& 0x000007ff) << 1;
10941 offset
-= (1 << 20);
10943 info
->print_address_func (pc
+ 4 + offset
, info
);
10949 unsigned int S
= (given
& 0x04000000u
) >> 26;
10950 unsigned int I1
= (given
& 0x00002000u
) >> 13;
10951 unsigned int I2
= (given
& 0x00000800u
) >> 11;
10952 bfd_vma offset
= 0;
10954 offset
|= !S
<< 24;
10955 offset
|= !(I1
^ S
) << 23;
10956 offset
|= !(I2
^ S
) << 22;
10957 offset
|= (given
& 0x03ff0000u
) >> 4;
10958 offset
|= (given
& 0x000007ffu
) << 1;
10959 offset
-= (1 << 24);
10962 /* BLX target addresses are always word aligned. */
10963 if ((given
& 0x00001000u
) == 0)
10966 info
->print_address_func (offset
, info
);
10972 unsigned int shift
= 0;
10974 shift
|= (given
& 0x000000c0u
) >> 6;
10975 shift
|= (given
& 0x00007000u
) >> 10;
10976 if (WRITEBACK_BIT_SET
)
10977 func (stream
, ", asr #%u", shift
);
10979 func (stream
, ", lsl #%u", shift
);
10980 /* else print nothing - lsl #0 */
10986 unsigned int rot
= (given
& 0x00000030) >> 4;
10989 func (stream
, ", ror #%u", rot
* 8);
10994 if ((given
& 0xf0) == 0x60)
10996 switch (given
& 0xf)
10998 case 0xf: func (stream
, "sy"); break;
11000 func (stream
, "#%d", (int) given
& 0xf);
11006 const char * opt
= data_barrier_option (given
& 0xf);
11008 func (stream
, "%s", opt
);
11010 func (stream
, "#%d", (int) given
& 0xf);
11015 if ((given
& 0xff) == 0)
11017 func (stream
, "%cPSR_", (given
& 0x100000) ? 'S' : 'C');
11019 func (stream
, "f");
11021 func (stream
, "s");
11023 func (stream
, "x");
11025 func (stream
, "c");
11027 else if ((given
& 0x20) == 0x20)
11030 unsigned sysm
= (given
& 0xf00) >> 8;
11032 sysm
|= (given
& 0x30);
11033 sysm
|= (given
& 0x00100000) >> 14;
11034 name
= banked_regname (sysm
);
11037 func (stream
, "%s", name
);
11039 func (stream
, "(UNDEF: %lu)", (unsigned long) sysm
);
11043 func (stream
, "%s", psr_name (given
& 0xff));
11048 if (((given
& 0xff) == 0)
11049 || ((given
& 0x20) == 0x20))
11052 unsigned sm
= (given
& 0xf0000) >> 16;
11054 sm
|= (given
& 0x30);
11055 sm
|= (given
& 0x00100000) >> 14;
11056 name
= banked_regname (sm
);
11059 func (stream
, "%s", name
);
11061 func (stream
, "(UNDEF: %lu)", (unsigned long) sm
);
11064 func (stream
, "%s", psr_name (given
& 0xff));
11067 case '0': case '1': case '2': case '3': case '4':
11068 case '5': case '6': case '7': case '8': case '9':
11073 c
= arm_decode_bitfield (c
, given
, &val
, &width
);
11079 func (stream
, "%s", mve_vec_sizename
[val
]);
11081 func (stream
, "<undef size>");
11085 func (stream
, "%lu", val
);
11086 value_in_comment
= val
;
11090 func (stream
, "%lu", val
+ 1);
11091 value_in_comment
= val
+ 1;
11095 func (stream
, "%lu", val
* 4);
11096 value_in_comment
= val
* 4;
11101 is_unpredictable
= TRUE
;
11102 /* Fall through. */
11105 is_unpredictable
= TRUE
;
11106 /* Fall through. */
11108 func (stream
, "%s", arm_regnames
[val
]);
11112 func (stream
, "%s", arm_conditional
[val
]);
11117 if (val
== ((1ul << width
) - 1))
11118 func (stream
, "%c", *c
);
11124 func (stream
, "%c", *c
);
11128 func (stream
, "%c", c
[(1 << width
) - (int) val
]);
11133 func (stream
, "0x%lx", val
& 0xffffffffUL
);
11143 /* PR binutils/12534
11144 If we have a PC relative offset in an LDRD or STRD
11145 instructions then display the decoded address. */
11146 if (((given
>> 16) & 0xf) == 0xf)
11148 bfd_vma offset
= (given
& 0xff) * 4;
11150 if ((given
& (1 << 23)) == 0)
11152 func (stream
, "\t; ");
11153 info
->print_address_func ((pc
& ~3) + 4 + offset
, info
);
11162 if (value_in_comment
> 32 || value_in_comment
< -16)
11163 func (stream
, "\t; 0x%lx", value_in_comment
);
11165 if (is_unpredictable
)
11166 func (stream
, UNPREDICTABLE_INSTRUCTION
);
11172 func (stream
, UNKNOWN_INSTRUCTION_32BIT
, (unsigned)given
);
11176 /* Print data bytes on INFO->STREAM. */
11179 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED
,
11180 struct disassemble_info
*info
,
11183 switch (info
->bytes_per_chunk
)
11186 info
->fprintf_func (info
->stream
, ".byte\t0x%02lx", given
);
11189 info
->fprintf_func (info
->stream
, ".short\t0x%04lx", given
);
11192 info
->fprintf_func (info
->stream
, ".word\t0x%08lx", given
);
11199 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
11200 being displayed in symbol relative addresses.
11202 Also disallow private symbol, with __tagsym$$ prefix,
11203 from ARM RVCT toolchain being displayed. */
11206 arm_symbol_is_valid (asymbol
* sym
,
11207 struct disassemble_info
* info ATTRIBUTE_UNUSED
)
11214 name
= bfd_asymbol_name (sym
);
11216 return (name
&& *name
!= '$' && strncmp (name
, "__tagsym$$", 10));
11219 /* Parse the string of disassembler options. */
11222 parse_arm_disassembler_options (const char *options
)
11226 FOR_EACH_DISASSEMBLER_OPTION (opt
, options
)
11228 if (CONST_STRNEQ (opt
, "reg-names-"))
11231 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11232 if (disassembler_options_cmp (opt
, regnames
[i
].name
) == 0)
11234 regname_selected
= i
;
11238 if (i
>= NUM_ARM_OPTIONS
)
11239 /* xgettext: c-format */
11240 opcodes_error_handler (_("unrecognised register name set: %s"),
11243 else if (CONST_STRNEQ (opt
, "force-thumb"))
11245 else if (CONST_STRNEQ (opt
, "no-force-thumb"))
11248 /* xgettext: c-format */
11249 opcodes_error_handler (_("unrecognised disassembler option: %s"), opt
);
11256 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11257 enum map_type
*map_symbol
);
11259 /* Search back through the insn stream to determine if this instruction is
11260 conditionally executed. */
11263 find_ifthen_state (bfd_vma pc
,
11264 struct disassemble_info
*info
,
11265 bfd_boolean little
)
11267 unsigned char b
[2];
11270 /* COUNT is twice the number of instructions seen. It will be odd if we
11271 just crossed an instruction boundary. */
11274 unsigned int seen_it
;
11277 ifthen_address
= pc
;
11284 /* Scan backwards looking for IT instructions, keeping track of where
11285 instruction boundaries are. We don't know if something is actually an
11286 IT instruction until we find a definite instruction boundary. */
11289 if (addr
== 0 || info
->symbol_at_address_func (addr
, info
))
11291 /* A symbol must be on an instruction boundary, and will not
11292 be within an IT block. */
11293 if (seen_it
&& (count
& 1))
11299 status
= info
->read_memory_func (addr
, (bfd_byte
*) b
, 2, info
);
11304 insn
= (b
[0]) | (b
[1] << 8);
11306 insn
= (b
[1]) | (b
[0] << 8);
11309 if ((insn
& 0xf800) < 0xe800)
11311 /* Addr + 2 is an instruction boundary. See if this matches
11312 the expected boundary based on the position of the last
11319 if ((insn
& 0xff00) == 0xbf00 && (insn
& 0xf) != 0)
11321 enum map_type type
= MAP_ARM
;
11322 bfd_boolean found
= mapping_symbol_for_insn (addr
, info
, &type
);
11324 if (!found
|| (found
&& type
== MAP_THUMB
))
11326 /* This could be an IT instruction. */
11328 it_count
= count
>> 1;
11331 if ((insn
& 0xf800) >= 0xe800)
11334 count
= (count
+ 2) | 1;
11335 /* IT blocks contain at most 4 instructions. */
11336 if (count
>= 8 && !seen_it
)
11339 /* We found an IT instruction. */
11340 ifthen_state
= (seen_it
& 0xe0) | ((seen_it
<< it_count
) & 0x1f);
11341 if ((ifthen_state
& 0xf) == 0)
11345 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
11349 is_mapping_symbol (struct disassemble_info
*info
, int n
,
11350 enum map_type
*map_type
)
11354 name
= bfd_asymbol_name (info
->symtab
[n
]);
11355 if (name
[0] == '$' && (name
[1] == 'a' || name
[1] == 't' || name
[1] == 'd')
11356 && (name
[2] == 0 || name
[2] == '.'))
11358 *map_type
= ((name
[1] == 'a') ? MAP_ARM
11359 : (name
[1] == 't') ? MAP_THUMB
11367 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
11368 Returns nonzero if *MAP_TYPE was set. */
11371 get_map_sym_type (struct disassemble_info
*info
,
11373 enum map_type
*map_type
)
11375 /* If the symbol is in a different section, ignore it. */
11376 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11379 return is_mapping_symbol (info
, n
, map_type
);
11382 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
11383 Returns nonzero if *MAP_TYPE was set. */
11386 get_sym_code_type (struct disassemble_info
*info
,
11388 enum map_type
*map_type
)
11390 elf_symbol_type
*es
;
11393 /* If the symbol is in a different section, ignore it. */
11394 if (info
->section
!= NULL
&& info
->section
!= info
->symtab
[n
]->section
)
11397 es
= *(elf_symbol_type
**)(info
->symtab
+ n
);
11398 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11400 /* If the symbol has function type then use that. */
11401 if (type
== STT_FUNC
|| type
== STT_GNU_IFUNC
)
11403 if (ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11404 == ST_BRANCH_TO_THUMB
)
11405 *map_type
= MAP_THUMB
;
11407 *map_type
= MAP_ARM
;
11414 /* Search the mapping symbol state for instruction at pc. This is only
11415 applicable for elf target.
11417 There is an assumption Here, info->private_data contains the correct AND
11418 up-to-date information about current scan process. The information will be
11419 used to speed this search process.
11421 Return TRUE if the mapping state can be determined, and map_symbol
11422 will be updated accordingly. Otherwise, return FALSE. */
11425 mapping_symbol_for_insn (bfd_vma pc
, struct disassemble_info
*info
,
11426 enum map_type
*map_symbol
)
11428 bfd_vma addr
, section_vma
= 0;
11429 int n
, last_sym
= -1;
11430 bfd_boolean found
= FALSE
;
11431 bfd_boolean can_use_search_opt_p
= FALSE
;
11433 /* Default to DATA. A text section is required by the ABI to contain an
11434 INSN mapping symbol at the start. A data section has no such
11435 requirement, hence if no mapping symbol is found the section must
11436 contain only data. This however isn't very useful if the user has
11437 fully stripped the binaries. If this is the case use the section
11438 attributes to determine the default. If we have no section default to
11439 INSN as well, as we may be disassembling some raw bytes on a baremetal
11440 HEX file or similar. */
11441 enum map_type type
= MAP_DATA
;
11442 if ((info
->section
&& info
->section
->flags
& SEC_CODE
) || !info
->section
)
11444 struct arm_private_data
*private_data
;
11446 if (info
->private_data
== NULL
11447 || bfd_asymbol_flavour (*info
->symtab
) != bfd_target_elf_flavour
)
11450 private_data
= info
->private_data
;
11452 /* First, look for mapping symbols. */
11453 if (info
->symtab_size
!= 0)
11455 if (pc
<= private_data
->last_mapping_addr
)
11456 private_data
->last_mapping_sym
= -1;
11458 /* Start scanning at the start of the function, or wherever
11459 we finished last time. */
11460 n
= info
->symtab_pos
+ 1;
11462 /* If the last stop offset is different from the current one it means we
11463 are disassembling a different glob of bytes. As such the optimization
11464 would not be safe and we should start over. */
11465 can_use_search_opt_p
11466 = private_data
->last_mapping_sym
>= 0
11467 && info
->stop_offset
== private_data
->last_stop_offset
;
11469 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11470 n
= private_data
->last_mapping_sym
;
11472 /* Look down while we haven't passed the location being disassembled.
11473 The reason for this is that there's no defined order between a symbol
11474 and an mapping symbol that may be at the same address. We may have to
11475 look at least one position ahead. */
11476 for (; n
< info
->symtab_size
; n
++)
11478 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11481 if (get_map_sym_type (info
, n
, &type
))
11490 n
= info
->symtab_pos
;
11491 if (n
>= private_data
->last_mapping_sym
&& can_use_search_opt_p
)
11492 n
= private_data
->last_mapping_sym
;
11494 /* No mapping symbol found at this address. Look backwards
11495 for a preceeding one, but don't go pass the section start
11496 otherwise a data section with no mapping symbol can pick up
11497 a text mapping symbol of a preceeding section. The documentation
11498 says section can be NULL, in which case we will seek up all the
11501 section_vma
= info
->section
->vma
;
11503 for (; n
>= 0; n
--)
11505 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11506 if (addr
< section_vma
)
11509 if (get_map_sym_type (info
, n
, &type
))
11519 /* If no mapping symbol was found, try looking up without a mapping
11520 symbol. This is done by walking up from the current PC to the nearest
11521 symbol. We don't actually have to loop here since symtab_pos will
11522 contain the nearest symbol already. */
11525 n
= info
->symtab_pos
;
11526 if (n
>= 0 && get_sym_code_type (info
, n
, &type
))
11533 private_data
->last_mapping_sym
= last_sym
;
11534 private_data
->last_type
= type
;
11535 private_data
->last_stop_offset
= info
->stop_offset
;
11537 *map_symbol
= type
;
11541 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
11542 of the supplied arm_feature_set structure with bitmasks indicating
11543 the supported base architectures and coprocessor extensions.
11545 FIXME: This could more efficiently implemented as a constant array,
11546 although it would also be less robust. */
11549 select_arm_features (unsigned long mach
,
11550 arm_feature_set
* features
)
11552 arm_feature_set arch_fset
;
11553 const arm_feature_set fpu_any
= FPU_ANY
;
11555 #undef ARM_SET_FEATURES
11556 #define ARM_SET_FEATURES(FSET) \
11558 const arm_feature_set fset = FSET; \
11559 arch_fset = fset; \
11562 /* When several architecture versions share the same bfd_mach_arm_XXX value
11563 the most featureful is chosen. */
11566 case bfd_mach_arm_2
: ARM_SET_FEATURES (ARM_ARCH_V2
); break;
11567 case bfd_mach_arm_2a
: ARM_SET_FEATURES (ARM_ARCH_V2S
); break;
11568 case bfd_mach_arm_3
: ARM_SET_FEATURES (ARM_ARCH_V3
); break;
11569 case bfd_mach_arm_3M
: ARM_SET_FEATURES (ARM_ARCH_V3M
); break;
11570 case bfd_mach_arm_4
: ARM_SET_FEATURES (ARM_ARCH_V4
); break;
11571 case bfd_mach_arm_4T
: ARM_SET_FEATURES (ARM_ARCH_V4T
); break;
11572 case bfd_mach_arm_5
: ARM_SET_FEATURES (ARM_ARCH_V5
); break;
11573 case bfd_mach_arm_5T
: ARM_SET_FEATURES (ARM_ARCH_V5T
); break;
11574 case bfd_mach_arm_5TE
: ARM_SET_FEATURES (ARM_ARCH_V5TE
); break;
11575 case bfd_mach_arm_XScale
: ARM_SET_FEATURES (ARM_ARCH_XSCALE
); break;
11576 case bfd_mach_arm_ep9312
:
11577 ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T
,
11578 ARM_CEXT_MAVERICK
| FPU_MAVERICK
));
11580 case bfd_mach_arm_iWMMXt
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT
); break;
11581 case bfd_mach_arm_iWMMXt2
: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2
); break;
11582 case bfd_mach_arm_5TEJ
: ARM_SET_FEATURES (ARM_ARCH_V5TEJ
); break;
11583 case bfd_mach_arm_6
: ARM_SET_FEATURES (ARM_ARCH_V6
); break;
11584 case bfd_mach_arm_6KZ
: ARM_SET_FEATURES (ARM_ARCH_V6KZ
); break;
11585 case bfd_mach_arm_6T2
: ARM_SET_FEATURES (ARM_ARCH_V6KZT2
); break;
11586 case bfd_mach_arm_6K
: ARM_SET_FEATURES (ARM_ARCH_V6K
); break;
11587 case bfd_mach_arm_7
: ARM_SET_FEATURES (ARM_ARCH_V7VE
); break;
11588 case bfd_mach_arm_6M
: ARM_SET_FEATURES (ARM_ARCH_V6M
); break;
11589 case bfd_mach_arm_6SM
: ARM_SET_FEATURES (ARM_ARCH_V6SM
); break;
11590 case bfd_mach_arm_7EM
: ARM_SET_FEATURES (ARM_ARCH_V7EM
); break;
11591 case bfd_mach_arm_8
:
11593 /* Add bits for extensions that Armv8.5-A recognizes. */
11594 arm_feature_set armv8_5_ext_fset
11595 = ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
11596 ARM_SET_FEATURES (ARM_ARCH_V8_5A
);
11597 ARM_MERGE_FEATURE_SETS (arch_fset
, arch_fset
, armv8_5_ext_fset
);
11600 case bfd_mach_arm_8R
: ARM_SET_FEATURES (ARM_ARCH_V8R
); break;
11601 case bfd_mach_arm_8M_BASE
: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE
); break;
11602 case bfd_mach_arm_8M_MAIN
: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN
); break;
11603 case bfd_mach_arm_8_1M_MAIN
:
11604 ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN
);
11607 /* If the machine type is unknown allow all architecture types and all
11609 case bfd_mach_arm_unknown
: ARM_SET_FEATURES (ARM_FEATURE_ALL
); break;
11613 #undef ARM_SET_FEATURES
11615 /* None of the feature bits related to -mfpu have an impact on Tag_CPU_arch
11616 and thus on bfd_mach_arm_XXX value. Therefore for a given
11617 bfd_mach_arm_XXX value all coprocessor feature bits should be allowed. */
11618 ARM_MERGE_FEATURE_SETS (*features
, arch_fset
, fpu_any
);
11622 /* NOTE: There are no checks in these routines that
11623 the relevant number of data bytes exist. */
11626 print_insn (bfd_vma pc
, struct disassemble_info
*info
, bfd_boolean little
)
11628 unsigned char b
[4];
11631 int is_thumb
= FALSE
;
11632 int is_data
= FALSE
;
11634 unsigned int size
= 4;
11635 void (*printer
) (bfd_vma
, struct disassemble_info
*, long);
11636 bfd_boolean found
= FALSE
;
11637 struct arm_private_data
*private_data
;
11639 if (info
->disassembler_options
)
11641 parse_arm_disassembler_options (info
->disassembler_options
);
11643 /* To avoid repeated parsing of these options, we remove them here. */
11644 info
->disassembler_options
= NULL
;
11647 /* PR 10288: Control which instructions will be disassembled. */
11648 if (info
->private_data
== NULL
)
11650 static struct arm_private_data
private;
11652 if ((info
->flags
& USER_SPECIFIED_MACHINE_TYPE
) == 0)
11653 /* If the user did not use the -m command line switch then default to
11654 disassembling all types of ARM instruction.
11656 The info->mach value has to be ignored as this will be based on
11657 the default archictecture for the target and/or hints in the notes
11658 section, but it will never be greater than the current largest arm
11659 machine value (iWMMXt2), which is only equivalent to the V5TE
11660 architecture. ARM architectures have advanced beyond the machine
11661 value encoding, and these newer architectures would be ignored if
11662 the machine value was used.
11664 Ie the -m switch is used to restrict which instructions will be
11665 disassembled. If it is necessary to use the -m switch to tell
11666 objdump that an ARM binary is being disassembled, eg because the
11667 input is a raw binary file, but it is also desired to disassemble
11668 all ARM instructions then use "-marm". This will select the
11669 "unknown" arm architecture which is compatible with any ARM
11671 info
->mach
= bfd_mach_arm_unknown
;
11673 /* Compute the architecture bitmask from the machine number.
11674 Note: This assumes that the machine number will not change
11675 during disassembly.... */
11676 select_arm_features (info
->mach
, & private.features
);
11678 private.last_mapping_sym
= -1;
11679 private.last_mapping_addr
= 0;
11680 private.last_stop_offset
= 0;
11682 info
->private_data
= & private;
11685 private_data
= info
->private_data
;
11687 /* Decide if our code is going to be little-endian, despite what the
11688 function argument might say. */
11689 little_code
= ((info
->endian_code
== BFD_ENDIAN_LITTLE
) || little
);
11691 /* For ELF, consult the symbol table to determine what kind of code
11692 or data we have. */
11693 if (info
->symtab_size
!= 0
11694 && bfd_asymbol_flavour (*info
->symtab
) == bfd_target_elf_flavour
)
11699 enum map_type type
= MAP_ARM
;
11701 found
= mapping_symbol_for_insn (pc
, info
, &type
);
11702 last_sym
= private_data
->last_mapping_sym
;
11704 is_thumb
= (private_data
->last_type
== MAP_THUMB
);
11705 is_data
= (private_data
->last_type
== MAP_DATA
);
11707 /* Look a little bit ahead to see if we should print out
11708 two or four bytes of data. If there's a symbol,
11709 mapping or otherwise, after two bytes then don't
11713 size
= 4 - (pc
& 3);
11714 for (n
= last_sym
+ 1; n
< info
->symtab_size
; n
++)
11716 addr
= bfd_asymbol_value (info
->symtab
[n
]);
11718 && (info
->section
== NULL
11719 || info
->section
== info
->symtab
[n
]->section
))
11721 if (addr
- pc
< size
)
11726 /* If the next symbol is after three bytes, we need to
11727 print only part of the data, so that we can use either
11728 .byte or .short. */
11730 size
= (pc
& 1) ? 1 : 2;
11734 if (info
->symbols
!= NULL
)
11736 if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_coff_flavour
)
11738 coff_symbol_type
* cs
;
11740 cs
= coffsymbol (*info
->symbols
);
11741 is_thumb
= ( cs
->native
->u
.syment
.n_sclass
== C_THUMBEXT
11742 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTAT
11743 || cs
->native
->u
.syment
.n_sclass
== C_THUMBLABEL
11744 || cs
->native
->u
.syment
.n_sclass
== C_THUMBEXTFUNC
11745 || cs
->native
->u
.syment
.n_sclass
== C_THUMBSTATFUNC
);
11747 else if (bfd_asymbol_flavour (*info
->symbols
) == bfd_target_elf_flavour
11750 /* If no mapping symbol has been found then fall back to the type
11751 of the function symbol. */
11752 elf_symbol_type
* es
;
11755 es
= *(elf_symbol_type
**)(info
->symbols
);
11756 type
= ELF_ST_TYPE (es
->internal_elf_sym
.st_info
);
11759 ((ARM_GET_SYM_BRANCH_TYPE (es
->internal_elf_sym
.st_target_internal
)
11760 == ST_BRANCH_TO_THUMB
) || type
== STT_ARM_16BIT
);
11762 else if (bfd_asymbol_flavour (*info
->symbols
)
11763 == bfd_target_mach_o_flavour
)
11765 bfd_mach_o_asymbol
*asym
= (bfd_mach_o_asymbol
*)*info
->symbols
;
11767 is_thumb
= (asym
->n_desc
& BFD_MACH_O_N_ARM_THUMB_DEF
);
11775 info
->display_endian
= little
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
11777 info
->display_endian
= little_code
? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_BIG
;
11779 info
->bytes_per_line
= 4;
11781 /* PR 10263: Disassemble data if requested to do so by the user. */
11782 if (is_data
&& ((info
->flags
& DISASSEMBLE_DATA
) == 0))
11786 /* Size was already set above. */
11787 info
->bytes_per_chunk
= size
;
11788 printer
= print_insn_data
;
11790 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, size
, info
);
11793 for (i
= size
- 1; i
>= 0; i
--)
11794 given
= b
[i
] | (given
<< 8);
11796 for (i
= 0; i
< (int) size
; i
++)
11797 given
= b
[i
] | (given
<< 8);
11799 else if (!is_thumb
)
11801 /* In ARM mode endianness is a straightforward issue: the instruction
11802 is four bytes long and is either ordered 0123 or 3210. */
11803 printer
= print_insn_arm
;
11804 info
->bytes_per_chunk
= 4;
11807 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 4, info
);
11809 given
= (b
[0]) | (b
[1] << 8) | (b
[2] << 16) | (b
[3] << 24);
11811 given
= (b
[3]) | (b
[2] << 8) | (b
[1] << 16) | (b
[0] << 24);
11815 /* In Thumb mode we have the additional wrinkle of two
11816 instruction lengths. Fortunately, the bits that determine
11817 the length of the current instruction are always to be found
11818 in the first two bytes. */
11819 printer
= print_insn_thumb16
;
11820 info
->bytes_per_chunk
= 2;
11823 status
= info
->read_memory_func (pc
, (bfd_byte
*) b
, 2, info
);
11825 given
= (b
[0]) | (b
[1] << 8);
11827 given
= (b
[1]) | (b
[0] << 8);
11831 /* These bit patterns signal a four-byte Thumb
11833 if ((given
& 0xF800) == 0xF800
11834 || (given
& 0xF800) == 0xF000
11835 || (given
& 0xF800) == 0xE800)
11837 status
= info
->read_memory_func (pc
+ 2, (bfd_byte
*) b
, 2, info
);
11839 given
= (b
[0]) | (b
[1] << 8) | (given
<< 16);
11841 given
= (b
[1]) | (b
[0] << 8) | (given
<< 16);
11843 printer
= print_insn_thumb32
;
11848 if (ifthen_address
!= pc
)
11849 find_ifthen_state (pc
, info
, little_code
);
11853 if ((ifthen_state
& 0xf) == 0x8)
11854 ifthen_next_state
= 0;
11856 ifthen_next_state
= (ifthen_state
& 0xe0)
11857 | ((ifthen_state
& 0xf) << 1);
11863 info
->memory_error_func (status
, pc
, info
);
11866 if (info
->flags
& INSN_HAS_RELOC
)
11867 /* If the instruction has a reloc associated with it, then
11868 the offset field in the instruction will actually be the
11869 addend for the reloc. (We are using REL type relocs).
11870 In such cases, we can ignore the pc when computing
11871 addresses, since the addend is not currently pc-relative. */
11874 printer (pc
, info
, given
);
11878 ifthen_state
= ifthen_next_state
;
11879 ifthen_address
+= size
;
11885 print_insn_big_arm (bfd_vma pc
, struct disassemble_info
*info
)
11887 /* Detect BE8-ness and record it in the disassembler info. */
11888 if (info
->flavour
== bfd_target_elf_flavour
11889 && info
->section
!= NULL
11890 && (elf_elfheader (info
->section
->owner
)->e_flags
& EF_ARM_BE8
))
11891 info
->endian_code
= BFD_ENDIAN_LITTLE
;
11893 return print_insn (pc
, info
, FALSE
);
11897 print_insn_little_arm (bfd_vma pc
, struct disassemble_info
*info
)
11899 return print_insn (pc
, info
, TRUE
);
11902 const disasm_options_and_args_t
*
11903 disassembler_options_arm (void)
11905 static disasm_options_and_args_t
*opts_and_args
;
11907 if (opts_and_args
== NULL
)
11909 disasm_options_t
*opts
;
11912 opts_and_args
= XNEW (disasm_options_and_args_t
);
11913 opts_and_args
->args
= NULL
;
11915 opts
= &opts_and_args
->options
;
11916 opts
->name
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11917 opts
->description
= XNEWVEC (const char *, NUM_ARM_OPTIONS
+ 1);
11919 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11921 opts
->name
[i
] = regnames
[i
].name
;
11922 if (regnames
[i
].description
!= NULL
)
11923 opts
->description
[i
] = _(regnames
[i
].description
);
11925 opts
->description
[i
] = NULL
;
11927 /* The array we return must be NULL terminated. */
11928 opts
->name
[i
] = NULL
;
11929 opts
->description
[i
] = NULL
;
11932 return opts_and_args
;
11936 print_arm_disassembler_options (FILE *stream
)
11938 unsigned int i
, max_len
= 0;
11939 fprintf (stream
, _("\n\
11940 The following ARM specific disassembler options are supported for use with\n\
11941 the -M switch:\n"));
11943 for (i
= 0; i
< NUM_ARM_OPTIONS
; i
++)
11945 unsigned int len
= strlen (regnames
[i
].name
);
11950 for (i
= 0, max_len
++; i
< NUM_ARM_OPTIONS
; i
++)
11951 fprintf (stream
, " %s%*c %s\n",
11953 (int)(max_len
- strlen (regnames
[i
].name
)), ' ',
11954 _(regnames
[i
].description
));