ba03b9baef1cc5301b29d5ae97584d835c5bb85d
[deliverable/binutils-gdb.git] / opcodes / arm-dis.c
1 /* Instruction printing code for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modification by James G. Smith (jsmith@cygnus.co.uk)
5
6 This file is part of libopcodes.
7
8 This program is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2 of the License, or (at your option)
11 any later version.
12
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
22 #include "dis-asm.h"
23 #define DEFINE_TABLE
24 #include "arm-opc.h"
25 #include "coff/internal.h"
26 #include "libcoff.h"
27 #include "opintl.h"
28
29 /* FIXME: This shouldn't be done here */
30 #include "elf-bfd.h"
31 #include "elf/internal.h"
32 #include "elf/arm.h"
33
34 static char *arm_conditional[] =
35 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
36 "hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
37
38 static char *arm_regnames_raw[] =
39 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
40 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
41
42 static char *arm_regnames_standard[] =
43 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
44 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc"};
45
46 static char *arm_regnames_apcs[] =
47 {"a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4",
48 "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc"};
49
50 /* Choose which register name set to use. */
51 static char **arm_regnames = arm_regnames_standard;
52
53 static char *arm_fp_const[] =
54 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
55
56 static char *arm_shift[] =
57 {"lsl", "lsr", "asr", "ror"};
58
59 static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *,
60 long));
61
62 static void
63 arm_decode_shift (given, func, stream)
64 long given;
65 fprintf_ftype func;
66 void *stream;
67 {
68 func (stream, "%s", arm_regnames[given & 0xf]);
69 if ((given & 0xff0) != 0)
70 {
71 if ((given & 0x10) == 0)
72 {
73 int amount = (given & 0xf80) >> 7;
74 int shift = (given & 0x60) >> 5;
75 if (amount == 0)
76 {
77 if (shift == 3)
78 {
79 func (stream, ", rrx");
80 return;
81 }
82 amount = 32;
83 }
84 func (stream, ", %s #%d", arm_shift[shift], amount);
85 }
86 else
87 func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
88 arm_regnames[(given & 0xf00) >> 8]);
89 }
90 }
91
92 /* Print one instruction from PC on INFO->STREAM.
93 Return the size of the instruction (always 4 on ARM). */
94
95 static int
96 print_insn_arm (pc, info, given)
97 bfd_vma pc;
98 struct disassemble_info *info;
99 long given;
100 {
101 struct arm_opcode * insn;
102 void * stream = info->stream;
103 fprintf_ftype func = info->fprintf_func;
104
105 for (insn = arm_opcodes; insn->assembler; insn++)
106 {
107 if ((given & insn->mask) == insn->value)
108 {
109 char * c;
110
111 for (c = insn->assembler; *c; c++)
112 {
113 if (*c == '%')
114 {
115 switch (*++c)
116 {
117 case '%':
118 func (stream, "%%");
119 break;
120
121 case 'a':
122 if (((given & 0x000f0000) == 0x000f0000)
123 && ((given & 0x02000000) == 0))
124 {
125 int offset = given & 0xfff;
126
127 func (stream, "[pc");
128
129 if (given & 0x01000000)
130 {
131 if ((given & 0x00800000) == 0)
132 offset = - offset;
133
134 /* pre-indexed */
135 func (stream, ", #%x]", offset);
136
137 offset += pc + 8;
138
139 /* Cope with the possibility of write-back being used.
140 Probably a very dangerous thing for the programmer
141 to do, but who are we to argue ? */
142 if (given & 0x00200000)
143 func (stream, "!");
144 }
145 else
146 {
147 /* post indexed */
148 func (stream, "], #%x", offset);
149
150 offset = pc + 8; /* ie ignore the offset */
151 }
152
153 func (stream, "\t; ");
154 info->print_address_func (offset, info);
155 }
156 else
157 {
158 func (stream, "[%s",
159 arm_regnames[(given >> 16) & 0xf]);
160 if ((given & 0x01000000) != 0)
161 {
162 if ((given & 0x02000000) == 0)
163 {
164 int offset = given & 0xfff;
165 if (offset)
166 func (stream, ", %s#%d",
167 (((given & 0x00800000) == 0)
168 ? "-" : ""), offset);
169 }
170 else
171 {
172 func (stream, ", %s",
173 (((given & 0x00800000) == 0)
174 ? "-" : ""));
175 arm_decode_shift (given, func, stream);
176 }
177
178 func (stream, "]%s",
179 ((given & 0x00200000) != 0) ? "!" : "");
180 }
181 else
182 {
183 if ((given & 0x02000000) == 0)
184 {
185 int offset = given & 0xfff;
186 if (offset)
187 func (stream, "], %s#%d",
188 (((given & 0x00800000) == 0)
189 ? "-" : ""), offset);
190 else
191 func (stream, "]");
192 }
193 else
194 {
195 func (stream, "], %s",
196 (((given & 0x00800000) == 0)
197 ? "-" : ""));
198 arm_decode_shift (given, func, stream);
199 }
200 }
201 }
202 break;
203
204 case 's':
205 if ((given & 0x004f0000) == 0x004f0000)
206 {
207 /* PC relative with immediate offset */
208 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
209
210 if ((given & 0x00800000) == 0)
211 offset = -offset;
212
213 func (stream, "[pc, #%x]\t; ", offset);
214
215 (*info->print_address_func)
216 (offset + pc + 8, info);
217 }
218 else
219 {
220 func (stream, "[%s",
221 arm_regnames[(given >> 16) & 0xf]);
222 if ((given & 0x01000000) != 0)
223 {
224 /* pre-indexed */
225 if ((given & 0x00400000) == 0x00400000)
226 {
227 /* immediate */
228 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
229 if (offset)
230 func (stream, ", %s#%d",
231 (((given & 0x00800000) == 0)
232 ? "-" : ""), offset);
233 }
234 else
235 {
236 /* register */
237 func (stream, ", %s%s",
238 (((given & 0x00800000) == 0)
239 ? "-" : ""),
240 arm_regnames[given & 0xf]);
241 }
242
243 func (stream, "]%s",
244 ((given & 0x00200000) != 0) ? "!" : "");
245 }
246 else
247 {
248 /* post-indexed */
249 if ((given & 0x00400000) == 0x00400000)
250 {
251 /* immediate */
252 int offset = ((given & 0xf00) >> 4) | (given & 0xf);
253 if (offset)
254 func (stream, "], %s#%d",
255 (((given & 0x00800000) == 0)
256 ? "-" : ""), offset);
257 else
258 func (stream, "]");
259 }
260 else
261 {
262 /* register */
263 func (stream, "], %s%s",
264 (((given & 0x00800000) == 0)
265 ? "-" : ""),
266 arm_regnames[given & 0xf]);
267 }
268 }
269 }
270 break;
271
272 case 'b':
273 (*info->print_address_func)
274 (BDISP (given) * 4 + pc + 8, info);
275 break;
276
277 case 'c':
278 func (stream, "%s",
279 arm_conditional [(given >> 28) & 0xf]);
280 break;
281
282 case 'm':
283 {
284 int started = 0;
285 int reg;
286
287 func (stream, "{");
288 for (reg = 0; reg < 16; reg++)
289 if ((given & (1 << reg)) != 0)
290 {
291 if (started)
292 func (stream, ", ");
293 started = 1;
294 func (stream, "%s", arm_regnames[reg]);
295 }
296 func (stream, "}");
297 }
298 break;
299
300 case 'o':
301 if ((given & 0x02000000) != 0)
302 {
303 int rotate = (given & 0xf00) >> 7;
304 int immed = (given & 0xff);
305 func (stream, "#%d",
306 ((immed << (32 - rotate))
307 | (immed >> rotate)) & 0xffffffff);
308 }
309 else
310 arm_decode_shift (given, func, stream);
311 break;
312
313 case 'p':
314 if ((given & 0x0000f000) == 0x0000f000)
315 func (stream, "p");
316 break;
317
318 case 't':
319 if ((given & 0x01200000) == 0x00200000)
320 func (stream, "t");
321 break;
322
323 case 'h':
324 if ((given & 0x00000020) == 0x00000020)
325 func (stream, "h");
326 else
327 func (stream, "b");
328 break;
329
330 case 'A':
331 func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
332 if ((given & 0x01000000) != 0)
333 {
334 int offset = given & 0xff;
335 if (offset)
336 func (stream, ", %s#%d]%s",
337 ((given & 0x00800000) == 0 ? "-" : ""),
338 offset * 4,
339 ((given & 0x00200000) != 0 ? "!" : ""));
340 else
341 func (stream, "]");
342 }
343 else
344 {
345 int offset = given & 0xff;
346 if (offset)
347 func (stream, "], %s#%d",
348 ((given & 0x00800000) == 0 ? "-" : ""),
349 offset * 4);
350 else
351 func (stream, "]");
352 }
353 break;
354
355 case 'C':
356 switch (given & 0x00090000)
357 {
358 default:
359 func (stream, "_???");
360 break;
361 case 0x90000:
362 func (stream, "_all");
363 break;
364 case 0x10000:
365 func (stream, "_ctl");
366 break;
367 case 0x80000:
368 func (stream, "_flg");
369 break;
370 }
371 break;
372
373 case 'F':
374 switch (given & 0x00408000)
375 {
376 case 0:
377 func (stream, "4");
378 break;
379 case 0x8000:
380 func (stream, "1");
381 break;
382 case 0x00400000:
383 func (stream, "2");
384 break;
385 default:
386 func (stream, "3");
387 }
388 break;
389
390 case 'P':
391 switch (given & 0x00080080)
392 {
393 case 0:
394 func (stream, "s");
395 break;
396 case 0x80:
397 func (stream, "d");
398 break;
399 case 0x00080000:
400 func (stream, "e");
401 break;
402 default:
403 func (stream, _("<illegal precision>"));
404 break;
405 }
406 break;
407 case 'Q':
408 switch (given & 0x00408000)
409 {
410 case 0:
411 func (stream, "s");
412 break;
413 case 0x8000:
414 func (stream, "d");
415 break;
416 case 0x00400000:
417 func (stream, "e");
418 break;
419 default:
420 func (stream, "p");
421 break;
422 }
423 break;
424 case 'R':
425 switch (given & 0x60)
426 {
427 case 0:
428 break;
429 case 0x20:
430 func (stream, "p");
431 break;
432 case 0x40:
433 func (stream, "m");
434 break;
435 default:
436 func (stream, "z");
437 break;
438 }
439 break;
440
441 case '0': case '1': case '2': case '3': case '4':
442 case '5': case '6': case '7': case '8': case '9':
443 {
444 int bitstart = *c++ - '0';
445 int bitend = 0;
446 while (*c >= '0' && *c <= '9')
447 bitstart = (bitstart * 10) + *c++ - '0';
448
449 switch (*c)
450 {
451 case '-':
452 c++;
453 while (*c >= '0' && *c <= '9')
454 bitend = (bitend * 10) + *c++ - '0';
455 if (!bitend)
456 abort ();
457 switch (*c)
458 {
459 case 'r':
460 {
461 long reg;
462 reg = given >> bitstart;
463 reg &= (2 << (bitend - bitstart)) - 1;
464 func (stream, "%s", arm_regnames[reg]);
465 }
466 break;
467 case 'd':
468 {
469 long reg;
470 reg = given >> bitstart;
471 reg &= (2 << (bitend - bitstart)) - 1;
472 func (stream, "%d", reg);
473 }
474 break;
475 case 'x':
476 {
477 long reg;
478 reg = given >> bitstart;
479 reg &= (2 << (bitend - bitstart)) - 1;
480 func (stream, "0x%08x", reg);
481 }
482 break;
483 case 'f':
484 {
485 long reg;
486 reg = given >> bitstart;
487 reg &= (2 << (bitend - bitstart)) - 1;
488 if (reg > 7)
489 func (stream, "#%s",
490 arm_fp_const[reg & 7]);
491 else
492 func (stream, "f%d", reg);
493 }
494 break;
495 default:
496 abort ();
497 }
498 break;
499 case '`':
500 c++;
501 if ((given & (1 << bitstart)) == 0)
502 func (stream, "%c", *c);
503 break;
504 case '\'':
505 c++;
506 if ((given & (1 << bitstart)) != 0)
507 func (stream, "%c", *c);
508 break;
509 case '?':
510 ++c;
511 if ((given & (1 << bitstart)) != 0)
512 func (stream, "%c", *c++);
513 else
514 func (stream, "%c", *++c);
515 break;
516 default:
517 abort ();
518 }
519 break;
520
521 default:
522 abort ();
523 }
524 }
525 }
526 else
527 func (stream, "%c", *c);
528 }
529 return 4;
530 }
531 }
532 abort ();
533 }
534
535 /* Print one instruction from PC on INFO->STREAM.
536 Return the size of the instruction. */
537
538 static int
539 print_insn_thumb (pc, info, given)
540 bfd_vma pc;
541 struct disassemble_info *info;
542 long given;
543 {
544 struct thumb_opcode *insn;
545 void *stream = info->stream;
546 fprintf_ftype func = info->fprintf_func;
547
548 for (insn = thumb_opcodes; insn->assembler; insn++)
549 {
550 if ((given & insn->mask) == insn->value)
551 {
552 char *c = insn->assembler;
553
554 /* Special processing for Thumb 2 instruction BL sequence: */
555 if (!*c) /* check for empty (not NULL) assembler string */
556 {
557 info->bytes_per_chunk = 4;
558 info->bytes_per_line = 4;
559
560 func (stream, "%04x\tbl\t", given & 0xffff);
561 (*info->print_address_func)
562 (BDISP23 (given) * 2 + pc + 4, info);
563 return 4;
564 }
565 else
566 {
567 info->bytes_per_chunk = 2;
568 info->bytes_per_line = 4;
569
570 given &= 0xffff;
571 func (stream, "%04x\t", given);
572 for (; *c; c++)
573 {
574 if (*c == '%')
575 {
576 int domaskpc = 0;
577 int domasklr = 0;
578 switch (*++c)
579 {
580 case '%':
581 func (stream, "%%");
582 break;
583
584 case 'S':
585 {
586 long reg;
587 reg = (given >> 3) & 0x7;
588 if (given & (1 << 6))
589 reg += 8;
590 func (stream, "%s", arm_regnames[reg]);
591 }
592 break;
593
594 case 'D':
595 {
596 long reg;
597 reg = given & 0x7;
598 if (given & (1 << 7))
599 reg += 8;
600 func (stream, "%s", arm_regnames[reg]);
601 }
602 break;
603
604 case 'T':
605 func (stream, "%s",
606 arm_conditional [(given >> 8) & 0xf]);
607 break;
608
609 case 'N':
610 if (given & (1 << 8))
611 domasklr = 1;
612 /* fall through */
613 case 'O':
614 if (*c == 'O' && (given & (1 << 8)))
615 domaskpc = 1;
616 /* fall through */
617 case 'M':
618 {
619 int started = 0;
620 int reg;
621 func (stream, "{");
622 /* It would be nice if we could spot
623 ranges, and generate the rS-rE format: */
624 for (reg = 0; (reg < 8); reg++)
625 if ((given & (1 << reg)) != 0)
626 {
627 if (started)
628 func (stream, ", ");
629 started = 1;
630 func (stream, "%s", arm_regnames[reg]);
631 }
632
633 if (domasklr)
634 {
635 if (started)
636 func (stream, ", ");
637 started = 1;
638 func (stream, "lr");
639 }
640
641 if (domaskpc)
642 {
643 if (started)
644 func (stream, ", ");
645 func (stream, "pc");
646 }
647
648 func (stream, "}");
649 }
650 break;
651
652
653 case '0': case '1': case '2': case '3': case '4':
654 case '5': case '6': case '7': case '8': case '9':
655 {
656 int bitstart = *c++ - '0';
657 int bitend = 0;
658 while (*c >= '0' && *c <= '9')
659 bitstart = (bitstart * 10) + *c++ - '0';
660
661 switch (*c)
662 {
663 case '-':
664 {
665 long reg;
666 c++;
667 while (*c >= '0' && *c <= '9')
668 bitend = (bitend * 10) + *c++ - '0';
669 if (!bitend)
670 abort ();
671 reg = given >> bitstart;
672 reg &= (2 << (bitend - bitstart)) - 1;
673 switch (*c)
674 {
675 case 'r':
676 func (stream, "%s", arm_regnames[reg]);
677 break;
678
679 case 'd':
680 func (stream, "%d", reg);
681 break;
682
683 case 'H':
684 func (stream, "%d", reg << 1);
685 break;
686
687 case 'W':
688 func (stream, "%d", reg << 2);
689 break;
690
691 case 'a':
692 /* PC-relative address -- the bottom two
693 bits of the address are dropped before
694 the calculation. */
695 info->print_address_func
696 (((pc + 4) & ~3) + (reg << 2), info);
697 break;
698
699 case 'x':
700 func (stream, "0x%04x", reg);
701 break;
702
703 case 'I':
704 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
705 func (stream, "%d", reg);
706 break;
707
708 case 'B':
709 reg = ((reg ^ (1 << bitend)) - (1 << bitend));
710 (*info->print_address_func)
711 (reg * 2 + pc + 4, info);
712 break;
713
714 default:
715 abort();
716 }
717 }
718 break;
719
720 case '\'':
721 c++;
722 if ((given & (1 << bitstart)) != 0)
723 func (stream, "%c", *c);
724 break;
725
726 case '?':
727 ++c;
728 if ((given & (1 << bitstart)) != 0)
729 func (stream, "%c", *c++);
730 else
731 func (stream, "%c", *++c);
732 break;
733
734 default:
735 abort();
736 }
737 }
738 break;
739
740 default:
741 abort ();
742 }
743 }
744 else
745 func (stream, "%c", *c);
746 }
747 }
748 return 2;
749 }
750 }
751
752 /* no match */
753 abort ();
754 }
755
756 /* Select a different register name set.
757 Returns true if the name set selected is the APCS name set. */
758 int
759 arm_toggle_regnames ()
760 {
761 if (arm_regnames == arm_regnames_standard)
762 arm_regnames = arm_regnames_apcs;
763 else
764 arm_regnames = arm_regnames_standard;
765
766 return arm_regnames == arm_regnames_apcs;
767 }
768
769 static void
770 parse_disassembler_options (options)
771 char * options;
772 {
773 if (options == NULL)
774 return;
775
776 if (strncmp (options, "reg-names-", 10) == 0)
777 {
778 options += 10;
779
780 if (strcmp (options, "std") == 0)
781 arm_regnames = arm_regnames_standard;
782 else if (strcmp (options, "apcs") == 0)
783 arm_regnames = arm_regnames_apcs;
784 else if (strcmp (options, "raw") == 0)
785 arm_regnames = arm_regnames_raw;
786 else
787 fprintf (stderr, "Unrecognised register name set: %s\n", options);
788 }
789 else
790 fprintf (stderr, "Unrecognised disassembler option: %s\n", options);
791
792 return;
793 }
794
795 /* NOTE: There are no checks in these routines that the relevant number of data bytes exist */
796
797 int
798 print_insn_big_arm (pc, info)
799 bfd_vma pc;
800 struct disassemble_info *info;
801 {
802 unsigned char b[4];
803 long given;
804 int status;
805 coff_symbol_type *cs;
806 elf_symbol_type *es;
807 int is_thumb;
808
809 if (info->disassembler_options)
810 {
811 parse_disassembler_options (info->disassembler_options);
812
813 /* To avoid repeated parsing of this option, we remove it here. */
814 info->disassembler_options = NULL;
815 }
816
817 is_thumb = false;
818 if (info->symbols != NULL)
819 {
820 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
821 {
822 cs = coffsymbol (*info->symbols);
823 is_thumb = (cs->native->u.syment.n_sclass == C_THUMBEXT
824 || cs->native->u.syment.n_sclass == C_THUMBSTAT
825 || cs->native->u.syment.n_sclass == C_THUMBLABEL
826 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
827 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
828
829 }
830 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
831 {
832 es = *(elf_symbol_type **)(info->symbols);
833 is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) ==
834 STT_ARM_TFUNC;
835 }
836 }
837
838 info->bytes_per_chunk = 4;
839 info->display_endian = BFD_ENDIAN_BIG;
840
841 /* Always fetch word aligned values. */
842
843 status = (*info->read_memory_func) (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
844 if (status != 0)
845 {
846 (*info->memory_error_func) (status, pc, info);
847 return -1;
848 }
849
850 if (is_thumb)
851 {
852 if (pc & 0x2)
853 {
854 given = (b[2] << 8) | b[3];
855
856 status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
857 if (status != 0)
858 {
859 info->memory_error_func (status, pc + 4, info);
860 return -1;
861 }
862
863 given |= (b[0] << 24) | (b[1] << 16);
864 }
865 else
866 {
867 given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
868 }
869 }
870 else
871 {
872 given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
873 }
874
875 if (is_thumb)
876 {
877 status = print_insn_thumb (pc, info, given);
878 }
879 else
880 {
881 status = print_insn_arm (pc, info, given);
882 }
883
884 return status;
885 }
886
887 int
888 print_insn_little_arm (pc, info)
889 bfd_vma pc;
890 struct disassemble_info * info;
891 {
892 unsigned char b[4];
893 long given;
894 int status;
895 coff_symbol_type *cs;
896 elf_symbol_type *es;
897 int is_thumb;
898
899 if (info->disassembler_options)
900 {
901 parse_disassembler_options (info->disassembler_options);
902
903 /* To avoid repeated parsing of this option, we remove it here. */
904 info->disassembler_options = NULL;
905 }
906
907 is_thumb = false;
908 if (info->symbols != NULL)
909 {
910 if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
911 {
912 cs = coffsymbol (*info->symbols);
913 is_thumb = (cs->native->u.syment.n_sclass == C_THUMBEXT
914 || cs->native->u.syment.n_sclass == C_THUMBSTAT
915 || cs->native->u.syment.n_sclass == C_THUMBLABEL
916 || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
917 || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
918
919 }
920 else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
921 {
922 es = *(elf_symbol_type **)(info->symbols);
923 is_thumb = ELF_ST_TYPE (es->internal_elf_sym.st_info) ==
924 STT_ARM_TFUNC;
925 }
926 }
927
928 info->bytes_per_chunk = 4;
929 info->display_endian = BFD_ENDIAN_LITTLE;
930
931 status = (*info->read_memory_func) (pc, (bfd_byte *) &b[0], 4, info);
932 if (status != 0 && is_thumb)
933 {
934 info->bytes_per_chunk = 2;
935
936 status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
937 b[3] = b[2] = 0;
938 }
939 if (status != 0)
940 {
941 (*info->memory_error_func) (status, pc, info);
942 return -1;
943 }
944
945 given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
946
947 if (is_thumb)
948 {
949 status = print_insn_thumb (pc, info, given);
950 }
951 else
952 {
953 status = print_insn_arm (pc, info, given);
954 }
955
956 return status;
957 }
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